US2489303A - Counter frequency divider without time delay - Google Patents

Description

Nov. 29, 1949A H. LII-SCHUTZ 2,489,303

Now BY JUDICIAL CHANGE oF NAME H. I YoNs COUNTER FREQUENCY DIVIDER WITHOUT TIME DELAY Filed April e, 1942 :E: l :an-...[5177 Patented Nov. 29, 1949 COUNTER FREQUENCY DIVIDER WITHOUT TIME DELAY Harold Lifschutz, Washington, D. C., now by judicial change of name Harold Lyons Application April 6, 1942, Serial No. 437,813

(Cl. Z50-27 (Granted under the act of March 3, 1883, as amended April 30, 1928; 370 0. G. 757) 4 Claims.

This invention relates to electronic frequency dividers and more particularly to frequency dividers employing electronic counter circuits of the scale-of-two type.

It is well known in the art that electronic frequency dividers must, if the same are capable of practical utilization, operate in such a manner as to produce an output frequency of some submultiple of the input frequency and in synchronism therewith. It has been found advantageous in certain instances to utilize electronic counter circuits, of the scale-of-two type for example, as the primary components of electronic frequency dividers. However, due to certain inherent operating characteristics of conventional electronic counter circuits, the prior frequency dividers employing such circuits do not operate in the manner noted above. Electronic counter circuits of the scale-of-two type operate to generate one output pulse, of a certain polarity, upon application of every two input pulses of like polarity thereto. The output pulse is not generated at the instant the second pulse is applied to the circuit thus producing a time delay which is inherent in counter circuits of this type. Before electronic counter circuits may be employed to produce an efficient electronic frequency divider such time delay must be negatived.

It is therefore an object of the present invention to provide an eflicient electronic frequency divider that employs electronic counter circuits.

Another object is to provide means compensating for the time delay inherent in operation of conventional electronic counter circuits of the scale-of-two type whereby the latter may be employed in electronic frequency dividers.

Another object is to provide a frequency divider comprising a plurality of electronic counter circuits which operates to produce an output frequency of some sub-multiple of the input frequency and in synchronism therewith.

Another object is to provide a frequency divider that operates in response to equally spaced input `pulses to produce equally spaced output pulses, in synchronism with the input pulses, at a frequency less than the frequency of the input pulses.

Still another object of the invention is to provide an electronic frequency divider having a scale-of-two counter circuit for producing an electrical impulse at the instant an electrical pulse is applied thereto, and being of such construction to render the circuit non-responsive to subsequent impulses applied thereto, with means responsive to a predetermined number of irnpulses to again render the -counter circuit responsive to application of an electrical impulse to produce a second impulse.

Still another object is to provide a frequency divider of the above type having a plurality of scale-of-two electronic counter circuits connected in cascade relation for producing an electrical impulse following application of a predetermined number of electrical impulses thereto for rendering a separate scale-of-two counter circuit responsive to an electrical impulse.

Other objects and features of the invention will appear more fully from the following detailed description when considered in connection with the accompanying drawing which discloses one embodiment of the invention. It is to be expressly understood, however, that the drawing is designed for purposes of illustration only and not as a definition of the limits of the invention, reference for the latter purpose being had to the appended claims.

In the drawing, wherein similar reference characters denote similar parts throughout the several views:

Fig. 1 is a schematic showing of an electronic counter circuit of the scale-of-two type employed by the present invention, and

Fig. 2 is a diagrammatic showing of an electronic frequency divider embodying the principles of the present invention.

With reference more particularly to Fig. 1 of the drawing, a conventional electronic counter circuit is disclosed therein which includes a pair of vacuum tubes I0 and II each including a cathode I2, I3 and a plate I4, I5 respectively. Plates I4 and I5 are respectively supplied with positive potential from point I6 through resistances I'I and I 8, while cathodes I2 and I3 are connected together at point I9. Each of the tubes further respectively include a rst control grid 20, 2l, a second control grid or screen grid 22, 23 and a third control grid 24, 25. Control grids 2E! and 2| are connected through resistance 26 to point I9; screen grids 22 and 23 are supplied with high positive potential as indicated on the drawing; while f control grids 24 and 25 are connected through resistances 21 and 28, respectively, to a source of negative potential at point 29. Electrical impulses to be counted are supplied to the circuit through input terminal 30, which is connected to control grids 20 and 2l, while the output of the circuit is fed through capacitance 3| to terminal 32. The output of tube I0 is connected to the input of tube II by a connection from plate I4, through resistance 33, to grid 25, while the output of tube II is connected to the input of tube I0 by means of a connection, including resistance 34, between control grid 24 and plate l5. The foregoing connections form a two-stage resistance coupled ampliiier with regenerative feedback in which resistances 33 and 34 are respectively bypassed by capacitances 35 and 36, of small capacity, in order to obtain strong coupling and positive action of the circuit.

The foregoing circuit possesses two states of equilibrium, namely, first, when tube l is in a conducting state while tube il is not in a conducting state, and second, when tube iii is not conducting while tube 'll is conducting. Whenever a negative electrical impulseA is applied to grids and 2l, through input terminal 30, the tube in the conducting state is rendered less conducting, While the tube that was not passing the current is rendered conducting after the negative impulse to either grid 29 or 2i diminishes, consequently blocking the tube that was originally conducting.` This action produces a positive or a negative impulse at the output of each of the tubes, the tube that is rendered conducting producing a negative pulse, while the tube that is blocked produces a positive impulse. This action continues upon application of each negative impulse to the circuit, and each of the tubes therefore alternately produce negative impulses upon applicationof alternate negative impulses to inputterminal 30. Since output terminal 32 is connected to plate i5 it can be As mentioned heretofore, conventional electronic counter circuits of the vscale-of-tvvo type, such as an electronic counter circuit of the type discussed heretofore, possess an inherent time delay which renders similar circuits incapable of operating as efficient frequency dividers. Assuming an application of a negative impulse to grids 2) and 2i, when tube Iii is passing current while tube IlA is in a non-conducting state, a positive pulse appears atthe output of tube l0 when the tube is cutl olf. However, the negative impulse of the tube Il will not appear at the same instant since the tube will not be rendered conducting until Asuch negative potential diminishes from the lgrid thereof. VIt can be readily seen, therefore, that the negative pulse at terminal 32 does not'appear at the instant the second negative impulse is applied to input terminal 30, and for this reason electronic counter circuitsY are notcapable to operate as efficient electronic frequency dividers vwithout providing means compensating for such time delay.

In Fig. 2 of the drawings, an electronic frequency divider constructed in accordance with the principles of the present invention is disclosed therein including an electronic counter circuit of the scale-of-two type indicated generally at A. This counter circuit is similar to the counter circuitpreviously described with the exception that the impulses applied thereto, through input terminals are only applied to grid 20. In this embodiment cathodes i2 and i3 are connected together; however, grids 26 and 2i are connected to their respective cathodes through resistances 3l and 3B. Also, in this embodiment, the output terminal 39 is connected through capacitance 40 to plate I4 of tube ill. Since the negative impulses from input terminal 30 are only applied to grid'20, the circuit will lil 4 only be affected thereby when in that state of equilibrium in which tube I0 is passing current and tube i l is in a non-conducting state. With the circuit in the foregoing condition, the negative impulse applied to grid 20 cuts off the plate current flow in tube l0 causing a positive pulse to appear at output terminal 39 at substantially the instant a negative impulse is applied to grid 20, while also rendering tube ll in a conducting state. Since tube l0 is maintained in a non-conducting state by a negative potential on grid 24, and since the negative impulses from input terminal 3i) are not applied to grid 2| of tube l l, application of subsequent negative pulses from input terminal 30 will not affect the counter circuit.

In accordance with the principles of the presentv invention, means are provided for rendering the counter circuit responsive to a negative impulse, from terminal 3u, after a predetermined number of negative impulses are applied therefrom following the initial negative impulse, to produce another positive impulse at output terminal 39 at substantially the instant a certain negative impulse is applied to the counter circuit. As shown in Fig. 2, such means includes a plurality of electronic counter circuits 4I, 42, 4? and 4, which respectively comprise the first, second, third and nth stages of a counter arrangement. Each of the stages comprise an electronic counter circuit of the scaleof-two type, such as thetype disclosed in Fig. 1, connected in cascade as distinguished from a ring connection. The term cascade connection indicates that type of connection of a plurality of scale-of-two counter circuits in which only the iirst circuit of the group is connected to receive the incident pulses to be counted, subsequent circuits of the group each receiving triggering impulses from the next preceding circuit only. Since, as stated heretofore, the scale-of-two counter circuit disclosed in Fig. 1 produces one negative impulse at output terminal 32 for each two negative impulses applied thereto from terminal 3|, it can be readily seen that the counter arrangement disclosed in Fig. 2 produces one negative impulse upon application of a predetermined numberfof negative impulses thereto. For example, with a counter arrangement com'- prising stages 4l, 42, 43 and 44 connected in cascade relation, the number N of negative im.,- pulses applied to the rst stage through input conductor 45 for producing a negative impulse at output conductor 43, of stage 44, is equal to 2 raised to a power equal to the number of stages connected in cascade relation. WhenconSdering 4 stages connectedin cascade relation, 16 negative pulses must be applied to the first stage, through terminal 45, before a negative impulse appears at terminal 4E; It is to be expressly understood that any number of scaleof-two electroni-c counters or stages may be connected in cascade relationto obtain' an output pulse at terminal 46, after application of any predetermined number of negative impulses to the first stage. The foregoing counter arrangement is connected tothe electronic counter circuit, designated generally at A, in such a manner to render tube Ill responsive to a negative impulse after an impulse is produced at terminal 46. Input terminal 30 is connected to input terminal 45 so that negative impulses are applied to stage 4I and to grid 20 simultaneously,

accesos while `the outputof stage 44 is connected, by

way of terminal 46, to grid 2I of tube I I.

On operation ofthe frequency divider describedheretofore, assuming tube I0 to be passing current while tube I I is in a non-conducting state, upon application of a negative impulse to input terminal 45, grid 2|] is driven sufficiently ,negative to block tube I0 to thus cause a positive `impulse to appear at output terminal 39 at sub,-

stantially the instant the negative pulse is applied .Lto grid 20, while at the same time, actuating stage 4I of the plurality of counter circuits connected in cascade relation. Upon the application of the next negative impulse, tube I0 will not be affected afor. the reasons mentioned heretofore, while the counter circuit comprising stage 4I produces' an :output pulse which initiates actuation of stage A42,. After a number of negative impulses, equal :to 2 raised to a power equal to the number of `stages connected in cascade relation, are applied to the first stage from terminal 45, a negative in such a condition that the tube is responsive to the next negative impulse applied to grid 2li. VUpon application of the next negative impulse from the terminal 45, tube IIJ is cut off thus generating another positive impulse at terminal 39 Aand againrendering tube I0 non-responsive to subsequent negative impulses. It is to'be eX- pressly understood, therefore, that the impulse at terminal 39 appears simultaneously when the first ,g I

negative impulse is applied to terminal 45, and thereafter impulses appear at terminal 39 simultaneously upon application of every Nth negative impulse applied to terminal 45, where N equals 2 raised to a power equal to the number of scaleof-two counter circuits connected in cascade relation. With this arrangement an efficient frequency divider is provided which functions to produce impulses at the instant certain negative impulses are applied thereto. vSince the scaleof-two counter A is actuated directly by the impulses applied from terminal45 no time delay is present between the input and the output of the frequency divider, the positive output impulses being generated at substantially the in- Y stant negative impulses are applied to grid 2li, with tube I0 in a conducting state. Counter circuits 4I, 42, 43 and 44 function to determine the frequency reduction of the output impulses of scale-of-two counter A, and it is to be expressly understood that substantially any number of scale-of-two counter circuits may be connected in cascade relation to provide varied frequency reductions.

Since counter circuits 4 I, 42, 43 and 44 function to determine the frequency reduction of the output of counter circuit A, these circuits must operate to produce a negative impulse to render tube IU conducting, when the Nth negative impulse is applied to terminal 46, before the input negative impulse following the Nth pulse is applied from the input terminal. The maximum input frequency that may be employed then depends upon the number, and the speed of operation, of the scale-of-two counter circuits connected in cascade relation. In order to provide a circuit which allows operation of the highest maximum frequency, high speed counter circuits are provided in each of the stages, and the stages are interconnected in such a manner as to nullify Ainput impulses.

the time delay between eacn stage. With reference to Fig. 1 of the drawing, an arrangement is disclosed` therein for interconnecting the counter circuits in cascade relation to allow operation thereof without a time delay. As shown, a vacuum tube 4'I is provided which includes a plate 48, cathode-49 and a control grid 5B. Plate 48 is maintained atl high positive potential by a connection through resistance 5I to point `I6,

:While cathode 49 is connected to cathodes I2 and I3'. Output terminal 32 is connected to control ,grid 5B, While the latter is maintained at negative potential by a connection through resistance 52 to point 53. Output terminal 54, which supplies negative impulses to the next stage, is connected to plate 48 through capacitance 55.' Since control @grid 50 is maintained at negative potential tube 41 will not be effected upon the application of negative impulses from terminal 32; however, when positive pulses are generated in the output of tube II control grid 5D is driven positive to ,allow tube 41 to pass current and thus generate .a negative impulse at output terminal 54. Since positive impulses are generated at the output of tube I I at substantially the instant negative impulses from terminalll are applied to grids 20 and 2l it can be readily seen that tube 41 will pass current and generate a negative impulse at ter.- minal 54 at substantially the same instant.

There is thus provided by the present invention an electronic frequency divider, employing electronic counter circuits of the scale-of-two type, which operates to produce an output at a :frequency less than the input frequency and in synchronism with the latter. The arrangement disclosed herein is of such design to compensate .for certain time delays inherent in operation of conventional electronic counter circuits and is thus capable to produce equally spaced impulses, in ,synchronism with and at any desired fre,- quency less than the frequency of equally spaced Moreover, the present invention provides means for connecting a plurality of electronic counter circuits of the scale-of-two Atype in cascade relation to allow operation without a substantial time delay.

Although several embodiments of the invention .have been disclosed and described herein, it is to be expressly understood that various substitutions and changes may be made therein without de.- parting from the spirit of the invention as well understood by those skilled in the art. For example, any scale-oftwo type of counter circuit may be employed in the manner disclosed and described heretofore, such as triode or triple grid counter circuits. Reference therefor will be had to the appended claims as a definition of the limits of the invention.

The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

What is claimed is:

1. A frequency divider comprising a plurality of electronic counter circuits of the scale-of-two type connected in cascade relation, a separate electronic counter circuit of the scale-of-two type ineffective to inuence the cascade, means simultaneously applying incident electrical impulses to only the first circuit of said cascade and to said separate circuit, an output circuit individual to said separate circuit, means in said separate circuit for generating an electrical impulse in said output circuit at the instant the first inch ,v 7 dent impulse is applied, other means in said separate circuit for rendering' the latter non-respon- 'sive to application of electrical impulses following said iirst impulse, and means responsive to the output of said cascade for rendering said separate circuit responsive to the application of the rnext impulse following a predetermined number 4of impulses subsequent to said first impulse.`

2. An electronic frequency divider comprising a plurality of scale-of-two counter circuits, means 'connecting n' number of said circuits in cascade relation for producing an electrical impulse at the last circuit of said cascade upon application of 2n number of electrical impulses to the first stage thereof, means simultaneously applying lelectrical impulses to said lir'st circuit and to a separate circuit of said plurality, said separate circuit responsive to application of the first electrical impulse for producing an electrical impulse, means in said separate circuit for rendering the latter non-responsive to application of electrical impulses following said first impulse,

and means responsiveto the output of said cascade for rendering said separate circuit respon- Vsive to application of another electrical impulse .whereby said separate circuit producesa second impulse upon application of the 2}-1 impulse thereto.

3. A frequency divider comprising a, plurality of scale-to-two counter circuits, each of said circuits including a pair of multiple grid vacuum tubes, certain of said circuits interconnected in .such a manner whereby each of said tubes alternately produce positive and negative impulses upon application of negative impulses thereto,

`said positive impulses appearing substantially at the instant of application of alternate negative impulses, means connecting said certain circuits ducting upon application of a negative impulse to a grid of the tube rendered non-conducting, means applying negative impulses to the .grid o1' one of said tubes of said another circuit whereby the latter tube is rendered non-conducting while the otherV tube of said another circuit is rendered conducting upon application of the iirst negative impulse when said one tube is conducting, means simultaneously applying said negative impulses to the rst circuit of said cascade whereby a negiative impulse is produced at the last circuit of Said cascade upon application of a predetermined number of said negative impulses thereto, and means applyingthe output of said cascade to a grid of the other tube of said another circuit for rendering said one tube conducting and responsive to application of the negative impulse following said predetermined number of negative impulses.

4. A frequency divider comprising a plurality of electronic counter circuits each having an input and an output terminal, means connecting all of said circuits in cascade relation, and an additional counter circuit of the scale-of-two type having a separate input terminal for each of two cross-connected electron discharge devices, one of said separate input terminals being connected only to the output terminal of the last circuit of the cascade, and means simultaneously applying electrical impulses to the input terminal of onl`3r the first circuit of said cascade and the other of said separate input terminals of said additional counter circuit.

HAROLD LIFSCHUTZ,

New by judicial change of name, Harold Lyons..

REFERENCES CITED yThe following references are of record in the le of this patent:

Umm) sTATEs PATENTS Number Name Date `1,733,614: Morrison Oct. 29, 1929 1,979,484 Mathes Nov. 6, 193A 2,022,969 Meacham Dec. 3, 1935 2,158,285 Koch May 16, A1939 2,212,173 Wheeler Aug. 20, 1940 2,212,420 Harriett Aug. 20, 1940 2,266,668 Tubbs Dec. 16, 1941 2,275,016 Koch Mar. 3, 1942 2,305,625 Lauer Dec. 22, 1942 2,404,918 Overbeek July 30, 1946

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