US20240057382A1 - Display device and electronic device - Google Patents

Display device and electronic device Download PDF

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Publication number
US20240057382A1
US20240057382A1 US18/260,976 US202218260976A US2024057382A1 US 20240057382 A1 US20240057382 A1 US 20240057382A1 US 202218260976 A US202218260976 A US 202218260976A US 2024057382 A1 US2024057382 A1 US 2024057382A1
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Prior art keywords
insulator
conductor
layer
transistor
oxide
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US18/260,976
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English (en)
Inventor
Shunpei Yamazaki
Takayuki Ikeda
Tatsuya Onuki
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ONUKI, TATSUYA, YAMAZAKI, SHUNPEI, IKEDA, TAKAYUKI
Publication of US20240057382A1 publication Critical patent/US20240057382A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/01—Head-up displays
    • G02B27/017—Head mounted
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
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    • H10K59/873—Encapsulations
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/879—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses

Definitions

  • One embodiment of the present invention relates to a display device.
  • One embodiment of the present invention relates to a method for manufacturing a display device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting apparatus, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input/output device, a driving method thereof, and a fabrication method thereof.
  • VR virtual reality
  • AR augmented reality
  • SR substitutional reality
  • MR mixed reality
  • Typical examples of a display device include a liquid crystal display device; a light-emitting device including a light-emitting element such as an organic electroluminescence (EL) element or a light emitting diode (LED); and electronic paper performing display by an electrophoretic method or the like.
  • a light-emitting device including a light-emitting element such as an organic electroluminescence (EL) element or a light emitting diode (LED); and electronic paper performing display by an electrophoretic method or the like.
  • EL organic electroluminescence
  • LED light emitting diode
  • the basic structure of an organic EL element is, for example, a structure in which a layer containing a light-emitting organic compound is provided between a pair of electrodes. By applying voltage to this element, light emission can be obtained from the light-emitting organic compound.
  • a display device using such an organic EL element does not need a backlight that is necessary for a liquid crystal display device and the like; thus, a thin, lightweight, high-contrast, and low-power display device can be achieved.
  • Patent Document 1 discloses an example of a display device using an organic EL element. In the case where a high display quality is required as in the display device in Patent Document 1, a high-resolution display device including a large number of pixels is required in some cases.
  • a display device having high display quality such as the one disclosed in Patent Document 1, is desired for VR and AR devices.
  • an image is displayed in a wearable housing, like in a glasses-type device or a goggle-type device; therefore, small size and light weight are important factors for the display device.
  • the size of the display device needs to be reduced to approximately 2 inches or smaller, or 1 inch or smaller.
  • a display device requires a driver circuit such as a gate driver or a source driver for driving pixels, or a functional circuit such as an application processor for generating a control signal or the like for performing display.
  • a driver circuit such as a gate driver or a source driver for driving pixels
  • a functional circuit such as an application processor for generating a control signal or the like for performing display.
  • the display device includes a driver circuit and a functional circuit separately, in addition to a pixel circuit with a plurality of pixels, the length of wirings for electrically connecting the circuits increases, which would make a reduction in size and weight of the display device difficult.
  • the display device includes a driver circuit and a functional circuit that are monolithically provided, in addition to a pixel circuit with a plurality of pixels, the addition of the driver circuit and the functional circuit to the pixel circuit increases the circuit area, which would make a reduction in size and weight of the display device difficult.
  • An object of one embodiment of the present invention is to provide a display device with a reduced size. Another object of one embodiment of the present invention is to provide a display device with a reduced weight. Another object of one embodiment of the present invention is to provide a display device having superior display quality. Another object of one embodiment of the present invention is to provide a novel display device.
  • One embodiment of the present invention is a display device including a first layer, a second layer, and a third layer, in which the first layer, the second layer, and the third layer are provided in different layers, the first layer includes a driver circuit and a functional circuit, the second layer includes a pixel circuit, the third layer includes a display element, the pixel circuit has a function of controlling light emission of the display element, the driver circuit has a function of controlling the pixel circuit, and the functional circuit has a function of controlling the driver circuit.
  • One embodiment of the present invention is a display device including a first layer, a second layer, and a third layer, in which the first layer, the second layer, and the third layer are provided in different layers, the first layer includes a driver circuit and a functional circuit, the second layer includes a pixel circuit, the third layer includes a display element, the first layer includes a first transistor with a semiconductor layer containing silicon in a channel formation region, the second layer includes a second transistor with a semiconductor layer containing a metal oxide in a channel formation region, the pixel circuit has a function of controlling light emission of the display element, the driver circuit has a function of controlling the pixel circuit, and the functional circuit has a function of controlling the driver circuit.
  • the display device with the display element including an organic EL element, the organic EL element being a display element processed by a photolithography method, is preferable.
  • the display device with the driver circuit including a gate driver circuit and a source driver circuit is preferable.
  • the display device with the pixel circuit being divided into a plurality of regions and provided, one of the plurality of regions including the source driver circuit and the gate driver circuit, a plurality of source lines being electrically connected to the source driver circuit, and a plurality of gate lines being electrically connected to the gate driver circuit, is preferable.
  • One embodiment of the present invention is an electronic device including the above display device, a fixing member, a pair of lenses, and a battery.
  • One embodiment of the present invention can provide a display device with reduced size. Another embodiment of the present invention can provide a display device with reduced weight. Another embodiment of the present invention can provide a display device having superior display quality. Another embodiment of the present invention can provide a novel display device.
  • FIG. 1 A and FIG. 1 B are diagrams illustrating a structure example of a display device.
  • FIG. 2 A and FIG. 2 B are diagrams illustrating a structure example of a display device.
  • FIG. 3 A and FIG. 3 B are diagrams illustrating a structure example of a display device.
  • FIG. 4 A and FIG. 4 B are diagrams illustrating a structure example of a display device.
  • FIG. 5 A and FIG. 5 B are diagrams illustrating a structure example of a display device.
  • FIG. 6 A to FIG. 6 D are diagrams each illustrating a structure example of a display device.
  • FIG. 7 A to FIG. 7 D are diagrams each illustrating a structure example of a display device.
  • FIG. 8 is a diagram illustrating a structure example of a display device.
  • FIG. 9 A and FIG. 9 B are diagrams each illustrating a structure example of a display device.
  • FIG. 10 is a diagram illustrating a structure example of a display device.
  • FIG. 11 is a diagram illustrating a structure example of a display device.
  • FIG. 12 A to FIG. 12 C are diagrams illustrating a structure example of a display device.
  • FIG. 13 A is a diagram showing classification of crystal structures.
  • FIG. 13 B is a graph showing an XRD spectrum of a CAAC-IGZO film.
  • FIG. 13 C is an image showing nanobeam electron diffraction patterns of a CAAC-IGZO film.
  • FIG. 14 A to FIG. 14 D are diagrams each illustrating a structure example of a display element.
  • FIG. 15 A to FIG. 15 D are diagrams each illustrating a structure example of a display element.
  • FIG. 16 A and FIG. 16 B are diagrams each illustrating a structure example of a display element.
  • FIG. 17 A and FIG. 17 B are layout diagrams of display devices manufactured using a 12-inch wafer.
  • FIG. 18 A to FIG. 18 D are diagrams each illustrating a structure example of an electronic device.
  • FIG. 19 A and FIG. 19 B are diagrams each illustrating a structure example of an electronic device.
  • an off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as a non-conduction state or a cutoff state).
  • an off state refers to, in an n-channel transistor, a state where voltage V gs between its gate and source is lower than the threshold voltage V th (in a p-channel transistor, higher than V th ).
  • a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in an active layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be called a transistor including a metal oxide or an oxide semiconductor.
  • a device formed using a metal mask or an FMM may be referred to as a device having an MM (metal mask) structure.
  • a device formed without using a metal mask or an FMM is sometimes referred to as a device having an MML (metal maskless) structure.
  • FIG. 1 A is a schematic perspective view of a display device 10 .
  • the display device 10 includes a substrate 11 and a substrate 12 .
  • the display device includes a display portion 13 composed of elements provided between the substrate 11 and the substrate 12 .
  • the display portion 13 is a region where an image is displayed on the display device 10 .
  • the display portion 13 corresponds to a region where pixel circuits and pixels including display elements connected to the pixel circuits are provided.
  • a display element can be replaced with the term “device” in some cases.
  • a display element, a light-emitting element, and a liquid crystal element can be replaced with a display device, a light-emitting device, and a liquid crystal device, respectively.
  • various kinds of signals and power supply potentials are input from the outside via a terminal portion 14 , whereby an image can be displayed on the display portion 13 .
  • a plurality of layers are provided between the substrate 11 and the substrate 12 , and each of the layers is provided with a transistor for circuit operation, or a display element which emits light.
  • a pixel circuit having a function of controlling light emission of the display element, a driver circuit having a function of controlling the pixel circuit, a functional circuit having a function of controlling the driver circuit, and the like are provided in the plurality of layers.
  • FIG. 1 B is a perspective view schematically illustrating structures of layers provided between the substrate 11 and the substrate 12 .
  • a layer 20 is provided over the substrate 11 .
  • a driver circuit 30 and a functional circuit 40 are provided in the layer 20 .
  • the layer 20 includes a transistor 21 containing silicon in a channel formation region 22 (such a transistor is also referred to as a Si transistor).
  • the substrate 11 is, for example, a silicon substrate.
  • a silicon substrate is preferable because it has higher thermal conductivity than a glass substrate.
  • the transistor 21 can be a transistor containing single crystal silicon in its channel formation region, for example.
  • the use of a transistor containing single crystal silicon in a channel formation region as the transistor provided in the layer 20 can increase the on-state current of the transistor. This is preferable because circuits included in the layer 20 can be driven at high speed.
  • the Si transistor can be formed by microfabrication to have a channel length of 3 nm to 10 nm, for example; thus, the display device 10 can be provided with a CPU, an accelerator such as a GPU, an application processor, or the like.
  • the driver circuit 30 includes a gate driver circuit, a source driver circuit, or the like, for example.
  • an arithmetic circuit, a memory circuit, a power supply circuit, or the like may be included. Since the gate driver circuit, the source driver circuit, and other circuits can be placed to overlap with the display portion 13 , the width of a non-display region (also referred to as a bezel) provided along the outer periphery of the display portion 13 of the display device 10 can be extremely narrow compared with the case where these circuits are placed in the same plane as the display portion 13 , whereby the display device 10 with a small size can be achieved.
  • the functional circuit 40 has a function of application processor for controlling the circuits in the display device 10 and generating signals used for controlling the circuits, for example.
  • the functional circuit 40 may include a CPU and a circuit used for correcting image data, such as an accelerator (e.g., a GPU).
  • the functional circuit 40 may include an LVDS (Low Voltage Differential Signaling) circuit, an MIPI (Mobile Industry Processor Interface) circuit, and/or a D/A (Digital to Analog) converter circuit, for example, having a function of interface for receiving image data or the like from the outside of the display device 10 .
  • the functional circuit may include a circuit for compressing and decompressing image data and/or a power supply circuit, for example.
  • a layer 50 is provided over the layer 20 .
  • the layer 50 is provided with a plurality of pixel circuits 51 .
  • the layer 50 includes a transistor 52 containing a metal oxide (also referred to as an oxide transistor) in a channel formation region 54 (such a transistor is also referred to as an OS transistor). Note that the layer 50 can be stacked over the layer 20 .
  • the layer 50 may be formed over another substrate and bonded to the layer 20 .
  • the transistor 52 which is an OS transistor, a transistor including an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region.
  • an OS transistor has a characteristic of an extremely low off-state current.
  • the OS transistor it is particularly preferable to use the OS transistor as a transistor provided in a pixel circuit, in which case analog data written to the pixel circuit can be retained for a long period.
  • a layer 60 is provided over the layer 50 .
  • the substrate 12 is provided.
  • the substrate 12 is preferably a light-transmitting substrate or a layer formed of a light-transmitting material.
  • the layer 60 includes a plurality of display elements 61 .
  • the layer 60 can be stacked over the layer 50 .
  • an organic electroluminescent element also referred to as an organic EL element
  • the display element 61 is not limited thereto, and an inorganic EL element formed of an inorganic material may be used, for example. Note that an “organic EL element” and an “inorganic EL element” are collectively referred to as “EL element” in some cases.
  • the display element 61 may contain an inorganic compound such as quantum dots.
  • the quantum dots can function as a light-emitting material.
  • FIG. 2 A is a block diagram schematically showing the display device 10 illustrated in FIG. 1 A and FIG. 1 B .
  • the display device 10 of one embodiment of the present invention can have a structure in which the display elements 61 , the pixel circuits 51 , the driver circuit 30 , and the functional circuit 40 are stacked; thus, the aperture ratio (effective display area ratio) of the pixels can be significantly increased.
  • the pixel aperture ratio can be greater than or equal to 40% and less than 100%, preferably greater than or equal to 50% and less than or equal to 95%, and further preferably greater than or equal to 60% and less than or equal to 95%.
  • the pixel circuits 51 can be arranged extremely densely, and thus the resolution of the pixels can be extremely high.
  • the pixels can be arranged in the display portion of the display device 10 (a region where the pixel circuits 51 and the display elements 61 are stacked) with a resolution higher than or equal to 2000 ppi, preferably higher than or equal to 3000 ppi, further preferably higher than or equal to 5000 ppi, still further preferably higher than or equal to 6000 ppi, and lower than or equal to 20000 ppi or lower than or equal to 30000 ppi.
  • the display device 10 described above has extremely high resolution, and thus can be suitably used for a device for VR such as a head-mounted display or a glasses-type device for AR.
  • a device for VR such as a head-mounted display or a glasses-type device for AR.
  • the display device 10 can also be suitably used for an electronic device having a relatively small display portion.
  • the display device 10 can be suitably used in a display portion of a wearable electronic device such as a smart watch.
  • the diagonal size of the display portion 13 can be greater than or equal to 0.1 inches and less than or equal to 5 inches, preferably greater than or equal to 0.5 inches and less than or equal to 3 inches, further preferably greater than or equal to 1 inch and less than or equal to 2 inches.
  • the width of the bezel in the display device 10 of one embodiment of the present invention can be extremely narrow; in the case where the diagonal size of the substrate 11 over which the layer 20 is provided is 1 inch, for example, the amount of light to be obtained can be approximately four times larger than that of a case with a substrate with a diagonal size of 0.5 inches, which is suitable.
  • the display device 10 shown in FIG. 2 B is a block diagram illustrating a plurality of wirings connecting pixel circuits 51 , the driver circuit 30 , and the functional circuit 40 , a bus wiring, and the like.
  • the plurality of pixel circuits 51 are arranged in a matrix in the layer 50 .
  • the driver circuit 30 and the functional circuit 40 are provided in the layer in the display device 10 shown in FIG. 2 B .
  • the driver circuit 30 includes, for example, a source driver circuit 31 , a digital-to-analog converter circuit 32 , a gate driver circuit 33 , and a level shifter 34 .
  • the functional circuit 40 includes, for example, a memory device 41 , a GPU (AI accelerator) 42 , an EL correction circuit 43 , a timing controller 44 , a CPU 45 , a sensor controller 46 , and a power supply circuit 47 .
  • the functional circuit 40 has a function of an application processor.
  • the bus wiring BSL is electrically connected to each of the circuits included in the driver circuit 30 and each of the circuits included in the functional circuit 40 .
  • the source driver circuit 31 has a function of transmitting image data to the pixel circuit 51 , for example.
  • the source driver circuit 31 is electrically connected to the pixel circuit 51 through the wiring SL.
  • the digital-analog converter circuit 32 has a function of, for example, converting image data that has been digitally processed by a GPU described later, a correction circuit, or the like, into analog data.
  • the image data converted into analog data is transmitted to the pixel circuit 51 via the source driver circuit 31 .
  • the digital-analog converter circuit 32 may be included in the source driver circuit 31 , or the image data may be transmitted to the source driver circuit 31 , the digital-analog converter circuit 32 , and the pixel circuit 51 in this order.
  • the gate driver circuit 33 has a function of selecting a circuit to which image data is to be transmitted in the pixel circuit 51 , for example. Thus, the gate driver circuit 33 is electrically connected to the pixel circuit 51 through the wiring GL.
  • the level shifter 34 has a function of converting signals to be input to the source driver circuit 31 , the digital-analog converter circuit 32 , the gate driver circuit 33 , and the like into signals having appropriate levels, for example.
  • the memory device 41 has a function of storing image data to be displayed by the pixel circuit 51 , for example. Note that the memory device 41 can be configured to store the image data as digital data or analog data.
  • the memory device 41 stores image data
  • the memory device 41 is preferably a nonvolatile memory.
  • a NAND memory or the like can be used as the memory device 41 , for example.
  • the memory device 41 stores temporary data generated in the GPU 42 , the EL correction circuit 43 , the CPU 45 , or the like
  • the memory device 41 is preferably a volatile memory.
  • an SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the memory device 41 can be used as the memory device 41 , for example.
  • the GPU 42 has a function of performing processing for outputting image data read from the memory device 41 to the pixel circuit 51 , for example.
  • the GPU 42 is configured to perform pipeline processing in parallel and thus can perform high-speed processing of image data to be output to the pixel circuit 51 .
  • the GPU 42 can also has a function of a decoder for decoding an encoded image.
  • the functional circuit 40 may include a plurality of circuits that can improve the display quality of the display device 10 .
  • circuits for example, correction (dimming and toning) circuits that detect color irregularity of a displayed image and correct the color irregularity to obtain an optimal image may be provided.
  • the display element includes a light-emitting device including an organic EL material
  • the functional circuit 40 may be provided with an EL correction circuit.
  • the functional circuit 40 includes, for example, the EL correction circuit 43 .
  • the above-described image correction may be performed using artificial intelligence.
  • a current flowing in a pixel circuit (or a voltage applied to the pixel circuit) may be monitored and acquired, a displayed image may be acquired with an image sensor or the like, the current (or voltage) and the image may be used as input data in an arithmetic operation of the artificial intelligence (e.g., an artificial neural network), and the output result may be used to determine whether the image should be corrected.
  • the artificial intelligence e.g., an artificial neural network
  • FIG. 2 B illustrates the GPU 42 that includes blocks for performing arithmetic operations for various kinds of correction (e.g., color irregularity correction 42 a and upconversion 42 b ).
  • the timing controller 44 has a function of changing the frame rate at which an image is displayed, for example.
  • the display device 10 can be driven at a frame rate decreased by the timing controller 44 in the case where the display device 10 displays a still image; for another example, the display device 10 can be driven at a frame rate increased by the timing controller 44 in the case where the display device 10 displays a moving image.
  • the CPU 45 has a function of performing general-purpose processing such as execution of an operating system, control of data, and execution of various kinds of arithmetic operations or programs, for example.
  • the CPU 45 has a function of, for example, giving an instruction for a writing operation or a reading operation of image data in the memory device 41 , an operation for correcting image data, an operation for a later-described sensor, or the like.
  • the CPU 45 may have a function of transmitting a control signal to at least one of the circuits included in the functional circuit 40 , for example.
  • the sensor controller 46 has a function of controlling a sensor, for example.
  • FIG. 2 B illustrates a wiring SNCL as a wiring electrically connected to the sensor.
  • the sensor can be, for example, a touch sensor that can be provided in the display portion.
  • the sensor can be an illuminance sensor, for example.
  • the power supply circuit 47 has a function of generating voltages to be supplied to the pixel circuits 51 , the circuits included in the driver circuit 30 and the functional circuit 40 , and the like. Note that the power supply circuit 47 may have a function of selecting a circuit to which voltage is to be supplied. The power supply circuit 47 can stop supply of voltage to the CPU 45 , the GPU 42 , and the like during a period in which a still image is displayed so that the power consumption of the whole display device 10 is reduced, for example.
  • the display device of one embodiment of the present invention can have a structure in which display elements, pixel circuits, a driver circuit, and a functional circuit are stacked.
  • the driver circuit and a functional circuit which are peripheral circuits, can be provided so as to overlap with the pixel circuits and thus the width of the bezel can be made extremely small, so that a reduction in size of the display device can be achieved.
  • a structure of the display device of one embodiment of the present invention in which circuits are stacked enables its wirings connecting the circuits to be shortened, resulting in a reduction in weight of the display device.
  • the display device of one embodiment of the present invention can include a display portion with a high pixel resolution; thus, the display device can have high display quality.
  • FIG. 3 A and FIG. 3 B illustrate a configuration example of the pixel circuit 51 and the display element 61 connected to the pixel circuit 51 .
  • FIG. 3 A schematically illustrates the connection relation of the elements
  • FIG. 3 B schematically illustrates the vertical position relation of the layer 20 including the driver circuit, the layer 50 including a plurality of transistors of the pixel circuit, and the layer 60 including the light-emitting element.
  • the pixel circuit 51 illustrated as an example in FIG. 3 A and FIG. 3 B includes a transistor 52 A, a transistor 52 B, a transistor 52 C, and a capacitor 53 .
  • the transistor 52 A, the transistor 52 B, and the transistor 52 C can be OS transistors.
  • Each of the OS transistors, the transistor 52 A, the transistor 52 B, and the transistor 52 C preferably includes a back gate electrode, in which case the structure in which the back gate electrode is supplied with the same signals as those supplied to the gate electrode or the structure in which the back gate electrode is supplied with signals different from those supplied to the gate electrode can be used.
  • the transistor 52 B includes a gate electrode electrically connected to the transistor 52 A, a first terminal electrically connected to the display element 61 , and a second terminal electrically connected to a wiring ANO.
  • the wiring ANO is a wiring for supplying a potential for supplying a current to the display element 61 .
  • the transistor 52 A includes a first terminal electrically connected to the gate electrode of the transistor 52 B and a second terminal electrically connected to the wiring SL which functions as a source line, and has a function of controlling its conduction state or non-conduction state on the basis of the potential of a wiring GL 1 which functions as a gate line.
  • the transistor 52 C includes a first terminal electrically connected to a wiring V 0 and a second terminal electrically connected to the display element 61 , and has a function of controlling its conduction state or non-conduction state on the basis of the potential of a wiring GL 2 which functions as a gate line.
  • the wiring V 0 is a wiring for supplying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the driver circuit 30 or the functional circuit 40 .
  • the capacitor 53 includes a conductive film electrically connected to the gate electrode of the transistor 52 B and a conductive film electrically connected to the second terminal of the transistor 52 C.
  • the display element 61 includes a first electrode electrically connected to the first terminal of the transistor 52 B and a second electrode electrically connected to a wiring VCOM.
  • the wiring VCOM is a wiring for supplying a potential for supplying a current to the display element 61 .
  • the intensity of light emitted from the display element 61 can be controlled in accordance with an image signal supplied to the gate electrode of the transistor 52 B. Furthermore, variations in the gate-source voltage of the transistor 52 B can be inhibited by the reference potential of the wiring V 0 supplied through the transistor 52 C.
  • a current value that can be used for setting of pixel parameters can be output from the wiring V 0 .
  • the wiring V 0 can function as a monitor line for outputting a current flowing through the transistor 52 B or current flowing through the display element 61 to the outside.
  • a current output to the wiring V 0 is converted into a voltage by a source follower circuit or the like and output to the outside.
  • a current output to the wiring V 0 can be converted into a digital signal by an A-D converter or the like and output to the functional circuit 40 or the like.
  • the light-emitting element described in one embodiment of the present invention refers to a self-luminous display element such as an organic EL element (also referred to as an OLED (Organic Light Emitting Diode)).
  • the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.
  • the wirings electrically connecting the pixel circuit 51 and the driver circuit 30 can be shortened, so that wiring resistance of the wirings can be reduced.
  • data can be written at high speed, which enables high-speed driving of the display device 10 . Therefore, even when the number of the pixel circuits 51 included in the display device 10 is increased, a sufficiently long frame period can be ensured, and thus, the pixel density of the display device 10 can be increased.
  • the increased pixel density of the display device 10 can increase the resolution of an image displayed by the display device 10 .
  • the pixel density of the display device 10 can be higher than or equal to 1000 ppi, higher than or equal to 5000 ppi, or higher than or equal to 7000 ppi.
  • the display device 10 can be, for example, a display device for AR or VR and can be suitably used in an electronic device with a short distance between the display portion and the user, such as an HMD.
  • FIG. 4 A illustrates an example of the driver circuit 30 provided to overlap with the pixel circuit 51 .
  • the source driver circuit 31 and the gate driver circuit 33 are shown as the driver circuit 30 .
  • the plurality of pixel circuits 51 (not illustrated) can be divided into a plurality of regions 59 . Each of the regions 59 is provided in a region overlapping with the source driver circuit 31 and the gate driver circuit 33 .
  • the source driver circuit 31 and the gate driver circuit 33 can be divided into predetermined regions in the layer 20 and placed to correspond to the region 59 .
  • FIG. 4 B is an enlarged view of the region 59 .
  • a plurality of wirings SL and a plurality of wirings GL are each shown by dashed lines.
  • the plurality of wirings SL extending in the longitudinal direction are each electrically connected to the source driver circuit 31 .
  • the plurality of wirings GL extending in the lateral direction are each electrically connected to the gate driver circuit 33 .
  • the wirings SL and the wirings GL are each electrically connected to the plurality of pixel circuits 51 .
  • the pixel circuit 51 composed of OS transistors with an extremely low off-state current, can retain the data written to the pixel for a long period of time.
  • the frame frequency of display can be set as desired (can be changed).
  • the display device is capable of individually driving the regions 59 , different frame frequencies can be set for different regions 59 in some cases.
  • the pixel circuit and the functional circuit can be stacked; thus, a defective pixel can be detected with the use of the functional circuit provided below the pixel circuit. Data on the defective pixel can be used to correct a display defect due to the defective pixel, leading to normal display.
  • Some or all of steps of a correction method described below as an example may be performed by a circuit provided outside the display device. Part of the correction method may be performed by the functional circuit 40 of the display device 10 .
  • FIG. 5 A is a flow chart of the correction method described below.
  • Step S 1 the correction operation starts in Step S 1 .
  • Step S 2 currents of the pixels are read in Step S 2 .
  • each of the pixels can be driven so as to output a current to a monitor line electrically connected to the pixel.
  • the current reading operations can be performed simultaneously in the plurality of regions 59 .
  • the time required to read currents of all pixels can be extremely short.
  • Step S 3 the read currents are converted into voltages in Step S 3 .
  • conversion to digital data can be performed in Step S 3 .
  • analog data can be converted into digital data using an analog-digital converter circuit (ADC).
  • ADC analog-digital converter circuit
  • the pixel parameter includes the threshold voltage or field-effect mobility of the driving transistor, the threshold voltage of the light-emitting element, or a current value at a certain voltage, for example.
  • each of the pixels is determined to be abnormal or not on the basis of the pixel parameter in Step S 5 .
  • a pixel is determined to be abnormal when its pixel parameter has a value exceeding (or lower than) a predetermined threshold value.
  • An abnormal pixel is recognized as a dark spot defect when luminance is significantly lower than that corresponding to an input data potential, or recognized as a bright spot defect when luminance is significantly higher than that corresponding to an input data potential, for example.
  • the address of the abnormal pixel and the kind of the defect can be specified and acquired in Step S 5 .
  • Step S 6 correction processing is performed in Step S 6 .
  • FIG. 5 B schematically illustrates pixels arranged in a matrix of 3 ⁇ 3 each of which includes the pixel circuit 51 and the display element 61 .
  • a pixel 151 at the center is regarded as a dark spot defect.
  • FIG. 5 B schematically illustrates a state where the pixel 151 is in a non-lighting state and pixels 150 around the pixel 151 are in lighting states with predetermined luminance.
  • a dark spot defect is due to a pixel unlikely to have normal luminance even when correction for increasing a data potential input to the pixel is performed.
  • correction for increasing luminance is performed on the pixels 150 around the pixel 151 recognized as a dark spot defect, as illustrated in FIG. 5 B .
  • a normal image can be displayed even when a dark spot defect exists.
  • the luminance of pixels around the defect is decreased, so that the bright spot defect can be less noticeable.
  • Such a correction method for compensating for an abnormal pixel by pixels around the abnormal pixel is effective particularly in the case of a display device with a higher resolution (e.g., 1000 ppi or higher) because it is difficult to see individual pixels separately from each other.
  • correction be performed such that a data potential is not input to an abnormal pixel recognized as a dark spot defect, a bright spot defect, or the like.
  • a correction parameter can be set for each pixel.
  • correction image data which enables the display device 10 to display an optimal image can be generated.
  • correction parameters for the pixels not determined to be abnormal can be set so as to cancel (level off) the variation of the pixel parameters.
  • a reference value based on the mean value, average value, or the like of pixel parameters of some or all of the pixels can be set, and a correction value used for canceling a difference of a pixel parameter of a certain pixel from the reference value can be set as a correction parameter of the pixel.
  • correction data For each of pixels around an abnormal pixel, it is preferred to set correction data that takes into consideration both a correction amount for compensating for the abnormal pixel and a correction amount for canceling pixel parameter variation.
  • Step S 7 the correction operation terminates in Step S 7 .
  • an image can be displayed on the basis of the correction parameters obtained in the correction operation and image data to be input.
  • a neural network may be used for the correction operation.
  • the neural network can determine correction parameters on the basis of inference results obtained by machine learning, for example.
  • high-accuracy correction can be performed to make an abnormal pixel less noticeable without using a detailed algorithm for correction.
  • FIG. 3 A and FIG. 3 B illustrate, as an example, the pixel circuit 51 including three transistors in total, one embodiment of the present invention is not limited thereto. Configuration examples and a driving method example of a pixel circuit which can be used for the pixel circuit 51 will be described below.
  • a pixel circuit 51 A illustrated in FIG. 6 A includes the transistor 52 A, the transistor 52 B, and the capacitor 53 .
  • FIG. 6 A illustrates the display element 61 connected to the pixel circuit 51 A.
  • the wiring SL, the wiring GL, the wiring ANO, and the wiring VCOM are electrically connected to the pixel circuit 51 A.
  • a gate is electrically connected to wiring GL
  • one of a source and a drain is electrically connected to the wiring SL
  • the other thereof is electrically connected to a gate of the transistor 52 B and one electrode of the capacitor 53 .
  • One of a source and a drain of the transistor 52 B is electrically connected to the wiring ANO and the other thereof is electrically connected to an anode of the display element 61 .
  • the other electrode of the capacitor 53 is electrically connected to the anode of the display element 61 .
  • a cathode of the display element 61 is electrically connected to the wiring VCOM.
  • a pixel circuit 51 B illustrated in FIG. 6 B has a structure in which a transistor 52 C is added to the pixel circuit 51 A.
  • the wiring V 0 is electrically connected to the pixel circuit 51 B.
  • a pixel circuit 51 C illustrated in FIG. 6 C is an example in the case where a transistor in which a pair of gates are electrically connected to each other is used as each of the transistor 52 A and the transistor 52 B of the pixel circuit 51 A.
  • a pixel circuit 51 D illustrated in FIG. 6 D is an example in the case where such transistors are used in the pixel circuit 51 B.
  • the current that can flow through the transistor can be increased.
  • a transistor with a pair of gates being electrically connected to each other is used for each of the transistors here, one embodiment of the present invention is not limited thereto.
  • a transistor that includes a pair of gates electrically connected to different wirings may be used. When, for example, a transistor in which one of the gates is electrically connected to the source is used, the reliability can be increased.
  • a pixel circuit 51 E illustrated in FIG. 7 A has a structure in which a transistor 52 D is added to the pixel circuit 51 B.
  • Three wirings (wiring GL 1 , wiring GL 2 , and wiring GL 3 ) functioning as gate lines are electrically connected to the pixel circuit 51 E.
  • a gate of the transistor 52 D is electrically connected to the wiring GL 3 , one of a source and a drain of the transistor 52 D is electrically connected to the gate of the transistor 52 B, and the other of the source and the drain of the transistor 52 D is electrically connected to the wiring V 0 .
  • the gate of the transistor 52 A is electrically connected to the wiring GL 1
  • the gate of the transistor 52 C is electrically connected to the wiring GL 2 .
  • Such a pixel circuit is suitable for the case of using a display method in which a display period and an off period are alternately provided.
  • a pixel circuit 51 F illustrated in FIG. 7 B is an example in the case where a capacitor 53 A is added to the pixel circuit 51 E.
  • the capacitor 53 A functions as a storage capacitor.
  • a pixel circuit 51 G illustrated in FIG. 7 C and a pixel circuit 51 H illustrated in FIG. 7 D are each an example in the case where a transistor including a pair of gates is used in the pixel circuit 51 E or the pixel circuit 51 F.
  • a transistor in which a pair of gates are electrically connected to each other is used as each of the transistor 52 A, the transistor 52 C, and the transistor 52 D, and a transistor in which one of gates is electrically connected to a source is used as the transistor 52 B.
  • FIG. 8 shows a timing chart of a method for driving the display device in which the pixel circuit 51 E is used. Changes in the potentials of wirings GL 1 [ k ], GL 2 [ k ], and GL 3 [ k ] that are gate lines of the k-th row and changes in the potentials of wirings GL 1 [ k +1], GL 2 [ k +1], and GL 3 [ k +1] that are gate lines of the k+1-th row are shown here. FIG. 8 also shows the timing of supplying a signal to the wiring SL functioning as a source line.
  • a horizontal period of the k-th row is shifted from a horizontal period of the k+1-th row by a selection period of the gate line.
  • the wirings GL 1 [ k ] and GL 2 [ k ] are supplied with a high-level potential and the wiring SL is supplied with a source signal.
  • the transistor 52 A and the transistor 52 C are turned on, so that a potential corresponding to the source signal is written from the wiring SL to the gate of the transistor 52 B.
  • the wiring GL 1 [ k ] and the wiring GL 2 [ k ] are supplied with a low-level potential, so that the transistor 52 A and the transistor 52 C are turned off and the gate potential of the transistor 52 B is retained.
  • the non-lighting period is described.
  • the wiring GL 2 [ k ] and the wiring GL 3 [ k ] are supplied with a high-level potential. Accordingly, the transistor 52 C and the transistor 52 D are turned on, and the source and the gate of the transistor 52 B are supplied with the same potential, so that almost no current flows through the transistor 52 B. Thus, the display element 61 is turned off. All the subpixels that are positioned in the k-th row are turned off. The subpixels of the k-th row remain in the off state until the next lighting period.
  • Such a driving method described above, in which the subpixels are not constantly on through one horizontal period and a non-lighting period is provided in one horizontal period, can be called duty driving.
  • duty driving an afterimage phenomenon can be inhibited at the time of displaying moving images; therefore, a display device with high performance in displaying moving images can be achieved.
  • a reduction in an afterimage can reduce what is called VR sickness.
  • the proportion of the lighting period in one horizontal period can be called a duty cycle.
  • a duty cycle of 50% means that the lighting period and the non-lighting period have the same lengths.
  • the duty cycle can be set freely and can be adjusted appropriately within a range higher than 0% and lower than or equal to 100%, for example.
  • FIG. 9 A and FIG. 9 B A configuration different from the configurations of the above-described pixel circuits will be described with reference to FIG. 9 A and FIG. 9 B .
  • FIG. 9 A is a block diagram of an element included in the pixel circuit and a pixel including the light-emitting element.
  • the pixel illustrated in FIG. 9 A includes a memory in addition to a switching transistor (Switching Tr), a driving transistor (Driving Tr), and a light-emitting element (LED).
  • switching Tr switching transistor
  • driving Tr driving transistor
  • LED light-emitting element
  • Data Data_W is supplied to the memory.
  • the data Data_W is supplied to the pixel in addition to display data Data, a current flowing through the light-emitting element becomes large, so that the display device can have high luminance.
  • FIG. 9 B is a specific circuit diagram of the pixel circuit.
  • a pixel circuit 521 illustrated in FIG. 9 B includes a transistor 52 _ w , the transistor 52 A, the transistor 52 B, the transistor 52 C, a capacitor 53 _ s , and a capacitor 53 _ w .
  • FIG. 9 B illustrates the display element 61 connected to the pixel circuit 51 I.
  • One of a source and a drain of the transistor 52 _ w is electrically connected to one electrode of the capacitor 53 _ w .
  • the other electrode of the capacitor 53 _ w is electrically connected to one of a source and a drain of the transistor 52 A.
  • the one of the source and the drain of the transistor 52 A is electrically connected to a gate of the transistor 52 B.
  • the gate of the transistor 52 B is electrically connected to one electrode of the capacitor 53 _ s .
  • the other electrode of the capacitor 53 _ s is electrically connected to one of a source and a drain of the transistor 52 B.
  • the one of the source and the drain of the transistor 52 B is electrically connected to one of a source and a drain of the transistor 52 C.
  • the one of the source and the drain of the transistor 52 C is electrically connected to one electrode of the display element 61 .
  • the transistors illustrated in FIG. 9 B each include a back gate electrically connected to its gate; however, the connection of the back gate is not limited thereto. The transistor does not have to include the back gate.
  • a node to which the other electrode of the capacitor 53 _ w , the one of the source and the drain of the transistor 52 A, the gate of the transistor 52 B, and the one electrode of the capacitor 53 _ s are connected is referred to as a node NM.
  • a node to which the other electrode of the capacitor 53 _ s , the one of the source and the drain of the transistor 52 B, the one of the source and the drain of the transistor 52 C, and the one electrode of the display element 61 are connected is referred to as a node NA.
  • a gate of the transistor 52 _ w is electrically connected to the wiring GL 1 .
  • the gate of the transistor 52 C is electrically connected to the wiring GL 1 .
  • the gate of the transistor 52 A is electrically connected to the wiring GL 2 .
  • the other of the source and the drain of the transistor 52 _ w is electrically connected to a wiring SL 1 .
  • the other of the source and the drain of the transistor 52 C is electrically connected to the wiring V 0 .
  • the other of the source and the drain of the transistor 52 A is electrically connected to a wiring SL 2 .
  • the other of the source and the drain of the transistor 52 B is electrically connected to the wiring ANO.
  • the other electrode of the display element 61 is electrically connected to the wiring VCOM.
  • the wiring GL 1 and the wiring GL 2 can have a function of signal lines for controlling the operation of the transistors.
  • the wiring SL 1 can have a function of a signal line for supplying an image signal to the pixel.
  • the wiring SL 2 can have a function of a signal line for writing data to a memory circuit MEM.
  • the wiring SL 2 can have a function of a signal line for supplying a correction signal to the pixel.
  • the wiring V 0 has a function of a monitor line for obtaining the electrical characteristics of the transistor 52 B. A specific potential is supplied from the wiring V 0 to the other electrode of the capacitor 53 _ s through the transistor 52 C, whereby writing of an image signal can be stable.
  • a node NM is a storage node; when the transistor 52 _ w is turned on, a signal supplied to the wiring SL 2 can be written to the node NM.
  • the use of an OS transistor with an extremely low off-state current as the transistor 52 A allows the potential of the node NM to be retained for a long time.
  • the signal written to the node NM is capacitively coupled to the image signal supplied from the wiring SL 1 , and the resulting data can be output to the node NA.
  • the transistor 52 _ w can have a function of selecting a pixel.
  • the correction signal when an intended correction signal is stored in the node NM in advance, the correction signal can be added to the supplied image signal.
  • operation combined with the structure where the source driver circuit 31 and the gate driver circuit 33 are divided into predetermined regions in the layer 20 and operate in response to the divided region of the display portion, which is illustrated with reference to FIG. 4 A and FIG. 4 B , enables a structure where the correction signal is added only to the region in which the image data is updated so that the region is operated.
  • the correction signal is sometimes attenuated by a component on the transmission path; hence, the signal is preferably produced in consideration of the attenuation.
  • the amount of current flowing through the light-emitting device can be increased, and high luminance can be achieved.
  • a voltage higher than or equal to the output voltage of the source driver circuit can be applied as the gate voltage of the driving transistor, so that the power consumption of the source driver circuit can be reduced. Since high-luminance light can be used for a light source, the sensitivity of the sensor can be increased.
  • FIG. 10 is a cross-sectional view illustrating a structure example of the display device 10 .
  • the display device 10 includes a substrate 11 and a substrate 12 , and the substrate 11 and the substrate 12 are attached to each other with a sealant 712 .
  • a single crystal semiconductor substrate such as a single crystal silicon substrate can be used.
  • a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 11 .
  • a transistor 441 and a transistor 601 are provided on the substrate 11 .
  • the transistor 441 and the transistor 601 can each be the transistor 21 provided in the layer 20 described in Embodiment 1.
  • the transistor 441 is formed of a conductor 443 functioning as a gate electrode, an insulator 445 functioning as a gate insulator, and part of the substrate 11 and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449 a functioning as one of a source region and a drain region, and a low-resistance region 449 b functioning as the other of the source region and the drain region.
  • the transistor 441 can be a p-channel transistor or an n-channel transistor.
  • the transistor 441 is electrically isolated from other transistors by an element isolation layer 403 .
  • FIG. 10 illustrates the case where the transistor 441 and the transistor 601 are electrically isolated from each other by the element isolation layer 403 .
  • the element isolation layer 403 can be formed by a LOCOS (local oxidation of silicon) method, an STI (shallow trench isolation) method, or the like.
  • the semiconductor region 447 has a projecting shape.
  • the conductor 443 is provided to cover the side surface and the top surface of the semiconductor region 447 with the insulator 445 therebetween. Note that FIG. 10 does not illustrate the state where the conductor 443 covers the side surface of the semiconductor region 447 .
  • a material adjusting the work function can be used for the conductor 443 .
  • a transistor having a projecting semiconductor region like the transistor 441 , can be referred to as a fin-type transistor because a projecting portion of a semiconductor substrate is used.
  • An insulator functioning as a mask for forming a projecting portion may be provided in contact with the top surface of the projecting portion.
  • FIG. 10 illustrates the structure in which the projecting portion is formed by processing part of the substrate 11 , a semiconductor having a projecting shape may be formed by processing an SOI substrate.
  • the structure of the transistor 441 illustrated in FIG. 10 is only an example; the structure of the transistor 441 is not limited thereto and can be changed as appropriate in accordance with the circuit structure, an operation method of the circuit, or the like.
  • the transistor 441 may be a planar transistor.
  • the transistor 601 can have a structure similar to that of the transistor 441 .
  • An insulator 405 , an insulator 407 , an insulator 409 , and an insulator 411 are provided over the substrate 11 , in addition to the element isolation layer 403 and the transistors 441 and 601 .
  • a conductor 451 is embedded in the insulator 405 , the insulator 407 , the insulator 409 , and the insulator 411 .
  • the top surface of the conductor 451 and the top surface of the insulator 411 can be substantially level with each other.
  • An insulator 421 and an insulator 214 are provided over the conductor 451 and the insulator 411 .
  • a conductor 453 is embedded in the insulator 421 and the insulator 214 .
  • the top surface of the conductor 453 and the top surface of the insulator 214 can be substantially level with each other.
  • An insulator 216 is provided over the conductor 453 and the insulator 214 .
  • a conductor 455 is embedded in the insulator 216 .
  • the top surface of the conductor 455 and the top surface of the insulator 216 can be substantially level with each other.
  • An insulator 222 , an insulator 224 , an insulator 254 , an insulator 280 , an insulator 274 , and an insulator 281 are provided over the conductor 455 and the insulator 216 .
  • a conductor 305 is embedded in the insulator 222 , the insulator 224 , the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .
  • the top surface of the conductor 305 and the top surface of the insulator 281 can be substantially level with each other.
  • An insulator 361 is provided over the conductor 305 and the insulator 281 .
  • a conductor 317 and a conductor 337 are embedded in the insulator 361 .
  • the top surface of the conductor 337 and the top surface of the insulator 361 can be substantially level with each other.
  • An insulator 363 is provided over the conductor 337 and the insulator 361 .
  • a conductor 347 , a conductor 353 , a conductor 355 , and a conductor 357 are embedded in the insulator 363 .
  • the top surfaces of the conductor 353 , the conductor 355 , and the conductor 357 and the top surface of the insulator 363 can be substantially level with each other.
  • a connection electrode 760 is provided over the conductor 353 , the conductor 355 , the conductor 357 , and the insulator 363 .
  • an anisotropic conductor 780 is provided to be electrically connected to the connection electrode 760
  • a flexible printed circuit (FPC) 716 is provided to be electrically connected to the anisotropic conductor 780 .
  • FPC flexible printed circuit
  • the low-resistance region 449 b having a function of the other of the source region and the drain region of the transistor 441 is electrically connected to the FPC 716 through the conductor 451 , the conductor 453 , the conductor 455 , the conductor 305 , the conductor 317 , the conductor 337 , the conductor 347 , the conductor 353 , the conductor 355 , the conductor 357 , the connection electrode 760 , and the anisotropic conductor 780 .
  • FIG. 10 the anisotropic conductor 780 .
  • connection electrode 760 and the conductor 347 illustrates three conductors of the conductor 353 , the conductor 355 , and the conductor 357 as conductors that electrically connect the connection electrode 760 and the conductor 347 , one embodiment of the present invention is not limited thereto.
  • the number of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. Providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 can reduce the contact resistance.
  • a transistor 750 is provided over the insulator 214 .
  • the transistor 750 can be the transistor 52 provided in the layer 50 described in Embodiment 1.
  • the transistor 750 can be the transistor provided in the pixel circuit 51 .
  • An OS transistor can be suitably used as the transistor 750 .
  • the OS transistor has a feature of an extremely low off-state current. Consequently, the retention time for image data or the like can be increased, so that the frequency of the refresh operation can be reduced. Thus, power consumption of the display device 10 can be reduced.
  • a conductor 301 a and a conductor 301 b are embedded in the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .
  • the conductor 301 a is electrically connected to one of a source and a drain of the transistor 750
  • the conductor 301 b is electrically connected to the other of the source and the drain of the transistor 750 .
  • the top surfaces of the conductor 301 a and the conductor 301 b and the top surface of the insulator 281 can be substantially level with each other.
  • a conductor 311 , a conductor 313 , a conductor 331 , a capacitor 790 , a conductor 333 , and a conductor 335 are embedded in the insulator 361 .
  • the conductor 311 and the conductor 313 are electrically connected to the transistor 750 and have a function of a wiring.
  • the conductor 333 and the conductor 335 are electrically connected to the capacitor 790 .
  • the top surfaces of the conductor 331 , the conductor 333 , and the conductor 335 and the top surface of the insulator 361 can be substantially level with each other.
  • a conductor 341 , a conductor 343 , and a conductor 351 are embedded in the insulator 363 .
  • the top surface of the conductor 351 and the top surface of the insulator 363 can be substantially level with each other.
  • the insulator 405 , the insulator 407 , the insulator 409 , the insulator 411 , the insulator 421 , the insulator 214 , the insulator 280 , the insulator 274 , the insulator 281 , the insulator 361 , and the insulator 363 have a function of an interlayer film and may also have a function of a planarization film that covers unevenness thereunder.
  • the top surface of the insulator 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to have the increased evenness.
  • CMP chemical mechanical polishing
  • the capacitor 790 includes a lower electrode 321 and an upper electrode 325 .
  • An insulator 323 is provided between the lower electrode 321 and the upper electrode 325 . That is, the capacitor 790 has a stacked-layer structure in which the insulator 323 functioning as a dielectric is positioned between the pair of electrodes.
  • FIG. 10 illustrates an example in which the capacitor 790 is provided over the insulator 281 , the capacitor 790 may be provided over an insulator different from the insulator 281 .
  • the conductor 301 a , the conductor 301 b , and the conductor 305 are formed in the same layer.
  • the conductor 311 , the conductor 313 , and the conductor 317 and the lower electrode 321 are formed in the same layer.
  • the conductor 331 , the conductor 333 , the conductor 335 , and the conductor 337 are formed in the same layer.
  • the conductor 341 , the conductor 343 , and the conductor 347 are formed in the same layer.
  • the conductor 351 , the conductor 353 , the conductor 355 , and the conductor 357 are formed in the same layer. Forming a plurality of conductors in the same layer simplifies the manufacturing process of the display device 10 and thus the manufacturing cost of the display device 10 can be reduced. Note that these conductors may be formed in different layers or may contain different types of materials.
  • the display device 10 illustrated in FIG. 10 includes the display element 61 .
  • the display element 61 includes a conductor 772 , an EL layer 786 , and a conductor 788 .
  • the EL layer 786 contains an organic compound or an inorganic compound such as quantum dots.
  • Examples of materials that can be used as an organic compound include a fluorescent material and a phosphorescent material.
  • Examples of materials that can be used as quantum dots include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material.
  • the conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductor 351 , the conductor 341 , the conductor 331 , the conductor 313 , and the conductor 301 b .
  • the conductor 772 is formed over the insulator 363 and has a function of a pixel electrode.
  • a material that transmits visible light or a material that reflects visible light can be used for the conductor 772 .
  • a light-transmitting material for example, an oxide material containing indium, zinc, tin, or the like is preferably used.
  • a reflective material for example, a material containing aluminum, silver, or the like is preferably used.
  • an optical member such as a polarizing member, a retardation member, or an anti-reflection member can be provided in the display device 10 as appropriate, for example.
  • a light-blocking layer 738 and an insulator 734 that is in contact with the light-blocking layer 738 are provided on the substrate 12 .
  • the light-blocking layer 738 has a function of blocking light emitted from adjacent regions.
  • the light-blocking layer 738 has a function of preventing external light from reaching the transistor 750 or the like.
  • an insulator 730 is provided over the insulator 363 .
  • the insulator 730 can cover part of the conductor 772 .
  • the display element 61 is a top-emission light-emitting element, which includes the conductor 788 having a light-transmitting property.
  • the light-blocking layer 738 is provided to include a region overlapping with the insulator 730 .
  • the light-blocking layer 738 is covered with the insulator 734 .
  • a space between the display element 61 and the insulator 734 is filled with a sealing layer 732 .
  • a component 778 is provided between the insulator 730 and the EL layer 786 . Moreover, the component 778 is provided between the insulator 730 and the insulator 734 .
  • FIG. 11 illustrates a variation example of the display device 10 illustrated in FIG. 10 .
  • the display device 10 illustrated in FIG. 11 is different from the display device 10 illustrated in FIG. 10 in that a coloring layer 736 is provided.
  • the coloring layer 736 is provided to include a region overlapping with the display element 61 .
  • Providing the coloring layer 736 can improve the color purity of light emitted from the display element 61 .
  • the display device 10 can display high-quality images.
  • all the light-emitting elements 61 for example, in the display device 10 can be light-emitting elements emitting white light; hence, the EL layers 786 are not necessarily formed separately for each color, leading to higher resolution of the display device 10 .
  • the display element 61 can have a micro-optical resonator (microcavity) structure.
  • light of predetermined colors e.g., RGB
  • the structure without a coloring layer can prevent light absorption by the coloring layer.
  • the display device 10 can display high-luminance images, and power consumption of the display device 10 can be reduced.
  • a structure without a coloring layer can be employed even when the EL layer 786 is formed into an island shape for each pixel or formed into a stripe shape for each pixel column, i.e., the EL layers 786 are formed separately for each color.
  • the luminance of the display device 10 can be, for example, 500 cd/m 2 or higher, preferably higher than or equal to 1000 cd/m 2 and lower than or equal to 10000 cd/m 2 , further preferably higher than or equal to 2000 cd/m 2 and lower than or equal to 5000 cd/m 2 .
  • FIG. 12 A , FIG. 12 B , and FIG. 12 C are a top view and cross-sectional views of the transistor 750 that can be used in the display device of one embodiment of the present invention, and the periphery of the transistor 750 .
  • the transistor 750 can be used in the display device of one embodiment of the present invention.
  • FIG. 12 A is the top view of the transistor 750 .
  • FIG. 12 B and FIG. 12 C are the cross-sectional views of the transistor 750 .
  • FIG. 12 B is a cross-sectional view taken along dashed-dotted line A 1 -A 2 in FIG. 12 A , which corresponds to a cross-sectional view of the transistor 750 in the channel length direction.
  • FIG. 12 C is a cross-sectional view taken along the dashed-dotted line A 3 -A 4 in FIG. 12 A , which corresponds to a cross-sectional view of the transistor 750 in the channel width direction. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 12 A .
  • the transistor 750 includes a metal oxide 230 a placed over a substrate (not illustrated); a metal oxide 230 b placed over the metal oxide 230 a ; a conductor 242 a and a conductor 242 b that are placed apart from each other over the metal oxide 230 b ; the insulator 280 that is placed over the conductor 242 a and the conductor 242 b and has an opening between the conductor 242 a and the conductor 242 b ; a conductor 260 placed in the opening; an insulator 250 placed between the conductor 260 and the metal oxide 230 b , the conductor 242 a , the conductor 242 b , and the insulator 280 ; and a metal oxide 230 c placed between the insulator 250 and the metal oxide 230 b , the conductor 242 a , the conductor 242 b , and the insulator 280 .
  • the top surface of the conductor 260 is substantially aligned with the top surfaces of the insulator 250 , the insulator 254 , the metal oxide 230 c , and the insulator 280 .
  • the metal oxide 230 a , the metal oxide 230 b , and the metal oxide 230 c may be collectively referred to as a metal oxide 230 .
  • the conductor 242 a and the conductor 242 b may be collectively referred to as a conductor 242 .
  • the side surfaces of the conductor 242 a and the conductor 242 b on the conductor 260 side are substantially perpendicular.
  • the transistor 750 illustrated in FIG. 12 is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductor 242 a and the conductor 242 b may range from 10° to 80°, preferably from 30° to 60°.
  • the side surfaces of the conductor 242 a and the conductor 242 b that face each other may have a plurality of surfaces.
  • the insulator 254 is preferably provided between the insulator 280 and the insulator 224 , the metal oxide 230 a , the metal oxide 230 b , the conductor 242 a , the conductor 242 b , and the metal oxide 230 c .
  • the insulator 254 is preferably in contact with the side surface of the metal oxide 230 c , the top surface and the side surface of the conductor 242 a , the top surface and the side surface of the conductor 242 b , the side surfaces of the metal oxide 230 a and the metal oxide 230 b , and the top surface of the insulator 224 .
  • the present invention is not limited thereto.
  • a two-layer structure of the metal oxide 230 b and the metal oxide 230 c or a stacked-layer structure of four or more layers may be employed.
  • the conductor 260 has a two-layer structure in the transistor 750 , the present invention is not limited thereto.
  • the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.
  • each of the metal oxide 230 a , the metal oxide 230 b , and the metal oxide 230 c may have a stacked-layer structure of two or more layers.
  • the metal oxide 230 c has a stacked-layer structure including a first metal oxide and a second metal oxide over the first metal oxide
  • the first metal oxide preferably has a composition similar to that of the metal oxide 230 b
  • the second metal oxide preferably has a composition similar to that of the metal oxide 230 a.
  • the conductor 260 functions as a gate electrode of the transistor and the conductor 242 a and the conductor 242 b function as a source electrode and a drain electrode.
  • the conductor 260 is formed to be embedded in the opening of the insulator 280 and the region between the conductor 242 a and the conductor 242 b .
  • the positions of the conductor 260 , the conductor 242 a , and the conductor 242 b with respect to the opening of the insulator 280 are selected in a self-aligned manner. That is, in the transistor 750 , the gate electrode can be placed between the source electrode and the drain electrode in a self-aligned manner.
  • the conductor 260 can be formed without an alignment margin, resulting in a reduction in the area occupied by the transistor 750 . Accordingly, the display apparatus can have higher resolution. In addition, the display apparatus can have a narrow bezel.
  • the conductor 260 preferably includes a conductor 260 a provided on the inner side of the insulator 250 and a conductor 260 b provided to be embedded on the inner side of the conductor 260 a.
  • the transistor 750 preferably includes the insulator 214 placed over the substrate (not illustrated); the insulator 216 placed over the insulator 214 ; a conductor 205 placed to be embedded in the insulator 216 ; the insulator 222 placed over the insulator 216 and the conductor 205 ; and the insulator 224 placed over the insulator 222 .
  • the metal oxide 230 a is preferably placed over the insulator 224 .
  • the insulator 274 and the insulator 281 functioning as interlayer films are preferably placed over the transistor 750 .
  • the insulator 274 is preferably placed in contact with the top surfaces of the conductor 260 , the insulator 250 , the insulator 254 , the metal oxide 230 c , and the insulator 280 .
  • the insulator 222 , the insulator 254 , and the insulator 274 preferably have a function of inhibiting diffusion of hydrogen (e.g., a hydrogen atom, a hydrogen molecule, or the like).
  • hydrogen e.g., a hydrogen atom, a hydrogen molecule, or the like.
  • the insulator 222 , the insulator 254 , and the insulator 274 preferably have a lower hydrogen permeability than the insulator 224 , the insulator 250 , and the insulator 280 .
  • the insulator 222 and the insulator 254 preferably have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule).
  • the insulator 222 and the insulator 254 preferably have a lower oxygen permeability than the insulator 224 , the insulator 250 , and the insulator 280 .
  • the insulator 224 , the metal oxide 230 , and the insulator 250 are separated from the insulator 280 and the insulator 281 by the insulator 254 and the insulator 274 . This can inhibit entry of excess oxygen or impurities such as hydrogen contained in the insulator 280 and the insulator 281 into the insulator 224 , the metal oxide 230 a , the metal oxide 230 b , and the insulator 250 .
  • a conductor 240 (a conductor 240 a and a conductor 240 b ) that is electrically connected to the transistor 750 and functions as a plug is preferably provided.
  • an insulator 241 (an insulator 241 a and an insulator 241 b ) is provided in contact with the side surface of the conductor 240 functioning as a plug.
  • the insulator 241 is provided in contact with the inner wall of an opening in the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .
  • a structure may be employed in which a first conductor of the conductor 240 is provided in contact with the side surface of the insulator 241 and a second conductor of the conductor 240 is provided on the inner side of the first conductor.
  • the top surface of the conductor 240 and the top surface of the insulator 281 can be substantially level with each other.
  • the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked in the transistor 750 , the present invention is not limited thereto.
  • the conductor 240 may have a single-layer structure or a stacked-layer structure of three or more layers. In the case where a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 230 including the channel formation region (the metal oxide 230 a , the metal oxide 230 b , and the metal oxide 230 c ).
  • an oxide semiconductor a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more as the metal oxide to be the channel formation region of the metal oxide 230 .
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains indium (In) and zinc (Zn).
  • an element M is preferably contained.
  • the element M one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co) can be used.
  • the element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn).
  • the element M preferably contains one or both of Ga and Sn.
  • the metal oxide 230 b may have a smaller thickness in a region not overlapping with the conductor 242 than in a region overlapping with the conductor 242 .
  • the thin region is formed when part of the top surface of the metal oxide 230 b is removed at the time of forming the conductor 242 a and the conductor 242 b .
  • a conductive film to be the conductor 242 is formed, a low-resistance region is sometimes formed on the top surface of the metal oxide 230 b in the vicinity of the interface with the conductive film. Removing the low-resistance region positioned between the conductor 242 a and the conductor 242 b on the top surface of the metal oxide 230 b in this manner can prevent formation of the channel in the region.
  • a display device that includes small-size transistors and has high resolution can be provided.
  • a display device that includes a transistor with a high on-state current and has high luminance can be provided.
  • a display device that includes a transistor operating at high speed and thus operates at high speed can be provided.
  • a display device that includes a transistor having stable electrical characteristics and is highly reliable can be provided.
  • a display device that includes a transistor with a low off-state current and has low power consumption can be provided.
  • transistor 750 that can be used in the display apparatus of one embodiment of the present invention is described in detail.
  • the conductor 205 is placed to include a region overlapping with the metal oxide 230 and the conductor 260 . Furthermore, the conductor 205 is preferably provided to be embedded in the insulator 216 .
  • the conductor 205 includes the conductors 205 a , 205 b , and 205 c .
  • the conductor 205 a is provided in contact with the bottom surface and the side wall of the opening provided in the insulator 216 .
  • the conductor 205 b is provided to be embedded in a recessed portion formed by the conductor 205 a .
  • the level of the top surface of the conductor 205 b is lower than the levels of the top surfaces of the conductor 205 a and the insulator 216 .
  • the conductor 205 c is provided in contact with the top surface of the conductor 205 b and the side surface of the conductor 205 a .
  • the top surface of the conductor 205 c is substantially level with the top surfaces of the conductor 205 a and the insulator 216 . That is, the conductor 205 b is surrounded by the conductor 205 a and the conductor 205 c.
  • the conductor 205 a and the conductor 205 c are preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N 2 O, NO, and NO 2 ), and a copper atom.
  • the conductor 205 a and the conductor 205 c are preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule).
  • the conductors 205 a and 205 c are formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor 205 b can be prevented from diffusing into the metal oxide 230 through the insulator 224 and the like.
  • the conductors 205 a and 205 c are formed using a conductive material having a function of inhibiting diffusion of oxygen, the conductivity of the conductor 205 b can be inhibited from being lowered because of oxidation.
  • the conductive material having a function of inhibiting diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductor 205 a may be a single layer or a stacked layer of the above conductive materials.
  • titanium nitride may be used for the conductor 205 a.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205 b .
  • tungsten may be used for the conductor 205 b.
  • the conductor 260 sometimes functions as a first gate (also referred to as top gate) electrode.
  • the conductor 205 sometimes functions as a second gate (also referred to as bottom gate) electrode.
  • V th of the transistor 750 can be controlled.
  • V th of the transistor 750 can be higher than 0 V and the off-state current can be reduced.
  • a drain current at the time when a potential applied to the conductor 260 is 0 V can be lower in the case where a negative potential is applied to the conductor 205 than in the case where the negative potential is not applied to the conductor 205 .
  • the conductor 205 is preferably provided to be larger than the channel formation region in the metal oxide 230 .
  • the conductor 205 and the conductor 260 preferably overlap with each other with the insulator positioned therebetween, in a region on the outer side of the side surface of the metal oxide 230 in the channel width direction.
  • the channel formation region in the metal oxide 230 can be electrically surrounded by electric fields of the conductor 260 functioning as the first gate electrode and electric fields of the conductor 205 functioning as the second gate electrode.
  • the conductor 205 extends to function as a wiring as well.
  • a structure in which a conductor functioning as a wiring is provided below the conductor 205 may be employed.
  • the insulator 214 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water and hydrogen to the transistor 750 from the substrate side. Accordingly, it is preferable to use, for the insulator 214 , an insulating material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N 2 O, NO, and NO 2 ), and a copper atom (an insulating material through which the above impurities are less likely to pass). Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (an insulating material through which the oxygen is less likely to pass).
  • an insulating material having a function of inhibiting diffusion of oxygen e.g., at least one of an oxygen atom and an oxygen molecule
  • aluminum oxide or silicon nitride is preferably used for the insulator 214 . Accordingly, it is possible to inhibit diffusion of impurities such as water and hydrogen to the transistor 750 side from the substrate side through the insulator 214 . Alternatively, it is possible to inhibit diffusion of oxygen contained in the insulator 224 and the like to the substrate side through the insulator 214 .
  • each of the insulators 216 , 280 , and 281 functioning as an interlayer film is preferably lower than that of the insulator 214 .
  • the parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like may be used as appropriate.
  • the insulators 222 and 224 have a function as a gate insulator.
  • the insulator 224 in contact with the metal oxide 230 preferably releases oxygen by heating.
  • oxygen that is released by heating is referred to as excess oxygen in some cases.
  • silicon oxide, silicon oxynitride, or the like can be used as appropriate for the insulator 224 .
  • oxygen vacancies in the metal oxide 230 can be reduced, leading to improved reliability of the transistor 750 .
  • an oxide material that releases part of oxygen by heating is preferably used for the insulator 224 .
  • An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0 ⁇ 10 18 atoms/cm 3 , preferably greater than or equal to 1.0 ⁇ 10 19 atoms/cm 3 , further preferably greater than or equal to 2.0 ⁇ 10 19 atoms/cm 3 or greater than or equal to 3.0 ⁇ 10 20 atoms/cm 3 in thermal desorption spectroscopy (TDS) analysis.
  • TDS thermal desorption spectroscopy
  • the temperature of the film surface in the TDS analysis is preferably in the range of 100° C. to 700° C. or 100° C. to 400° C.
  • the insulator 224 is sometimes thinner in a region overlapping with neither the insulator 254 nor the metal oxide 230 b than in the other regions.
  • the region overlapping with neither the insulator 254 nor the metal oxide 230 b preferably has a thickness with which the above oxygen can be adequately diffused.
  • the insulator 222 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water and hydrogen into the transistor 750 from the substrate side.
  • the insulator 222 preferably has a lower hydrogen permeability than the insulator 224 .
  • the insulator 222 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (it is preferable that the above oxygen be less likely to pass through the insulator 222 ).
  • the insulator 222 preferably has a lower oxygen permeability than the insulator 224 .
  • the insulator 222 preferably has a function of inhibiting diffusion of oxygen and impurities, in which case oxygen contained in the metal oxide 230 can be prevented from diffusing to the substrate side.
  • the conductor 205 can be inhibited from reacting with oxygen contained in the insulator 224 or the metal oxide 230 .
  • an insulator containing an oxide of aluminum and/or an oxide of hafnium which are insulating materials, is preferably used.
  • the insulator containing an oxide of aluminum and/or an oxide of hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 222 formed using such a material functions as a layer inhibiting oxygen release from the metal oxide 230 and entry of impurities such as hydrogen into the metal oxide 230 from the periphery of the transistor 750 .
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators, for example.
  • these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 may be a single layer or a stacked layer using an insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • the insulators 222 and 224 may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. For example, an insulator similar to the insulator 224 may be provided below the insulator 222 .
  • the metal oxide 230 includes the metal oxide 230 a , the metal oxide 230 b over the metal oxide 230 a , and the metal oxide 230 c over the metal oxide 230 b .
  • the metal oxide 230 includes the metal oxide 230 a under the metal oxide 230 b , it is possible to inhibit diffusion of impurities into the metal oxide 230 b from the components formed below the metal oxide 230 a .
  • the metal oxide 230 includes the metal oxide 230 c over the metal oxide 230 b , it is possible to inhibit diffusion of impurities into the metal oxide 230 b from the components formed above the metal oxide 230 c.
  • the metal oxide 230 preferably has a stacked-layer structure of a plurality of oxide layers that differ in the atomic ratio of metal atoms.
  • the proportion of the number of atoms of the element M contained in the metal oxide 230 a to the number of atoms of all elements that constitute the metal oxide 230 a is preferably higher than the proportion of the number of atoms of the element M contained in the metal oxide 230 b to the number of atoms of all elements that constitute the metal oxide 230 b .
  • the atomic ratio of the element Mto In in the metal oxide 230 a is preferably higher than the atomic ratio of the element M to In in the metal oxide 230 b .
  • a metal oxide that can be used as the metal oxide 230 a or the metal oxide 230 b can be used as the metal oxide 230 c.
  • the energy of the conduction band minimum of each of the metal oxide 230 a and the metal oxide 230 c is preferably higher than that of the metal oxide 230 b .
  • the electron affinity of each of the metal oxide 230 a and the metal oxide 230 c is preferably smaller than that of the metal oxide 230 b .
  • a metal oxide that can be used as the metal oxide 230 a is preferably used as the metal oxide 230 c .
  • the proportion of the number of atoms of the element M contained in the metal oxide 230 c to the number of atoms of all elements that constitute the metal oxide 230 c is preferably higher than the proportion of the number of atoms of the element M contained in the metal oxide 230 b to the number of atoms of all elements that constitute the metal oxide 230 b .
  • the atomic ratio of the element M to In in the metal oxide 230 c is preferably higher than the atomic ratio of the element M to In in the metal oxide 230 b.
  • the energy level of the conduction band minimum gently changes at junction portions between the metal oxide 230 a , the metal oxide 230 b , and the metal oxide 230 c .
  • the energy level of the conduction band minimum at junction portions between the metal oxide 230 a , the metal oxide 230 b , and the metal oxide 230 c continuously changes or is continuously connected. This can be achieved by decreasing the density of defect states in a mixed layer formed at the interface between the metal oxide 230 a and the metal oxide 230 b and the interface between the metal oxide 230 b and the metal oxide 230 c.
  • the metal oxide 230 a and the metal oxide 230 b or the metal oxide 230 b and the metal oxide 230 c contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed.
  • the metal oxide 230 b is an In—Ga—Zn oxide
  • an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like may be used as the metal oxide 230 a and the metal oxide 230 c .
  • the metal oxide 230 c may have a stacked-layer structure.
  • a stacked-layer structure of an In—Ga—Zn oxide and a Ga—Zn oxide over the In—Ga—Zn oxide or a stacked-layer structure of an In—Ga—Zn oxide and gallium oxide over the In—Ga—Zn oxide can be employed.
  • the metal oxide 230 c may have a stacked-layer structure of an In—Ga—Zn oxide and an oxide that does not contain In.
  • the metal oxide 230 b serves as a main carrier path.
  • the metal oxide 230 a and the metal oxide 230 c have the above structure, the density of defect states at the interface between the metal oxide 230 a and the metal oxide 230 b and the interface between the metal oxide 230 b and the metal oxide 230 c can be made low. This reduces the influence of interface scattering on carrier conduction, and the transistor 750 can have a high on-state current and high frequency characteristics.
  • the metal oxide 230 c has a stacked-layer structure, not only the effect of reducing the density of defect states at the interface between the metal oxide 230 b and the metal oxide 230 c , but also the effect of inhibiting diffusion of the constituent element of the metal oxide 230 c to the insulator 250 side can be expected.
  • the metal oxide 230 c has a stacked-layer structure in which the upper layer is an oxide that does not contain In, whereby the amount of In that would diffuse to the insulator 250 side can be reduced. Since the insulator 250 functions as a gate insulator, the transistor would show poor characteristics when In diffuses into the insulator 250 .
  • the metal oxide 230 c having a stacked-layer structure allows a highly reliable display apparatus to be provided.
  • the conductor 242 (the conductor 242 a and the conductor 242 b ) functioning as the source electrode and the drain electrode is provided over the metal oxide 230 b .
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.
  • Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that maintain their conductivity even when absorbing oxygen.
  • the oxygen concentration of the metal oxide 230 in the vicinity of the conductor 242 sometimes decreases.
  • a metal compound layer that contains the metal contained in the conductor 242 and the component of the metal oxide 230 is sometimes formed in the metal oxide 230 in the vicinity of the conductor 242 .
  • the carrier density of the region in the metal oxide 230 in the vicinity of the conductor 242 increases, and the region becomes a low-resistance region.
  • the region between the conductor 242 a and the conductor 242 b is formed to overlap with the opening of the insulator 280 . Accordingly, the conductor 260 can be formed in a self-aligned manner between the conductor 242 a and the conductor 242 b.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably placed in contact with the top surface of the metal oxide 230 c .
  • any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and porous silicon oxide can be used.
  • silicon oxide and silicon oxynitride are preferable because of their thermal stability.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • a metal oxide may be provided between the insulator 250 and the conductor 260 .
  • the metal oxide preferably inhibits oxygen diffusion from the insulator 250 into the conductor 260 . Accordingly, oxidation of the conductor 260 due to oxygen in the insulator 250 can be inhibited.
  • the metal oxide functions as part of the gate insulator in some cases. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250 , a metal oxide that is a high-k material with a high dielectric constant is preferably used as the metal oxide.
  • the gate insulator has a stacked-layer structure of the insulator 250 and the metal oxide, the stacked-layer structure can be thermally stable and have a high dielectric constant. Accordingly, a gate potential applied during operation of the transistor can be lowered while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.
  • EOT equivalent oxide thickness
  • a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), in particular.
  • FIG. 12 illustrates the conductor 260 having a two-layer structure
  • the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.
  • the conductor 260 a is preferably formed using the aforementioned conductor having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N 2 O, NO, and NO 2 ), and a copper atom.
  • impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N 2 O, NO, and NO 2 ), and a copper atom.
  • the conductor 260 a is preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule).
  • the conductivity of the conductor 260 b can be inhibited from being lowered because of oxidation due to oxygen contained in the insulator 250 .
  • a conductive material having a function of inhibiting oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 260 b .
  • the conductor 260 also functions as a wiring and thus is preferably formed using a conductor having high conductivity.
  • a conductive material containing tungsten, copper, or aluminum as its main component can be used.
  • the conductor 260 b may have a stacked-layer structure, for example, a stacked-layer structure of any of the above conductive materials and titanium or titanium nitride.
  • the side surface of the metal oxide 230 is covered with the conductor 260 in a region where the metal oxide 230 b does not overlap with the conductor 242 , that is, the channel formation region of the metal oxide 230 . Accordingly, electric fields of the conductor 260 functioning as the first gate electrode are likely to act on the side surface of the metal oxide 230 . Hence, the transistor 750 can have a higher on-state current and higher frequency characteristics.
  • the insulator 254 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water and hydrogen into the transistor 750 from the insulator 280 side.
  • the insulator 254 preferably has lower hydrogen permeability than the insulator 224 , for example.
  • the insulator 254 is preferably in contact with the side surface of the metal oxide 230 c , the top and side surfaces of the conductor 242 a , the top and side surfaces of the conductor 242 b , the side surfaces of the metal oxide 230 a and the metal oxide 230 b , and the top surface of the insulator 224 .
  • Such a structure can inhibit the entry of hydrogen contained in the insulator 280 into the metal oxide 230 through the top surfaces or the side surfaces of the conductor 242 a , the conductor 242 b , the metal oxide 230 a , the metal oxide 230 b , and the insulator 224 .
  • the insulator 254 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (it is preferable that the above oxygen be less likely to pass through the insulator 254 ).
  • the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224 .
  • the insulator 254 is preferably formed by a sputtering method.
  • oxygen can be added to the vicinity of a region of the insulator 224 which is in contact with the insulator 254 .
  • oxygen can be supplied from the region to the metal oxide 230 through the insulator 224 .
  • the insulator 254 having a function of inhibiting upward oxygen diffusion oxygen can be prevented from diffusing from the metal oxide 230 into the insulator 280 .
  • the insulator 222 having a function of inhibiting downward oxygen diffusion oxygen can be prevented from diffusing from the metal oxide 230 to the substrate side.
  • oxygen is supplied to the channel formation region of the metal oxide 230 . Accordingly, oxygen vacancies in the metal oxide 230 can be reduced, so that the transistor can be prevented from having normally-on characteristics.
  • an insulator containing an oxide of one or both of aluminum and hafnium is formed, for example.
  • the insulator containing an oxide of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 224 , the insulator 250 , and the metal oxide 230 are covered with the insulator 254 having a barrier property against hydrogen, whereby the insulator 280 is isolated from the insulator 224 , the metal oxide 230 , and the insulator 250 by the insulator 254 .
  • This can inhibit the entry of impurities such as hydrogen from the outside of the transistor 750 , resulting in favorable electrical characteristics and high reliability of the transistor 750 .
  • the insulator 280 is provided over the insulator 224 , the metal oxide 230 , and the conductor 242 with the insulator 254 therebetween.
  • the insulator 280 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferable because of their thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferably used, in which case a region containing oxygen released by heating can be easily formed.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced.
  • the top surface of the insulator 280 may be planarized.
  • the insulator 274 preferably functions as a barrier insulating film that inhibits entry of impurities such as water and hydrogen into the insulator 280 from the above.
  • the insulator 274 for example, the insulator that can be used as the insulator 214 , the insulator 254 , and the like can be used.
  • the insulator 281 functioning as an interlayer film is preferably provided over the insulator 274 .
  • the concentration of impurities such as water and hydrogen in the insulator 281 is preferably reduced.
  • the conductor 240 a and the conductor 240 b are placed in openings formed in the insulators 281 , 274 , 280 , and 254 .
  • the conductors 240 a and 240 b are provided to face each other with the conductor 260 therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be level with the top surface of the insulator 281 .
  • the insulator 241 a is provided in contact with the inner walls of the openings in the insulators 281 , 274 , 280 , and 254 , and a first conductor of the conductor 240 a is formed in contact with the side surface of the insulator 241 a .
  • the conductor 242 a is positioned on at least part of the bottom portion of the opening, and the conductor 240 a is in contact with the conductor 242 a .
  • the insulator 241 b is provided in contact with the inner walls of the openings in the insulators 281 , 274 , 280 , and 254 , and a first conductor of the conductor 240 b is formed in contact with the side surface of the insulator 241 b .
  • the conductor 242 b is positioned on at least part of the bottom portion of the opening, and the conductor 240 b is in contact with the conductor 242 b.
  • the conductors 240 a and 240 b are preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component.
  • the conductors 240 a and 240 b may each have a stacked-layer structure.
  • the aforementioned conductor having a function of inhibiting diffusion of impurities such as water and hydrogen is preferably used as the conductor in contact with the metal oxide 230 a , the metal oxide 230 b , the conductor 242 , the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .
  • the metal oxide 230 a the metal oxide 230 b
  • the conductor 242 the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • the conductive material having a function of inhibiting diffusion of impurities such as water and hydrogen can be used as a single layer or stacked layers.
  • the use of the conductive material can inhibit oxygen added to the insulator 280 from being absorbed by the conductor 240 a and the conductor 240 b . Moreover, impurities such as water and hydrogen can be inhibited from entering the metal oxide 230 through the conductor 240 a and the conductor 240 b from a layer above the insulator 281 .
  • the insulator that can be used as the insulator 254 or the like can be used, for example. Since the insulator 241 a and the insulator 241 b are provided in contact with the insulator 254 , impurities such as water and hydrogen in the insulator 280 or the like can be inhibited from entering the metal oxide 230 through the conductor 240 a and the conductor 240 b . Furthermore, oxygen contained in the insulator 280 can be inhibited from being absorbed by the conductor 240 a and the conductor 240 b.
  • a conductor functioning as a wiring may be provided in contact with the top surfaces of the conductors 240 a and 240 b .
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used.
  • the conductor may have a stacked-layer structure and may be a stack of any of the above conductive materials and titanium or titanium nitride. Note that the conductor may be formed to be embedded in an opening provided in an insulator.
  • an insulator substrate As a substrate over which the transistor is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like and a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • Other examples include any of the above semiconductor substrates including an insulator region, e.g., a silicon on insulator (SOI) substrate.
  • SOI silicon on insulator
  • Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Other examples include a substrate including a metal nitride and a substrate including a metal oxide.
  • Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator.
  • these substrates provided with elements may be used.
  • Examples of the elements provided over the substrates include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.
  • an insulator examples include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide, each of which has an insulating property.
  • a problem such as generation of a leakage current may arise because of a thinner gate insulator.
  • a high-k material is used for the insulator functioning as a gate insulator, the voltage at the time of operation of the transistor can be reduced while the physical thickness is maintained.
  • a material with a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • a material is preferably selected depending on the function of an insulator.
  • Examples of the insulator having a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.
  • Examples of the insulator having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.
  • insulators having a function of inhibiting the passage of oxygen and impurities such as hydrogen e.g., the insulator 214 , the insulator 222 , the insulator 254 , and the insulator 274 ).
  • the electrical characteristics of the transistor can be stable.
  • An insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen can be formed to have a single layer or a stacked layer including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • An insulator functioning as a gate insulator preferably includes a region containing oxygen released by heating.
  • a structure where silicon oxide or silicon oxynitride that includes a region containing oxygen released by heating is provided in contact with the metal oxide 230 can compensate for oxygen vacancies in the metal oxide 230 .
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.
  • Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that maintain their conductivity even when absorbing oxygen.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductors formed using any of the above materials may be stacked.
  • a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed.
  • a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed.
  • a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • the conductor functioning as the gate electrode preferably employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen.
  • the conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide where the channel is formed is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide where the channel is formed.
  • a conductive material containing any of the above metal elements and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used.
  • Indium gallium zinc oxide containing nitrogen may be used.
  • FIG. 13 A shows the classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes a completely amorphous structure.
  • the term “Crystalline” includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) structures. Note that the term “Crystalline” excludes single crystal, poly crystal, and completely amorphous structures.
  • the term “Crystal” includes single crystal and poly crystal structures.
  • the structures in the thick frame in FIG. 13 A are in an intermediate state between “Amorphous” and “Crystal”, and belong to a new crystalline phase. That is, these structures are completely different from “Amorphous”, which is energetically unstable, or “Crystal”.
  • FIG. 13 B shows an XRD spectrum, which is obtained by grazing-incidence XRD (GIXD) measurement, of a CAAC-IGZO film classified into “Crystalline”.
  • a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum that is shown in FIG. 13 B and obtained by GIXD measurement is hereinafter simply referred to as an XRD spectrum.
  • the CAAC-IGZO film in FIG. 13 B has a thickness of 500 nm.
  • the horizontal axis represents 2 ⁇ [deg.], and the vertical axis represents intensity [a.u.].
  • a clear peak indicating crystallinity is observed in the XRD spectrum of the CAAC-IGZO film.
  • a peak indicating c-axis alignment is observed at 2 ⁇ of around 31° in the XRD spectrum of the CAAC-IGZO film.
  • the peak at 2 ⁇ of around 31° is asymmetric with the angle at which the peak intensity is observed as the axis.
  • a crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern).
  • FIG. 13 C shows a diffraction pattern of the CAAC-IGZO film.
  • FIG. 13 C shows a diffraction pattern obtained by the NBED method in which an electron beam is incident in the direction parallel to the substrate.
  • the nanobeam electron diffraction method electron diffraction is performed with a probe diameter of 1 nm.
  • Oxide semiconductors might be classified in a manner different from the one in FIG. 13 A when classified in terms of the crystal structure.
  • Oxide semiconductors are classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor, for example.
  • Examples of the non-single-crystal oxide semiconductor include the above-described CAAC-OS and nc-OS.
  • Other examples of the non-single-crystal oxide semiconductor include a polycrystalline oxide semiconductor, an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS CAAC-OS
  • the CAAC-OS is an oxide semiconductor that has a plurality of crystal regions each of which has c-axis alignment in a particular direction.
  • the particular direction refers to the film thickness direction of a CAAC-OS film, the normal direction of the surface where the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region refers to a region having a periodic atomic arrangement. When an atomic arrangement is regarded as a lattice arrangement, the crystal region also refers to a region with a uniform lattice arrangement.
  • the CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region has distortion in some cases.
  • distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected.
  • the CAAC-OS is an oxide semiconductor having c-axis alignment and having no clear alignment in the a-b plane direction.
  • each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be approximately several tens of nanometers.
  • the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M, Zn) layer) are stacked.
  • Indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M, Zn) layer.
  • the element M may be contained in the In layer.
  • Zn may be contained in the In layer.
  • Such a layered structure is observed as a lattice image in a high-resolution TEM image, for example.
  • a peak indicating c-axis alignment is detected at 2 ⁇ of 31° or around 31°.
  • the position of the peak indicating c-axis alignment may change depending on the kind, composition, or the like of the metal element contained in the CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that one spot and another spot are observed point-symmetrically with a spot of the incident electron beam passing through a sample (also referred to as a direct spot) as the symmetric center.
  • a lattice arrangement in the crystal region is basically a hexagonal lattice arrangement; however, a unit lattice is not always a regular hexagon and is a non-regular hexagon in some cases.
  • a pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear grain boundary cannot be observed even in the vicinity of the distortion in the CAAC-OS. That is, formation of a grain boundary is inhibited by the distortion of a lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to a low arrangement density of oxygen atoms in the a-b plane direction, an interatomic bond distance changed by substitution of a metal atom, or the like.
  • a crystal structure in which a clear grain boundary is observed is what is called a polycrystal structure. It is highly probable that the grain boundary becomes a recombination center and traps carriers and thus decreases the on-state current and field-effect mobility of a transistor, for example.
  • the CAAC-OS in which no clear grain boundary is observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
  • Zn is preferably contained to form the CAAC-OS.
  • an In—Zn oxide and an In—Ga—Zn oxide are suitable because they can inhibit generation of a grain boundary as compared with an In oxide.
  • the CAAC-OS is an oxide semiconductor with high crystallinity in which no clear grain boundary is observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor; thus, the CAAC-OS can be referred to as an oxide semiconductor having a small amount of impurities or defects (e.g., oxygen vacancies). Therefore, an oxide semiconductor including the CAAC-OS is physically stable. Accordingly, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperatures in the manufacturing process (i.e., thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.
  • nc-OS In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement.
  • the nc-OS includes a fine crystal.
  • the size of the fine crystal is, for example, greater than or equal to 1 nm and less than or equal to 10 nm, particularly greater than or equal to 1 nm and less than or equal to 3 nm; thus, the fine crystal is also referred to as a nanocrystal.
  • the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on the analysis method. For example, when an nc-OS film is subjected to structural analysis by out-of-plane XRD measurement with an XRD apparatus using ⁇ /2 ⁇ scanning, a peak indicating crystallinity is not observed.
  • a diffraction pattern like a halo pattern is observed when the nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than the diameter of a nanocrystal (e.g., larger than or equal to 50 nm).
  • electron diffraction also referred to as selected-area electron diffraction
  • a plurality of spots in a ring-like region with a direct spot as the center are observed in a nanobeam electron diffraction pattern of the nc-OS film obtained using an electron beam with a probe diameter nearly equal to or smaller than the diameter of a nanocrystal (e.g., larger than or equal to 1 nm and smaller than or equal to 30 nm).
  • the a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS includes a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Moreover, the a-like OS has higher hydrogen concentration than the nc-OS and the CAAC-OS.
  • CAC-OS relates to the material composition.
  • the CAC-OS refers to one composition of a material in which elements constituting a metal oxide are unevenly distributed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size, for example.
  • a state in which one or more metal elements are unevenly distributed and regions including the metal element(s) are mixed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size in a metal oxide is hereinafter referred to as a mosaic pattern or a patch-like pattern.
  • the CAC-OS has a composition in which materials are separated into a first region and a second region to form a mosaic pattern, and the first regions are distributed in the film.
  • This composition is hereinafter also referred to as a cloud-like composition. That is, the CAC-OS is a composite metal oxide having a composition in which the first regions and the second regions are mixed.
  • the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted with [In], [Ga], and [Zn], respectively.
  • the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than that in the composition of the CAC-OS film.
  • the second region of the CAC-OS in the In—Ga—Zn oxide has [Ga] higher than that in the composition of the CAC-OS film.
  • the first region has higher [In] and lower [Ga] than the second region.
  • the second region has higher [Ga] and lower [In] than the first region.
  • the first region includes indium oxide, indium zinc oxide, or the like as its main component.
  • the second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component.
  • the second region can be referred to as a region containing Ga as its main component.
  • the CAC-OS in the In—Ga—Zn oxide has a structure in which the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed.
  • a switching function (on/off switching function) can be given to the CAC-OS owing to the complementary action of the conductivity derived from the first region and the insulating property derived from the second region. That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, a high on-state current (I on), high field-effect mobility ( 1 . 1 ), and favorable switching operation can be achieved.
  • I on on-state current
  • 1 . 1 high field-effect mobility
  • An oxide semiconductor can have any of various structures that show various different properties. Two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, the CAC-OS, an nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.
  • the transistor When the oxide semiconductor is used for a transistor, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.
  • an oxide semiconductor having a low carrier concentration is preferably used for the transistor.
  • the carrier concentration of an oxide semiconductor is lower than or equal to 1 ⁇ 10 17 cm′, preferably lower than or equal to 1 ⁇ 10 15 cm ⁇ 3 , further preferably lower than or equal to 1 ⁇ 10 13 cm ⁇ 3 , still further preferably lower than or equal to 1 ⁇ 10 11 cm′, yet further preferably lower than 1 ⁇ 10 10 cm ⁇ 3 , and higher than or equal to 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the impurity concentration in the oxide semiconductor film is reduced so that the density of defect states can be reduced.
  • a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state.
  • an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.
  • a transistor whose channel formation region is formed in an oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.
  • the impurity concentration in the oxide semiconductor In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, the impurity concentration in a film that is adjacent to the oxide semiconductor is preferably reduced.
  • impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.
  • the concentration of each of silicon and carbon in the oxide semiconductor and in the vicinity of an interface with the oxide semiconductor is set lower than or equal to 2 ⁇ 10 18 atoms/cm 3 , preferably lower than or equal to 2 ⁇ 10 17 atoms/cm 3 .
  • the oxide semiconductor contains alkali metal or alkaline earth metal
  • defect states are formed and carriers are generated in some cases.
  • a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics.
  • the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor which is obtained by SIMS, is set lower than or equal to 1 ⁇ 10 18 atoms/cm 3 , preferably lower than or equal to 2 ⁇ 10 16 atoms/cm 3 .
  • the concentration of nitrogen in the oxide semiconductor is set lower than 5 ⁇ 10 19 atoms/cm 3 , preferably lower than or equal to 5 ⁇ 10 18 atoms/cm 3 , further preferably lower than or equal to 1 ⁇ 10 18 atoms/cm 3 , still further preferably lower than or equal to 5 ⁇ 10 17 atoms/cm 3 .
  • Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, some hydrogen may be bonded to oxygen bonded to a metal atom and generate an electron serving as a carrier. Thus, a transistor including an oxide semiconductor that contains hydrogen tends to have normally-on characteristics. For this reason, hydrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the hydrogen concentration in the oxide semiconductor which is obtained by SIMS, is set lower than 1 ⁇ 10 20 atoms/cm 3 , preferably lower than 1 ⁇ 10 19 atoms/cm 3 , further preferably lower than 5 ⁇ 10 18 atoms/cm 3 , still further preferably lower than 1 ⁇ 10 18 atoms/cm 3 .
  • the transistor When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.
  • An EL layer 786 included in the display element 61 can be formed of a plurality of layers such as a layer 4420 , a light-emitting layer 4411 , and a layer 4430 , as illustrated in FIG. 14 A .
  • the layer 4420 can include, for example, a layer containing a substance with a high electron-injection property (an electron-injection layer) and a layer containing a substance with a high electron-transport property (an electron-transport layer).
  • the light-emitting layer 4411 contains a light-emitting compound, for example.
  • the layer 4430 can include, for example, a layer containing a substance with a high hole-injection property (a hole-injection layer) and a layer containing a substance with a high hole-transport property (a hole-transport layer).
  • the structure including the layer 4420 , the light-emitting layer 4411 , and the layer 4430 , which are provided between a pair of electrodes, can serve as a single light-emitting unit, and the structure in FIG. 14 A is referred to as a single structure in this specification.
  • FIG. 14 B shows a modification example of the EL layer 786 included in the display element 61 illustrated in FIG. 14 A .
  • the display element 61 illustrated in FIG. 14 B includes a layer 4430 - 1 over the conductor 772 , a layer 4430 - 2 over the layer 4430 - 1 , the light-emitting layer 4411 over the layer 4430 - 2 , a layer 4420 - 1 over the light-emitting layer 4411 , a layer 4420 - 2 over the layer 4420 - 1 , and the conductor 788 over the layer 4420 - 2 .
  • the layer 4430 - 1 functions as a hole-injection layer
  • the layer 4430 - 2 functions as a hole-transport layer
  • the layer 4420 - 1 functions as an electron-transport layer
  • the layer 4420 - 2 functions as an electron-injection layer
  • the layer 4430 - 1 functions as an electron-injection layer
  • the layer 4430 - 2 functions as an electron-transport layer
  • the layer 4420 - 1 functions as a hole-transport layer
  • the layer 4420 - 2 functions as the hole-injection layer.
  • the structure in which a plurality of light-emitting layers (light-emitting layers 4411 , 4412 , and 4413 ) are provided between the layer 4420 and the layer 4430 as illustrated in FIG. 14 C is a variation of the single structure.
  • FIG. 14 D A structure in which a plurality of light-emitting units (EL layers 786 a and 786 b ) are connected in series with an intermediate layer (a charge-generation layer) 4440 therebetween as illustrated in FIG. 14 D is referred to as a tandem structure in this specification. Note that in this specification and the like, the structure illustrated in FIG. 14 D is referred to as a tandem structure; however, without being limited to this, a tandem structure may be referred to as a stack structure, for example. The tandem structure enables a light-emitting element capable of high-luminance light emission.
  • the layer 4420 and the layer 4430 may each have a stacked-layer structure of two or more layers as illustrated in FIG. 14 B .
  • the emission color of the display element 61 can be red, green, blue, cyan, magenta, yellow, white, or the like depending on the material that constitutes the EL layer 786 . Furthermore, the color purity can be further increased when the display element 61 has a microcavity structure.
  • the light-emitting element that emits white light preferably contains two or more kinds of light-emitting substances in the light-emitting layer. To obtain white light emission, two or more light-emitting substances may be selected so that their emission colors are complementary.
  • the light-emitting layer preferably contains two or more light-emitting substances that emit light of R (red), G (green), B (blue), Y (yellow), 0 (orange), and the like.
  • the light-emitting layer preferably contains two or more light-emitting substances that each emit light containing two or more spectral components of R, G, and B.
  • FIG. 15 A is a schematic top view of display elements 61 _R, 61 _G, and 61 _B which can be used for the display element 61 .
  • the display element 61 _R is a light-emitting element that exhibits red
  • the display element 61 _G is a light-emitting element that exhibits green
  • the display element 61 _B is a light-emitting element that exhibits blue.
  • light-emitting regions of the light-emitting elements are denoted by R, G, and B to easily differentiate the light-emitting elements.
  • the structure illustrated in FIG. 15 A may be referred to as an SBS (Side By Side) structure.
  • SBS Side By Side
  • the structure illustrated in FIG. 15 A has three colors, red (R), green (G), and blue (B), one embodiment of the present invention is not limited thereto. For example, the structure may have four or more colors.
  • the display elements 61 _R, 61 _G, and 61 _B are arranged in a matrix.
  • FIG. 15 A shows what is called a stripe arrangement, in which the light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited thereto; another arrangement method such as a delta arrangement or a zigzag arrangement may be used, or a PenTile arrangement may also be used.
  • an organic EL device such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used.
  • a light-emitting substance contained in the EL element a substance that emits fluorescence (a fluorescent material), a substance that emits phosphorescence (a phosphorescent material), an inorganic compound (e.g., a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (a thermally activated delayed fluorescent (TADF) material) can be given, for example.
  • FIG. 15 B is a cross-sectional schematic view taken along the dashed-dotted line A 1 -A 2 in FIG. 15 A .
  • FIG. 15 B illustrates cross sections of the display elements 61 _R, 61 _G, and 61 _B.
  • Each of the display elements 61 _R, 61 _G, and 61 _B is provided over a substrate 751 and includes a conductor 772 functioning as a pixel electrode and a conductor 788 functioning as a common electrode.
  • the display element 61 _R includes an EL layer 786 R between the conductor 772 and the conductor 788 .
  • the EL layer 786 R contains at least a light-emitting organic compound that emits light with a peak in a red wavelength range.
  • An EL layer 786 G included in the display element 61 _G contains at least a light-emitting organic compound that emits light with a peak in a green wavelength range.
  • An EL layer 786 B included in the display element 61 _B contains at least a light-emitting organic compound that emits light with a peak in a blue wavelength range
  • the EL layer 786 R, the EL layer 786 G, and the EL layer 786 B may each include one or more of an electron-injection layer, an electron-transport layer, a hole-injection layer, and a hole-transport layer in addition to the layer containing a light-emitting organic compound (the light-emitting layer).
  • the conductor 772 is provided for each of the light-emitting elements.
  • the conductor 788 is provided as a continuous layer shared by the light-emitting elements.
  • a conductive film that transmits visible light is used for either the conductor 772 or the conductor 788 functioning as a common electrode, and a reflective conductive film is used for the other.
  • the use of the light-transmitting conductor 772 and the reflective conductor 788 offers a bottom-emission display device, whereas the use of the reflective conductor 772 and the light-transmitting conductor 788 offers a top-emission display device. Note that when both the conductor 772 and the conductor 788 have a light-transmitting property, a dual-emission display device can be obtained.
  • An insulating layer 755 is provided to cover end portions of the conductor 772 . End portions of the insulating layer 755 are preferably tapered.
  • the EL layer 786 R, the EL layer 786 G, and the EL layer 786 B each include a region in contact with a top surface of the conductor 772 and a region in contact with a surface of the insulating layer 755 . End portions of the EL layer 786 R, the EL layer 786 G, and the EL layer 786 B are positioned over the insulating layer 755 .
  • the EL layer 786 R, the EL layer 786 G, and the EL layer 786 B are preferably provided so as not to be in contact with each other. This suitably prevents unintentional light emission (also referred to as crosstalk) from being caused by a current flowing through two adjacent EL layers. As a result, the contrast can be increased to achieve a display device with high display quality.
  • the EL layer 786 R, the EL layer 786 G, and the EL layer 786 B can be formed separately by a vacuum evaporation method or the like using a shadow mask such as a metal mask. Alternatively, these layers may be formed separately by a photolithography method. The use of the photolithography method achieves a display device with high resolution, which is difficult to obtain in the case of using a metal mask.
  • a protective layer 756 is provided to cover the display elements 61 _R, 61 _G, and 61 _B.
  • the protective layer 756 has a function of preventing diffusion of impurities such as water into the light-emitting elements from above.
  • the protective layer 756 can have, for example, a single-layer structure or a stacked-layer structure at least including an inorganic insulating film.
  • an oxide film or a nitride film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or a hafnium oxide film can be given.
  • a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 756 .
  • the protective layer 756 may be formed by an ALD method, a CVD method, or a sputtering method. Although the protective layer 756 includes an inorganic insulating film in this example, one embodiment of the present invention is not limited thereto. For example, the protective layer 756 may have a stacked-layer structure of an inorganic insulating film and an organic insulating film.
  • FIG. 15 C illustrates an example different from the above example.
  • a display element 61 _W emitting white light is provided.
  • the display element 61 _W includes an EL layer 786 W emitting white light between the conductor 772 and the conductor 788 .
  • the EL layer 786 W can have, for example, a structure in which two or more light-emitting layers that are selected so as to emit light of complementary colors are stacked. It is also possible to use a stacked EL layer, i.e., an EL layer having what is called a tandem structure, in which a charge-generation layer is provided between light-emitting layers.
  • the tandem structure enables a light-emitting element capable of high-luminance light emission.
  • FIG. 15 C illustrates three display elements 61 _W side by side.
  • a coloring layer 757 R is provided above the left display element 61 _W.
  • the coloring layer 757 R functions as a band path filter transmitting red light.
  • a coloring layer 757 G transmitting green light is provided above the middle display element 61 _W, and a coloring layer 757 B transmitting blue light is provided above the right display element 61 W.
  • the display device can display color images.
  • the EL layer 786 W and the conductor 788 are each separated between two adjacent display elements 61 W. This can suitably prevent unintentional light emission from being caused by current flowing through the EL layers 786 W of the two adjacent display elements 61 _W.
  • the EL layer 786 W is a stacked EL element in which a charge-generation layer is provided between two light-emitting layers, the effect of crosstalk is more significant as the resolution increases, i.e., as the distance between adjacent pixels decreases, leading to lower contrast.
  • the above structure can achieve a display device having both high resolution and high contrast.
  • a photolithography method is preferably used for the separation of the EL layer 786 W and the separation of the conductor 788 . This can reduce the distance between light-emitting elements, achieving a display device with a higher aperture ratio than that formed using, for example, a shadow mask such as a metal mask.
  • a coloring layer is provided between the conductor 772 and the substrate 751 .
  • FIG. 15 D illustrates an example different from the above.
  • the insulating layer 755 is not provided between the display element 61 _R, the display element 61 _G, and the display element 61 _B in the structure in FIG. 15 D .
  • the display device can have a high aperture ratio.
  • the protective layer 756 covers side surfaces of the display element 61 _R, the display element 61 _G, and the display element 61 _B.
  • impurities typically, water
  • the top shapes of the conductor 772 , the EL layer 786 R, and the conductor 788 are substantially aligned with each other.
  • This structure can be formed in such a manner that the conductor 772 , the EL layer 786 R, and the conductor 788 are formed and collectively processed using a resist mask or the like.
  • the EL layer 786 R and the conductor 753 are processed using the conductor 788 as a mask, and thus this process can be called self-alignment patterning.
  • the display element 61 _R is described here, the display element 61 _G and the display element 61 _B can have the same structure.
  • a protective layer 758 is further provided over the protective layer 756 .
  • the protective layer 756 can be formed with an apparatus that can deposit a film with excellent coverage (typically, an ALD apparatus), and the protective layer 758 can be formed with an apparatus that can deposit a film with coverage inferior to that of the protective layer 756 (typically, a sputtering apparatus), whereby a space 759 can be provided between the protective layer 756 and the protective layer 758 .
  • the space 759 is positioned between the display element 61 _R and the display element 61 _G and between the display element 61 _G and the display element 61 _B.
  • the space 759 includes, for example, any one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, and krypton).
  • a gas used during the deposition of the protective layer 758 is sometimes included in the space 759 .
  • the protective layer 758 is deposited by a sputtering method, one or more of the above-described Group 18 elements may be included in the space 759 .
  • a gas can be identified with a gas chromatography method or the like.
  • a gas used in the sputtering is sometimes included in the protective layer 758 .
  • an element such as argon is sometimes detected when the protective layer 758 is analyzed by an energy dispersive X-ray analysis (EDX analysis) or the like.
  • the refractive index of the space 759 is lower than the refractive index of the protective layer 756 .
  • light emitted from the display element 61 _R, the display element 61 _G, or the display element 61 _B is reflected in an interface between the protective layer 756 and the space 759 .
  • light emitted from the display element 61 _R, the display element 61 _G, or the display element 61 _B can be inhibited from entering an adjacent pixel.
  • mixture of light of different colors can be inhibited, so that the image quality of the display device can be improved.
  • a region between the display element 61 _R and the display element 61 _G or a region between the display element 61 _G and the display element 61 _B (hereinafter simply referred to as a distance between the light-emitting elements) can be shortened.
  • the distance between the light-emitting elements can be less than or equal to 1 ⁇ m, preferably less than or equal to 500 nm, further preferably less than or equal to 200 nm, less than or equal to 100 nm, less than or equal to 90 nm, less than or equal to 70 nm, less than or equal to 50 nm, less than or equal to 30 nm, less than or equal to 20 nm, less than or equal to 15 nm, or 10 nm.
  • the display device includes a region in which an interval between the side surface of the display element 61 _R and the side surface of the display element 61 _G or an interval between the side surface of the display element 61 _G and the side surface of the display element 61 _B is less than or equal to 1 ⁇ m, preferably less than or equal to 0.5 ⁇ m (500 nm), further preferably less than or equal to 100 nm.
  • the structure illustrated in FIG. 15 D can be referred to as an air isolation structure.
  • the air isolation structure allows the light-emitting elements to be isolated from each other and color mixing of light or crosstalk between the light-emitting elements can be inhibited.
  • FIG. 16 A illustrates an example different from the above. Specifically, the structure illustrated in FIG. 16 A is different from the structure illustrated in FIG. 15 D in the structure of the substrate 751 .
  • a top surface of the substrate 751 is partly removed when the display element 61 _R, the display element 61 _G, and the display element 61 _B are processed, and a depressed portion is formed.
  • the protective layer 756 is formed in the depressed portion. In other words, in the cross-sectional view, a region is provided, in which the bottom surface of the protective layer 756 is positioned below the bottom surface of the conductor 772 .
  • impurities typically, water or the like
  • the depressed portion can be formed when impurities (also referred to as residue) that could be attached to the side surfaces of the display element 61 _R, the display element 61 _G, and the display element 61 _B in processing of the display elements are removed by e.g., wet etching.
  • the residue is removed, the side surfaces of the light-emitting elements are covered with the protective layer 756 , whereby a highly reliable display device can be provided.
  • FIG. 16 B illustrates an example different from the above.
  • the structure illustrated in FIG. 16 B includes an insulating layer 776 and a microlens array 777 in addition to the structure illustrated in FIG. 16 A .
  • the insulating layer 776 has a function of an adhesive layer. Note that when the refractive index of the insulating layer 776 is lower than the refractive index of the microlens array 777 , the microlens array 777 can condense light emitted from the display element 61 _R, the display element 61 _G, and the display element 61 _B. This can increase the light extraction efficiency of the display device.
  • curable adhesives e.g., a photocurable adhesive such as an ultraviolet curable adhesive, a reactive curable adhesive, a thermosetting adhesive, and an anaerobic adhesive
  • these adhesives include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a PVC (polyvinyl chloride) resin, a PVB (polyvinyl butyral) resin, and an EVA (ethylene vinyl acetate) resin.
  • a material with low moisture permeability such as an epoxy resin, is preferred.
  • a two-component-mixture-type resin may be used.
  • An adhesive sheet or the like may be used.
  • Table 1 shows specifications used for the estimation. Note that the distance between regions (2.64 ⁇ 7.92 ⁇ m), which is defined by the pixel size, is estimated to be 0.55 ⁇ m when the pixel arrangement is in RGB stripes.
  • FIG. 17 A illustrates a layout of a display device 10 A that can be formed over a 12-inch S 1 wafer serving as s substrate 100 A. From one 12-inch S 1 wafer, 72 display devices 10 A can be manufactured.
  • FIG. 17 A also shows a layout diagram of the display device 10 that can be fabricated over a substrate 100 B, which is a 5-inch rectangular S 1 wafer.
  • Two display devices 10 can be fabricated over the substrate 100 B, which is a 5-inch S 1 wafer.
  • FIG. 17 B is diagram illustrating a layout of the display device 10 fabricated over the substrate 100 B, which is a 5-inch S 1 wafer. As illustrated in FIG. 17 B , a region 102 corresponding to the screen size has an aspect ratio of 4:3 and is 1.5 inches. Terminal portions 106 A and 106 B to be connected to an FPC are provided above and below the region 102 . Note that in FIG. 17 B , an arrow 103 and an arrow 104 each indicating the width (margin) for sealing the elements of the display device 10 are 7 mm and 6 mm, respectively, and an arrow 105 indicating the width of terminal portion 106 A or 106 B is 6.6 mm.
  • the display device of one embodiment of the present invention can be suitably used for a portable electronic device, a wearable electronic device (wearable device), an e-book reader, and the like.
  • the display device can be suitably used for a VR (Virtual Reality) device, an AR (Augmented Reality) device, and the like.
  • FIG. 18 A is a diagram illustrating an external view of a head-mounted display 8200 .
  • the head-mounted display 8200 includes a wearing portion 8201 , a lens 8202 , a main body 8203 , a display portion 8204 , a cable 8205 , and the like.
  • a battery 8206 is incorporated in the wearing portion 8201 .
  • the cable 8205 supplies electric power from the battery 8206 to the main body 8203 .
  • the main body 8203 includes a wireless receiver or the like and can display an image corresponding to the received image data or the like on the display portion 8204 .
  • the movement of the eyeball or the eyelid of the user can be captured by a camera provided in the main body 8203 and then coordinates of the sight line of the user can be calculated using the information to utilize the sight line of the user as an input means.
  • a plurality of electrodes may be provided in the wearing portion 8201 at a position in contact with the user.
  • the main body 8203 may have a function of sensing current flowing through the electrodes along with the movement of the user's eyeball to recognize the user's sight line.
  • the main body 8203 may have a function of sensing current flowing through the electrodes to monitor the user's pulse.
  • the wearing portion 8201 may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor to have a function of displaying the user's biological information on the display portion 8204 .
  • the main body 8203 may sense the movement of the user's head or the like to change an image displayed on the display portion 8204 in synchronization with the movement.
  • the display device of one embodiment of the present invention can be used in the display portion 8204 .
  • the power consumption of the head-mounted display 8200 can be reduced, so that the head-mounted display 8200 can be used continuously for a long time.
  • the power consumption of the head-mounted display 8200 can be reduced, which allows the battery 8206 to be downsized and lighter and accordingly allows the head-mounted display 8200 to be downsized and lighter.
  • a burden of the user of the head-mounted display 8200 can be reduced, and the user is less likely to feel fatigue.
  • FIG. 18 B , FIG. 18 C , and FIG. 18 D are external views of a head-mounted display 8300 .
  • the head-mounted display 8300 includes a housing 8301 , a display portion 8302 , a fixing band 8304 , and a pair of lenses 8305 .
  • a battery 8306 is incorporated in the housing 8301 , and electric power can be supplied from the battery 8306 to the display portion 8302 and the like.
  • a user can see display on the display portion 8302 through the lenses 8305 . It is suitable that the display portion 8302 be curved and placed. When the display portion 8302 is curved and placed, a user can feel a high realistic sensation. Note that although the structure in which one display portion 8302 is provided is described in this embodiment as an example, the structure is not limited thereto, and a structure in which two display portions 8302 are provided may also be employed. In that case, one display portion is placed for one eye of the user, so that three-dimensional display using parallax or the like is possible.
  • the above-described display device can be used in the display portion 8302 .
  • the power consumption of the head-mounted display 8300 can be reduced, so that the head-mounted display 8300 can be used continuously for a long time.
  • the power consumption of the head-mounted display 8300 can be reduced, which allows the battery 8306 to be downsized and lighter and accordingly allows the head-mounted display 8300 to be downsized and lighter.
  • a burden of the user of the head-mounted display 8300 can be reduced, and the user is less likely to feel fatigue.
  • FIG. 19 A and FIG. 19 B illustrate examples of electronic devices that are different from the electronic devices illustrated in FIG. 18 A to FIG. 18 D .
  • Electronic devices illustrated in FIG. 19 A and FIG. 19 B include a housing 9000 , a display portion 9001 , a speaker 9003 , an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006 , a sensor 9007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays), a battery 9009 , and the like.
  • the electronic devices illustrated in FIG. 19 A and FIG. 19 B have a variety of functions.
  • the functions include a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling processing with a variety of software (programs), a wireless communication function, a function of being connected to a variety of computer networks with a wireless communication function, a function of transmitting and receiving a variety of data with a wireless communication function, and a function of reading out a program or data stored in a memory medium and displaying it on the display portion.
  • the electronic devices can have a variety of functions.
  • the electronic devices may each include a plurality of display portions.
  • the electronic devices may each include a camera and the like and have a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a memory medium (externally attached or incorporated in the camera), a function of displaying the taken image on the display portion, and the like.
  • FIG. 19 A and FIG. 19 B The details of the electronic devices illustrated in FIG. 19 A and FIG. 19 B will be described below.
  • FIG. 19 A is a perspective view illustrating a portable information terminal 9101 .
  • the portable information terminal 9101 has a function of, for example, one or more selected from a telephone set, a notebook, an information browsing system, and the like. Specifically, the portable information terminal can be used as a smartphone.
  • the portable information terminal 9101 can display text, an image, or the like on its plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons, or simply, icons) can be displayed on one surface of the display portion 9001 .
  • Information 9051 indicated by a dashed rectangular can be displayed on another surface of the display portion 9001 .
  • Examples of the information 9051 include display indicating reception of an e-mail, an SNS (social networking service), a telephone call, or the like; the title of an e-mail, an SNS, or the like; the sender of an e-mail, an SNS, or the like; the date; the time; remaining battery; or the reception strength of an antenna.
  • the operation buttons 9050 or the like may be displayed on the position where the information 9051 is displayed, in place of the information 9051 .
  • the above-described display device can be used for the portable information terminal 9101 .
  • the power consumption of the portable information terminal 9101 can be reduced, so that the portable information terminal 9101 can be used continuously for a long time.
  • the power consumption of the portable information terminal 9101 can be reduced, which allows the battery 9009 to be downsized and lighter and accordingly allows the portable information terminal 9101 to be downsized and lighter.
  • the portability of the portable information terminal 9101 can be increased.
  • FIG. 19 B is a perspective view of a watch-type portable information terminal 9200 .
  • the portable information terminal 9200 can execute a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and computer games.
  • the display surface of the display portion 9001 is curved, and display can be performed on the curved display surface.
  • FIG. 19 B illustrates an example in which time 9251 , operation buttons 9252 (also referred to as operation icons, or simply, icons), and a content 9253 are displayed on the display portion 9001 .
  • the content 9253 can be a moving image, for example.
  • the portable information terminal 9200 is capable of executing near field communication conformable to a communication standard. For example, mutual communication with a headset capable of wireless communication enables hands-free calling.
  • the portable information terminal 9200 includes the connection terminal 9006 , and data can be directly transmitted to and received from another information terminal via a connector. Power charging through the connection terminal 9006 is also possible. Note that the charging operation may be performed by wireless power feeding without through the connection terminal 9006 .
  • the above-described display device can be used for the portable information terminal 9200 .
  • the power consumption of the portable information terminal 9200 can be reduced, so that the portable information terminal 9200 can be continuously used for a long time.
  • the power consumption of the portable information terminal 9200 can be reduced, which allows the battery 9009 to be downsized and lighter and accordingly allows the portable information terminal 9200 to be downsized and lighter.
  • the portability of the portable information terminal 9200 can be increased.
  • One embodiment of the present invention can be constituted by appropriately combining the structure described in an embodiment with any of the structures described in the other embodiments.
  • some of the structure examples can be combined as appropriate.
  • a content (or part thereof) described in one embodiment can be applied to, combined with, or replaced with another content (or part thereof) in the same embodiment and/or a content (or part thereof) described in another embodiment or other embodiments, for example.
  • a content described in the embodiment is a content described with reference to a variety of diagrams or a content described with text disclosed in the specification.
  • components are classified on the basis of the functions, and shown as blocks independent of one another in block diagrams.
  • such components are sometimes hard to classify functionally, and there is a case where one circuit is associated with a plurality of functions and a case where a plurality of circuits are associated with one function. Therefore, the blocks in the block diagrams are not limited by the components described in the specification, and the description can be changed appropriately depending on the situation.
  • the size, the layer thickness, or the region is shown arbitrarily for description convenience. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematically shown for clarity, and embodiments of the present invention are not limited to shapes, values, or the like shown in the drawings. For example, variation in signal, voltage, or current due to noise or variation in signal, voltage, or current due to difference in timing can be included.
  • the terms “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used to describe the connection relationship of a transistor. This is because a source and a drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.
  • electrode or “wiring” do not limit the functions of the components.
  • an “electrode” is used as part of a “wiring” in some cases, and vice versa.
  • the term such as “electrode” or “wiring” also includes the case where a plurality of “electrodes” and “wirings” are formed in an integrated manner, for example.
  • voltage and potential can be replaced with each other as appropriate.
  • the term voltage refers to a potential difference from a reference potential, and when the reference potential is a ground potential, for example, voltage can be replaced with potential.
  • the ground potential does not necessarily mean 0 V.
  • Potentials are relative values, and a potential supplied to a wiring or the like is sometimes changed depending on the reference potential.
  • the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances.
  • the term “conductive layer” can be changed into the term “conductive film” in some cases.
  • the term “insulating film” can be changed into the term “insulating layer” in some cases.
  • a switch is in a conduction state (on state) or in a non-conduction state (off state) to determine whether current flows therethrough or not.
  • a switch has a function of selecting and changing a current path.
  • the channel length refers to, for example, the distance between a source and a drain in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate overlap with each other or a region where a channel is formed in a top view of the transistor.
  • the channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed.
  • the expression “A and B are connected” means the case where A and B are electrically connected to each other as well as the case where A and B are directly connected to each other.
  • the expression “A and B are electrically connected” means the case where electric signals can be transmitted and received between A and B when an object having any electric action exists between A and B.
  • a structure in which light-emitting layers in light-emitting devices of different colors (here, blue (B), green (G), and red (R)) are separately formed or separately patterned may be referred to as an SBS (Side By Side) structure.
  • SBS Side By Side
  • a light-emitting device capable of emitting white light may be referred to as a white-light-emitting device.
  • a white-light-emitting device that is combined with coloring layers e.g., color filters
  • a device having a single structure includes one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers.
  • the light-emitting unit preferably includes one or more light-emitting layers.
  • two or more light-emitting layers are selected such that emission colors of the light-emitting layers are complementary colors.
  • the light-emitting device can be configured to emit white light as a whole. The same applies to a light-emitting device including three or more light-emitting layers.
  • a device having a tandem structure includes two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers.
  • the structure is made so that light from light-emitting layers of the light-emitting units can be combined to be white light.
  • a structure for obtaining white light emission is similar to a structure in the case of a single structure.
  • an intermediate layer such as a charge-generation layer is provided between a plurality of light-emitting units.
  • the white-light-emitting device (having a single structure or a tandem structure) and a light-emitting device having an SBS structure are compared to each other, the light-emitting device having a SBS structure can have lower power consumption than the white-light-emitting device.
  • a light-emitting device having an SBS structure is preferably used.
  • the white-light-emitting device is preferable in terms of lower manufacturing cost or higher manufacturing yield because the manufacturing process of the white-light-emitting device is simpler than that of a light-emitting device having a SBS structure.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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US18/260,976 2020-01-14 2022-01-06 Display device and electronic device Pending US20240057382A1 (en)

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JP2021004390 2021-01-14
PCT/IB2022/050076 WO2022153146A1 (fr) 2021-01-14 2022-01-06 Dispositif d'affichage et équipement électronique

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JP2003140571A (ja) * 2001-10-30 2003-05-16 Horon Kk ドットマトリックス表示装置
JP2007003699A (ja) * 2005-06-22 2007-01-11 Fuji Xerox Co Ltd 画像表示装置
JP5966412B2 (ja) * 2011-04-08 2016-08-10 ソニー株式会社 画素チップ、表示パネル、照明パネル、表示装置および照明装置
US10586495B2 (en) * 2016-07-22 2020-03-10 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
KR20180030325A (ko) * 2016-09-13 2018-03-22 삼성디스플레이 주식회사 표시장치
JP7247176B2 (ja) * 2018-05-17 2023-03-28 株式会社半導体エネルギー研究所 表示装置、及び電子機器
JP7308655B2 (ja) * 2018-07-13 2023-07-14 株式会社半導体エネルギー研究所 表示装置、及び電子機器
CN210926018U (zh) * 2019-09-20 2020-07-03 北京小米移动软件有限公司 显示面板、显示屏及电子设备

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WO2022153146A1 (fr) 2022-07-21

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