US20230268177A1 - SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - Google Patents

SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME Download PDF

Info

Publication number
US20230268177A1
US20230268177A1 US18/309,111 US202318309111A US2023268177A1 US 20230268177 A1 US20230268177 A1 US 20230268177A1 US 202318309111 A US202318309111 A US 202318309111A US 2023268177 A1 US2023268177 A1 US 2023268177A1
Authority
US
United States
Prior art keywords
sic
dislocation
sic epitaxial
single crystal
crystal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/309,111
Inventor
Koji Kamei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to US18/309,111 priority Critical patent/US20230268177A1/en
Publication of US20230268177A1 publication Critical patent/US20230268177A1/en
Assigned to RESONAC CORPORATION reassignment RESONAC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SHOWA DENKO K.K.
Pending legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/90—Carbides
    • C01B32/914—Carbides of single elements
    • C01B32/956—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C23C16/325—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/90—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation

Definitions

  • the present invention relates to a SiC epitaxial wafer and a method for manufacturing the same.
  • Silicon carbide has properties, which a dielectric breakdown electric field is one digit larger, a band gap is three times larger, and thermal conductivity is three times higher, than those of silicon (Si). Since silicon carbide has these characteristics, the silicon carbide is expected to be applied to a power device, a high frequency device, a high temperature operation device, and the like. Therefore, in recent years, a SiC epitaxial wafer is used for the above semiconductor devices.
  • a SiC device is generally manufactured using a SiC epitaxial wafer in which a SiC epitaxial layer (film) that becomes an active region of the device by chemical vapor deposition (CVD) or the like is grown on a SiC single crystal substrate (simply referred to as a SiC substrate, in some cases) obtained by processing from a SiC bulk single crystal grown by sublimation recrystallization or the like.
  • a SiC epitaxial layer film that becomes an active region of the device by chemical vapor deposition (CVD) or the like is grown on a SiC single crystal substrate (simply referred to as a SiC substrate, in some cases) obtained by processing from a SiC bulk single crystal grown by sublimation recrystallization or the like.
  • the SiC epitaxial wafer is generally obtained by growing 4H SiC epitaxial layer on a SiC single crystal substrate, in which a surface having an off angle from a (0001) plane to ⁇ 11-20> direction is used as a growth surface, by step flow growth (lateral direction growth from an atomic step).
  • the SiC single crystal substrate generally has crystal defects called a threading screw dislocation (TSD), a threading edge dislocation (TED), or a basal plane dislocation (BPD), and device characteristics may deteriorate due to these crystal defects in some cases. These dislocations basically propagate from the SiC single crystal substrate to the SiC epitaxial film.
  • TSD threading screw dislocation
  • TED threading edge dislocation
  • BPD basal plane dislocation
  • This interface dislocation is a kind of a basal plane dislocation, and extends in a direction perpendicular to a SiC substrate off-cut direction (in a case where an off-cut direction is ⁇ 11-20>, ⁇ 11-100> direction), near an interface between the SiC substrate and the SiC epitaxial film.
  • the interface dislocation is assumed to have been extended to relieve stress near the interface.
  • the threading edge dislocation row (“TED pairs 9 ” in FIG. 8 ) may be formed on the SiC epitaxial film.
  • the pairs of the two dislocations are continuous in a row in the ⁇ 1-100> direction, and the threading edge dislocation row may be formed.
  • the epitaxial film has a higher dislocation density than that of the SiC single crystal substrate, and may deteriorate crystallinity in epitaxial growth.
  • the pairs of threading edge dislocations are connected in a half loop shape by the basal plane dislocation at the base thereof.
  • FIG. 8 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate.
  • a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate.
  • an A point, a B point, a C point, and an AB part and a BC part connecting these are shown.
  • an L-shaped dislocation is observed.
  • the L-shaped dislocation is that the AB part (an interface dislocation 14 ) and the BC part (a basal plane dislocation 15 ) are observed in FIG. 8 .
  • the BC part crosses a SiC epitaxial film 5 while being placed on a (0001) basal plane 16 and terminates at the point C on a surface of the SiC epitaxial film 5 .
  • the BC part (the basal plane dislocation 15 ) moves to right direction during epitaxial growth. Accordingly, the AB part (the interface dislocation 14 ) extends to the right direction.
  • the threading edge dislocation row (a “TED pair 9 ” in FIG. 8 ) is sequentially formed in a portion of C, and an array of the threading edge dislocation row can be arrayed (hereinafter, a structure in which the threading edge dislocation rows are arranged in a direction perpendicular to a step flow direction is referred to as a pair array (a pair array 11 in FIG. 8 )).
  • a pair array a pair array 11 in FIG. 8
  • the array of the threading edge dislocation row is observed as an array of dots, and the BC part (the basal plane dislocation) is observed linearly.
  • the AB part the interface dislocation
  • the presence of the interface dislocation can be known.
  • the array of the threading edge dislocation rows extends perpendicular to the step flow direction, and one array of threading edge dislocation rows and one interface dislocation resulting from the generation of the array are present in parallel with each other. Accordingly, the presence of one interface dislocation extending perpendicular to the step flow direction can be confirmed by finding one array of dots.
  • the BC part (the basal plane dislocation) extends parallel with the step flow direction, and one BC part (the basal plane dislocation) and one interface dislocation resulting from the occurrence of the BC part extend perpendicular to each other. Therefore, the presence of one interface dislocation extending perpendicular to the step flow direction can be confirmed by finding a linear pattern corresponding to the one BC portion (the basal plane dislocation).
  • the interface dislocation known in the related art is generated at a location on the SiC substrate, where there is a basal plane dislocation (BPD).
  • BPD basal plane dislocation
  • the present inventors found a new interface dislocation (hereinafter, referred to as “outer edge interface dislocation”) that extends from an outer peripheral edge of a SiC substrate when a SiC epitaxial film grows on the SiC substrate.
  • the present inventors found that the outer edge interface dislocation is generated by increasing a thickness of a SiC epitaxial film, through repeated studies.
  • the interface dislocation of the related art starts from the location of the SiC substrate, where there is the BPD.
  • the interface dislocation (the outer edge interface dislocation) found by the present inventors is different therefrom in a point that the interface dislocation starts from an outer peripheral edge of the SiC substrate. Since the interface dislocation lowers the reliability of a device as in the interface dislocation of the related art, it should be reduced.
  • the present invention was made in view of the above circumstances, and an object thereof is to provide a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 ⁇ m or more and a low density of an outer edge interface dislocation, and a method for manufacturing the same.
  • the present invention provides means as follows, in order to solve the problems.
  • a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ⁇ m or more, which is formed on the 4H—SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ⁇ m or more, which is formed on the 4H—SiC single crystal substrate, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and the width of the slope part is 150 ⁇ m or more.
  • the density of an interface dislocation in a range of central angles of 25° to 155° and 205° to 335° with a center line in a ⁇ 11-20> direction may be 10 lines/cm or less.
  • the bevel part may include a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part may be 150 ⁇ m or more.
  • a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer may be 10 lines/cm or less.
  • a method for manufacturing a SiC epitaxial wafer in which a 4H—SiC single crystal substrate is used, wherein the 4H—SiC single crystal substrate has a bevel part in a peripheral part, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 ⁇ m or more, is used.
  • the method for manufacturing a SiC epitaxial wafer preferably includes: a step of preparing the H—SiC single crystal substrate; and a step of forming a SiC epitaxial film having a film thickness of 20 ⁇ m or more on the H—SiC single crystal substrate, in which a SiC epitaxial wafer obtained including the 4H—SiC single crystal substrate which has a bevel part on a peripheral part and has a surface with an off angle with respect to a c-plane as a main surface, and the SiC epitaxial film which is formed on the 4H—SiC single crystal substrate and has a film thickness of 20 ⁇ m or more, and a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • the step of forming a SiC epitaxial film having a film thickness of 20 ⁇ m or more preferably includes
  • SiC epitaxial wafer of the present invention it is possible to provide a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 ⁇ m or more and a low density of an outer edge interface dislocation.
  • FIG. 1 is a schematic sectional view of the vicinity of a peripheral part of a SiC single crystal substrate.
  • FIG. 2 is a schematic sectional view of the vicinity of a peripheral part of a SiC epitaxial wafer.
  • FIG. 3 is a schematic diagram showing a PL image obtained from a SiC epitaxial wafer and observation location, where (a) is a PL image at a position of an orientation flat, (b) is a PL image at a position on a side opposite the orientation flat, and (c) is a schematic diagram showing a relationship between the position of the orientation flat in the SiC epitaxial wafer and a step flow direction.
  • FIG. 4 A is a schematic sectional view showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon, in a case where a width of a slope part is large.
  • FIG. 4 B is a schematic sectional view showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon, in a case where a width of a slope part is small.
  • FIG. 5 is a graph showing results of examining a relationship between a film thickness of an epitaxial film and the presence or absence of generation of an outer edge interface dislocation.
  • FIG. 6 A is a confocal microscope image when an inclined part is 170 ⁇ m and a film thickness of a SiC epitaxial film is 28 ⁇ m, shown in FIG. 5 .
  • FIG. 6 B is a PL image when an inclined part is 170 ⁇ m and a film thickness of a SiC epitaxial film is 28 ⁇ m, shown in FIG. 5 .
  • FIG. 7 A is a PL image when an inclined part is 150 ⁇ m and a film thickness of a SiC epitaxial film is 33 ⁇ m, shown in FIG. 5 .
  • FIG. 7 B is a PL image when an inclined part is 0 ⁇ m and a film thickness of a SiC epitaxial film is 33 ⁇ m, shown in FIG. 5 .
  • FIG. 8 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate, for illustrating a relationship between generation of a threading edge dislocation row and an interface dislocation.
  • the present invention is not limited to only the following examples, and addition, omission, substitution, or change in a position, the number, a shape, a material, a configuration, and the like can be made within the scope not departing from the gist of the present invention.
  • a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ⁇ m or more, which is formed on the 4H—SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • the “interface dislocation extending from an outer peripheral edge” may be referred to as an “outer edge interface dislocation”.
  • the c-plane represents a ⁇ 0001 ⁇ surface.
  • the (0001) plane in the c-plane is described as a (0001) Si surface.
  • the density of the interface dislocation extending from the outer peripheral edge can be measured, for example, from a photoluminescence (PL) image.
  • PL image for example, a PL image obtained at a near-infrared (NIR) light receiving wavelength, by using a photoluminescence device (SICA88, manufactured by Lasertec Corporation) can be used.
  • NIR near-infrared
  • the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 20 ⁇ m or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 22 ⁇ m or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 24 ⁇ m or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 27 ⁇ m or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 29 ⁇ m or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • FIG. 1 is a schematic sectional view of the vicinity of a peripheral part of a SiC single crystal substrate.
  • the “bevel part” is a portion of the peripheral part of the substrate that is chamfered to prevent a substrate from chipping or particles from being generated, and is a portion thinner than the thickness of the substrate.
  • a SiC single crystal substrate 1 has a main surface (flat part) 1 a and a bevel part 1 A including a slope part 1 Aa and an outer peripheral edge part 1 Ab in the periphery thereof.
  • the “slope part” is a portion continuous from the flat part 1 a of the SiC single crystal substrate, and is a portion having an inclined surface that is inclined toward an outer periphery with a predetermined angle of 60° or less (an angle relative to a plane including the main surface) with respect to the flat part.
  • the inclined surface is not limited to a case of an inclined surface with only one angle, and may be inclined surface with a plurality of angles or a curved inclined surface having a curvature (smaller than a curvature of the “outer peripheral edge part”).
  • an angle of the inclined surface refers to an angle of a tangential plane.
  • An SiC single crystal substrate having an angle of 50° or less, 40° or less, 30° or less, or 20° or less as the angle of the inclined surface (an angle with respect to a plane including the main surface) that the “slope part” includes, may be used. Data shown in FIG. 5 , which will be described later, was obtained in a case where a SiC single crystal substrate having an angle of 30° or less was used.
  • the “outer peripheral edge part” is a portion disposed on the outermost side in a radial direction in the SiC single crystal substrate and a portion including a curved surface having a predetermined curvature.
  • the curved surface is not limited to a curved surface having only one curvature, and may have a curved surface with a plurality of curvatures or may have a plane (for example, a vertical plane) on a portion that does not continue to the “slope part” among portions forming the “outer peripheral edge part”.
  • FIG. 2 is a schematic sectional view of the vicinity of a peripheral part of a SiC epitaxial wafer.
  • an outer peripheral edge 2 a of a SiC epitaxial layer 2 refers to the outermost side in a radial direction, in the SiC epitaxial layer 2 formed on the main surface (the flat part) 1 a of the SiC single crystal substrate 1 .
  • FIG. 3 shows PL images obtained at different positions of the SiC epitaxial wafer.
  • (c) of FIG. 3 is a schematic diagram showing a relationship between the position of an orientation flat in the SiC epitaxial wafer and a step flow direction.
  • FIG. 3 is a PL image at a position of the orientation flat
  • (b) of FIG. 3 is a PL image at a position on a side opposite the orientation flat.
  • an array of dots and a linear pattern corresponding to a BC part (a basal plane dislocation) can be observed.
  • a basal plane dislocation since one array of dots and one linear pattern corresponding to the BC part (the basal plane dislocation) can be observed, it can be known that there is one outer edge interface dislocation.
  • b) of FIG. 3 since two arrays of dots and two linear patterns corresponding to the BC part (the basal plane dislocation) can be observed, it can be known that there are two outer edge interface dislocations.
  • the outer edge interface dislocation is the most in the vicinity of the orientation flat, and then many outer edge interface dislocations are in the position on the side opposite the orientation flat.
  • a direction perpendicular to the outer tangent that is, an inclined direction of the slope part of the bevel part is close to parallel with the step flow direction. Therefore, there is almost no generation of the outer edge interface dislocation.
  • the outer edge interface dislocation is often generated at 25° to 155° and 205° to 335° in terms of the central angle with respect to the center of the wafer.
  • a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ⁇ m or more, which is formed on the 4H—SiC single crystal substrate, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and the width of the slope part is 150 ⁇ m or more.
  • the “width of the slope part” refers to the length in the radial direction when the slope part is viewed from a direction perpendicular to the main surface.
  • FIGS. 4 A and 4 B are schematic sectional views showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon (an upper drawing shows an initial stage of growth and a lower drawing shows that growth is completed).
  • FIG. 4 A shows a case where the width of the slope part is large
  • FIG. 4 B shows a case where the width of the slope part is small.
  • the epitaxial film 5 is formed by step flow growth, and also in the slope part 1 Aa, the step flow growth is maintained if the c-plane is dominant. Since it is common to practically use a SiC substrate with an off angle, it is considered that the step flow growth is maintained, and a probability of forming the nucleus 7 that is the source of random growth is low.
  • the outer peripheral edge part 1 Ab a surface other than the c-plane (an r-plane or an m-plane) becomes dominant. Accordingly, it can be considered that, in the outer peripheral edge part 1 Ab, the step flow growth hardly occurs, and random growth occurs.
  • a substrate having a slope part with a small width (a distance from the outer peripheral edge part to the flat part is short)
  • FIG. 5 shows results of examining a relationship between a film thickness of an epitaxial film and the presence or absence of generation of the outer edge interface dislocation, when the slope part has a predetermined width.
  • the symbol “ ⁇ ” indicates that there is no outer edge interface dislocation, and the symbol “ ⁇ ” indicates that there is an outer edge interface dislocation.
  • a dotted line indicates a boundary where a density of the outer edge interface dislocation is zero.
  • a sample from which data was acquired was obtained as follows. Using a 4 or 6 inch 4H—SiC single crystal substrate having an off angle of 4° with respect to the (0001) Si surface in a ⁇ 11-20> direction, a known polishing step and a substrate surface cleaning (etching) step were performed. Thereafter, a SiC epitaxial growth step (a growth temperature is 1600° C. and a C/Si ratio is 1.22) was performed using silane and propane as source gases while supplying hydrogen as a carrier gas. In this way, a SiC epitaxial layer with a predetermined film thickness was formed on a SiC single crystal substrate to obtain a SiC epitaxial wafer.
  • 0 ⁇ m of slope part refers to slope in which a SiC single crystal substrate was only chamfered, and an angle of the chamfered portion exceeds 60°. Therefore, in accordance with the above definition of the slope part, this portion is not included in the slope part (accordingly, in this SiC single crystal substrate, the bevel part includes only the outer peripheral edge part).
  • FIG. 6 A shows a microscope image obtained by using a confocal microscope (SICA88, manufactured by Lasertec Corporation) which is a surface inspection device that uses a confocal differential interference optical system.
  • FIG. 6 B shows a PL image thereof.
  • the processing of the width of the inclined part can be performed using a known method. For example, contouring or the like can be used (see Patent Document 1).
  • a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 22 ⁇ m.
  • a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 24 ⁇ m.
  • a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 27 ⁇ m.
  • a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 29 ⁇ m.
  • FIGS. 7 A and 7 B show a PL image of a sample in a case where the inclined part is 150 ⁇ m and the film thickness of the SiC epitaxial film is 33 ⁇ m and a PL image of a sample in a case were the inclined part is 0 ⁇ m and the film thickness of the SiC epitaxial film is 33 ⁇ m, respectively, shown in FIG. 5 .
  • the 4H—SiC single crystal substrate used for the SiC epitaxial wafer of the present invention has an off angle of, for example, 0.4° or more and 8° or less. Typical examples thereof include an off angle of 4°.
  • a method for manufacturing a SiC epitaxial wafer in which a 4H—SiC single crystal substrate having a bevel part in a peripheral part, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part and a width of the slope part is 150 ⁇ m or more, is used.
  • This method may include a step of preparing the H—SiC single crystal substrate and a step of forming a SiC epitaxial film having a film thickness of 20 ⁇ m or more on the H—SiC single crystal substrate.
  • the step of forming the SiC epitaxial film having a film thickness of 20 ⁇ m or more may include a sub-step of determining a thickness of an epitaxial film, satisfying Formula (1), using a width of the slope part of the substrate to be used, and a sub-step of forming the SiC epitaxial film such that a thickness of a SiC epitaxial film to be manufactured is set to be equal to or smaller than the thickness of the epitaxial film, satisfying Formula (1), which is obtained by the aforementioned formula.
  • Y represents a width ( ⁇ m) of slope and X represents a thickness ( ⁇ m) of an epitaxial film
  • a known step can be used except for the setting step using a predetermined 4H—SiC single crystal substrate to use the aforementioned SiC wafer (SiC substrate).
  • a method of manufacturing a SiC epitaxial wafer preferably a method including:
  • Y represents a width ( ⁇ m) of slope and X represents a thickness ( ⁇ m) of an epitaxial film
  • the SiC epitaxial wafer of the present invention can be preferably manufactured.
  • the present invention provides a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 ⁇ m or more and a low density of an outer edge interface dislocation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional application of U.S. application Ser. No. 16/620,088 filed Dec. 6, 2019, which is a National Stage of International Application No. PCT/JP2018/018498 filed May 14, 2018, which claims priority to Japanese Patent Application No. 2017-126744 filed on Jun. 28, 2017; the disclosures of which are incorporated by reference herein in their entirety.
    • TECHNICAL FIELD
  • The present invention relates to a SiC epitaxial wafer and a method for manufacturing the same.
  • Priority is claimed on Japanese Patent Application No. 2017-126744, filed on Jun. 28, 2017, the content of which is incorporated herein by reference.
    • BACKGROUND ART
  • Silicon carbide (SiC) has properties, which a dielectric breakdown electric field is one digit larger, a band gap is three times larger, and thermal conductivity is three times higher, than those of silicon (Si). Since silicon carbide has these characteristics, the silicon carbide is expected to be applied to a power device, a high frequency device, a high temperature operation device, and the like. Therefore, in recent years, a SiC epitaxial wafer is used for the above semiconductor devices.
  • To promote practical application of a SiC device, it is essential to establish high-quality crystal growth technology and high-quality epitaxial growth technology.
  • A SiC device is generally manufactured using a SiC epitaxial wafer in which a SiC epitaxial layer (film) that becomes an active region of the device by chemical vapor deposition (CVD) or the like is grown on a SiC single crystal substrate (simply referred to as a SiC substrate, in some cases) obtained by processing from a SiC bulk single crystal grown by sublimation recrystallization or the like.
  • More specifically, the SiC epitaxial wafer is generally obtained by growing 4H SiC epitaxial layer on a SiC single crystal substrate, in which a surface having an off angle from a (0001) plane to <11-20> direction is used as a growth surface, by step flow growth (lateral direction growth from an atomic step).
  • The SiC single crystal substrate generally has crystal defects called a threading screw dislocation (TSD), a threading edge dislocation (TED), or a basal plane dislocation (BPD), and device characteristics may deteriorate due to these crystal defects in some cases. These dislocations basically propagate from the SiC single crystal substrate to the SiC epitaxial film.
  • On the other hand, it is known that a dislocation called an interface dislocation occurs in the SiC epitaxial film. This interface dislocation is a kind of a basal plane dislocation, and extends in a direction perpendicular to a SiC substrate off-cut direction (in a case where an off-cut direction is <11-20>, <11-100> direction), near an interface between the SiC substrate and the SiC epitaxial film.
  • The interface dislocation is assumed to have been extended to relieve stress near the interface.
  • Furthermore, not only the threading edge dislocation propagated from the SiC single crystal substrate but also the threading edge dislocation row (“TED pairs 9” in FIG. 8 ) may be formed on the SiC epitaxial film. Specifically, in a case where two threading edge dislocations newly generated during epitaxial growth are paired, and the off-cut direction is <11-20>, the pairs of the two dislocations are continuous in a row in the <1-100> direction, and the threading edge dislocation row may be formed. As a result of generation of the threading edge dislocation row, the epitaxial film has a higher dislocation density than that of the SiC single crystal substrate, and may deteriorate crystallinity in epitaxial growth. The pairs of threading edge dislocations are connected in a half loop shape by the basal plane dislocation at the base thereof.
    • CITATION LIST Patent Literature
    • [Patent Document 1] Japanese Unexamined Patent Application, First Publication No. 2008-34776
    Non-Patent Literature
    • [Non-Patent Document 1] X. Zhangetal., Journal of Applied Physics 102, 093520 (2007)
    DISCLOSURE OF INVENTION Technical Problem
  • A relationship between the generation of the threading edge dislocation row and the interface dislocation and features of an X-ray topography image and a PL image, which were clarified based on observations by X-ray topography, photoluminescence (PL), and the like in Non-Patent Document 1, will be described with reference to FIG. 8 .
  • FIG. 8 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate. For easy understanding, an A point, a B point, a C point, and an AB part and a BC part connecting these are shown.
  • In the X-ray topography image, an L-shaped dislocation is observed. The L-shaped dislocation is that the AB part (an interface dislocation 14) and the BC part (a basal plane dislocation 15) are observed in FIG. 8 . The BC part crosses a SiC epitaxial film 5 while being placed on a (0001) basal plane 16 and terminates at the point C on a surface of the SiC epitaxial film 5. In the L-shaped dislocation, the BC part (the basal plane dislocation 15) moves to right direction during epitaxial growth. Accordingly, the AB part (the interface dislocation 14) extends to the right direction. In this manner, when the AB part (the interface dislocation 14) extends to a right side, the threading edge dislocation row (a “TED pair 9” in FIG. 8 ) is sequentially formed in a portion of C, and an array of the threading edge dislocation row can be arrayed (hereinafter, a structure in which the threading edge dislocation rows are arranged in a direction perpendicular to a step flow direction is referred to as a pair array (a pair array 11 in FIG. 8 )). Thus, the generation of the threading edge dislocation row and the interface dislocation are closely related.
  • In the X-ray topography image, since an image of the threading edge dislocation row is in a position shallower from the surface as it goes to the right side, contrast becomes weaker.
  • In the X-ray topography image, all of the AB part (the interface dislocation), the BC part (the basal plane dislocation), and the threading edge dislocation row are often observed.
  • On the other hand, in the photoluminescence (PL) image, the array of the threading edge dislocation row is observed as an array of dots, and the BC part (the basal plane dislocation) is observed linearly. On the other hand, it is difficult to observe the AB part (the interface dislocation).
  • Therefore, when observing the array of dots and a linear pattern corresponding to the BC portion (the basal plane dislocation) in the PL image, the presence of the interface dislocation can be known.
  • The array of the threading edge dislocation rows extends perpendicular to the step flow direction, and one array of threading edge dislocation rows and one interface dislocation resulting from the generation of the array are present in parallel with each other. Accordingly, the presence of one interface dislocation extending perpendicular to the step flow direction can be confirmed by finding one array of dots. In addition, the BC part (the basal plane dislocation) extends parallel with the step flow direction, and one BC part (the basal plane dislocation) and one interface dislocation resulting from the occurrence of the BC part extend perpendicular to each other. Therefore, the presence of one interface dislocation extending perpendicular to the step flow direction can be confirmed by finding a linear pattern corresponding to the one BC portion (the basal plane dislocation).
  • The interface dislocation known in the related art is generated at a location on the SiC substrate, where there is a basal plane dislocation (BPD).
  • On the other hand, the present inventors found a new interface dislocation (hereinafter, referred to as “outer edge interface dislocation”) that extends from an outer peripheral edge of a SiC substrate when a SiC epitaxial film grows on the SiC substrate. The present inventors found that the outer edge interface dislocation is generated by increasing a thickness of a SiC epitaxial film, through repeated studies. The interface dislocation of the related art starts from the location of the SiC substrate, where there is the BPD. However, the interface dislocation (the outer edge interface dislocation) found by the present inventors is different therefrom in a point that the interface dislocation starts from an outer peripheral edge of the SiC substrate. Since the interface dislocation lowers the reliability of a device as in the interface dislocation of the related art, it should be reduced.
  • The reason why the outer edge interface dislocation was not found until now is considered that this is because the SiC epitaxial film of which a thickness is thick to extent that the outer edge interface dislocation is generated is rarely used.
  • The present invention was made in view of the above circumstances, and an object thereof is to provide a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 μm or more and a low density of an outer edge interface dislocation, and a method for manufacturing the same.
    • Solution to Problem
  • The present invention provides means as follows, in order to solve the problems.
  • (1) According to a first aspect of the present invention, there is provided a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H—SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • (2) According to a second aspect of the present invention, there is provided a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H—SiC single crystal substrate, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and the width of the slope part is 150 μm or more.
  • (3) In the SiC epitaxial wafer according to (1) or (2), the density of an interface dislocation in a range of central angles of 25° to 155° and 205° to 335° with a center line in a <11-20> direction may be 10 lines/cm or less.
  • (4) In the SiC epitaxial wafer according to any one of (1) and (3), the bevel part may include a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part may be 150 μm or more.
  • (5) In the SiC epitaxial wafer according to (2) or (3), a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer may be 10 lines/cm or less.
  • (6) According to a third aspect of the present invention, there is provided a method for manufacturing a SiC epitaxial wafer, in which a 4H—SiC single crystal substrate is used, wherein the 4H—SiC single crystal substrate has a bevel part in a peripheral part, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 μm or more, is used.
  • (7) The method for manufacturing a SiC epitaxial wafer, according the third aspect of the present invention preferably includes: a step of preparing the H—SiC single crystal substrate; and a step of forming a SiC epitaxial film having a film thickness of 20 μm or more on the H—SiC single crystal substrate, in which a SiC epitaxial wafer obtained including the 4H—SiC single crystal substrate which has a bevel part on a peripheral part and has a surface with an off angle with respect to a c-plane as a main surface, and the SiC epitaxial film which is formed on the 4H—SiC single crystal substrate and has a film thickness of 20 μm or more, and a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • In the method for manufacturing a SiC epitaxial wafer according to (6) or (7), the step of forming a SiC epitaxial film having a film thickness of 20 μm or more preferably includes
      • a sub-step of determining a thickness of an epitaxial film, satisfying Formula (1), using a width of the slope part of the substrate to be used,

  • Y=20X−400  (1)
      • (in Formula, Y represents a width (μm) of slope and X represents a thickness (μm) of an epitaxial film), and
      • a sub-step of forming a SiC epitaxial film so that the thickness of the epitaxial film is set to be equal to or smaller than the determined thickness of the epitaxial film, satisfying Formula (1), which is obtained by the aforementioned formula.
    Advantageous Effects of Invention
  • According to the SiC epitaxial wafer of the present invention, it is possible to provide a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 μm or more and a low density of an outer edge interface dislocation.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a schematic sectional view of the vicinity of a peripheral part of a SiC single crystal substrate.
  • FIG. 2 is a schematic sectional view of the vicinity of a peripheral part of a SiC epitaxial wafer.
  • FIG. 3 is a schematic diagram showing a PL image obtained from a SiC epitaxial wafer and observation location, where (a) is a PL image at a position of an orientation flat, (b) is a PL image at a position on a side opposite the orientation flat, and (c) is a schematic diagram showing a relationship between the position of the orientation flat in the SiC epitaxial wafer and a step flow direction.
  • FIG. 4A is a schematic sectional view showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon, in a case where a width of a slope part is large.
  • FIG. 4B is a schematic sectional view showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon, in a case where a width of a slope part is small.
  • FIG. 5 is a graph showing results of examining a relationship between a film thickness of an epitaxial film and the presence or absence of generation of an outer edge interface dislocation.
  • FIG. 6A is a confocal microscope image when an inclined part is 170 μm and a film thickness of a SiC epitaxial film is 28 μm, shown in FIG. 5 .
  • FIG. 6B is a PL image when an inclined part is 170 μm and a film thickness of a SiC epitaxial film is 28 μm, shown in FIG. 5 .
  • FIG. 7A is a PL image when an inclined part is 150 μm and a film thickness of a SiC epitaxial film is 33 μm, shown in FIG. 5 .
  • FIG. 7B is a PL image when an inclined part is 0 μm and a film thickness of a SiC epitaxial film is 33 μm, shown in FIG. 5 .
  • FIG. 8 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate, for illustrating a relationship between generation of a threading edge dislocation row and an interface dislocation.
    •  BEST MODE FOR CARRYING OUT THE INVENTION
  • Hereinafter, preferred examples of the present invention will be described. Specifically, a SiC epitaxial wafer and a method for manufacturing the same according to the preferred embodiments of the present invention will be described in detail, with reference to drawings. In the drawings used in the following description, to make features easier to understand, for the sake of convenience, a feature part may be enlarged and shown in some cases, and a dimensional ratio of each component may not be the same as that of an actual one. In addition, in the following description, a material, a dimension, and the like to be exemplified are examples. The present invention is not limited thereto, and can be performed with appropriate modifications within the range exhibiting an effect thereof. That is, the present invention is not limited to only the following examples, and addition, omission, substitution, or change in a position, the number, a shape, a material, a configuration, and the like can be made within the scope not departing from the gist of the present invention.
    • (SiC Epitaxial Wafer)
  • According to an embodiment of the present invention, there is provided a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H—SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
  • The “interface dislocation extending from an outer peripheral edge” may be referred to as an “outer edge interface dislocation”.
  • The c-plane represents a {0001} surface. The (0001) plane in the c-plane is described as a (0001) Si surface.
  • The density of the interface dislocation extending from the outer peripheral edge can be measured, for example, from a photoluminescence (PL) image. As the PL image, for example, a PL image obtained at a near-infrared (NIR) light receiving wavelength, by using a photoluminescence device (SICA88, manufactured by Lasertec Corporation) can be used.
  • The SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 20 μm or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • In addition, the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 22 μm or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • In addition, the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 24 μm or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • In addition, the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 27 μm or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • In addition, the SiC epitaxial wafer of the present invention can include a SiC epitaxial layer having a film thickness of 29 μm or more and the density of the interface dislocation of the outer edge interface dislocation of zero lines/cm.
  • FIG. 1 is a schematic sectional view of the vicinity of a peripheral part of a SiC single crystal substrate.
  • A shape of the “bevel part” as used in the present specification will be described using FIG. 1 . In the present specification, the “bevel part” is a portion of the peripheral part of the substrate that is chamfered to prevent a substrate from chipping or particles from being generated, and is a portion thinner than the thickness of the substrate.
  • A SiC single crystal substrate 1 has a main surface (flat part) 1 a and a bevel part 1A including a slope part 1Aa and an outer peripheral edge part 1Ab in the periphery thereof. The bevel part 1A can also be understood as the following formula. “Bevel part 1A”=“Slope part 1Aa”+“Outer peripheral edge part 1Ab”
  • The “slope part” is a portion continuous from the flat part 1 a of the SiC single crystal substrate, and is a portion having an inclined surface that is inclined toward an outer periphery with a predetermined angle of 60° or less (an angle relative to a plane including the main surface) with respect to the flat part. However, the inclined surface is not limited to a case of an inclined surface with only one angle, and may be inclined surface with a plurality of angles or a curved inclined surface having a curvature (smaller than a curvature of the “outer peripheral edge part”). In a case of the inclined surface having a curvature, an angle of the inclined surface refers to an angle of a tangential plane. An SiC single crystal substrate having an angle of 50° or less, 40° or less, 30° or less, or 20° or less as the angle of the inclined surface (an angle with respect to a plane including the main surface) that the “slope part” includes, may be used. Data shown in FIG. 5 , which will be described later, was obtained in a case where a SiC single crystal substrate having an angle of 30° or less was used.
  • Further, the “outer peripheral edge part” is a portion disposed on the outermost side in a radial direction in the SiC single crystal substrate and a portion including a curved surface having a predetermined curvature. However, the curved surface is not limited to a curved surface having only one curvature, and may have a curved surface with a plurality of curvatures or may have a plane (for example, a vertical plane) on a portion that does not continue to the “slope part” among portions forming the “outer peripheral edge part”. Based on an estimated mechanism of generation of the outer edge interface dislocation, which will be described later, if there is a structure having no “outer peripheral edge part” and vertically steep on an outer side from the “slope part”, it seems that there is no location where nucleus that is a source of random growth is formed, which is good. However, in a case of this structure, a corner is likely to be chipped. Therefore, the corner is rounded off to prevent the corner from chipping, to have the “outer peripheral edge part” in general.
  • FIG. 2 is a schematic sectional view of the vicinity of a peripheral part of a SiC epitaxial wafer.
  • In a SiC epitaxial wafer 10, an outer peripheral edge 2 a of a SiC epitaxial layer 2 refers to the outermost side in a radial direction, in the SiC epitaxial layer 2 formed on the main surface (the flat part) 1 a of the SiC single crystal substrate 1.
  • (a) and (b) in FIG. 3 show PL images obtained at different positions of the SiC epitaxial wafer. (c) of FIG. 3 is a schematic diagram showing a relationship between the position of an orientation flat in the SiC epitaxial wafer and a step flow direction.
  • (a) of FIG. 3 is a PL image at a position of the orientation flat, (b) of FIG. 3 is a PL image at a position on a side opposite the orientation flat.
  • In both (a) and (b) of FIG. 3 , an array of dots and a linear pattern corresponding to a BC part (a basal plane dislocation) can be observed. In (a) of FIG. 3 , since one array of dots and one linear pattern corresponding to the BC part (the basal plane dislocation) can be observed, it can be known that there is one outer edge interface dislocation. In (b) of FIG. 3 , since two arrays of dots and two linear patterns corresponding to the BC part (the basal plane dislocation) can be observed, it can be known that there are two outer edge interface dislocations.
  • Based on results of PL observation by the inventors, the outer edge interface dislocation is the most in the vicinity of the orientation flat, and then many outer edge interface dislocations are in the position on the side opposite the orientation flat. On the other hand, at a position between the orientation flat and the side opposite the orientation flat, a direction perpendicular to the outer tangent, that is, an inclined direction of the slope part of the bevel part is close to parallel with the step flow direction. Therefore, there is almost no generation of the outer edge interface dislocation. The outer edge interface dislocation is often generated at 25° to 155° and 205° to 335° in terms of the central angle with respect to the center of the wafer.
  • According to another embodiment of the present invention, there is provided a SiC epitaxial wafer including: a 4H—SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H—SiC single crystal substrate, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and the width of the slope part is 150 μm or more.
  • Here, the “width of the slope part” refers to the length in the radial direction when the slope part is viewed from a direction perpendicular to the main surface.
  • The estimated mechanism of generation of the outer edge interface dislocation will be described using FIG. 4 .
  • FIGS. 4A and 4B are schematic sectional views showing two stages of a SiC substrate and growth of a SiC epitaxial film grown thereon (an upper drawing shows an initial stage of growth and a lower drawing shows that growth is completed). FIG. 4A shows a case where the width of the slope part is large, and FIG. 4B shows a case where the width of the slope part is small.
  • In the initial stage of the epitaxial growth, it is considered that a nucleus 7 that is the source of random growth is formed in the outer peripheral edge part 1Ab. The reason is as follows.
  • In the flat part 1 a of the main surface, the epitaxial film 5 is formed by step flow growth, and also in the slope part 1Aa, the step flow growth is maintained if the c-plane is dominant. Since it is common to practically use a SiC substrate with an off angle, it is considered that the step flow growth is maintained, and a probability of forming the nucleus 7 that is the source of random growth is low. On the other hand, in the outer peripheral edge part 1Ab, a surface other than the c-plane (an r-plane or an m-plane) becomes dominant. Accordingly, it can be considered that, in the outer peripheral edge part 1Ab, the step flow growth hardly occurs, and random growth occurs.
  • Based on the estimated mechanism of generation of the outer edge interface dislocation with reference to FIG. 4A, the reason why the outer edge interface dislocation has not been discovered until now can be considered as follows.
  • Even if a polymorphous epitaxial film extends from the nucleus 7 that is formed on the outer peripheral edge part 1Ab and is the source of random growth when epitaxial growth is performed, the outer edge interface dislocation found by the present inventors is not generated in a case where the interface dislocation does not reach the flat part until a film thickness of the epitaxial film 5 increases to be a desired film thickness. In the related art, it is considered that since the desired film thickness of the epitaxial film was thin, this situation occurs, that is, the interface dislocation did not reach the flat part.
  • On the other hand, in trend of demanding a thick epitaxial film with high-quality, the present inventors found the outer edge interface dislocation in the thick-film epitaxial film.
  • On the other hand, as shown in FIG. 4B, a substrate having a slope part with a small width (a distance from the outer peripheral edge part to the flat part is short), it is considered that, even in a case where the epitaxial film is thin, the outer edge interface dislocation is generated on the flat part.
  • FIG. 5 shows results of examining a relationship between a film thickness of an epitaxial film and the presence or absence of generation of the outer edge interface dislocation, when the slope part has a predetermined width.
  • In the graph shown in FIG. 5 , the symbol “◯” indicates that there is no outer edge interface dislocation, and the symbol “×” indicates that there is an outer edge interface dislocation. In the table, a dotted line indicates a boundary where a density of the outer edge interface dislocation is zero.
  • A sample from which data was acquired was obtained as follows. Using a 4 or 6 inch 4H—SiC single crystal substrate having an off angle of 4° with respect to the (0001) Si surface in a <11-20> direction, a known polishing step and a substrate surface cleaning (etching) step were performed. Thereafter, a SiC epitaxial growth step (a growth temperature is 1600° C. and a C/Si ratio is 1.22) was performed using silane and propane as source gases while supplying hydrogen as a carrier gas. In this way, a SiC epitaxial layer with a predetermined film thickness was formed on a SiC single crystal substrate to obtain a SiC epitaxial wafer.
  • In FIG. 5 , “0 μm of slope part” refers to slope in which a SiC single crystal substrate was only chamfered, and an angle of the chamfered portion exceeds 60°. Therefore, in accordance with the above definition of the slope part, this portion is not included in the slope part (accordingly, in this SiC single crystal substrate, the bevel part includes only the outer peripheral edge part).
  • In a case of using a SiC single crystal substrate with “0 μm of slope part”, when the film thickness of the SiC epitaxial film was 6 μm, 9 μm, or 18 μm, there was no outer edge interface dislocation, but when the film thickness was 24 μm or 33 μm, the outer edge interface dislocation was generated. In each of 24 μm and 33 μm, the dislocation density of the outer edge interface dislocation was 50 lines/cm or higher.
  • In a case of using a SiC single crystal substrate with “60 μm of slope part” (an inclined angle of the slope part was 25°), when the film thickness of the SiC epitaxial film was 12 μm or 16 μm, there was no outer edge interface dislocation, but when the film thickness was 33 μm, the outer edge interface dislocation was generated. In the case of 33 μm, the dislocation density of the outer edge interface dislocation was 24 lines/cm.
  • In a case of using a SiC single crystal substrate with “150 μm of slope part” (an inclined angle of the slope part was 23°), when the film thickness of the SiC epitaxial film was 6 μm, 11 μm, 15 μm, or 18 μm, there was no outer edge interface dislocation, but when the film thickness was 33 μm or 38 μm, the outer edge interface dislocation was generated. In the cases of 33 μm and 38 μm, the dislocation density of the outer edge interface dislocation was 20 lines/cm and 41 lines/cm, respectively.
  • In a case of using a SiC single crystal substrate with “170 μm of slope part” (an inclined angle of the slope part was 23°), when the film thickness of the SiC epitaxial film was 28 μm, there was no outer edge interface dislocation.
  • For this sample, FIG. 6A shows a microscope image obtained by using a confocal microscope (SICA88, manufactured by Lasertec Corporation) which is a surface inspection device that uses a confocal differential interference optical system. In addition, FIG. 6B shows a PL image thereof.
  • In a case of using a SiC single crystal substrate with “200 μm of slope part” (an inclined angle of the slope part was 11°), when the film thickness of the SiC epitaxial film was 13 μm or 27.5 μm, there was no outer edge interface dislocation, but when the film thickness was 32 μm, the outer edge interface dislocation was generated. In the case of 32 μm, the dislocation density of the outer edge interface dislocation was 18 lines/cm.
  • In FIG. 5 , when a horizontal axis (X axis) is the film thickness of the SiC epitaxial film and a vertical axis (Y axis) is the width of the inclined part, if an estimated boundary of presence or absence of generation of the outer edge interface dislocation is represented linearly, this can be expressed as Y=20X−400 . . . (1).
  • Based on Formula (1), when processing the width of the inclined part and selecting the film thickness of the SiC epitaxial film in order to satisfy Inequality Y>20X−400, a SiC epitaxial wafer which has no outer edge interface dislocation, or has a low density of the outer edge interface dislocation can be obtained.
  • The processing of the width of the inclined part can be performed using a known method. For example, contouring or the like can be used (see Patent Document 1).
  • Based on FIG. 5 and Formula (1), in a case of using a SiC single crystal substrate in which the width of the slope part is 50 μm, a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 22 μm. In addition, in a case of using a SiC single crystal substrate in which the width of the slope part is 100 μm, a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 24 μm. In addition, in a case of using a SiC single crystal substrate in which the width of the slope part is 150 μm, a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 27 μm. In addition, in a case of using a SiC single crystal substrate in which the width of the slope part is 200 μm, a SiC epitaxial wafer with no density of the outer edge interface dislocation can be obtained until the thickness of the SiC epitaxial film arrives at 29 μm.
  • FIGS. 7A and 7B show a PL image of a sample in a case where the inclined part is 150 μm and the film thickness of the SiC epitaxial film is 33 μm and a PL image of a sample in a case were the inclined part is 0 μm and the film thickness of the SiC epitaxial film is 33 μm, respectively, shown in FIG. 5 .
  • In the PL image of FIG. 7A, the presence of 7 lines of interface dislocations can be confirmed from the number of L-shaped dislocations schematically shown in FIG. 8 .
  • In the PL image of FIG. 7B, the presence of 50 or more lines of interface dislocations can be confirmed from the number of L-shaped dislocations schematically shown in FIG. 8 .
  • The 4H—SiC single crystal substrate used for the SiC epitaxial wafer of the present invention has an off angle of, for example, 0.4° or more and 8° or less. Typical examples thereof include an off angle of 4°.
    • “Method for Manufacturing SiC Epitaxial Wafer”
  • According to still another embodiment of the present invention, there is provided a method for manufacturing a SiC epitaxial wafer, in which a 4H—SiC single crystal substrate having a bevel part in a peripheral part, in which the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part and a width of the slope part is 150 μm or more, is used.
  • This method may include a step of preparing the H—SiC single crystal substrate and a step of forming a SiC epitaxial film having a film thickness of 20 μm or more on the H—SiC single crystal substrate. The step of forming the SiC epitaxial film having a film thickness of 20 μm or more may include a sub-step of determining a thickness of an epitaxial film, satisfying Formula (1), using a width of the slope part of the substrate to be used, and a sub-step of forming the SiC epitaxial film such that a thickness of a SiC epitaxial film to be manufactured is set to be equal to or smaller than the thickness of the epitaxial film, satisfying Formula (1), which is obtained by the aforementioned formula.

  • Y=20X−400  (1)
  • (in Formula, Y represents a width (μm) of slope and X represents a thickness (μm) of an epitaxial film)
  • In the method for manufacturing a SiC epitaxial wafer according to the present embodiment, a known step can be used except for the setting step using a predetermined 4H—SiC single crystal substrate to use the aforementioned SiC wafer (SiC substrate). In addition, according to still another embodiment of the present invention, a method of manufacturing a SiC epitaxial wafer preferably a method including:
  • a step of selecting a thickness of an epitaxial film from a range of 20 μm or more;
  • a step of determining a width of slope satisfying Formula (1), using the selected thickness of the epitaxial film,

  • Y=20X−400  (1)
  • (in Formula, Y represents a width (μm) of slope and X represents a thickness (μm) of an epitaxial film);
  • a step of preparing a 4H—SiC single crystal substrate having a bevel part on a peripheral part in which a width of slope thereof is equal to or more than a value of the determined width of the slope obtained by Formula (1); and
  • a step of growing an epitaxial film with the determined thickness by using the prepared 4H—SiC single crystal substrate.
  • In the method for manufacturing a SiC epitaxial wafer of the present invention, the SiC epitaxial wafer of the present invention can be preferably manufactured.
    • INDUSTRIAL APPLICABILITY
  • The present invention provides a SiC epitaxial wafer having a SiC epitaxial film having a film thickness of 20 μm or more and a low density of an outer edge interface dislocation.
    • REFERENCE SIGNS LIST
      • 1 SiC single crystal substrate
      • 1 a Main surface (Flat part)
      • 1A Bevel part
      • 1Aa Slope part
      • 1Ab Outer peripheral edge part
      • 2 SiC epitaxial layer
      • 2 a Outer peripheral edge
      • 3 Width of slope part
      • 4 Orientation flat
      • 5 Epitaxial film
      • 9 TED pair
      • 10 SiC epitaxial wafer
      • 11 Pair array
      • 12 Interface
      • 13 Substrate
      • 14 Interface Transition
      • 15 Basal plane dislocation
      • 16 (0001) Basal plane
      • A Boundary at which outer edge interface dislocation density becomes zero
      • Y=20X−400

Claims (2)

What is claimed is:
1. A SiC epitaxial wafer comprising:
a 4H—SiC single crystal substrate which has
a surface with an off angle with respect to a c-plane as a main surface and
a bevel part on a peripheral part; and
a SiC epitaxial film having a film thickness of 20 μm or more, which is formed on the 4H—SiC single crystal substrate,
wherein the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and
a width of the slope part is 150 μm or more.
2. The SiC epitaxial wafer according to claim 1,
wherein the SiC epitaxial film is formed on the main surface and the bevel part of the substrate.
US18/309,111 2017-06-28 2023-04-28 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME Pending US20230268177A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/309,111 US20230268177A1 (en) 2017-06-28 2023-04-28 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2017-126744 2017-06-28
JP2017126744A JP7133910B2 (en) 2017-06-28 2017-06-28 SiC epitaxial wafer
PCT/JP2018/018498 WO2019003668A1 (en) 2017-06-28 2018-05-14 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME
US201916620088A 2019-12-06 2019-12-06
US18/309,111 US20230268177A1 (en) 2017-06-28 2023-04-28 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US16/620,088 Division US11705329B2 (en) 2017-06-28 2018-05-14 SiC epitaxial wafer and method for manufacturing same
PCT/JP2018/018498 Division WO2019003668A1 (en) 2017-06-28 2018-05-14 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME

Publications (1)

Publication Number Publication Date
US20230268177A1 true US20230268177A1 (en) 2023-08-24

Family

ID=64740550

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/620,088 Active 2039-07-22 US11705329B2 (en) 2017-06-28 2018-05-14 SiC epitaxial wafer and method for manufacturing same
US18/309,111 Pending US20230268177A1 (en) 2017-06-28 2023-04-28 SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US16/620,088 Active 2039-07-22 US11705329B2 (en) 2017-06-28 2018-05-14 SiC epitaxial wafer and method for manufacturing same

Country Status (5)

Country Link
US (2) US11705329B2 (en)
JP (1) JP7133910B2 (en)
CN (1) CN110709963B (en)
DE (1) DE112018003360T5 (en)
WO (1) WO2019003668A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3567139B1 (en) 2018-05-11 2021-04-07 SiCrystal GmbH Chamfered silicon carbide substrate and method of chamfering
EP3567138B1 (en) * 2018-05-11 2020-03-25 SiCrystal GmbH Chamfered silicon carbide substrate and method of chamfering

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034776A (en) 2006-07-31 2008-02-14 M Tec Kk Treatment method of work edge and treatment device
WO2008120469A1 (en) 2007-03-29 2008-10-09 Panasonic Corporation Method for manufacturing silicon carbide semiconductor element
US8293623B2 (en) * 2007-09-12 2012-10-23 Showa Denko K.K. Epitaxial SiC single crystal substrate and method of manufacture of epitaxial SiC single crystal substrate
JP5304713B2 (en) 2010-04-07 2013-10-02 新日鐵住金株式会社 Silicon carbide single crystal substrate, silicon carbide epitaxial wafer, and thin film epitaxial wafer
JP4850960B2 (en) 2010-04-07 2012-01-11 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate manufacturing method
JP5961357B2 (en) * 2011-09-09 2016-08-02 昭和電工株式会社 SiC epitaxial wafer and manufacturing method thereof
JP6069758B2 (en) 2012-08-26 2017-02-01 国立大学法人名古屋大学 Method for producing SiC single crystal
JP5803979B2 (en) * 2013-05-29 2015-11-04 住友電気工業株式会社 Silicon carbide substrate and silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate and silicon carbide semiconductor device
JP6315579B2 (en) 2014-07-28 2018-04-25 昭和電工株式会社 Method for manufacturing SiC epitaxial wafer
JP6601956B2 (en) 2014-12-19 2019-11-06 昭和電工株式会社 Wafer support, SiC epitaxial wafer manufacturing apparatus and method including the same
JP2017050446A (en) 2015-09-03 2017-03-09 住友電気工業株式会社 Silicon carbide epitaxial substrate and silicon carbide semiconductor device manufacturing method
JP2017108026A (en) 2015-12-10 2017-06-15 国立研究開発法人産業技術総合研究所 Method of manufacturing silicon carbide semiconductor substrate, silicon carbide semiconductor substrate, semiconductor device, and method of manufacturing semiconductor device
JP2018108916A (en) 2016-12-28 2018-07-12 住友電気工業株式会社 Method for manufacturing silicon carbide epitaxial substrate

Also Published As

Publication number Publication date
CN110709963A (en) 2020-01-17
WO2019003668A1 (en) 2019-01-03
US11705329B2 (en) 2023-07-18
CN110709963B (en) 2023-06-23
JP2019009400A (en) 2019-01-17
JP7133910B2 (en) 2022-09-09
DE112018003360T5 (en) 2020-03-05
US20200203163A1 (en) 2020-06-25

Similar Documents

Publication Publication Date Title
US20230268177A1 (en) SiC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME
JP5273741B2 (en) Epitaxial SiC single crystal substrate and method of manufacturing epitaxial SiC single crystal substrate
CN109642342B (en) SiC epitaxial wafer, method for producing same, and defect detection method
JP6762484B2 (en) SiC epitaxial wafer and its manufacturing method
US9966249B2 (en) Silicon carbide semiconductor substrate and method for manufacturing same
CN107407007B (en) SiC epitaxial wafer and method for producing SiC epitaxial wafer
US10837123B2 (en) Method of manufacturing SiC ingot
JP2010076967A (en) Production method of silicon carbide substrate, and silicon carbide substrate
CN112930423B (en) Method for manufacturing nitride semiconductor substrate, and laminated structure
US11320388B2 (en) SiC epitaxial wafer containing large pit defects with a surface density of 0.5 defects/CM2 or less, and production method therefor
JP6405767B2 (en) Gallium nitride substrate
JP6635579B2 (en) SiC epitaxial wafer
US10985042B2 (en) SiC substrate, SiC epitaxial wafer, and method of manufacturing the same
CN113166970B (en) Method for manufacturing nitride semiconductor substrate and laminated structure
JP6583989B2 (en) SiC single crystal seed, SiC ingot, method for producing SiC single crystal seed, and method for producing SiC single crystal ingot
JP2018104231A (en) MANUFACTURING METHOD OF SiC WAFER AND SiC WAFER
JP7302716B2 (en) SiC epitaxial wafer and manufacturing method thereof
JP2018016542A (en) Silicon carbide semiconductor substrate
JP2013209273A (en) Periodic table group 13 metal nitride semiconductor crystal
EP4064326A1 (en) Silicon carbide epitaxial substrate and method for manufacturing same
JP2014108916A (en) Production method of silicon carbide substrate
JP2017109912A (en) SiC SEED, SiC INGOT, SiC WAFER, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD OF SEMICONDUCTOR DEVICE
KR20220014873A (en) GaN substrate wafer and its manufacturing method

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

AS Assignment

Owner name: RESONAC CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:SHOWA DENKO K.K.;REEL/FRAME:065657/0874

Effective date: 20231002