JP7302716B2 - SiC epitaxial wafer and manufacturing method thereof - Google Patents

Description

The present invention relates to a SiC epitaxial wafer and its manufacturing method.

Silicon carbide (SiC) has properties such as a dielectric breakdown field that is one order of magnitude larger than silicon (Si), a bandgap that is three times larger, and a thermal conductivity that is approximately three times higher. Since silicon carbide has these characteristics, it is expected to be applied to power devices, high-frequency devices, high-temperature operation devices, and the like. Therefore, in recent years, SiC epitaxial wafers have come to be used for such semiconductor devices.

Establishment of high-quality crystal growth technology and high-quality epitaxial growth technology is indispensable for promoting the practical use of SiC devices.

SiC devices are manufactured by chemical vapor deposition (Chemical It is generally manufactured using a SiC epitaxial wafer on which a SiC epitaxial layer (film), which will be the active region of the device, is grown by Vapor Deposition (CVD) or the like.

More specifically, the SiC epitaxial wafer is step-flow grown (lateral growth from atomic steps) on a SiC single crystal substrate whose growth surface is a plane having an off-angle in the <11-20> direction from the (0001) plane. It is common to grow a 4H SiC epitaxial layer.

Crystal defects called Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), or Basal Plane Dislocation (BPD) are generally present in SiC single crystal substrates. These crystal defects may degrade device characteristics. These dislocations basically propagate from the SiC single crystal substrate to the SiC epitaxial film.

On the other hand, it is known that dislocations called interfacial dislocations occur in the SiC epitaxial film. This interfacial dislocation is a type of basal plane dislocation, and is a direction orthogonal to the offcut direction of the SiC substrate near the interface between the SiC substrate and the SiC epitaxial film (when the offcut direction is <11-20> is stretched in the <1-100> direction). Interfacial dislocations are considered to be elongated in order to relax the stress in the vicinity of the interface.

Furthermore, not only threading edge dislocations propagated from the SiC single crystal substrate, but also threading edge dislocation arrays (“TED pairs” in FIG. 8) may be formed in the SiC epitaxial film. Specifically, when two threading edge dislocations newly generated during epitaxial growth form a pair and the offcut direction is <11-20>, the pair of these two dislocations is <1-100 > direction, forming a threading edge dislocation array. As a result of the occurrence of threading edge dislocation arrays, the epitaxial film has a higher dislocation density than the SiC single crystal substrate, which may deteriorate the crystallinity in epitaxial growth. The pair of threading edge dislocations are connected in a half-loop shape by basal plane dislocations at their bottoms.

JP-A-2008-34776

X. Zhang et al., Journal of Applied Physics 102, 093520 (2007)

In Non-Patent Document 1, the relationship between the occurrence of threading edge dislocation arrays and the interfacial dislocations clarified based on observation by X-ray topography, photoluminescence (PL), etc., and X-ray topography images and PL Features of the image will be described with reference to FIG.
FIG. 8 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate.

In the X-ray topography image, L-shaped dislocations are observed. This L-shaped dislocation is obtained by observing the AB portion (interface dislocation) and the BC portion (basal plane dislocation) in FIG. The BC part traverses the SiC epitaxial film while resting on the (0001) basal plane and terminates at point C on the surface of the SiC epitaxial film. During epitaxial growth, the BC portion of the L-shaped dislocation moves rightward, and along with this, the AB portion (interfacial dislocation) extends rightward. In this way, when the AB portion (interface dislocation) extends to the right, threading edge dislocation arrays ("TED pairs" in FIG. 8) are sequentially formed at the portion C, forming an array of threading edge dislocation arrays ( A structure in which threading edge dislocation arrays are arranged in a direction orthogonal to the step flow direction is hereinafter referred to as a pair array). Thus, generation of threading edge dislocation arrays and interfacial dislocations are closely related.
In the X-ray topography image, the image of the threading edge dislocation arrays is present at a position shallower from the surface as it goes to the right side, so the contrast becomes weaker.
In the X-ray topography image, all of AB portion (interface dislocation), BC portion (basal plane dislocation) and threading edge dislocation arrays are often observed.

On the other hand, in a photoluminescence (PL) image, the array of threading edge dislocation arrays is observed as an array of dots, and the BC portions (basal plane dislocations) are observed linearly. On the other hand, it is difficult to observe the AB portion (interfacial dislocation).
Therefore, by observing the array of dots and the linear pattern corresponding to the BC portion (basal plane dislocation) in the PL image, the presence of interfacial dislocations can be known.
The array of threading edge dislocation arrays extends perpendicular to the step flow direction, and the array of one threading edge dislocation array and one interfacial dislocation caused by the array of threading edge dislocation arrays extend parallel to each other. Therefore, by finding an array of single dots, the existence of one interfacial dislocation extending perpendicular to the step flow direction can be confirmed. In addition, the BC portion (basal plane dislocation) extends parallel to the step flow direction, and one BC portion (basal plane dislocation) and one interfacial dislocation caused by the BC portion (basal plane dislocation) extend perpendicular to each other. Therefore, by finding a linear pattern corresponding to one BC portion (basal plane dislocation), the existence of one interfacial dislocation extending perpendicular to the step flow direction can be confirmed.

The conventionally known interfacial dislocations described above occur at locations where basal plane dislocations (BPDs) exist in the SiC substrate.

On the other hand, the present inventors discovered new interfacial dislocations (hereinafter referred to as "outer edge interfacial dislocations") extending from the outer edge of the SiC substrate when the SiC epitaxial film is grown on the SiC substrate. bottom. The inventor of the present invention has made intensive research on the outer edge interface dislocations and discovered that the dislocations are generated by increasing the thickness of the SiC epitaxial film. Conventional interfacial dislocations originate from the location of the BPD of the SiC substrate, but interfacial dislocations (outer edge interfacial dislocations) discovered by the present inventor originate from the outer peripheral edge of the SiC substrate. This interfacial dislocation, like the conventional interfacial dislocation, lowers the reliability of the device and should be reduced.
The reason why the outer edge interface dislocations have not been found so far is considered to be that the thickness of the SiC epitaxial film was not so thick as to cause outer edge interface dislocations.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a SiC epitaxial wafer having a SiC epitaxial film with a thickness of 20 μm or more and a low outer edge interface dislocation density, and a method for manufacturing the same. .

In order to solve the above problems, the present invention provides the following means.

(1) A SiC epitaxial wafer according to an aspect of the present invention includes a 4H—SiC single crystal substrate having a main surface having an off-angle with respect to the c-plane and a bevel portion in the peripheral portion, and the 4H—SiC single a SiC epitaxial layer having a thickness of 20 μm or more formed on a crystal substrate, and an interfacial dislocation density extending from an outer peripheral end of the SiC epitaxial layer is 10/cm or less.

(2) A SiC epitaxial wafer according to an aspect of the present invention includes a 4H—SiC single crystal substrate having a main surface having an off-angle with respect to the c-plane and a bevel portion in the peripheral edge portion, and the 4H—SiC single a SiC epitaxial layer having a thickness of 20 μm or more formed on a crystal substrate, wherein the bevel portion includes a slope portion continuous from the main surface and an outer peripheral edge portion, and the width of the slope portion is 150 μm. That's it.

(3) In the SiC epitaxial wafer according to any one of (1) or (2) above, 25° to 155° and 205° to 335° The interfacial dislocation density in the central angle range may be 10/cm or less.

(4) A method for manufacturing a SiC epitaxial wafer according to an aspect of the present invention is a 4H—SiC single crystal substrate having a beveled portion on a peripheral portion, wherein the beveled portion comprises a sloped portion continuous from the main surface and an outer periphery. A 4H—SiC single crystal substrate is used in which the width of the slope portion is 150 μm or more.

According to the SiC epitaxial wafer of the present invention, it is possible to provide a SiC epitaxial wafer having a SiC epitaxial film with a thickness of 20 μm or more and a low density of outer edge interface dislocations.

It is a cross-sectional schematic diagram of the peripheral part vicinity of a SiC single crystal substrate. It is a cross-sectional schematic diagram of the periphery part vicinity of a SiC epitaxial wafer. Schematic showing PL images and observation points obtained for a SiC epitaxial wafer, (a) PL image at the position of the orientation flat, (b) PL image at the position opposite the orientation flat, (c) ) is a schematic diagram showing the relationship between the position of the orientation flat in the SiC epitaxial wafer and the direction of the step flow. It is a cross-sectional schematic diagram showing two stages of the growth of the SiC substrate and the SiC epitaxial film grown thereon, (a) is when the width of the slope portion is large, and (b) is when the width of the slope portion is small. be. FIG. 5 is a diagram showing the results of examining the relationship between the thickness of an epitaxial film and the presence or absence of occurrence of outer-end interface dislocations; 5A and 5B are images when the slope is 170 μm and the film thickness of the SiC epitaxial film is 28 μm, where (a) is a confocal microscope image and (b) is a PL image. (a) is a PL image when the slope portion is 150 μm and the thickness of the SiC epitaxial film is 33 μm, and (b) is a PL image when the slope portion is 0 μm and the thickness of the SiC epitaxial film is 33 μm. It is a PL image in the case of FIG. 2 is a perspective view schematically showing a SiC epitaxial wafer in which a SiC epitaxial film is formed on a SiC single crystal substrate, for explaining the relationship between the generation of threading edge dislocation arrays and interfacial dislocations;

A SiC epitaxial wafer and a method for manufacturing the same, which are embodiments to which the present invention is applied, will be described in detail below with reference to the drawings. In addition, in the drawings used in the following explanation, in order to make the features easier to understand, the characteristic portions may be enlarged for convenience, and the dimensional ratios of each component may not necessarily be the same as the actual ones. do not have. In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be modified as appropriate within the scope of its effects.

(SiC epitaxial wafer)
A SiC epitaxial wafer according to one embodiment of the present invention includes a 4H-SiC single crystal substrate having a main surface having an off-angle with respect to the c-plane and a bevel portion on the peripheral edge, and the 4H-SiC single crystal substrate. a SiC epitaxial layer having a thickness of 20 μm or more formed thereon;
The density of interfacial dislocations extending from the outer peripheral edge of the SiC epitaxial layer is 10/cm or less.
"Interfacial dislocations extending from the outer edge" may be referred to as "outer edge interfacial dislocations".
The c plane indicates the {0001} plane. The (0001) plane inside the c-plane is referred to as the (0001) Si plane.

The density of interfacial dislocations extending from the outer edge can be measured, for example, from a photoluminescence (PL) image. As the PL image, for example, a PL image obtained at a near-infrared (NIR) receiving wavelength using a photoluminescence device (SICA88, manufactured by Lasertec Co., Ltd.) can be used.

The SiC epitaxial wafer of the present invention includes a SiC epitaxial layer having a film thickness of 20 μm or more and having a density of interfacial dislocations of outer edge interfacial dislocations of zero lines/cm.
Further, the SiC epitaxial wafer of the present invention includes a SiC epitaxial layer having a film thickness of 22 μm or more and having a density of interfacial dislocations of outer edge interfacial dislocations of zero lines/cm.
Further, the SiC epitaxial wafer of the present invention includes a SiC epitaxial layer having a film thickness of 24 μm or more and having a density of interfacial dislocations of outer edge interfacial dislocations of zero lines/cm.
Further, the SiC epitaxial wafer of the present invention includes a SiC epitaxial layer having a film thickness of 27 μm or more and having a density of interfacial dislocations of outer edge interfacial dislocations of zero lines/cm.
Further, the SiC epitaxial wafer of the present invention includes a SiC epitaxial layer having a film thickness of 29 μm or more and having a density of interfacial dislocations of outer edge interfacial dislocations of zero lines/cm.

FIG. 1 is a schematic cross-sectional view of the vicinity of the peripheral portion of a SiC single crystal substrate.
The shape of the “bevel portion” referred to in this specification will be described with reference to FIG. In this specification, the “bevel portion” refers to a portion of the peripheral portion of the substrate that is chamfered in order to prevent chipping of the substrate and generation of particles, and is thinner than the thickness of the substrate.

The SiC single crystal substrate 1 has a main surface (flat portion) 1a and a bevel portion 1A consisting of a slope portion 1Aa and an outer peripheral end portion 1Ab on the periphery thereof.
The “slope portion” is a portion continuous from the flat portion 1a of the SiC single crystal substrate, and is inclined toward the outer periphery at a predetermined angle of 60° or less (angle with respect to the plane including the main surface) with respect to the flat portion. It is a portion having an inclined surface that is However, the slanted surface is not limited to a slanted surface with only one angle, and may have slanted surfaces with multiple angles or a curved surface with a curvature (smaller than the curvature of the "peripheral edge"). It can be a face. In the case of an inclined surface with curvature, the angle of the inclined surface means the angle of the tangent plane. A SiC single crystal substrate may be used in which the angle of the inclined surface of the “slope portion” (the angle with respect to the plane including the main surface) is 50° or less, 40° or less, 30° or less, or 20° or less. The data shown in FIG. 5, which will be described later, is for the case of using a SiC single crystal substrate of 30° or less.
In addition, the “peripheral edge portion” is a portion of the SiC single crystal substrate that is arranged on the outermost side in the radial direction and includes a curved surface having a predetermined curvature. However, the curved surface is not limited to a curved surface with only one curvature, but a curved surface with multiple curvatures, or a portion that does not continue to the “slope portion” among the parts that constitute the “peripheral end” It may be planar (eg, vertical). In addition, based on the presumed mechanism of generation of the outer end interfacial dislocations, which will be described later, if there is no "peripheral edge" and the structure is vertically steep outside from the "slope portion", random growth will occur. It is thought that there may be no place where such a nucleus is formed. It is normal to have a "part".

FIG. 2 is a schematic cross-sectional view of the vicinity of the peripheral portion of the SiC epitaxial wafer.
In the SiC epitaxial wafer 10, the outer peripheral edge 2a of the SiC epitaxial layer 2 refers to the radially outermost portion of the SiC epitaxial layer 2 formed on the main surface (flat portion) 1a of the SiC single crystal substrate 1. and

FIGS. 3(a) and 3(b) show PL images obtained for the SiC epitaxial wafer. FIG. 3(c) is a schematic diagram showing the relationship between the position of the orientation flat in the SiC epitaxial wafer and the direction of the step flow.
FIG. 3(a) is a PL image at the position of the orientation flat, and FIG. 3(b) is a PL image at the position on the opposite side of the orientation flat.
In both FIGS. 3(a) and 3(b), an array of dots and linear patterns corresponding to BC portions (basal plane dislocations) can be observed. In FIG. 3(a), one linear pattern corresponding to the dot array and the BC portion (basal plane dislocation) can be observed, so the existence of one outer edge interfacial dislocation can be known. . In addition, in FIG. 3(b), two linear patterns corresponding to the dot array and the BC portion (basal plane dislocation) can be observed, respectively, so the existence of two outer edge interfacial dislocations can be known. be able to.

Based on the PL observation, the outer edge interfacial dislocations are most abundant near the orientation flat, followed by the outer edge interfacial dislocations on the opposite side of the orientation flat. On the other hand, since the orientation flat and the opposite side of the orientation flat are almost parallel to the step flow direction, almost no outer edge interfacial dislocations occur. Outer interface dislocations often occur at central angles of 25° to 155° and 205° to 335° with respect to the center of the wafer.

A SiC epitaxial wafer according to another embodiment of the present invention includes a 4H—SiC single crystal substrate having a main surface having an off-angle with respect to the c-plane and a bevel portion in the peripheral portion, and the 4H—SiC single crystal a SiC epitaxial layer having a thickness of 20 μm or more formed on a substrate, wherein the bevel portion includes a slope portion continuous from the main surface and an outer peripheral edge portion, and the width of the slope portion is 150 μm or more. is.
Here, the "width of the slope" refers to the length in the radial direction when the slope is viewed from the direction perpendicular to the main surface.

A presumed mechanism of generation of outer-end interfacial dislocations will be described with reference to FIG.
4(a) and 4(b) are schematic cross-sectional views showing two stages of the growth of the SiC substrate and the SiC epitaxial film grown thereon (the upper figure is the initial stage of growth, and the lower figure is the completed stage of growth). ), (a) is the case where the width of the slant portion is large, and (b) is the case where the width of the slant portion is small.
It is considered that at the initial stage of epitaxial growth, nuclei are formed at the outer peripheral end portion 1Ab as sources of random growth. The reason for this is as follows.
An epitaxial film is formed by step-flow growth on the flat portion 1a, and step-flow growth is maintained on the slope portion 1Aa if the c-plane is dominant. Since it is common to actually use an off-angle SiC substrate, it is considered that the step flow growth is maintained and the probability of forming nuclei that cause random growth is low. On the other hand, at the outer peripheral end portion 1Ab, planes other than the c-plane (r-plane and m-plane) are dominant. Therefore, step-flow growth is unlikely to occur in the outer peripheral edge portion 1Ab, and it can be considered that the growth is random.

With reference to FIG. 4(a), based on the presumed mechanism of generation of outer edge interface dislocations, the reason why outer edge interface dislocations have not been discovered so far can be considered as follows.
Even if the polymorphic epitaxial film extends from the nucleus that is the source of random growth formed at the edge of the outer circumference until the film thickness of the epitaxial film increases until it reaches the desired film thickness, the interfacial dislocations are flat. When it did not reach the part, the outer edge interfacial dislocations found by the inventors did not occur. It is considered that such a situation occurred because conventionally, the film thickness of the desired epitaxial film was thin.
On the other hand, in the trend of demanding a thick epitaxial film of high quality, the present inventors discovered outer edge interfacial dislocations in a thick epitaxial film.

On the other hand, in FIG. 4(b), it is thought that outer edge interfacial dislocations occur in a substrate with a small width of the slanted portion (a short distance from the outer edge to the flat portion) even if the thickness of the epitaxial film is thin. be done.

FIG. 5 shows the result of examining the relationship between the thickness of the epitaxial film and the presence or absence of occurrence of outer edge interface dislocations when the width of the slope portion is predetermined.
The samples for which data were acquired were obtained as follows. Using a 4 or 6 inch 4H—SiC single crystal substrate having an off angle of 4° in the <11-20> direction with respect to the (0001) Si plane, a known polishing process and substrate surface cleaning (etching) process After that, a SiC epitaxial growth step (growth temperature: 1600° C., C/Si ratio: 1.22) is performed using silane and propane as raw material gases and supplying hydrogen as a carrier gas to obtain a predetermined film thickness. A SiC epitaxial layer was formed on the SiC single crystal substrate to obtain a SiC epitaxial wafer.

In FIG. 5 , “slope portion 0 μm” is a slope where only the SiC single crystal substrate is chamfered and the angle of the chamfered portion exceeds 60°, so the above definition of the slope portion In addition, this portion is not included in the slope portion (therefore, in this SiC single crystal substrate, the bevel portion consists only of the outer peripheral end portion).
When using a SiC single crystal substrate with a “slope portion of 0 μm”, when the thickness of the SiC epitaxial film was 6 μm, 9 μm, and 18 μm, there was no outer edge interface dislocation, but when the thickness was 24 μm and 33 μm, the outer edge interface dislocation was occurring. The dislocation density of outer edge interfacial dislocations was 50 lines/cm or more at each of 24 μm and 33 μm.

When using a SiC single crystal substrate with a "slope portion of 60 μm" (the inclination angle of the slope portion was 25°), when the film thickness of the SiC epitaxial film was 12 μm and 16 μm, there was no outer edge interface dislocation, but the thickness of the SiC epitaxial film was 33 μm. At that time, outer edge interface dislocations were generated. At 33 μm, the dislocation density of outer edge interfacial dislocations was 24 lines/cm.

When a SiC single crystal substrate having a “slant portion of 150 μm” was used (the tilt angle of the slant portion was 23°), outer edge interface dislocations did not occur when the film thickness of the SiC epitaxial film was 6 μm, 11 μm, 15 μm, and 18 μm. However, outer edge interfacial dislocations were generated at 33 μm and 38 μm. The dislocation densities of outer edge interfacial dislocations were 20/cm and 41/cm at 33 μm and 38 μm, respectively.

When a SiC single crystal substrate having a "slope portion of 170 μm" was used (the inclination angle of the slope portion was 23°), there was no outer edge interface dislocation when the thickness of the SiC epitaxial film was 28 μm. FIG. 6(a) shows a microscopic image of this sample obtained by a confocal microscope (SICA88 manufactured by Lasertec Co., Ltd.), which is a surface inspection device using a confocal differential interference optical system, and FIG. 6(b). ) shows the PL image.

When a SiC single crystal substrate having a “slope portion of 200 μm” was used (the inclination angle of the slope portion was 11°), there was no outer edge interface dislocation when the thickness of the SiC epitaxial film was 13 μm or 27.5 μm. , and 32 μm, outer edge interfacial dislocations were generated. At 32 μm, the dislocation density of outer edge interfacial dislocations was 18 lines/cm.

In FIG. 5, when the horizontal axis (X-axis) is the film thickness of the SiC epitaxial film and the vertical axis (Y-axis) is the width of the inclined portion, the estimated boundary line for the occurrence of the outer-end interfacial dislocations is represented by a linear formula. represented as
Y=20X-400 (1)
can be written as
Based on the formula (1), by processing the width of the inclined portion and selecting the film thickness of the SiC epitaxial film so as to satisfy the inequality Y>20X-400, there is no outer edge interfacial dislocation, or A SiC epitaxial wafer with a low outer edge interface dislocation density can be obtained.
Processing of the width of the inclined portion can be performed using a known method. For example, contouring processing or the like can be used (see Patent Document 1).

Based on FIG. 5 and formula (1), when a SiC single crystal substrate having a slope portion width of 50 μm is used, a SiC epitaxial wafer having a SiC epitaxial film having a thickness of up to 22 μm and no outer edge interface dislocation density can be obtained. . Further, when a SiC single crystal substrate having a slope portion width of 100 μm is used, a SiC epitaxial wafer having a SiC epitaxial film having a thickness of up to 24 μm and having no outer edge interface dislocation density can be obtained. Further, when a SiC single crystal substrate having a slope portion width of 150 μm is used, a SiC epitaxial wafer having a SiC epitaxial film having a thickness of up to 27 μm and having no outer edge interface dislocation density can be obtained. Further, when a SiC single crystal substrate having a slope portion width of 200 μm is used, a SiC epitaxial wafer having a SiC epitaxial film having a thickness of up to 29 μm and having no outer edge interface dislocation density can be obtained.

7(a) and 7(b) are respectively the PL image and the thickness of the SiC epitaxial film with an inclination portion of 0 μm and a thickness of 33 μm when the inclination portion is 150 μm and the thickness of the SiC epitaxial film is 33 μm. is a PL image when is 33 μm.
From the number of L-shaped dislocations schematically shown in FIG. 8, seven interfacial dislocations can be confirmed in the PL image of FIG. 7(a).
From the number of L-shaped dislocations schematically shown in FIG. 8, the presence of 50 or more interfacial dislocations can be confirmed in the PL image of FIG. 7(b).

The 4H—SiC single crystal substrate used for the SiC epitaxial wafer of the present invention has an off-angle of, for example, 0.4° or more and 8° or less. A typical angle is 4°.

"Manufacturing method of SiC epitaxial wafer"
A method for manufacturing a SiC epitaxial wafer according to one embodiment of the present invention is a 4H-SiC single crystal substrate having a beveled portion on the peripheral edge, wherein the beveled portion comprises a sloped portion and an outer peripheral end portion that are continuous from the main surface. A 4H—SiC single crystal substrate is used in which the width of the slope portion is 150 μm or more.

In the SiC epitaxial wafer manufacturing method according to the present embodiment, a predetermined 4H—SiC single crystal substrate is used, and known steps can be used except for the step of setting the SiC wafer (SiC substrate) described above.

REFERENCE SIGNS LIST 1 SiC single crystal substrate 1a main surface 1A bevel portion 2 SiC epitaxial layer 2a outer peripheral edge 10 SiC epitaxial wafer

Claims (3)

a 4H—SiC single crystal substrate having a main surface having an off-angle with respect to the c-plane and having a bevel portion in the peripheral portion;
a SiC epitaxial layer having a thickness of 20 μm or more formed on the 4H—SiC single crystal substrate;
The SiC epitaxial layer is formed on the main surface and the bevel portion,
the bevel portion is composed of a slope portion and an outer peripheral end portion that are continuous from the main surface;
The inclined surface portion is a portion continuous from the main surface and has an inclined surface inclined toward the outer periphery at a predetermined angle of 60° or less with respect to a plane containing the main surface, A SiC epitaxial wafer that satisfies Y>20X-400, where the width of the slope portion is Y μm and the thickness of the SiC epitaxial layer is X μm. 2. The SiC epitaxial wafer according to claim 1, wherein the slope portion has a width of 150 μm or more. A method for manufacturing the SiC epitaxial wafer according to claim 1 or 2,
A 4H-SiC single crystal substrate having a beveled portion on its peripheral edge, wherein said beveled portion comprises a sloped portion continuous from a main surface of said 4H-SiC single crystal substrate and an outer peripheral end portion. using
A SiC epitaxial layer is formed on the main surface and the bevel portion of the 4H-SiC single crystal substrate,
A method of manufacturing a SiC epitaxial wafer, wherein the SiC epitaxial layer is formed so as to satisfy Y>20X-400 when the width of the slope portion is Y μm and the thickness of the SiC epitaxial layer is X μm.

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