US20230138460A1 - Method and system for manufacturing a semiconductor package structure - Google Patents
Method and system for manufacturing a semiconductor package structure Download PDFInfo
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- US20230138460A1 US20230138460A1 US18/089,458 US202218089458A US2023138460A1 US 20230138460 A1 US20230138460 A1 US 20230138460A1 US 202218089458 A US202218089458 A US 202218089458A US 2023138460 A1 US2023138460 A1 US 2023138460A1
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- package body
- tape
- film
- encapsulant
- unit
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 description 18
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
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- 230000001070 adhesive effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 8
- 239000004952 Polyamide Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229920002647 polyamide Polymers 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
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- 239000004593 Epoxy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Definitions
- the present disclosure relates to a method and system for manufacturing a semiconductor package structure, and to a method including a thinning step and a system for accomplishing the same.
- a molded wafer that is in an intermediate state of fabrication is thinned.
- the molded wafer may include a semiconductor die and a molding compound covering the semiconductor die.
- the thinned molded wafer may have a severe warpage due to the small thickness of the thinned molded wafer, and the CTE mismatch between the semiconductor die and the molding compound.
- the chuck may not handle the thinned molded wafer successfully.
- the following step may be difficult to be conducted to the warped and thinned molded wafer.
- a method for manufacturing a semiconductor package structure includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
- a system for manufacturing a semiconductor package structure includes a grinding unit, a film attaching unit and a tape removing unit.
- the grinding unit is used for grinding a package body with a tape.
- the film attaching unit is used for attaching a film to the package body.
- the tape removing unit is used for removing the tape from the package body.
- the film attaching unit is disposed between the grinding unit and the tape removing unit.
- FIG. 1 illustrates a schematic arrangement of a system for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 2 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 3 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 4 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 4 A illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 5 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 6 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 7 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 8 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 9 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 10 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 11 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 12 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 13 illustrates a schematic arrangement of a system for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 14 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- FIG. 15 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- first and second features are formed or disposed in direct contact
- additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- FIG. 1 illustrates a schematic arrangement of a system 5 for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- the system 5 may include a tape attaching unit 50 , a grinding unit 51 , an adhesive releasing unit 52 , a film attaching unit 53 , an overturning unit 54 , a tape removing unit 55 , a curing unit 56 , a marking unit 57 and a sawing unit 58 .
- the tape attaching unit 50 , the grinding unit 51 , the adhesive releasing unit 52 , the film attaching unit 53 , the overturning unit 54 , the tape removing unit 55 , the curing unit 56 , the marking unit 57 and the sawing unit 58 may be disposed or arranged in sequence. That is, a workpiece may be sequentially processed in the tape attaching unit 50 , the grinding unit 51 , the adhesive releasing unit 52 , the film attaching unit 53 , the overturning unit 54 , the tape removing unit 55 , the curing unit 56 , the marking unit 57 and the sawing unit 58 . That is, the workpiece may be delivered or transferred in such order.
- the film attaching unit 53 is disposed between the grinding unit 51 and the tape removing unit 55
- the overturning unit 54 is disposed between the film attaching unit 53 and the tape removing unit 55 .
- the tape attaching unit 50 and the film attaching unit 53 are used for attaching a tape of a film onto the workpiece.
- the grinding unit 51 is used for grinding a surface of the workpiece so as to thin the workpiece.
- the adhesive releasing unit 52 is used for releasing the adhesive of a tape on the workpiece.
- the overturning unit 54 is used for turning the workpiece over.
- the tape removing unit 55 is used for removing a tape from the workpiece.
- the curing unit 56 is used for curing or solidifying at least a portion of the workpiece.
- the marking unit 57 is used for forming a mark on or in the workpiece.
- the sawing unit 58 is used for sawing or cutting the workpiece into a plurality of singulated devices.
- FIG. 2 through FIG. 11 illustrate a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- the method is for manufacturing the semiconductor package structure 6 shown in FIG. 11 .
- a package body 1 may be formed on a carrier 9 .
- the carrier 9 may be a glass carrier, and may be in a wafer type, a panel type or a strip type.
- the package body 1 may be in a molded wafer type or in a molded panel type, and may have a first surface 11 (e.g., a top surface) and a second surface 12 (e.g., a bottom surface) opposite to the first surface 11 .
- the package body 1 may include at least one semiconductor device 13 , an encapsulant 14 , a redistribution structure 15 , a plurality of under bump metallurgies (UBMs) 154 and a plurality of external connectors 16 .
- the at least one semiconductor device 13 may include a plurality of semiconductor dice 13 disposed side by side.
- the semiconductor device 13 has a first surface 131 (e.g., an active surface), a second surface 132 (e.g., a backside surface) and a lateral side surface 133 .
- the first surface 131 (e.g., an active surface) of the semiconductor device 13 is adjacent to the first surface 11 of the package body 1 .
- the first surface 11 of the package body 1 is nearer the first surface 131 (e.g., an active surface) of the semiconductor device 13 than the second surface 12 of the package body 1 is.
- a distance between the first surface 11 of the package body 1 and the first surface 131 (e.g., an active surface) is less than a distance between the second surface 12 of the package body 1 and the first surface 131 (e.g., an active surface) of the semiconductor device 13 .
- the second surface 132 is opposite to the first surface 131 , and the lateral side surface 133 extends between the first surface 131 and the second surface 132 .
- the second surface 132 of the semiconductor device 13 may be disposed on or attached to the carrier 9 .
- the semiconductor device 13 may include a plurality of conductive pads 133 and a plurality of stud bumps 134 .
- the conductive pads 133 may include copper, aluminum or gold, and may be disposed adjacent to or exposed from the first surface 131 of the semiconductor device 13 .
- the stud bumps 134 may be disposed on the conductive pads 133 and may protrude from the first surface 131 of the semiconductor device 13 .
- the stud bump 134 may include copper (Cu), and may be in a pillar form.
- the encapsulant 14 may be a cured molding compound with or without fillers.
- the encapsulant 14 may cover the carrier 9 , the second surface 132 of the semiconductor device 13 , the lateral side surface 133 of the semiconductor device 13 and the stud bumps 134 of the semiconductor device 13 .
- the encapsulant 14 encapsulates the stud bumps 134 and the semiconductor device 13 .
- the semiconductor device 13 is encapsulated in the encapsulant 14 .
- the encapsulant 14 has a first surface 141 and a second surface 142 opposite to the first surface 141 .
- the first surface 141 of the encapsulant 14 may be ground, and the top surfaces of the stud bumps 134 may be substantially coplanar with the first surface 141 of the encapsulant 14 .
- the top surfaces of the stud bumps 134 may be exposed from the first surface 141 of the encapsulant 14 .
- the second surface 132 of the semiconductor device 13 may be substantially coplanar with the second surface 142 of the encapsulant 14 , and they may be the second surface 12 of the package body 1 .
- the redistribution structure 15 may be disposed on the first surface 141 of the encapsulant 14 , and may include a first dielectric layer 151 , an interconnection structure 152 and a second dielectric layer 153 .
- the first dielectric layer 151 may cover the encapsulant 14 , and may define a plurality of openings 1511 to expose the top surfaces of the stud bumps 134 .
- the first dielectric layer 151 may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof.
- PID cured photoimageable dielectric
- PA polyamide
- ABSF Ajinomoto build-up film
- BT bismaleimide-triazine
- PI polyimide
- PBO polybenzoxazole
- the interconnection structure 152 may be formed on a top surface of the first dielectric layer 151 and in the openings 1511 of the first dielectric layer 151 .
- the interconnection structure 152 may be a fan-out redistribution layer or a fan-in redistribution layer.
- the interconnection structure 152 may include a plurality of conductive traces 1521 and a plurality of conductive pads 1522 , 1523 .
- the conductive pads 1522 may be disposed in the openings 1511 of the first dielectric layer 151 and contact the top surfaces of the stud bumps 134 .
- the conductive pads 1523 may be disposed right under the UBMs 154 and may be also referred to as “capture lands”.
- the conductive traces 1521 extend between the conductive pads 1522 , 1523 .
- the conductive traces 1521 and the conductive pads 1522 , 1523 may be formed integrally and concurrently.
- the interconnection structure 152 may include one circuit layer; however, in other embodiments, the interconnection structure 152 may include a plurality of circuit layers electrically connected to one another.
- the second dielectric layer 153 may cover the first dielectric layer 151 and the interconnection structure 152 , and may define a plurality of openings 1531 to expose the conductive pads 1523 (i.e., the capture lands) of the interconnection structure 152 .
- the second dielectric layer 153 may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof.
- PA polyamide
- ABSF Ajinomoto build-up film
- BT bismaleimide-triazine
- PI polyimide
- PBO polybenzoxazole
- the UBMs 154 may be formed on a top surface of the second dielectric layer 153 and in the openings 1531 of the second dielectric layer 153 so as to contact the conductive pads 1523 (i.e., the capture lands) of the interconnection structure 152 .
- the external connectors 16 e.g., solder balls
- the external connectors 16 may be formed or disposed on the UBMs 154 .
- the external connectors 16 are disposed on the redistribution structure 15 .
- a flattening force may be provided or applied to the package body 1 .
- the package body 1 and the carrier 9 may be provided or moved to the tape attaching unit 50 ( FIG. 1 ).
- a tape 2 may be attached to or disposed on the first surface 11 of the package body 1 to cover the redistribution structure 15 of the package body 1 and the external connectors 16 . That is, the tape attaching unit 50 may be used for attaching the tape 2 to the first surface 11 of the package body 1 .
- the tape 2 may be a back grinding (BG) tape, and a thickness of the tape 2 may be greater than a thickness of the package body 1 .
- BG back grinding
- the thickness of the tape 2 may be about 500 ⁇ m, and the thickness of the package body 1 may be about 300 ⁇ m. Meanwhile, an assembly 4 including the tape 2 , the package body 1 and the carrier 9 is formed.
- the thick tape 2 e.g., the BG tape
- the thick tape 2 may provide stiffness and rigidity, which may provide flattening force to the package body 1 and reduce the warpage of the package body 1 .
- the flattening force may be further provided or applied to the package body 1 by holding the package body 1 on a flatterning chuck 9 ′.
- the assembly 4 of the tape 2 , the package body 1 and the carrier 9 is attached to or fixed on a flatterning chuck 9 ′ by suction, for example, vacuum suction. That is, the flatterning chuck 9 ′ is utilized to suck the assembly 4 of the tape 2 , the package body 1 and the carrier 9 .
- the flatterning chuck 9 ′ has a receiving surface 91 ′, and includes a plurality of suction holes 93 ′.
- Each of the suction holes 93 ′ is communicated with a vacuum source, and has an opening at the receiving surface 91 ′.
- the assembly 4 is sucked on the receiving surface 91 ′ of the flatterning chuck 9 ′ through the suction holes 93 ′.
- the carrier 9 of the assembly 4 may contact the receiving surface 91 ′ of the flatterning chuck 9 ′.
- the flatterning chuck 9 ′ may provide suction force to the entire package body 1 , which may provide flattening force to the package body 1 and reduce the warpage of the package body 1 .
- the assembly 4 of the tape 2 , the package body 1 and the carrier 9 is attached to or fixed on a first chuck 8 by suction, for example, vacuum suction. That is, the first chuck 8 is utilized to suck the assembly 4 of the tape 2 , the package body 1 and the carrier 9 .
- the first chuck 8 has a receiving surface 81 , and includes a plurality of suction holes 83 . Each of the suction holes 83 is communicated with a vacuum source, and has an opening at the receiving surface 81 .
- the assembly 4 is sucked on the receiving surface 81 of the first chuck 8 through the suction holes 83 .
- the tape 2 of the assembly 4 may contact the receiving surface 81 of the first chuck 8 .
- the assembly 4 and the first chuck 8 may be provided or moved to the grinding unit 51 ( FIG. 1 ).
- the carrier 9 is removed, and the second surface 12 of the package body 1 is ground by the grinding head 7 .
- the package body 1 is thinned from the second surface 12 of the package body 1 .
- the tape 2 e.g., a back grinding (BG) tape
- BG back grinding
- the thinned package body 1 may have a large warpage due to the thinness of the thinned package body 1 , and the CTE (coefficient of thermal expansion) mismatch between the encapsulant 14 , the semiconductor devices 13 and the redistribution structure 15 .
- the large warpage may be greater than 7 ⁇ m.
- the adhesive releasing unit 52 may include a light irradiation source such as a UV (Ultra Violet) light source.
- a light irradiation source such as a UV (Ultra Violet) light source.
- the tape 2 is irradiated by the UV light so that the adhesive of the tape 2 is reduced or released. That is, the adhesive releasing unit 52 may be used for releasing the adhesive of the tape 2 .
- the thinned package body 1 and the tape 2 that are sucked on the first chuck 8 may be provided or moved to the film attaching unit 53 ( FIG. 1 ).
- a film 3 may be attached to or disposed on the second surface 12 of the package body 1 . That is, the film attaching unit 53 may be used for attaching the film 3 to the second surface 12 of the package body 1 .
- the film 3 may be a pre-cut lamination film.
- the pre-cut lamination film may be a double-layered structure that includes a back side coating film (or back side film) 31 and a dicing tape 32 .
- the pre-cut lamination film may be a combination of the dicing tape 32 and the back side coating film 31 .
- the back side coating film 31 may be used for forming a mark thereon, and a thickness of the back side coating film 31 may be about 25 ⁇ m to about 40 ⁇ m.
- the dicing tape 32 may be used in a dicing step or a sawing step, and a thickness of the dicing tape 32 may be about 80 ⁇ m to about 100 ⁇ m.
- an assembly 4 ′ including the tape 2 , the package body 1 and the film 3 is formed.
- the film 3 is attached to the package body 1 before the tape 2 (e.g., the BG tape) is removed. That is, the package body 1 may be interposed between the tape 2 (e.g., the BG tape) and the film 3 .
- the film 3 can be attached to the package body 1 easily since the package body 1 has a small warpage such as a warpage of less than 7 ⁇ m.
- the film 3 is attached to the package body 1 after the tape 2 (e.g., the BG tape) is removed.
- the thinned package body 1 may have a severe warpage (e.g., a warpage of greater than 7 ⁇ m) and may be difficult to be sucked by a chuck. As a result, the film 3 is difficult to be attached to the package body 1 in the subsequent stage.
- the thick tape 2 e.g., the BG tape
- the film 3 may be attached to the second surface 12 of the package body 1 by a roller. Thus, the warpage of the package body 1 may be reduced due to the press force of the roller.
- the assembly 4 ′ of the tape 2 , the package body 1 and the film 3 sucked by the first chuck 8 is turned over in the overturning unit 54 ( FIG. 1 ) so that the assembly 4 ′ of the tape 2 , the package body 1 and the film 3 is attached to or fixed on a second chuck 8 ′ by suction, for example, vacuum suction. That is, the overturning unit 54 is used for turning over the assembly 4 ′ of the package body 1 , the tape 2 and the film 3 .
- the second chuck 8 ′ is utilized to suck the assembly 4 ′ of the tape 2 , the package body 1 and the film 3 .
- the second chuck 8 ′ has a receiving surface 81 ′, and includes a plurality of suction holes 83 ′. Each of the suction holes 83 ′ is communicated with a vacuum source, and has an opening at the receiving surface 81 ′. In some embodiments, the assembly 4 ′ is sucked on the receiving surface 81 ′ of the second chuck 8 ′ through the suction holes 83 ′. The film 3 of the assembly 4 ′ may contact the receiving surface 81 ′ of the second chuck 8 ′. Then, the first chuck 8 is removed.
- the assembly 4 ′ and the second chuck 8 ′ may be provided or moved to the tape removing unit 55 ( FIG. 1 ).
- the tape removing unit 55 the tape 2 is removed from the package body land the external connectors 16 are exposed. That is, the film-removing unit 53 may be used for removing the tape 2 . Since the adhesive of the tape 2 is released or reduced, the tape 2 may be removed easily and no residue will be left on the package body 1 after removal.
- the package body 1 and the film 3 that are sucked on the second chuck 8 ′ may be provided or moved to the curing unit 56 ( FIG. 1 ).
- the back side coating film 31 of the film 3 may be cured or solidified. That is, the curing unit 56 may be used for curing or solidifying the back side coating film 31 of the film 3 .
- the package body 1 and the film 3 are removed from the second chuck 8 ′, and then may be provided or moved to the marking unit 57 ( FIG. 1 ).
- a mark may be formed on or in the back side coating film 31 of the film 3 . That is, the marking unit 57 may be used for forming a mark on or in the back side coating film 31 of the film 3 . It is noted that during the formation of the mark, the dicing tape 32 is still on the back side coating film 31 . Thus, the light irradiation source (e.g., laser light) that is used for forming the mark may pass through the dicing tape 32 of the film 3 .
- the light irradiation source e.g., laser light
- the package body 1 and the film 3 may be provided or moved to the sawing unit 58 ( FIG. 1 ).
- the package body 1 and the film 3 may be attached to or mounted on a cutting frame, and then they are sawed or singulated to form a plurality of semiconductor package structures 6 of FIG. 11 .
- the semiconductor package structure 6 may include the singulated package body 1 and the singulated back side coating film 31 .
- the singulated package body 1 may include the semiconductor device 13 , the encapsulant 14 , the redistribution structure 15 , the UBMs 154 and the external connectors 16 .
- FIG. 12 illustrates a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- the initial stages of the illustrated process are the same as, or similar to, the stage illustrated in FIG. 2 to FIG. 7 .
- FIG. 12 depicts a stage subsequent to that depicted in FIG. 7 .
- the thinned package body 1 and the tape 2 that are sucked on the first chuck 8 may be provided or moved to the film attaching unit 53 ( FIG. 1 ).
- a film 3 ′ may be formed or disposed on the second surface 12 of the package body 1 .
- the film 3 ′ may be a single layer structure that is a dicing tape 32 ′.
- the dicing tape 32 ′ may be used in a dicing step or a sawing step, and a thickness of the dicing tape 32 ′ may be about 80 ⁇ m to about 100 ⁇ m.
- the following stages of the method may be similar to the stages illustrated in FIG. 9 to FIG. 11 so as to obtain a plurality of semiconductor package structures.
- the semiconductor package structure formed from the illustrated process may be similar to the semiconductor package structure 6 of FIG. 11 , except that the semiconductor package structure of the illustrated embodiment may not include the back side coating film 31 .
- FIG. 13 illustrates a schematic arrangement of a system 5 a for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- the system 5 a of FIG. 13 is similar to the system 5 of FIG. 1 , except that the system 5 a of FIG. 13 further include an additional film attaching unit 53 a disposed between the film attaching unit 53 and the tape removing unit 55 .
- FIG. 14 through 15 illustrates a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.
- the method is for manufacturing the semiconductor package structure 6 shown in FIG. 11 .
- the initial stages of the illustrated process are the same as, or similar to, the stage illustrated in FIG. 2 to FIG. 7 .
- FIG. 14 depicts a stage subsequent to that depicted in FIG. 7 .
- the thinned package body 1 and the tape 2 that are sucked on the first chuck 8 may be provided or moved to the film attaching unit 53 ( FIG. 13 ).
- a film 3 a may be formed or disposed on the second surface 12 of the package body 1 .
- the film 3 a may be a single layer structure that is a back side coating film 31 .
- the film 3 a , the thinned package body 1 and the tape 2 that are sucked on the first chuck 8 may be provided or moved to the additional film attaching unit 53 a ( FIG. 13 ).
- a film 3 b may be attached or disposed on the film 3 a (e.g., the back side coating film 31 ).
- the film 3 b may be a single layer structure that is a dicing tape.
- the following stages of the method may be similar to the stages illustrated in FIG. 9 to FIG. 11 so as to obtain a plurality of semiconductor package structures 6 of FIG. 11 .
- the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
- the terms can refer to a range of variation of less than or equal to ⁇ 10% of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ⁇ 10% of the second numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- substantially perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ⁇ 10°, such as less than or equal to ⁇ 5°, less than or equal to ⁇ 4°, less than or equal to ⁇ 3°, less than or equal to ⁇ 2°, less than or equal to ⁇ 1°, less than or equal to ⁇ 0.5°, less than or equal to ⁇ 0.1°, or less than or equal to ⁇ 0.05°.
- a characteristic or quantity can be deemed to be “substantially” consistent if a maximum numerical value of the characteristic or quantity is within a range of variation of less than or equal to +10% of a minimum numerical value of the characteristic or quantity, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%.
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 ⁇ m, no greater than 2 ⁇ m, no greater than 1 ⁇ m, or no greater than 0.5 ⁇ m.
- a surface can be deemed to be substantially flat if a displacement between a highest point and a lowest point of the surface is no greater than 5 ⁇ m, no greater than 2 ⁇ m, no greater than 1 ⁇ m, or no greater than 0.5 ⁇ m.
- conductive As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 10 4 S/m, such as at least 10 5 S/m or at least 10 6 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
Abstract
A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
Description
- This application is a continuation of U.S. patent application Ser. No. 17/086,179 filed Oct. 30, 2020, now issued as U.S. Pat. No. 11,538,787, the contents of which is incorporated herein by reference in its entirety.
- The present disclosure relates to a method and system for manufacturing a semiconductor package structure, and to a method including a thinning step and a system for accomplishing the same.
- In order to reduce a thickness of a semiconductor package structure, a molded wafer that is in an intermediate state of fabrication is thinned. However, the molded wafer may include a semiconductor die and a molding compound covering the semiconductor die. The thinned molded wafer may have a severe warpage due to the small thickness of the thinned molded wafer, and the CTE mismatch between the semiconductor die and the molding compound. Thus, the chuck may not handle the thinned molded wafer successfully. Thus, the following step may be difficult to be conducted to the warped and thinned molded wafer.
- In some embodiments, a method for manufacturing a semiconductor package structure includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
- In some embodiments, a system for manufacturing a semiconductor package structure includes a grinding unit, a film attaching unit and a tape removing unit. The grinding unit is used for grinding a package body with a tape. The film attaching unit is used for attaching a film to the package body. The tape removing unit is used for removing the tape from the package body. The film attaching unit is disposed between the grinding unit and the tape removing unit.
- Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a schematic arrangement of a system for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 2 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 3 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 4 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 4A illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 5 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 6 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 7 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 8 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 9 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 10 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 11 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 12 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 13 illustrates a schematic arrangement of a system for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 14 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. -
FIG. 15 illustrates one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. - Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
- The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
-
FIG. 1 illustrates a schematic arrangement of a system 5 for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. The system 5 may include atape attaching unit 50, agrinding unit 51, an adhesive releasingunit 52, afilm attaching unit 53, an overturningunit 54, atape removing unit 55, acuring unit 56, amarking unit 57 and asawing unit 58. - As shown in
FIG. 1 , thetape attaching unit 50, thegrinding unit 51, theadhesive releasing unit 52, thefilm attaching unit 53, the overturningunit 54, thetape removing unit 55, thecuring unit 56, themarking unit 57 and thesawing unit 58 may be disposed or arranged in sequence. That is, a workpiece may be sequentially processed in thetape attaching unit 50, thegrinding unit 51, theadhesive releasing unit 52, thefilm attaching unit 53, the overturningunit 54, thetape removing unit 55, thecuring unit 56, themarking unit 57 and thesawing unit 58. That is, the workpiece may be delivered or transferred in such order. For example, according to such arrangement, thefilm attaching unit 53 is disposed between thegrinding unit 51 and thetape removing unit 55, and the overturningunit 54 is disposed between thefilm attaching unit 53 and thetape removing unit 55. - The
tape attaching unit 50 and thefilm attaching unit 53 are used for attaching a tape of a film onto the workpiece. Thegrinding unit 51 is used for grinding a surface of the workpiece so as to thin the workpiece. The adhesive releasingunit 52 is used for releasing the adhesive of a tape on the workpiece. The overturningunit 54 is used for turning the workpiece over. Thetape removing unit 55 is used for removing a tape from the workpiece. Thecuring unit 56 is used for curing or solidifying at least a portion of the workpiece. Themarking unit 57 is used for forming a mark on or in the workpiece. Thesawing unit 58 is used for sawing or cutting the workpiece into a plurality of singulated devices. -
FIG. 2 throughFIG. 11 illustrate a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the semiconductor package structure 6 shown inFIG. 11 . - Referring to
FIG. 2 andFIG. 3 , whereinFIG. 3 illustrates a partially enlarged view of a region of thepackage body 1 inFIG. 2 , apackage body 1 may be formed on acarrier 9. Thecarrier 9 may be a glass carrier, and may be in a wafer type, a panel type or a strip type. Thepackage body 1 may be in a molded wafer type or in a molded panel type, and may have a first surface 11 (e.g., a top surface) and a second surface 12 (e.g., a bottom surface) opposite to thefirst surface 11. Thepackage body 1 may include at least onesemiconductor device 13, anencapsulant 14, aredistribution structure 15, a plurality of under bump metallurgies (UBMs) 154 and a plurality ofexternal connectors 16. The at least onesemiconductor device 13 may include a plurality ofsemiconductor dice 13 disposed side by side. Thesemiconductor device 13 has a first surface 131 (e.g., an active surface), a second surface 132 (e.g., a backside surface) and alateral side surface 133. The first surface 131 (e.g., an active surface) of thesemiconductor device 13 is adjacent to thefirst surface 11 of thepackage body 1. That is, thefirst surface 11 of thepackage body 1 is nearer the first surface 131 (e.g., an active surface) of thesemiconductor device 13 than thesecond surface 12 of thepackage body 1 is. A distance between thefirst surface 11 of thepackage body 1 and the first surface 131 (e.g., an active surface) is less than a distance between thesecond surface 12 of thepackage body 1 and the first surface 131 (e.g., an active surface) of thesemiconductor device 13. Thesecond surface 132 is opposite to thefirst surface 131, and thelateral side surface 133 extends between thefirst surface 131 and thesecond surface 132. Thesecond surface 132 of thesemiconductor device 13 may be disposed on or attached to thecarrier 9. Thesemiconductor device 13 may include a plurality ofconductive pads 133 and a plurality of stud bumps 134. Theconductive pads 133 may include copper, aluminum or gold, and may be disposed adjacent to or exposed from thefirst surface 131 of thesemiconductor device 13. The stud bumps 134 may be disposed on theconductive pads 133 and may protrude from thefirst surface 131 of thesemiconductor device 13. In some embodiments, thestud bump 134 may include copper (Cu), and may be in a pillar form. - The
encapsulant 14 may be a cured molding compound with or without fillers. Theencapsulant 14 may cover thecarrier 9, thesecond surface 132 of thesemiconductor device 13, thelateral side surface 133 of thesemiconductor device 13 and the stud bumps 134 of thesemiconductor device 13. Thus, theencapsulant 14 encapsulates the stud bumps 134 and thesemiconductor device 13. Thesemiconductor device 13 is encapsulated in theencapsulant 14. Theencapsulant 14 has afirst surface 141 and asecond surface 142 opposite to thefirst surface 141. In some embodiments, thefirst surface 141 of theencapsulant 14 may be ground, and the top surfaces of the stud bumps 134 may be substantially coplanar with thefirst surface 141 of theencapsulant 14. Thus, the top surfaces of the stud bumps 134 may be exposed from thefirst surface 141 of theencapsulant 14. Thesecond surface 132 of thesemiconductor device 13 may be substantially coplanar with thesecond surface 142 of theencapsulant 14, and they may be thesecond surface 12 of thepackage body 1. - The
redistribution structure 15 may be disposed on thefirst surface 141 of theencapsulant 14, and may include a firstdielectric layer 151, aninterconnection structure 152 and asecond dielectric layer 153. Thefirst dielectric layer 151 may cover theencapsulant 14, and may define a plurality ofopenings 1511 to expose the top surfaces of the stud bumps 134. In some embodiments, thefirst dielectric layer 151 may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof. - The
interconnection structure 152 may be formed on a top surface of thefirst dielectric layer 151 and in theopenings 1511 of thefirst dielectric layer 151. Theinterconnection structure 152 may be a fan-out redistribution layer or a fan-in redistribution layer. For example, theinterconnection structure 152 may include a plurality ofconductive traces 1521 and a plurality ofconductive pads conductive pads 1522 may be disposed in theopenings 1511 of thefirst dielectric layer 151 and contact the top surfaces of the stud bumps 134. Theconductive pads 1523 may be disposed right under theUBMs 154 and may be also referred to as “capture lands”. The conductive traces 1521 extend between theconductive pads conductive traces 1521 and theconductive pads FIG. 2 andFIG. 3 , theinterconnection structure 152 may include one circuit layer; however, in other embodiments, theinterconnection structure 152 may include a plurality of circuit layers electrically connected to one another. - The
second dielectric layer 153 may cover thefirst dielectric layer 151 and theinterconnection structure 152, and may define a plurality ofopenings 1531 to expose the conductive pads 1523 (i.e., the capture lands) of theinterconnection structure 152. In some embodiments, thesecond dielectric layer 153 may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof. - The
UBMs 154 may be formed on a top surface of thesecond dielectric layer 153 and in theopenings 1531 of thesecond dielectric layer 153 so as to contact the conductive pads 1523 (i.e., the capture lands) of theinterconnection structure 152. The external connectors 16 (e.g., solder balls) may be formed or disposed on theUBMs 154. Thus, theexternal connectors 16 are disposed on theredistribution structure 15. - Referring to
FIG. 4 , a flattening force may be provided or applied to thepackage body 1. In some embodiments, thepackage body 1 and thecarrier 9 may be provided or moved to the tape attaching unit 50 (FIG. 1 ). In thetape attaching unit 50, atape 2 may be attached to or disposed on thefirst surface 11 of thepackage body 1 to cover theredistribution structure 15 of thepackage body 1 and theexternal connectors 16. That is, thetape attaching unit 50 may be used for attaching thetape 2 to thefirst surface 11 of thepackage body 1. In some embodiments, thetape 2 may be a back grinding (BG) tape, and a thickness of thetape 2 may be greater than a thickness of thepackage body 1. For example, the thickness of thetape 2 may be about 500 μm, and the thickness of thepackage body 1 may be about 300 μm. Meanwhile, an assembly 4 including thetape 2, thepackage body 1 and thecarrier 9 is formed. In addition, the thick tape 2 (e.g., the BG tape) may provide stiffness and rigidity, which may provide flattening force to thepackage body 1 and reduce the warpage of thepackage body 1. - Referring to
FIG. 4A , the flattening force may be further provided or applied to thepackage body 1 by holding thepackage body 1 on aflatterning chuck 9′. As shown inFIG. 4A , the assembly 4 of thetape 2, thepackage body 1 and thecarrier 9 is attached to or fixed on aflatterning chuck 9′ by suction, for example, vacuum suction. That is, theflatterning chuck 9′ is utilized to suck the assembly 4 of thetape 2, thepackage body 1 and thecarrier 9. Theflatterning chuck 9′ has a receiving surface 91′, and includes a plurality of suction holes 93′. Each of the suction holes 93′ is communicated with a vacuum source, and has an opening at the receiving surface 91′. In some embodiments, the assembly 4 is sucked on the receiving surface 91′ of theflatterning chuck 9′ through the suction holes 93′. Thecarrier 9 of the assembly 4 may contact the receiving surface 91′ of theflatterning chuck 9′. Theflatterning chuck 9′ may provide suction force to theentire package body 1, which may provide flattening force to thepackage body 1 and reduce the warpage of thepackage body 1. - Referring to
FIG. 5 , the assembly 4 of thetape 2, thepackage body 1 and thecarrier 9 is attached to or fixed on afirst chuck 8 by suction, for example, vacuum suction. That is, thefirst chuck 8 is utilized to suck the assembly 4 of thetape 2, thepackage body 1 and thecarrier 9. Thefirst chuck 8 has a receivingsurface 81, and includes a plurality of suction holes 83. Each of the suction holes 83 is communicated with a vacuum source, and has an opening at the receivingsurface 81. In some embodiments, the assembly 4 is sucked on the receivingsurface 81 of thefirst chuck 8 through the suction holes 83. Thetape 2 of the assembly 4 may contact the receivingsurface 81 of thefirst chuck 8. - Referring to
FIG. 6 , the assembly 4 and thefirst chuck 8 may be provided or moved to the grinding unit 51 (FIG. 1 ). In the grindingunit 51, thecarrier 9 is removed, and thesecond surface 12 of thepackage body 1 is ground by the grinding head 7. Thus, thepackage body 1 is thinned from thesecond surface 12 of thepackage body 1. During the grinding process, the tape 2 (e.g., a back grinding (BG) tape) can provide buffer, so as to protect theexternal connectors 16 from damage caused by the press of the grinding head 7. - Referring to
FIG. 7 , after the grinding head 7 is removed from the thinnedpackage body 1, the thinnedpackage body 1 may have a large warpage due to the thinness of the thinnedpackage body 1, and the CTE (coefficient of thermal expansion) mismatch between the encapsulant 14, thesemiconductor devices 13 and theredistribution structure 15. In some embodiments, the large warpage may be greater than 7 μm. - Then, the thinned
package body 1 and thetape 2 that are sucked on thefirst chuck 8 may be provided or moved to the adhesive releasing unit 52 (FIG. 1 ). The adhesive releasingunit 52 may include a light irradiation source such as a UV (Ultra Violet) light source. In the adhesive releasingunit 52, thetape 2 is irradiated by the UV light so that the adhesive of thetape 2 is reduced or released. That is, the adhesive releasingunit 52 may be used for releasing the adhesive of thetape 2. - Referring to
FIG. 8 , the thinnedpackage body 1 and thetape 2 that are sucked on thefirst chuck 8 may be provided or moved to the film attaching unit 53 (FIG. 1 ). In thefilm attaching unit 53, afilm 3 may be attached to or disposed on thesecond surface 12 of thepackage body 1. That is, thefilm attaching unit 53 may be used for attaching thefilm 3 to thesecond surface 12 of thepackage body 1. In some embodiments, thefilm 3 may be a pre-cut lamination film. For example, the pre-cut lamination film may be a double-layered structure that includes a back side coating film (or back side film) 31 and a dicingtape 32. That is, the pre-cut lamination film may be a combination of the dicingtape 32 and the backside coating film 31. The backside coating film 31 may be used for forming a mark thereon, and a thickness of the backside coating film 31 may be about 25 μm to about 40 μm. The dicingtape 32 may be used in a dicing step or a sawing step, and a thickness of the dicingtape 32 may be about 80 μm to about 100 μm. Meanwhile, an assembly 4′ including thetape 2, thepackage body 1 and thefilm 3 is formed. - In the illustrated embodiment, the
film 3 is attached to thepackage body 1 before the tape 2 (e.g., the BG tape) is removed. That is, thepackage body 1 may be interposed between the tape 2 (e.g., the BG tape) and thefilm 3. Thus, thefilm 3 can be attached to thepackage body 1 easily since thepackage body 1 has a small warpage such as a warpage of less than 7 μm. In a comparative embodiment, thefilm 3 is attached to thepackage body 1 after the tape 2 (e.g., the BG tape) is removed. When the tape 2 (e.g., the BG tape) is removed from the thinnedpackage body 1, the thinnedpackage body 1 may have a severe warpage (e.g., a warpage of greater than 7 μm) and may be difficult to be sucked by a chuck. As a result, thefilm 3 is difficult to be attached to thepackage body 1 in the subsequent stage. Further, in the illustrated embodiment, the thick tape 2 (e.g., the BG tape) may provide stiffness and rigidity, which may reduce the warpage of thepackage body 1. In addition, in the illustrated embodiment, thefilm 3 may be attached to thesecond surface 12 of thepackage body 1 by a roller. Thus, the warpage of thepackage body 1 may be reduced due to the press force of the roller. - Referring to
FIG. 9 , the assembly 4′ of thetape 2, thepackage body 1 and thefilm 3 sucked by thefirst chuck 8 is turned over in the overturning unit 54 (FIG. 1 ) so that the assembly 4′ of thetape 2, thepackage body 1 and thefilm 3 is attached to or fixed on asecond chuck 8′ by suction, for example, vacuum suction. That is, the overturningunit 54 is used for turning over the assembly 4′ of thepackage body 1, thetape 2 and thefilm 3. In addition, thesecond chuck 8′ is utilized to suck the assembly 4′ of thetape 2, thepackage body 1 and thefilm 3. Thesecond chuck 8′ has a receivingsurface 81′, and includes a plurality of suction holes 83′. Each of the suction holes 83′ is communicated with a vacuum source, and has an opening at the receivingsurface 81′. In some embodiments, the assembly 4′ is sucked on the receivingsurface 81′ of thesecond chuck 8′ through the suction holes 83′. Thefilm 3 of the assembly 4′ may contact the receivingsurface 81′ of thesecond chuck 8′. Then, thefirst chuck 8 is removed. - Referring to
FIG. 10 , the assembly 4′ and thesecond chuck 8′ may be provided or moved to the tape removing unit 55 (FIG. 1 ). In thetape removing unit 55, thetape 2 is removed from the package body land theexternal connectors 16 are exposed. That is, the film-removingunit 53 may be used for removing thetape 2. Since the adhesive of thetape 2 is released or reduced, thetape 2 may be removed easily and no residue will be left on thepackage body 1 after removal. - Then, the
package body 1 and thefilm 3 that are sucked on thesecond chuck 8′ may be provided or moved to the curing unit 56 (FIG. 1 ). In thecuring unit 56, the backside coating film 31 of thefilm 3 may be cured or solidified. That is, the curingunit 56 may be used for curing or solidifying the backside coating film 31 of thefilm 3. - Then, the
package body 1 and thefilm 3 are removed from thesecond chuck 8′, and then may be provided or moved to the marking unit 57 (FIG. 1 ). In the markingunit 57, a mark may be formed on or in the backside coating film 31 of thefilm 3. That is, the markingunit 57 may be used for forming a mark on or in the backside coating film 31 of thefilm 3. It is noted that during the formation of the mark, the dicingtape 32 is still on the backside coating film 31. Thus, the light irradiation source (e.g., laser light) that is used for forming the mark may pass through the dicingtape 32 of thefilm 3. - Referring to
FIG. 11 , thepackage body 1 and thefilm 3 may be provided or moved to the sawing unit 58 (FIG. 1 ). In thesawing unit 58, thepackage body 1 and thefilm 3 may be attached to or mounted on a cutting frame, and then they are sawed or singulated to form a plurality of semiconductor package structures 6 ofFIG. 11 . - As shown in
FIG. 11 , the semiconductor package structure 6 may include thesingulated package body 1 and the singulated backside coating film 31. Thesingulated package body 1 may include thesemiconductor device 13, theencapsulant 14, theredistribution structure 15, theUBMs 154 and theexternal connectors 16. -
FIG. 12 illustrates a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIG. 2 toFIG. 7 .FIG. 12 depicts a stage subsequent to that depicted inFIG. 7 . - Referring to
FIG. 12 , the thinnedpackage body 1 and thetape 2 that are sucked on thefirst chuck 8 may be provided or moved to the film attaching unit 53 (FIG. 1 ). In thefilm attaching unit 53, afilm 3′ may be formed or disposed on thesecond surface 12 of thepackage body 1. In some embodiments, thefilm 3′ may be a single layer structure that is a dicingtape 32′. The dicingtape 32′ may be used in a dicing step or a sawing step, and a thickness of the dicingtape 32′ may be about 80 μm to about 100 μm. - Then, the following stages of the method may be similar to the stages illustrated in
FIG. 9 toFIG. 11 so as to obtain a plurality of semiconductor package structures. The semiconductor package structure formed from the illustrated process may be similar to the semiconductor package structure 6 ofFIG. 11 , except that the semiconductor package structure of the illustrated embodiment may not include the backside coating film 31. -
FIG. 13 illustrates a schematic arrangement of asystem 5 a for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. Thesystem 5 a ofFIG. 13 is similar to the system 5 ofFIG. 1 , except that thesystem 5 a ofFIG. 13 further include an additionalfilm attaching unit 53 a disposed between thefilm attaching unit 53 and thetape removing unit 55. -
FIG. 14 through 15 illustrates a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the semiconductor package structure 6 shown inFIG. 11 . The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIG. 2 toFIG. 7 .FIG. 14 depicts a stage subsequent to that depicted inFIG. 7 . - Referring to
FIG. 14 , the thinnedpackage body 1 and thetape 2 that are sucked on thefirst chuck 8 may be provided or moved to the film attaching unit 53 (FIG. 13 ). In thefilm attaching unit 53, afilm 3 a may be formed or disposed on thesecond surface 12 of thepackage body 1. In some embodiments, thefilm 3 a may be a single layer structure that is a backside coating film 31. - Referring to
FIG. 15 , thefilm 3 a, the thinnedpackage body 1 and thetape 2 that are sucked on thefirst chuck 8 may be provided or moved to the additionalfilm attaching unit 53 a (FIG. 13 ). In the additionalfilm attaching unit 53 a, afilm 3 b may be attached or disposed on thefilm 3 a (e.g., the back side coating film 31). In some embodiments, thefilm 3 b may be a single layer structure that is a dicing tape. - Then, the following stages of the method may be similar to the stages illustrated in
FIG. 9 toFIG. 11 so as to obtain a plurality of semiconductor package structures 6 ofFIG. 11 . - Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
- As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, a characteristic or quantity can be deemed to be “substantially” consistent if a maximum numerical value of the characteristic or quantity is within a range of variation of less than or equal to +10% of a minimum numerical value of the characteristic or quantity, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%.
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be deemed to be substantially flat if a displacement between a highest point and a lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
- As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
- As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (20)
1. A method for manufacturing a semiconductor package structure, comprising:
providing a package body including a semiconductor device encapsulated in an encapsulant;
attaching a combination of a dicing tape and a back side film to the package body; and
forming a mark on the back side film by a light irradiation passing through the dicing tape.
2. The method of claim 1 , further comprising:
curing the back side film.
3. The method of claim 1 , further comprising:
grinding a portion of the encapsulant, the portion covering an active surface of the semiconductor device.
4. The method of claim 3 , further comprising:
exposing a stud bump disposed over the active surface of the semiconductor device from the encapsulant.
5. The method of claim 1 , further comprising:
applying a flattening force to the package body.
6. The method of claim 5 , further comprising:
thinning the package body.
7. The method of claim 6 , further comprising
releasing the flattening force after attaching the combination of the dicing tape and the back side film to the package body.
8. A method for manufacturing a semiconductor package structure, comprising:
providing a package body including a semiconductor device encapsulated in an encapsulant;
removing a portion of the encapsulant to expose a plurality of stud bumps disposed over an active surface of the semiconductor device;
providing a flattening force to the package body;
thinning the package body; and
attaching a tape to the package body before releasing the flattening force.
9. The method of claim 8 , further comprising:
grinding a portion of the encapsulant, the portion covering the active surface of the semiconductor device.
10. The method of claim 9 , further comprising:
exposing the plurality of stud bumps from the encapsulant.
11. The method of claim 10 , further comprising:
disposing a redistribution structure over the plurality of stud bumps.
12. The method of claim 11 , wherein the redistribution structure is disposed over an interface between one of the plurality of stud bumps and the encapsulant.
13. The method of claim 8 , further comprising attaching a back side film to the package body.
14. The method of claim 13 , further comprising:
curing the back side film.
15. The method of claim 14 , further comprising:
forming a mark on the semiconductor package structure by a light irradiation before releasing the dicing tape.
16. The method of claim 8 , further comprising:
attaching a back grinding (BG) tape on the package body adjacent to the active surface.
17. The method of claim 16 , further comprising:
applying a suction force to the package body.
18. A method for manufacturing a semiconductor package structure, comprising:
providing a package body including a semiconductor device encapsulated in an encapsulant;
attaching a dicing tape to the package body; and
forming a mark by a light irradiation passing through the dicing tape.
19. The method of claim 18 , further comprising:
grinding the package body to expose a plurality of stud bumps of the semiconductor device.
20. The method of claim 19 , further comprising:
forming a redistribution structure over an interface between the plurality of stud bumps and the encapsulant.
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US20110012258A1 (en) * | 2007-09-25 | 2011-01-20 | Stats Chippac, Ltd. | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface |
US20160322251A1 (en) * | 2015-04-30 | 2016-11-03 | Nitto Denko Corporation | Film for semiconductor device, method for manufacturing semiconductor device, and semiconductor device |
US20170033026A1 (en) * | 2015-07-30 | 2017-02-02 | Semtech Corporation | Semiconductor Device and Method of Forming Small Z Semiconductor Package |
US20170271307A1 (en) * | 2016-01-27 | 2017-09-21 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
WO2019097819A1 (en) * | 2017-11-16 | 2019-05-23 | 日東電工株式会社 | Semiconductor process sheet and method for manufacturing semiconductor package |
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TWI651783B (en) * | 2013-11-02 | 2019-02-21 | 史達晶片有限公司 | Semiconductor device and method of forming embedded wafer level chip scale packages |
JP2018056502A (en) * | 2016-09-30 | 2018-04-05 | 株式会社ディスコ | Method of machining device wafer |
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Patent Citations (5)
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US20110012258A1 (en) * | 2007-09-25 | 2011-01-20 | Stats Chippac, Ltd. | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface |
US20160322251A1 (en) * | 2015-04-30 | 2016-11-03 | Nitto Denko Corporation | Film for semiconductor device, method for manufacturing semiconductor device, and semiconductor device |
US20170033026A1 (en) * | 2015-07-30 | 2017-02-02 | Semtech Corporation | Semiconductor Device and Method of Forming Small Z Semiconductor Package |
US20170271307A1 (en) * | 2016-01-27 | 2017-09-21 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
WO2019097819A1 (en) * | 2017-11-16 | 2019-05-23 | 日東電工株式会社 | Semiconductor process sheet and method for manufacturing semiconductor package |
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