US20230070511A1 - Display device and method for manufacturing same - Google Patents

Display device and method for manufacturing same Download PDF

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Publication number
US20230070511A1
US20230070511A1 US17/794,723 US202017794723A US2023070511A1 US 20230070511 A1 US20230070511 A1 US 20230070511A1 US 202017794723 A US202017794723 A US 202017794723A US 2023070511 A1 US2023070511 A1 US 2023070511A1
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Prior art keywords
layer
light emitting
area
emitting element
insulating layer
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Inventor
Jae Min Shin
Sang Woo Kim
Jang Yeol YOON
Gyung Soon Park
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIN, JAE MIN, KIM, SANG WOO, PARK, GYUNG SOON, YOON, JANG YEOL
Publication of US20230070511A1 publication Critical patent/US20230070511A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
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    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
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    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present disclosure relates to a display device and a method of manufacturing the same.
  • An object of the present disclosure is to provide a display device having improved light output efficiency.
  • an object of the disclosure is to provide a method of manufacturing the above-described display device.
  • a display device may include a substrate including a display area including a plurality of pixel areas each having an emission area and a non-display area surrounding at least one side of the display area, and a pixel provided in each of the pixel areas and including a display element part.
  • the display element part may include a first insulating layer disposed on the substrate, at least one light emitting element disposed on the first insulating layer and each having a first end and a second end in a longitudinal direction, a first layer disposed on the first insulating layer and the light emitting element and being in contact with a first area of each of the first and second ends of the light emitting element, a second layer disposed on the light emitting element and being in contact with a second area of each of the first and second ends of the light emitting element, and an interlayer insulating layer provided between the first layer and the second layer.
  • the first layer and the second layer may include a semiconductor material.
  • the light emitting element may include a first semiconductor layer doped with a first conductive dopant, a second semiconductor layer doped with a second conductive dopant, and an active layer provided between the first semiconductor layer and the second semiconductor layer.
  • each of the first and second semiconductor layers may include a gallium nitride (GaN) semiconductor material.
  • the first conductive dopant may include an n-type dopant
  • the second conductive dopant may include a p-type dopant
  • the first end of the light emitting element may include the first semiconductor layer, and the second end of the light emitting element may include the second semiconductor layer.
  • the first layer may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material
  • the second layer may include a transparent oxide semiconductor material
  • the display device may further include a first power line provided between the substrate and the first insulating layer and electrically connected to the first layer, and a second power line provided between the substrate and the first insulating layer, spaced apart from the first power line, and electrically connected to the second layer.
  • the first layer may be a hole injection layer receiving first power from the first power line and injecting a hole into the first area of the second end of the light emitting element
  • the second layer may be an electron injection layer receiving second power from the second power line and injecting an electron into the second area of the first end of the light emitting element
  • the interlayer insulating layer may be positioned between the first area and the second area of each of the first and second ends of the light emitting element.
  • the first area of the first end of the light emitting element that is in contact with the first layer and the second area of the first end of the light emitting element that is in contact with the second layer may have the same width or different widths.
  • the second area of the first end of the light emitting element that is in contact with the second layer and the second area of the second end of the light emitting element that is in contact with the second layer may have the same width or different widths.
  • the display element part may further include a first conductive line provided between the substrate and the first insulating layer, a second insulating layer disposed on the second layer, and a second conductive line disposed on the second insulating layer.
  • different voltages may be applied to the first conductive line and the second conductive line, respectively, and an electric field may be formed in a direction crossing the longitudinal direction of the light emitting element.
  • the second conductive line may include a transparent conductive material.
  • the display element part may further include a cover layer disposed on the second conductive line to correspond to the light emitting element.
  • the cover layer may include an opaque conductive material.
  • the cover layer may guide light emitted from the light emitting element in a predetermined direction to determine a position of the emission area of each of the pixel areas.
  • the pixel may further include a pixel circuit part provided between the substrate and the display element part.
  • a display device may include a stretchable substrate including a plurality of islands and bridges connecting the islands, and a plurality of pixels provided in each of the plurality of islands and each including a display element part.
  • the display element part may include a first insulating layer provided in each of the plurality of islands, a plurality of light emitting elements disposed on the first insulating layer and each having a first end and a second end in a longitudinal direction, a first layer disposed on the first insulating layer and the light emitting elements and being in contact with a first area of each of the first and second ends of each of the light emitting elements, a second layer disposed on the light emitting elements and being in contact with a second area of each of the first and second ends of each of the light emitting elements, and an interlayer insulating layer provided between the first layer and the second layer.
  • the first layer and the second layer may include a semiconductor material.
  • the first layer may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material
  • the second layer may include a transparent oxide semiconductor material
  • the first end of each of the light emitting elements may include a first semiconductor layer doped with an n-type dopant
  • the second end of each of the light emitting elements may include a second semiconductor layer doped with a p-type dopant
  • the stretchable substrate may further include a cutout positioned between the plurality of islands and the bridges.
  • the above-described display device may be manufactured by including providing a pixel prepared in a pixel area of a substrate.
  • providing the pixel may include forming a pixel circuit part on the substrate, and forming a display element part on the pixel circuit part.
  • forming the display element part may include forming a first insulating layer on the pixel circuit part, supplying a plurality of light emitting elements each having a first end and a second end in a longitudinal direction on the first insulating layer, forming a first layer including a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material on the light emitting elements, forming an interlayer insulating layer on the first layer, forming a second layer including a transparent oxide semiconductor material on the interlayer insulating layer, and forming a second insulating layer on the second layer.
  • a-Si:H p-type hydrogenated amorphous silicon
  • the first layer may be in contact with each of a first area of the first end and a second area of the second end of the light emitting element
  • the second layer may be in contact with each of a second area of the first end and a second area of the second end of the light emitting element
  • the interlayer insulating layer may be in contact between the first area and the second area of each of the first and second ends of the light emitting element.
  • forming the display element part may include forming a first conductive line between the pixel circuit part and the first insulating layer, forming a second conductive line on the second insulating layer, and forming a cover layer on the second conductive line.
  • a display device and a method of manufacturing the same capable of omitting configurations (alignment electrode or an alignment line) for alignment of light emitting elements by disposing a first layer including a hydrogenated amorphous silicon (a-Si:H) semiconductor material that is in contact with a first areas of both ends of each light emitting element and a second layer including a transparent oxide semiconductor material that is in contact with a second area of the both ends of each light emitting element after inputting the light emitting elements on a substrate may be provided.
  • a first layer including a hydrogenated amorphous silicon (a-Si:H) semiconductor material that is in contact with a first areas of both ends of each light emitting element
  • a second layer including a transparent oxide semiconductor material that is in contact with a second area of the both ends of each light emitting element after inputting the light emitting elements on a substrate
  • a display device and a method of manufacturing the same capable of improving light output efficiency by disposing a cover layer on the light emitting element to reflect or scatter light emitted from the light emitting element in a desired direction (or a desired direction) may be provided.
  • FIG. 1 a is a perspective view schematically illustrating a light emitting element according to an embodiment of the present disclosure.
  • FIG. 1 b is a cross-sectional view of the light emitting element of FIG. 1 a .
  • FIGS. 2 a to 2 c are circuit diagrams illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure, and in particular, are circuit diagrams illustrating an example of a pixel configuring a light emitting display panel.
  • FIG. 3 is a schematic plan view illustrating an area of a light emitting device including a unit emission area according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view taken along a line I ⁇ I' of FIG. 3 .
  • FIG. 5 a is an enlarged cross-sectional view of a portion EA 1
  • FIG. 5 b is an enlarged cross-sectional view of a portion EA 2 of FIG. 4 .
  • FIGS. 6 a and 6 b are diagrams schematically illustrating an energy band diagram of a first layer, a first semiconductor layer, a second semiconductor layer, and a second layer.
  • FIG. 7 is a cross-sectional view illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure, and is a cross-sectional view taken along the line I ⁇ I' of FIG. 3 .
  • FIG. 8 is a schematic plan view illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view corresponding to a line II ⁇ II' of FIG. 8 .
  • FIG. 10 is a plan view illustrating a display device according to an embodiment of the present disclosure and schematically illustrating an example of a display device using the light emitting element shown in FIGS. 1 a and 1 b as a light emitting source.
  • FIGS. 11 a and 11 b are enlarged plan views of a portion EA 3 of FIG. 10 .
  • FIGS. 12 a and 12 b are circuit diagrams illustrating an electrical connection relationship between components included in one pixel shown in FIG. 10 according to an embodiment.
  • FIG. 13 is a plan view schematically illustrating one pixel among pixels shown in FIG. 10 .
  • FIG. 14 is a cross-sectional view taken along a line III ⁇ III' of FIG. 13 .
  • FIG. 15 is an enlarged plan view of a portion EA 4 of FIG. 14 .
  • FIG. 16 is a schematic plan view implementing a cover layer shown in FIG. 13 according to another embodiment.
  • FIGS. 17 a to 17 k are schematic plan views sequentially illustrating a method of manufacturing one pixel shown in FIG. 13 .
  • FIGS. 18 a to 18 k are schematic cross-sectional views sequentially illustrating a method of manufacturing one pixel shown in FIG. 14 .
  • a term of “include”, “have”, or the like is used to specify that there is a feature, a number, a step, an operation, a component, a part, or a combination thereof described in the specification, but does not exclude a possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof in advance.
  • a case where a portion of a layer, a film, an area, a plate, or the like is referred to as being “on” another portion, it includes not only a case where the portion is “directly on” another portion, but also a case where there is further another portion between the portion and another portion.
  • a forming direction is not limited to an upper direction but includes forming the portion on a side surface or in a lower direction.
  • a portion of a layer, a film, an area, a plate, or the like is formed “under” another portion, this includes not only a case where the portion is “directly beneath” another portion but also a case where there is further another portion between the portion and another portion.
  • FIG. 1 a is a perspective view schematically illustrating a light emitting element according to an embodiment of the present disclosure
  • FIG. 1 b is a cross-sectional view of the light emitting element of FIG. 1 a .
  • FIGS. 1 a and 1 b a light emitting element LD of a cylinder shape is shown, but the type and/or shape of the light emitting element LD according to the present disclosure are/is not limited thereto.
  • the light emitting element LD may include a first semiconductor layer 11 , a second semiconductor layer 13 , and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13 .
  • the light emitting element LD may be implemented as an emission stack pattern 10 in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked.
  • the light emitting element LD may be provided in a shape extending in a direction.
  • an extension direction of the light emitting element LD is referred to as a longitudinal direction
  • the light emitting element LD may include one side end and another side end along the extension direction. Any one of the first and second semiconductor layers 11 and 13 may be disposed at the one side end of the light emitting element LD, and the other of the first and second semiconductor layers 11 and 13 may be disposed at the other side end of the light emitting element LD.
  • the light emitting element LD may be provided in various shapes.
  • the light emitting element LD may have a rod-like shape or a bar-like shape that is long in the longitudinal direction (that is, an aspect ratio is greater than 1).
  • a length L of the light emitting element LD in the longitudinal direction may be greater than a diameter D (or a width of a cross section) of the light emitting element LD.
  • the light emitting element LD may include, for example, a light emitting diode manufactured to be extremely small to have the diameter D and/or the length L of about a micro scale or a nano scale.
  • a size of the light emitting element LD may be changed to accord with a requirement condition (or a design condition) of a lighting device or a self-luminous display device.
  • the first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer.
  • the first semiconductor layer 11 may include any one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or an n-type dopant) such as Si, Ge, or Sn.
  • a first conductive dopant or an n-type dopant
  • the material configuring the first semiconductor layer 11 is not limited thereto, and various other materials may configure the first semiconductor layer 11 .
  • the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with the first conductive dopant (or the n-type dopant).
  • the first semiconductor layer 11 may be an n-type GaN semiconductor.
  • the first semiconductor layer 11 may include an upper surface 11 b that is in contact with the active layer 12 and a lower surface 11 a exposed to the outside.
  • the active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single or multiple quantum well structure. A position of the active layer 12 may be variously changed according to the type of the light emitting element LD.
  • the active layer 12 may emit light of a wavelength of 400 nm to 900 nm, and may use a double hetero structure.
  • a clad layer (not shown) doped with a conductive dopant may be formed on and/or under the active layer 12 .
  • the clad layer may be formed of an AlGaN layer or an InAlGaN layer.
  • a material such as AlGaN or InAlGaN may be used to form the active layer 12 , and various other materials may configure the active layer 12 .
  • the active layer 12 may include a first surface 12 a that is in contact with the first semiconductor layer 11 and a second surface 12 b that is in contact with the second semiconductor layer 13 .
  • the light emitting element LD When an electric field of a predetermined voltage or more is applied to both ends of the light emitting element LD, the light emitting element LD emits light while an electron-hole pair is recombined in the active layer 12 .
  • the light emitting element LD may be used as a light source (or a light emitting source) of various light emitting devices including a pixel of the display device.
  • the second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a type different from that of the first semiconductor layer 11 .
  • the second semiconductor layer 13 may include at least one p-type semiconductor layer.
  • the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or a p-type dopant) such as Mg.
  • the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials may configure the second semiconductor layer 13 .
  • the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with the second conductive dopant (or the p-type dopant).
  • the second semiconductor layer 13 may be a p-type GaN semiconductor.
  • the second semiconductor layer 13 may include a lower surface 13 a that is in contact with the active layer 12 and an upper surface 13 b exposed to the outside.
  • the first semiconductor layer 11 and the second semiconductor layer 13 may have widths (or thicknesses) different from each other in a length L direction of the light emitting element LD.
  • the first semiconductor layer 11 may have a width relatively wider (or a thickness thicker) than that of the second semiconductor layer 13 along the length L direction of the light emitting element LD. Therefore, the active layer 12 of the light emitting element LD may be positioned to be closer to the upper surface 13 b of the second semiconductor layer 13 than to the lower surface 11 a of the first semiconductor layer 11 as shown in FIGS. 1 a and 1 b .
  • the light emitting element LD may include the lower surface 11 a of the first semiconductor layer 11 and the upper surface 13 b of the second semiconductor layer 13 exposed to the outside.
  • the lower surface 11 a of the first semiconductor layer 11 and the upper surface 13 b of the second semiconductor layer 13 may be surfaces that are in contact with an external material, for example, a conductive material or a semiconductor material to be electrically connected thereto.
  • the light emitting element LD may further include an insulating film 14 .
  • the insulating film 14 may be omitted and may be provided so as to cover only a portion of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .
  • the insulating film 14 may prevent an electrical short that may occur when the active layer 12 is in contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13 .
  • lifespan and efficiency of the light emitting element LD may be improved by minimizing a surface defect of the light emitting element LD.
  • the insulating film 14 may prevent an unwanted short that may occur between the light emitting elements LD.
  • the insulating film 14 may be provided in a form entirely surrounding an outer circumferential surface of the emission stack pattern 10 including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .
  • a portion of the insulating film 14 is removed in FIG. 1 a , but the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 included in the actual emission stack pattern 10 may be surrounded by the insulating film 14 .
  • the insulating film 14 entirely surrounds the outer circumferential surface of each of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 , but the present disclosure is not limited thereto. According to an embodiment, the insulating film 14 may cover the entire outer circumferential surface of the active layer 12 , and may cover only a portion of the outer circumferential surface of each of the first and second semiconductor layers 11 and 13 .
  • the insulating film 14 may include a transparent insulating material.
  • the insulating film 14 may include one or more insulating materials selected from a group consisting of SiO 2 , Si 3 N 4 , Al 2 O 3 , and TiO 2 , but is not limited thereto, and various materials having insulating properties may be used.
  • the insulating film 14 When the insulating film 14 is provided to the light emitting element LD, a short between the active layer 12 and an external conductive material may be prevented. In addition, by forming the insulating film 14 , the lifespan and efficiency of the light emitting element LD may be improved by minimizing the surface defect of the light emitting element LD. In addition, when the plurality of light emitting elements LD are closely disposed, the insulating film 14 may prevent the unwanted short that may occur between the light emitting elements LD.
  • the above-described light emitting element LD may be used as a light emitting source of various display devices.
  • the light emitting element LD may be manufactured by a surface treatment process. For example, when the plurality of light emitting elements LD are mixed in a fluid solution (or a solvent) and supplied to each emission area (for example, an emission area of each pixel or an emission area of each sub-pixel), the surface treatment may be performed on each of the light emitting elements LD so that the light emitting elements LD may be uniformly sprayed without being not uniformly aggregated in the solution.
  • the light emitting device including the light emitting element LD described above may be used in various types of devices that require a light source, including a display device.
  • a display device For example, when a plurality of light emitting elements LD are disposed in an emission area of each pixel of a display panel, the light emitting elements LD may be used as a light source of each of the pixels.
  • an application field of the light emitting element LD is not limited to the above-described example.
  • the light emitting element LD may be used in other types of devices that require a light source, such as a lighting device.
  • FIGS. 2 a to 2 c are circuit diagrams illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure, and in particular, are circuit diagrams illustrating an example of a pixel configuring a light emitting display panel.
  • the unit emission area may be a pixel area in which one pixel PXL among a plurality of pixels included in the light emitting display panel is disposed, and may be an area in which the light emitting element LD of FIGS. 1 a and 1 b and signal lines electrically connected to the light emitting element LD are provided.
  • one pixel PXL may include the light emitting element LD and first and second power lines PL 1 and PL 2 connected to the light emitting element LD.
  • One side end (for example, the second semiconductor layer 13 ) of the light emitting element LD may be connected to the first power line PL 1
  • the other side end (for example, the first semiconductor layer 11 ) of the light emitting element LD may be connected to the second power line PL 2 .
  • a predetermined signal (or voltage) may be transferred from the first power line PL 1 to the one side end of the light emitting element LD
  • a predetermined signal (or voltage) may be transferred from the second power line PL 2 to the other side end of the light emitting element LD.
  • the predetermined signal applied to the first power line PL 1 and the predetermined signal applied to the second power line PL 2 may have different levels.
  • the predetermined signal applied to the first power line PL 1 may be set as high potential power and the predetermined signal applied to the second power line PL 2 may be set as low potential power.
  • the light emitting element LD may emit light with a luminance corresponding to a magnitude of the applied voltage. That is, light emission of the pixel PXL may be controlled by adjusting the predetermined signal applied from the first power line PL 1 and/or the predetermined signal applied from the second power line PL 2 .
  • the pixel PXL may include a plurality of light emitting elements LD connected in parallel.
  • a luminance of the pixel PXL may correspond to a sum of brightness of the plurality of light emitting elements LD.
  • a connection direction of the light emitting element LD included in the pixel PXL may be changed.
  • one side end of the light emitting element LD may be connected to the second power line PL 2 , and the other side end thereof may be connected to the first power line PL 1 .
  • directions of the voltages applied between the first power line PL 1 and the second power line PL 2 may be opposite to each other.
  • FIG. 3 is a schematic plan view illustrating an area of a light emitting device including a unit emission area according to an embodiment of the present disclosure
  • FIG. 4 is a cross-sectional view taken along a line I ⁇ I' of FIG. 3
  • FIG. 5 a is an enlarged cross-sectional view of a portion EA 1 of FIG. 4
  • FIG. 5 b is an enlarged cross-sectional view of a portion EA 2 of FIG. 4
  • FIGS. 6 a and 6 b are diagrams schematically illustrating an energy band diagram of a first layer, the first semiconductor layer, the second semiconductor layer, and a second layer.
  • the unit emission area of the light emitting device is a pixel area PXA in which one pixel PXL including at least one light emitting element LD is disposed, and may include an emission area where light is emitted.
  • the unit emission area is referred to as the pixel area PXA.
  • a display element part DPL including the light emitting element LD may be provided in the pixel area PXA.
  • the display element part DPL may be connected to the first and second power lines PL 1 and PL 2 .
  • the first power line PL 1 and the second power line PL 2 may be provided and/or formed on the substrate SUB to be spaced apart from each other.
  • Each of the first and second power lines PL 1 and PL 2 may extend in one direction, for example, in a second direction DR 2 .
  • the first and second power lines PL 1 and PL 2 may extend in various directions.
  • the first and second power lines PL 1 and PL 2 may be formed of a conductive material (or substance).
  • a predetermined signal (or voltage) of a constant level may be applied to each of the first and second power lines PL 1 and PL 2 .
  • an external signal or voltage
  • each of the first and second power lines PL 1 and PL 2 may receive the predetermined signal (or voltage) from a configuration through an electrical connection with the configuration to which the predetermined signal (or voltage) is applied in the light emitting device.
  • a barrier layer BRL may be provided and/or formed on the first and second power lines PL 1 and PL 2 .
  • the barrier layer BRL may prevent an impurity from diffusing into the display element part DPL.
  • the barrier layer BRL may include an inorganic insulating layer including an inorganic material.
  • the barrier layer BRL may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the barrier layer BRL may be provided as a single layer, but may be provided as a multilayer of at least a double layer. When the barrier layer BRL is provided as the multilayer, each layer may be formed of the same material or may be formed of different materials.
  • the barrier layer BRL may be omitted according to a material, a process condition, and the like of the substrate SUB.
  • the first and second power lines PL 1 and PL 2 or at least one of the first and second power lines PL 1 and PL 2 may be provided and/or formed on the barrier layer BRL.
  • one area of the first power line PL 1 may be exposed to the outside through a first contact hole CH 1 passing through the barrier layer BRL
  • one area of the second power line PL 2 may be exposed to the outside through a second contact hole CH 2 passing through the barrier layer BRL.
  • the display element part DPL may be provided and/or formed on the barrier layer BRL.
  • the display element part DPL may be formed on the barrier layer BRL on the substrate SUB.
  • the display element part DPL may include at least one insulating layer.
  • one insulating layer is formed on each of an upper portion and a lower portion of the light emitting element LD, but the present disclosure is not limited thereto.
  • a first insulating layer INS 1 in the display element part DPL, a first insulating layer INS 1 , the light emitting element LD disposed on the first insulating layer INS 1 , first and second layers FL and SL that are in contact with both ends EP 1 and EP 2 of the light emitting element LD, a second insulating layer INS 2 disposed on the second layer SL, and the like may be formed.
  • the display element part DPL may further include a bank pattern (not shown) provided and/or formed in a peripheral area of the pixel area PXA of each pixel PXL to define the pixel area PXA of each pixel PXL.
  • a bank pattern (not shown) provided and/or formed in a peripheral area of the pixel area PXA of each pixel PXL to define the pixel area PXA of each pixel PXL.
  • Each of the first and second power lines PL 1 and PL 2 may overlap the bank pattern on the substrate SUB or may be disposed outside the bank pattern.
  • the first insulating layer INS 1 may be disposed on the barrier layer BRL.
  • the first insulating layer INS 1 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the first insulating layer INS 1 may be provided as a single layer, but may be provided as a multilayer of a double layer or more. In an embodiment of the present disclosure, the first insulating layer INS 1 may be formed of silicon oxide (SiO x ) and may be provided as a single layer.
  • At least one light emitting element LD may be disposed on the first insulating layer INS 1 .
  • a plurality of light emitting elements LD may be disposed on the first insulating layer INS 1 .
  • Each of the light emitting elements LD may be a light emitting element having an ultra-small size, for example, as small as a nano scale to a micro scale, using a material of an inorganic crystal structure.
  • each of the light emitting elements LD may be a light emitting element of an ultra-small size manufactured by an etching method.
  • each of the light emitting elements LD may be the light emitting element including the emission stack pattern 10 in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked along the length L direction, and the insulating film 14 surrounding the outer circumferential surface (or surface) of the emission stack pattern 10 , and manufactured by an etching method, as shown in FIGS. 1 a to 4 .
  • Two to tens of light emitting elements LD may be provided in the pixel area PXA, but the number of light emitting elements LD is not limited thereto.
  • each of the light emitting elements LD may emit any one of color light and/or white light.
  • Each of the light emitting elements LD may be disposed on the first insulating layer INS 1 so that the length L direction corresponds to a first direction DR 1 crossing a thickness direction DR 3 of the display element part DPL.
  • each light emitting element LD may be disposed on the first insulating layer INS 1 so that the length L direction is parallel to the first direction DR 1 .
  • the light emitting elements LD may be input to the pixel area PXA through an inkjet printing method, a slit coating method, or other various methods.
  • the light emitting elements LD may be mixed with a volatile solvent and supplied to the pixel area PXA through an inkjet printing method or a slit coating method.
  • the light emitting elements LD may be disposed on the first insulating layer INS 1 disposed in the pixel area PXA. After the light emitting elements LD are supplied, the solvent may be evaporated or removed by other methods to finally provide the light emitting elements LD to the pixel area PXA.
  • Each of the light emitting elements LD may have the first end EP 1 and the second end EP 2 in the length L direction.
  • the first end EP 1 of each of the light emitting elements LD may be one of the first and second semiconductor layers 11 and 13
  • the second end EP 2 of each of the light emitting elements LD may be the other one of the first and second semiconductor layers 11 and 13 .
  • the first end EP 1 of each of the light emitting elements LD may be the first semiconductor layer 11 including the n-type semiconductor layer
  • the second end EP 2 thereof may be the second semiconductor layer 13 including the p-type semiconductor layer.
  • the first layer FL may be provided and/or formed on the light emitting elements LD.
  • the first layer FL may include a hydrogenated amorphous silicon (a-Si:H) semiconductor material.
  • the first layer FL may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material doped with a p-type dopant such as Mg.
  • the first layer FL may be in contact with the both ends EP 1 and EP 2 of each of the light emitting elements LD.
  • the first layer FL may be in contact with each of one area of the first end EP 1 of each of the light emitting elements LD and one area of the second end EP 2 of each of the light emitting elements LD.
  • the first layer FL may be in direct contact with a first area A 1 of the upper surface 13 b of the second semiconductor layer 13 of each light emitting element LD.
  • the first layer FL may be in direct contact with a first area B 1 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD.
  • the upper surface 13 b of the second semiconductor layer 13 and the lower surface 11 a of the first semiconductor layer 11 may be surfaces which are not surrounded by the insulating film 14 and which are at least partially exposed to the outside.
  • the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the first layer FL, and the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the first layer FL, may be less than the diameter D of the emission stack pattern 10 .
  • the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the first layer FL, and the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the first layer FL, may have the same thickness (or width).
  • first area A 1 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the first layer FL
  • first area B 1 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the first layer FL, may have different thicknesses (or widths).
  • the first layer FL may be provided and/or formed on an upper surface of each of the light emitting elements LD.
  • the first layer FL may be provided and/or formed on the first insulating layer INS 1 provided with the light emitting elements LD, and may be provided and/or formed on each of the upper surface of the light emitting elements LD and the first insulating layer INS 1 .
  • the above-described first layer FL may be electrically and/or physically connected to the first power line PL 1 through the first contact hole CH 1 .
  • the first layer FL may be electrically and/or physically connected to the first power line PL 1 through a separate connection means (not shown) and the first contact hole CH 1 .
  • the separate connection means may be a configuration for connecting the first power line PL 1 and the first layer FL, and may correspond to a second bridge pattern BRP 2 of FIG. 9 to be described later. Accordingly, the predetermined signal (or voltage) applied to the first power line PL 1 may be transferred to the first layer FL.
  • An interlayer insulating layer ILD may be provided and/or formed on the first layer FL.
  • the interlayer insulating layer ILD may be provided and/or formed on each of the light emitting elements LD and the first layer FL.
  • the interlayer insulating layer ILD may be an inorganic insulating layer including an inorganic material.
  • the interlayer insulating layer ILD may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the interlayer insulating layer ILD may be provided as a single layer, but may be provided as a multilayer of at least a double layer.
  • the interlayer insulating layer ILD may be formed of silicon oxide (SiO x ) and may be configured as a single layer.
  • the present disclosure is not limited thereto.
  • the interlayer insulating layer ILD may be provided and/or formed on the first layer FL that is in contact with the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 of each light emitting element LD.
  • the interlayer insulating layer ILD may be provided and/or formed on the first layer FL that is in contact with the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD. Accordingly, the interlayer insulating layer ILD may be in contact with another area of the upper surface 13 b of the second semiconductor layer 13 of each light emitting element LD and another area of the lower surface 11 a of the first semiconductor layer 11 . For example, as shown in FIG.
  • the interlayer insulating layer ILD may be in directly contact with the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 of each light emitting element LD.
  • the interlayer insulating layer ILD may be in contact with the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD.
  • the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the interlayer insulating layer ILD, and the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the interlayer insulating layer ILD, may be less than the diameter D of the emission stack pattern 10 .
  • the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the interlayer insulating layer ILD, and the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the interlayer insulating layer ILD may have the same thickness (or width).
  • the present disclosure is not limited thereto, and according to an embodiment, the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the interlayer insulating layer ILD, and the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the interlayer insulating layer ILD, may have different thicknesses (or widths).
  • the second layer SL may be provided and/or formed on the interlayer insulating layer ILD.
  • the second layer SL may be provided and/or formed on each of the light emitting elements LD and the interlayer insulating layer ILD.
  • the second layer SL may be formed of a transparent oxide semiconductor material having high electron mobility.
  • the second layer SL may be formed of a transparent oxide semiconductor material such as a-IGZO.
  • the second layer SL may be in contact with the both ends EP 1 and EP 2 of each of the light emitting elements LD.
  • the second layer SL may be in contact with still another area of the first end EP 1 of each light emitting element LD and still another area of the second end EP 2 of each light emitting element LD.
  • the second layer SL may be in directly contact with a third area A 3 of the upper surface 13 b of the second semiconductor layer 13 of each light emitting element LD.
  • the second layer SL may be in direct contact with a third area B 3 of the lower surface 11 a of each light emitting element LD.
  • the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL, and the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the second layer SL, may be less than the diameter D of the emission stack pattern 10 .
  • the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL, and the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the second layer SL, may have the same thickness (or width).
  • the present disclosure is not limited thereto, and according to an embodiment, the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL, and the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the second layer SL, may have different thicknesses (or widths).
  • the second layer SL may be provided and/or formed on the interlayer insulating layer ILD disposed on the upper surfaces of the light emitting elements LD.
  • the above-described interlayer insulating layer ILD may be positioned between the first layer FL and the second layer SL.
  • the first layer FL and the second layer SL may be spaced apart from each other because of the interlayer insulating layer ILD. That is, the first layer FL and the second layer SL may be electrically and/or physically separated from each other.
  • the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the first layer FL
  • the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the interlayer insulating layer ILD
  • the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 which is in contact with the second layer SL may have the same thickness (or width).
  • the present disclosure is not limited thereto, and according to an embodiment, the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the first layer FL, the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the interlayer insulating layer ILD, and the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL may have different thicknesses (or widths).
  • two areas among the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the first layer FL, the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the interlayer insulating layer ILD, and the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL may have the same thickness (or width).
  • the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the first layer FL
  • the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the interlayer insulating layer ILD
  • the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the second layer SL may have the same thickness (or width).
  • first area B 1 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the first layer FL
  • the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the interlayer insulating layer ILD
  • the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 which is in contact with the second layer SL may have different thicknesses (or widths).
  • two areas among the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the first layer FL, the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the interlayer insulating layer ILD, and the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the second layer SL may have the same thickness (or width).
  • the second layer SL may be electrically and/or physically connected to the second power line PL 2 through the second contact hole CH 2 .
  • the second layer SL may extend to the outside of the pixel area PXA where the bank pattern is positioned (for example, one area of the second power line PL 2 exposed by the second contact hole CH 2 ), and may be connected to the second power line PL 2 .
  • the predetermined signal (or voltage) applied to the second power line PL 2 may be transferred to the second layer SL.
  • the predetermined signal applied to the second power line PL 2 may be set as low potential power
  • the predetermined signal (or voltage) applied to the first power line PL 1 may be set as high potential power.
  • the above-described first layer FL may be formed of a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material, and may have a band gap lower than that of the second layer SL because of a material property.
  • a Fermi level Ef of the second semiconductor layer 13 including the p-type GaN semiconductor may exist slightly above a valence band Ev.
  • the Fermi level Ef of the first semiconductor layer 11 including the n-type GaN semiconductor material may exit slightly under a conduction band Ec.
  • the first layer FL including the p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material and the second semiconductor layer 13 including the p-type GaN semiconductor are in contact with each other may have a low energy barrier with respect to a hole h+ because of a material property of the second semiconductor layer 13 that is in contact with the first layer FL, for example, the Fermi level Ef.
  • the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 where the first layer FL including the p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material and the first semiconductor layer 11 including the n-type GaN semiconductor are in contact with each other may have a high energy barrier with respect to an electron e- because of a material property of the first semiconductor layer 11 that is in contact with the first layer FL, for example, the Fermi level Ef.
  • the second layer SL may have a band gap higher than that of the first layer FL formed of the p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material.
  • a-Si:H p-type hydrogenated amorphous silicon
  • the second layer SL may have high electron mobility because of the material property having a high band gap. As shown in FIG.
  • the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 where the second layer SL formed of the a-IGZO and the second semiconductor layer 13 including the p-type GaN semiconductor are in contact with each other may have a high energy barrier with respect to the hole h+ and the electron e- because of the material property of the second semiconductor layer 13 that is in contact with the second layer SL.
  • the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 where the second layer SL formed of the a-IGZO and the first semiconductor layer 11 including the n-type GaN semiconductor are in contact with each other may have a low energy barrier with respect to the electron e- because of the material property of the first semiconductor layer 11 that is in contact with the second layer SL.
  • the electron e- may be selectively injected into the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , and the hole h+ may be selectively injected into the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 .
  • the hole h+ may be injected into the second semiconductor layer 13 through a junction surface of the first layer FL having the low energy barrier for the hole h+ and the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 .
  • the electron e- may be injected into the first semiconductor layer 11 through a junction surface of the second layer SL having the low energy barrier for the electron e- and the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 .
  • the second semiconductor layer 13 may supply the hole h+ to the active layer 12
  • the first semiconductor layer 11 may supply the electron e- to the active layer 12 . Accordingly, the electron e- and the hole h+ may recombine in the active layer 12 of each light emitting element LD to transit to a low energy level, and light (or rays) having a wavelength corresponding thereto may be emitted.
  • the electron e- and the hole h+ do not move to the first semiconductor layer 11 because of the material property of the first semiconductor layer 11 in the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the first layer FL. That is, flow of the electron e- and flow of the hole h+ may be blocked in the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the first layer FL.
  • the electron e- and the hole h+ do not move to the second semiconductor layer 13 because of the material property of the second semiconductor layer 13 in the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL. That is, flow of the electron e- and flow of the hole h+ may be blocked in the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the second layer SL.
  • the hole h+ may be injected into the second semiconductor layer 13 through the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 , which is in contact with the first layer FL, the electron e- may be injected into the first semiconductor layer 11 through the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 , which is in contact with the second layer SL, and thus each light emitting element LD may emit light.
  • the first layer FL may function as a hole injection layer for injecting the hole h+ into one area of the second semiconductor layer 13
  • the second layer SL may function as an electron injection layer for injecting the electron e- into one area of the first semiconductor layer 11 .
  • a second insulating layer INS 2 may be provided and/or formed on the second layer SL.
  • the second insulating layer INS 2 may cover the second layer SL to protect the second layer SL.
  • the second insulating layer INS 2 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the first insulating layer INS 1 may be provided as a single layer, but may be also provided as a multilayer of a double layer or more.
  • the second insulating layer INS 2 may include the same material as the first insulating layer INS 1 , but the present disclosure is not limited thereto.
  • the first layer FL, the interlayer insulating layer ILD, and the second layer SL may be disposed on the light emitting elements LD supplied to the pixel area PXA, and a predetermined signal (or voltage) may be applied to the both ends EP 1 and EP 2 of each of the light emitting elements LD through the first layer FL that is in contact with the first semiconductor layer 11 of each light emitting element LD and the second layer SL that is in contact with the first semiconductor layer 11 of each light emitting element LD. Accordingly, each of the light emitting elements LD may emit light.
  • alignment electrodes or alignment lines
  • the light emitting elements LD may be aligned in the pixel area PXA without alignment electrodes (or alignment lines), a manufacturing process of the light emitting element may be simplified and manufacturing cost may be reduced.
  • a size of the pixel PXL may be reduced by minimizing a process margin of the pixel area PXA. Accordingly, high resolution implementation of the light emitting device may become easy.
  • FIG. 7 is a cross-sectional view illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure, and is a cross-sectional view taken along the line I ⁇ I' of FIG. 3 .
  • FIG. 7 a point different from that of the above-described embodiment is mainly described in order to avoid an overlapping description.
  • a portion which is not specifically described in the present disclosure is in accordance with the above-described embodiment, and the same numbers indicate the same components and similar numbers indicate similar components.
  • the display element part DPL including the light emitting element LD may be provided in the pixel area PXA in which one pixel PXL is provided (or prepared).
  • the display element part DPL may further include first and second conductive lines CL 1 and CL 2 .
  • the display element part DPL may include the first conductive line CL 1 disposed on the barrier layer BRL on the substrate SUB, the first insulating layer INS 1 disposed on the first conductive line CL 1 , the light emitting element LD disposed on the first insulating layer INS 1 , the first layer FL disposed on the light emitting element LD, the interlayer insulating layer ILD disposed on the first layer FL, the second layer SL disposed on the interlayer insulating layer ILD, the second insulating layer INS 2 disposed on the second layer SL and the second conductive line CL 2 disposed on the second insulating layer INS 2 .
  • the first conductive line CL 1 may be provided and/or formed between the barrier layer BRL and the first insulating layer INS 1 .
  • the first conductive line CL 1 may include a metal or a metal oxide, and may use, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, an oxide or an alloy thereof, and the like alone or in combination, but is not limited thereto.
  • the first conductive line CL 1 may include indium tin oxide (ITO).
  • a predetermined signal (or voltage) may be applied to the first conductive line CL 1 .
  • the second conductive line CL 2 may be provided and/or formed on the second insulating layer INS 2 .
  • the second conductive line CL 2 may include the same material as the first conductive line CL 1 , but the present disclosure is not limited thereto. According to an embodiment, the second conductive line CL 2 may include a material different from that of the first conductive line CL 1 .
  • the second conductive line CL 2 may include indium tin oxide (ITO). A predetermined signal (or voltage) may be applied to the second conductive line CL 2 .
  • the predetermined signal (or voltage) applied to the first conductive line CL 1 and the predetermined signal (or voltage) applied to the second conductive line CL 2 may be different from each other, and for example, the signals applied to each of the first and second conductive lines CL 1 and CL 2 may be driving power for driving the pixel PXL.
  • the predetermined signal (or voltage) applied to the first conductive line CL 1 may be set as low potential power
  • the predetermined signal (or voltage) applied to the second conductive line CL 2 may be set as high potential power.
  • the predetermined signal (or voltage) applied to the first conductive line CL 1 may be same as the predetermined signal (or voltage) applied to the second power line PL 2 .
  • an electric field may be formed in an arrow direction shown in FIG. 7 between the first conductive line CL 1 and the second conductive line CL 2 .
  • the electric field may be formed in a direction from the first conductive line CL 1 to the second conductive line CL 2 .
  • an HE11 mode of light emitted from the active layer 12 of the light emitting element LD may be strengthened.
  • the HE11 mode may include an HE11x mode and an HE11y mode in which polarization states of light are perpendicular to each other within an optical fiber of a single mode.
  • the HE11x mode may mean a state in which the light emitted from the active layer 12 of each light emitting element LD is polarized along the length L direction of each light emitting element LD.
  • the HE11x mode may mean a state in which the light emitted from the active layer 12 of each light emitting element LD is polarized along the first direction DR1.
  • the HE11y mode may mean a state in which the light emitted from the active layer 12 of each light emitting element LD is polarized along a direction crossing the length L direction of each light emitting element LD.
  • the HE11y mode may mean a state in which the light emitted from the active layer 12 of each light emitting element LD is polarized along the third direction DR3.
  • the HE11x mode may be strengthened. Accordingly, amount (or intensity) of the light emitted from the active layer 12 of each light emitting element LD and polarized in the first direction DR1 may increase. For example, the amount (or the intensity) of light proceeding from the active layer 12 of each light emitting element LD to each of the first semiconductor layer 11 and the second semiconductor layer 13 in the first direction DR 1 may increase. Accordingly, light output efficiency of each light emitting element LD may be further improved.
  • FIG. 8 is a schematic plan view illustrating a unit emission area of a light emitting device according to an embodiment of the present disclosure
  • FIG. 9 is a cross-sectional view corresponding to a line II ⁇ II' of FIG. 8 .
  • FIGS. 8 and 9 a point different from that of the above-described embodiment is mainly described in order to avoid an overlapping description.
  • the display element part DPL including the light emitting element LD may be provided in the pixel area PXA in which one pixel PXL is provided (or prepared).
  • the display element part DPL may include the first conductive line CL 1 , the first insulating layer INS 1 , the light emitting element LD, the first layer FL, the interlayer insulating layer ILD, the second layer SL, the second insulating layer INS 2 , and the second conductive line CL 2 .
  • the display element part DPL may further include a cover layer CVL provided and/or formed on the second conductive line CL 2 .
  • the cover layer CVL may be provided and/or formed on the second conductive line CL 2 to overlap each of the light emitting elements LD.
  • the cover layer CVL may function as a light guide member for guiding light emitted from each of the light emitting elements LD to be concentrated in a specific direction of the pixel area PXA.
  • the cover layer CVL may be formed of a conductive material (or substance) having a constant reflectance.
  • the conductive material (or substance) may include an opaque metal advantageous for guiding the light emitted from the light emitting elements LD in a specific direction (for example, a desired direction) by reflecting or scattering the light.
  • the opaque metal may include, for example, a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof.
  • the cover layer CVL may include a transparent conductive material.
  • the transparent conductive material may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), a conductive polymer such as PEDOT, and the like.
  • a separate conductive layer formed of an opaque metal for guiding the light emitted from the light emitting elements LD in a specific direction (for example, a desired direction) may be additionally included.
  • the material of the cover layer CVL is not limited to the above-described materials.
  • a grating may be formed on an inner or outer surface of the cover layer CVL to more efficiently generate a light path.
  • the light emitted from the light emitting elements LD may be intensively guided in a specific direction (for example, a desired direction).
  • a direction of the light emitted from each pixel PXL may be substantially the same, and thus a light output deviation between each pixel PXL and the pixel PXL adjacent thereto may be reduced. Accordingly, the light emitting device may have a uniform light output distribution over the entire area.
  • FIG. 10 is a plan view illustrating a display device according to an embodiment of the present disclosure and schematically illustrating an example of a display device using the light emitting element shown in FIGS. 1 a and 1 b as a light emitting source.
  • FIG. 10 for convenience, a structure of the display device is briefly shown based on a display area where an image is displayed.
  • at least one driving circuit part for example, a scan driver, a data driver, and the like
  • a plurality of signal lines which are not shown, may be further disposed in the display device.
  • the display device may include the substrate SUB, a plurality of pixels PXL provided on the substrate SUB, a driver (not shown) for driving the pixels PXL, and a line part (not shown) connecting the pixels PXL and the driver.
  • the display device may be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD.
  • each of the pixels PXL may include a driving transistor that controls a current amount supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, and the like.
  • the substrate SUB may include a transparent insulating material and may transmit light.
  • the substrate SUB may be a rigid substrate or a flexible substrate.
  • the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.
  • the flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material.
  • the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.
  • the material applied to the substrate SUB may preferably have resistance (or heat resistance) to a high processing temperature during a manufacturing process of the display device.
  • the substrate SUB may include a display area DA including at least one pixel area in which each pixel PXL is disposed, and a non-display area NDA disposed around the display area DA.
  • the display area DA may be disposed in a central area of the display device, and the non-display area NDA may be disposed in an edge area of the display device to surround the display area DA.
  • positions of the display area DA and the non-display area NDA are not limited thereto, and according to an embodiment, the positions of the display area DA and the non-display area NDA may be changed.
  • the display area DA may be an area in which the pixels PXL displaying an image are provided.
  • the non-display area NDA may be an area in which the driver for driving the pixels PXL and a portion of the line part connecting the pixels PXL and the driver are provided.
  • the display area DA may have various shapes.
  • the display area DA may be provided in various shapes, such as a polygon of a closed shape including a side formed of a straight line, a circle, an ellipse, and the like including a side of a curve, a semicircle, a semi-ellipse, and the like including a side formed of a straight line and a curve.
  • the non-display area NDA may be provided at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the display area DA.
  • Each of the pixels PXL may be provided in the display area DA on the substrate SUB.
  • the pixels PXL may be arranged in the display area DA in a stripe or pentile array structure, but the present disclosure is not limited thereto.
  • Each of the pixels PXL may include at least one light emitting element LD driven by corresponding scan signal and data signal.
  • the light emitting element LD may have a size as small as a micro scale or a nano scale and may be spaced apart with adjacent light emitting elements by a predetermined distance, but the present disclosure is not limited thereto.
  • the light emitting element LD may configure a light source of each pixel PXL.
  • Each of the pixels PXL may be driven by a predetermined signal (for example, a scan signal and a data signal) and/or predetermined power (for example, first driving power and second driving power).
  • a type of the light emitting element LD that may be used as the light source of each pixel PXL is not limited thereto.
  • the color, type, number, and/or the like of the pixels PXL are/is not particularly limited, and for example, the color of light emitted from each pixel PXL may be variously changed.
  • the driver may provide a predetermined signal and predetermined power to each pixel PXL through the line part to control driving of the pixel PXL.
  • the line part is omitted for convenience of description.
  • the driver may include a scan driver that provides a scan signal to the pixels PXL through a scan line, an emission driver that provides an emission control signal to the pixels PXL through an emission control line, a data driver that provides a data signal to the pixels PXL through a data line, and a timing controller.
  • the timing controller may control the scan driver, the emission driver, and the data driver.
  • the above-described display device may include a plurality of stretching parts to implement a stretchable display device.
  • the plurality of stretching parts are described with reference to FIGS. 11 a and 11 b .
  • FIGS. 11 a and 11 b are enlarged plan views of a portion EA 3 of FIG. 10 .
  • the display device may include the substrate SUB provided with the pixels PXL.
  • the substrate SUB may include a plurality of islands IS of an island shape, and bridges BR for connecting islands IS neighboring in the first and second directions DR 1 and DR 2 .
  • the substrate SUB may include a cutout V formed by removing one area of the substrate SUB.
  • the islands IS, the bridges BR, and the cutout V may configure a plurality of stretching parts STU of the display device. Each stretching part STU may correspond to a basic stretching part of a stretchable display device.
  • Each island IS may be a substrate SUB of an island shape, and may be spaced apart from an island IS adjacent (or neighboring) in the first direction DR 1 with the cutout V interposed therebetween. In addition, each island IS may be spaced apart from an island IS adjacent (or neighboring) in the second direction DR 2 with the cutout V interposed therebetween. At least one pixel PXL including an emission area EMA from which red, blue, green, and/or white light is emitted may be positioned (or provided) on each island IS.
  • the bridge BR may be provided between the two islands IS spaced apart in the first direction DR 1 and between the two islands IS spaced apart in the second direction DR 2 , respectively.
  • the bridge BR may be one area of the substrate SUB connecting two islands IS adjacent to each other. Lines for transferring power and/or a signal to the pixel PXL provided in each island IS may be provided on the bridge BR. Because of the lines provided on the bridge BR, the pixels PXL positioned on each island IS may be driven while receiving the power and/or the signal.
  • a shape and an area (or a size) of the cutout V may change for stretch of the display device.
  • the cutout V may be positioned between two islands IS adjacent to each other in the first and second directions DR1 and DR2, between one island IS and the bridge BR, and between two bridges BR adjacent to each other in the first and second directions DR 1 and DR 2 .
  • the cutout V may be formed to pass through the substrate SUB.
  • the cutout V may provide a separation area between the islands IS, reduce a weight of the substrate SUB, and improve flexibility of the substrate SUB.
  • stress generation during deformation of the substrate SUB may be effectively reduced, thereby preventing abnormal deformation of the substrate SUB and improving durability.
  • the cutout V may be formed by removing one area of the substrate SUB in a method of etching or the like, but the present disclosure is not limited thereto.
  • the substrate SUB may be formed to include the cutout V when the substrate SUB is manufactured.
  • the cutout V may be formed by patterning the substrate SUB after forming the islands IS and the bridges BR.
  • a method of forming the cutout V in the substrate SUB is not limited to the above-described embodiment, and the cutout V may be formed through various methods.
  • the display device may be stretched while the shape and the area (or the size) of the cutout V included in the substrate SUB is changed.
  • the display device may be stretched in various directions, for example, the first direction DR 1 , the second direction DR 2 , an oblique direction of each of the first and second directions DR 1 and DR 2 , a direction (for example, a left direction) opposite to the first direction DR 1 , a direction (for example, an upward direction) opposite to the second direction DR 2 , and the like.
  • the shape and/or the area (or the size) of each island IS may hardly change, and only a position thereof may change.
  • the pixels PXL positioned on each of the islands IS may be maintained without damage.
  • a shape and/or an area (or a size) of the bridges BR connecting the two adjacent islands IS may be deformed.
  • each island IS is similar to a quadrangle shape, but the present disclosure is not limited thereto, and the shape of the island IS may be variously modified.
  • the shape of each bridge BR connecting the two adjacent islands IS is not limited to that shown in FIGS. 11 a and 11 b and may be variously modified.
  • FIGS. 12 a and 12 b are circuit diagrams illustrating an electrical connection relationship between components included in one pixel shown in FIG. 10 according to an embodiment.
  • FIGS. 12 a and 12 b show the electrical connection relationship between the components included in the pixel PXL that may be applied to the active type display device, according to different embodiments.
  • types of the components included in the pixel PXL to which an embodiment of the present disclosure may be applied are not limited thereto.
  • each pixel PXL shown in FIGS. 12 a and 12 b may be any one of the pixels PXL included in the display device of FIG. 10 , and the pixels PXL may have substantially the same or similar structure.
  • one pixel PXL may include an emission unit EMU that emits light.
  • the pixel PXL may selectively further include a pixel circuit 144 for driving the emission unit EMU and improving light output efficiency of light emitted from the emission unit EMU.
  • the emission unit EMU may include a plurality of light emitting elements LD disposed between the first power line PL 1 to which the first driving power VDD is applied and the second power line PL 2 to which the second driving power VSS is applied.
  • the one end (for example, the second semiconductor layer 13 ) of the both ends of each of the light emitting elements LD may be connected to the first driving power VDD through the first layer FL, and the other end (for example, the first semiconductor layer 11 ) of the both ends of each of the light emitting elements LD may be connected to the second driving power VSS through the second layer SL.
  • the first driving power VDD and the second driving power VSS may have different potentials.
  • the first driving power VDD may be set as high potential power
  • the second driving power VSS may be set as low potential power.
  • a potential difference between the first driving power VDD and the second driving power VSS may be set as a threshold voltage or more of the light emitting elements LD during an emission period of the pixel PXL.
  • the respective the light emitting elements LD disposed between the first power line PL 1 and the second power line PL 2 to which signals (or voltages) of different potentials are respectively supplied may configure respective effective light sources.
  • Such effective light sources may be gathered to form the emission unit EMU of the pixel PXL.
  • the light emitting elements LD of the emission unit EMU may emit light with a luminance corresponding to a driving current supplied through the corresponding pixel circuit 144 .
  • the pixel circuit 144 may supply a driving current corresponding to a grayscale value of corresponding frame data to the emission unit EMU during each frame period.
  • the driving current supplied to the emission unit EMU may be divided and flow to the light emitting elements LD. Therefore, each of the light emitting elements LD may emit light with a luminance corresponding to the current flowing through the light emitting element LD, and thus the emission unit EMU may emit light of the luminance corresponding to the driving current.
  • the pixel circuit 144 may be connected to a scan line Si and a data line Dj of a corresponding pixel PXL.
  • the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.
  • the pixel circuit 144 may include first and second transistors T 1 and T 2 and a storage capacitor Cst as shown in FIG. 12 a .
  • a structure of the pixel circuit 144 is not limited to the embodiment shown in FIG. 12 a .
  • the pixel circuit 144 may include the first and second transistors T 1 and T 2 and the storage capacitor Cst.
  • a first terminal of the second transistor T 2 may be connected to the data line Dj, and a second terminal may be connected to a first node N 1 .
  • the first terminal and the second terminal of the second transistor T 2 may be different terminals, and for example, when the first terminal is a source electrode, the second terminal may be a drain electrode.
  • a gate electrode of the second transistor T 2 may be connected to the scan line Si.
  • the second transistor T 2 may be turned on when a scan signal of a voltage (for example, a low voltage) at which the second transistor T 2 may be turned on from the scan line Si is supplied, to electrically connect the data line Dj and the first node N 1 to each other. At this time, a data signal of a corresponding frame is supplied to the data line Dj, and thus the data signal is transferred to the first node N 1 . The data signal transferred to the first node N 1 is charged in the storage capacitor Cst.
  • a scan signal of a voltage for example, a low voltage
  • a first terminal of the first transistor T 1 may be connected to the first driving power VDD, and a second terminal thereof may be electrically connected to the first electrode of each of the light emitting elements LD.
  • a gate electrode of the first transistor T 1 may be connected to the first node N 1 .
  • the first transistor T 1 controls an amount of the driving current supplied to the light emitting elements LD in response to a voltage of the first node N 1 .
  • One electrode of the storage capacitor Cst may be connected to the first driving power VDD, and another electrode thereof may be connected to the first node N 1 .
  • the storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N 1 and maintains the charged voltage until the data signal of a next frame is supplied.
  • FIG. 12 a shows the pixel circuit 144 including the second transistor T 2 for transferring the data signal into the pixel PXL, the storage capacitor Cst for storing the data signal, and the first transistor T 1 for supplying the driving current corresponding to the data signal to the light emitting elements LD.
  • the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be variously modified and implemented.
  • the pixel circuit 144 may further include other circuit elements such as at least one transistor element such as a transistor element for compensating for a threshold voltage of the first transistor T 1 , a transistor element for initializing the first node N 1 , and/or a transistor element for controlling a light emission time of the light emitting element LD, or a boosting capacitor for boosting the voltage of the first node N 1 .
  • the transistors included in the pixel circuit 144 for example, the first and second transistors T 1 and T 2 are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first and second transistors T 1 and T 2 included in the pixel circuit 144 may be changed to an N-type transistor.
  • the pixel circuit 144 may be connected to the scan line Si and the data line Dj of the pixel PXL.
  • the pixel circuit 144 of the corresponding pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.
  • the pixel circuit 144 may be further connected to at least another scan line.
  • the pixel PXL disposed in the i-th row of the display area DA may be further connected to an (i-1)-th scan line Si-1 and/or an (i+1)-th scan line Si+1.
  • the pixel circuit 144 may be further connected to third power in addition to the first driving power VDD and the second driving power VSS.
  • the pixel circuit 144 may also be connected to initialization power Vint.
  • the pixel circuit 144 may include first to seventh transistors T 1 to T 7 and a storage capacitor Cst.
  • One electrode for example, a source electrode of the first transistor T 1 (driving transistor) may be connected to the first driving power VDD via the fifth transistor T 5 , and another electrode thereof, for example, a drain electrode may be connected to one side end of the light emitting elements LD via the sixth transistor T 6 .
  • a gate electrode of the first transistor T 1 may be connected to a first node N 1 .
  • the first transistor T 1 controls the driving current flowing between the first driving power VDD and the second driving power VSS via the light emitting elements LD in response to a voltage of the first node N 1 .
  • the second transistor T 2 (switching transistor) may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T 1 .
  • a gate electrode of the second transistor T 2 may be connected to the i-th scan line Si connected to the pixel PXL.
  • the second transistor T 2 may be turned on when a scan signal of a gate-on voltage (for example, a low voltage) is supplied from the i-th scan line Si, to electrically connect the j-th data line Dj to the source electrode of the first transistor T 1 . Therefore, when the second transistor T 2 is turned on, the data signal supplied from the j-th data line Dj is transferred to the first transistor T 1 .
  • a gate-on voltage for example, a low voltage
  • the third transistor T 3 may be connected between the drain electrode of the first transistor T 1 and the first node N 1 .
  • a gate electrode of the third transistor T 3 may be connected to the i-th scan line Si.
  • the third transistor T 3 may be turned on when the scan signal of the gate-on voltage is supplied from the i-th scan line Si, to electrically connect the drain electrode of the first transistor T 1 and the first node N 1 to each other.
  • the fourth transistor T 4 may be connected between the first node N 1 and an initialization power line to which the initialization power Vint is applied.
  • a gate electrode of the fourth transistor T 4 may be connected to a previous scan line, for example, the (i-1)-th scan line Si-1.
  • the fourth transistor T 4 may be turned on when the scan signal of the gate-on voltage is supplied to the (i-1)-th scan line Si-1, to transmit a voltage of the initialization power Vint to the first node N 1 .
  • the initialization power Vint may have a voltage equal to or less than the lowest voltage of the data signal.
  • the fifth transistor T 5 may be connected between the first driving power VDD and the first transistor T 1 .
  • a gate electrode of the fifth transistor T 5 may be connected to a corresponding emission control line, for example, an i-th emission control line Ei.
  • the fifth transistor T 5 may be turned off when an emission control signal of a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.
  • the sixth transistor T 6 may be connected between the first transistor T 1 and the one end of the light emitting elements LD.
  • a gate electrode of the sixth transistor T 6 may be connected to the i-th emission control line Ei.
  • the sixth transistor T 6 may be turned off when the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.
  • the seventh transistor T 7 may be connected between the one end of the light emitting elements LD and the initialization power line to which the initialization power Vint is applied.
  • a gate electrode of the seventh transistor T 7 may be connected to any one of next scan lines, for example, the (i+1)-th scan line Si+1.
  • the seventh transistor T 7 may be turned on when the scan signal of the gate-on voltage is supplied to the (i+1)-th scan line Si+1, to supply the voltage of the initialization power Vint to the one end of the light emitting elements LD.
  • the storage capacitor Cst may be connected between the first driving power VDD and the first node N 1 .
  • the storage capacitor Cst may store a data signal supplied to the first node N 1 and a voltage corresponding to the threshold voltage of the first transistor T 1 during each frame period.
  • a structure of the pixel PXL applicable to the present disclosure is not limited to the embodiments shown in FIGS. 12 a and 12 b , and the corresponding pixel PXL may have various structures.
  • FIG. 13 is a plan view schematically illustrating one pixel among the pixels shown in FIG. 10
  • FIG. 14 is a cross-sectional view taken along a line III ⁇ III' of FIG. 13
  • FIG. 15 is an enlarged plan view of a portion EA 4 of FIG. 14
  • FIG. 16 is a schematic plan view implementing the cover layer shown in FIG. 13 according to another embodiment.
  • FIGS. 13 to 16 simplify and show a structure of the one pixel PXL, such as showing each electrode as a single electrode layer and each insulating layer as a single insulating layer, but the disclosure is not limited thereto.
  • the term “formed and/or disposed on the same layer” may mean formed in the same process, and the term “formed and/or disposed on different layers” may mean formed in different processes.
  • connection between two configurations may mean that both of an electrical connection and a physical connection are used inclusively.
  • the display device may include the substrate SUB, the line part, and the plurality of pixels PXL.
  • the substrate SUB may be a stretchable substrate formed of a material having flexibility to be bent or folded, and may have a single layer structure or a multilayer structure.
  • the substrate SUB may include a polymer material such as silicon elastomer or polyurethane, but the present disclosure is not limited thereto.
  • the substrate SUB may include the display area DA including at least one pixel area PXA in which the pixel PXL is disposed, and the non-display area NDA disposed around the display area DA.
  • Each pixel PXL may include the island IS including at least one pixel PXL and at least one bridge BR connected to the island IS.
  • the bridge BR may include first to fourth bridges BR 1 to BR 4 respectively connected to four sides of the island IS of the corresponding pixel PXL.
  • the number of bridges BR is not limited thereto.
  • the island IS may include the pixel area PXA in which the pixel PXL is provided.
  • the first and third bridges BR 1 and BR 3 may be areas of the substrate SUB extending in the second direction DR 2 or ‘vertical direction’, and may connect two pixels PXL adjacent (or neighboring) in the second direction DR2 when viewed in a plan view.
  • the second and fourth bridges BR 2 and BR 4 may be areas of the substrate SUB extending in the first direction DR 1 or ‘horizontal direction’, and may connect two pixels PXL adjacent (or neighboring) in the first direction DR 1 when viewed in a plan view.
  • the pixel area PXA in which each pixel PXL is disposed (or prepared) may include the emission area EMA in which light is emitted and a peripheral area surrounding a periphery of the emission area EMA.
  • the peripheral area may include a non-emission area in which light is not emitted.
  • the line part may include a plurality of signal lines that transfer a signal (or a voltage) to each pixel PXL.
  • the signal lines may include, for example, the scan line Si transferring the scan signal to each pixel PXL, the data line Dj transferring the data signal to each pixel PXL, the first power line PL 1 transferring the first driving power VDD to each pixel PXL, the second power line PL 2 transferring the second driving power VSS to each pixel PXL, and the like.
  • the line part may further include signal lines transferring other signals in addition to the above-described signal lines.
  • the substrate SUB, the pixel circuit part PCL, and the display element part DPL may be provided and/or formed in the pixel area PXA of each pixel PXL.
  • the pixel circuit part PCL is described first, and then the display element part DPL is described.
  • the pixel circuit part PCL may include a buffer layer BFL, the pixel circuit 144 , and a protective layer PSV.
  • the buffer layer BFL may prevent an impurity from diffusing into a transistor included in the pixel circuit (refer to ‘ 144 ’ of FIG. 12 ).
  • the buffer layer BFL may be the same configuration as the barrier layer BRL described with reference to FIG. 4 .
  • the pixel circuit 144 may include at least one transistor and the storage capacitor Cst.
  • the transistor may include a driving transistor Tdr controlling a driving current of each of the light emitting elements LD and a switching transistor (not shown) connected to the driving transistor Tdr.
  • the above-described switching transistor may have the same configuration as the second transistor T 2 described with reference to FIGS. 12 a and 12 b .
  • a configuration included in the pixel circuit 144 is not limited to the above-described embodiment, and the pixel circuit 144 may include circuit elements that perform another function in addition to the driving transistor Tdr and the switching transistor.
  • the driving transistor Tdr and the switching transistor when one of the driving transistor Tdr and the switching transistor is arbitrarily referred to or the driving transistor Tdr and the switching transistor are collectively referred to, the one of the driving transistor Tdr and the switching transistor or the driving transistor Tdr and the switching transistor are referred to as the transistor T or transistors T.
  • Each of the transistors T may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE.
  • the first terminal SE may be any one of a source electrode and a drain electrode
  • the second terminal DE may be the other electrode.
  • the first terminal SE is a source electrode
  • the second terminal DE may be a drain electrode.
  • the transistor semiconductor pattern SCL may be provided and/or formed on the buffer layer BFL.
  • the transistor semiconductor pattern SCL may include a first contact area contacting the first terminal SE and a second contact area contacting the second terminal DE. An area between the first contact area and the second contact area may be a channel area.
  • the transistor semiconductor pattern SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, oxide semiconductor, or the like.
  • the channel area is a semiconductor pattern that is not doped with an impurity, and may be an intrinsic semiconductor.
  • the first contact area and the second contact area may be semiconductor patterns doped with an impurity.
  • the gate electrode GE may be provided and/or formed on the transistor semiconductor pattern SCL with a first gate insulating layer GI 1 interposed therebetween.
  • the first gate insulating layer GI 1 may be an inorganic insulating layer including an inorganic material.
  • the first gate insulating layer GI 1 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the material of the first gate insulating layer GI 1 is not limited to the above-described embodiments.
  • the first gate insulating layer GI 1 may be formed of an organic insulating layer including an organic material.
  • the first gate insulating layer GI 1 may be provided as a single layer, but may be also provided as a multilayer of at least a double layer.
  • the respective first terminal SE and second terminal DE may be in contact with the first contact area and the second contact area of the transistor semiconductor pattern SCL through a contact hole sequentially passing through the first interlayer insulating layer GI 1 and a second gate insulating layer GI 2 .
  • the second gate insulating layer GI 2 may be an inorganic insulating layer including an inorganic material.
  • the second gate insulating layer GI 2 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the second gate insulating layer GI 2 may include the same material as the first gate insulating layer GI 1 .
  • the second gate insulating layer GI 2 may be provided as a single layer, but may be also provided as a multilayer of at least a double layer.
  • the first and second terminals SE and DE of each of the transistors T are described as separate electrodes electrically connected to the transistor semiconductor pattern SCL, but the present disclosure is not limited thereto.
  • the first terminal SE of each of the transistors T may be one of the first and second contact areas adjacent to the channel area of the corresponding transistor semiconductor pattern SCL
  • the second terminal DE of each of the transistors T may be the other of the first and second contact areas adjacent to the channel area of the corresponding transistor semiconductor pattern SCL.
  • the second terminal DE of each of the transistors T may be electrically connected to the light emitting elements LD of the corresponding pixel PXL through a separate connection means such as a bridge electrode or a contact electrode.
  • the transistors T included in the pixel circuit 144 may be configured of LTPS thin film transistors, but the present disclosure is not limited thereto, and may be configured of an oxide semiconductor thin film transistor according to an embodiment.
  • the transistors T are thin film transistors having a top gate structure is described as an example, but the present disclosure is not limited thereto.
  • the transistors T may be thin film transistors having a bottom gate structure.
  • the first power line PL 1 and the second power line PL 2 may be provided and/or formed on the second gate insulating layer GI 2 .
  • the first power line PL 1 and the second power line PL 2 may be spaced apart from each other by a predetermined distance on the second gate insulating layer GI 2 and may be electrically separated from each other.
  • the first driving power VDD may be applied to the first power line PL 1
  • the second driving power VSS may be applied to the second power line PL 2 .
  • the protective layer PSV may be provided and/or formed on the first and second power lines PL 1 and PL 2 and the transistors T.
  • the protective layer PSV may be disposed on the second interlayer insulating layer ILD 2 .
  • the protective layer PSV may be provided in a form including an organic insulating layer, an inorganic insulating layer, or the organic insulating layer disposed on the inorganic insulating layer.
  • the inorganic insulating layer may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ).
  • the organic insulating layer may include an organic insulating material capable of transmitting light.
  • the organic insulating layer may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimides resin, an unsaturated polyesters resin, a poly-phenylene ethers resin, a poly-phenylene sulfides resin, and a benzocyclobutene resin.
  • the protective layer PSV may be formed of the organic insulating layer.
  • the protective layer PSV may include first to fourth contact holes CH 1 to CH 4 .
  • the first contact hole CH 1 may expose a portion of the first power line PL 1
  • the second contact hole CH 2 may expose a portion of the second power line PL 2
  • the third contact hole CH 3 may expose a portion of the driving transistor Tdr, for example, a portion of the second terminal DE
  • the fourth contact hole CH 4 may expose another portion of the second power line PL 2 .
  • the display element part DPL may include first and second bridge patterns BRP 1 and BRP 2 , a bank pattern BNK, the light emitting elements LD, the first and second layers FL and SL, the interlayer insulating layer ILD, the first and second conductive lines CL 1 and CL 2 , the first and second insulating layers INS 1 and INS 2 , and the cover layer CVL, which are disposed on the pixel circuit part PCL.
  • the first bridge pattern BRP 1 and the second bridge pattern BRP 2 may be provided in the pixel area PXA of each pixel PXL to be spaced apart from each other.
  • the first and second bridge patterns BRP 1 and BRP 2 may be provided and/or formed on the protective layer PSV.
  • the first bridge pattern BRP 1 may be connected to the second terminal DE of the driving transistor Tdr through a third contact hole CH 3 passing through the protective layer PSV.
  • the second bridge pattern BRP 2 may be connected to the first power line PL 1 through the first contact hole CH 1 passing through the protective layer PSV. Accordingly, the first driving power VDD applied to the first power line PL 1 may be transferred to the second bridge pattern BRP 2 , and a predetermined signal (or voltage) applied to the driving transistor Tdr may be transferred to the first bridge pattern BRP 1 .
  • the first conductive line CL 1 may be provided and/or formed on the same layer as the first and second bridge patterns BRP 1 and BRP 2 .
  • the first conductive line CL 1 may be disposed on the protective layer PSV to be spaced apart from the first and second bridge patterns BRP 1 and BRP 2 .
  • the first and second bridge patterns BRP 1 and BRP 2 and the first conductive line CL 1 may include the same material.
  • the first and second bridge patterns BRP 1 and BRP 2 and the first conductive line CL 1 may include metal or metal oxide, and for example, may use chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or an alloy thereof, ITO and the like alone or in combination, but the present disclosure is not limited thereto.
  • the first and second bridge patterns BRP 1 and BRP 2 and the first conductive line CL 1 may include indium tin oxide (ITO).
  • the first conductive line CL 1 may be connected to the second power line PL 2 through second and fourth contact holes CH 2 and CH 4 passing through the protective layer PSV. Accordingly, the second driving power VSS applied to the second power line PL 2 may be transferred to the first conductive line CL 1 .
  • the first insulating layer INS 1 may be provided and/or formed on the first conductive line CL 1 .
  • the first insulating layer INS 1 corresponds to the same configuration as the first insulating layer INS 1 described with reference to FIG. 4 , and thus a description thereof is omitted.
  • the first insulating layer INS 1 may cover a portion of the first conductive line CL 1 , for example, a portion of the protective layer PSV except for a portion that is in contact with the second and fourth contact holes CH 2 and CH 4 .
  • the bank pattern BNK may be provided and/or formed in the peripheral area of the pixel area PXA of each pixel PXL.
  • the bank pattern BNK may surround at least one side of the peripheral area included in the pixel area PXA of each of the pixels PXL.
  • the bank pattern BNK may be a structure defining (or partitioning) the emission area EMA of each pixel PXL and each of the pixels PXL adjacent thereto, and may be, for example, a pixel defining layer.
  • the bank pattern BNK may be configured to include at least one light blocking material and/or reflective material to prevent a light leakage defect in which light (or rays) is leaked between each pixel PXL and the pixels PXL adjacent thereto.
  • a reflective material layer may be formed on the bank pattern BNK to further improve efficiency of light emitted from each pixel PXL.
  • the light emitting elements LD may be provided and/or formed on the first insulating layer INS 1 positioned in one area (for example, a center area of the pixel area PXA in a plan view) of the pixel area PXA surrounded by the bank pattern BNK.
  • Each of the light emitting elements LD may be the light emitting element including the emission stack pattern 10 in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked along the length L direction, and the insulating film 14 surrounding the outer circumferential surface (or surface) of the emission stack pattern 10 , and manufactured by an etching method.
  • Each of the light emitting elements LD may be disposed on the first insulating layer INS 1 so that the length L direction is parallel to the first direction DR 1 .
  • the light emitting elements LD may be input to the pixel area PXA through an inkjet printing method, a slit coating method, or other various methods.
  • Each of the light emitting elements LD may have the first end EP 1 and the second end EP 2 in the length L direction.
  • the first end EP 1 of each of the light emitting elements LD may be the first semiconductor layer 11
  • the second end EP 2 of each of the light emitting elements LD may be the second semiconductor layer 13 .
  • the first layer FL may be provided and/or formed on the light emitting elements LD.
  • the first layer FL may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material doped with a p-type dopant such as Mg.
  • a-Si:H p-type hydrogenated amorphous silicon
  • the first layer FL may be in contact with the both ends EP 1 and EP 2 of each of the light emitting elements LD.
  • the first layer FL may be in direct contact with the first area B 1 of the first semiconductor layer 11 of each light emitting element LD, and may be in direct contact with the first area A 1 of the second semiconductor layer 13 .
  • the first layer FL may be in contact with the second bridge pattern BRP 2 to be connected to the second bridge pattern BRP 2 . Accordingly, the first driving power VDD applied to the second bridge pattern BRP 2 may be transferred to the first layer FL.
  • the hole may be selectively injected into one of the first and second semiconductor layers 11 and 13 .
  • the first semiconductor layer 11 may be made of n-type GaN
  • the second semiconductor layer 13 may be made of p-type GaN. Accordingly, the material properties (for example, Fermi levels) of the first semiconductor layer 11 and the second semiconductor layer 13 may be different.
  • the hole may be selectively injected into only one area of the second semiconductor layer 13 .
  • a predetermined signal for example, the first driving power VDD is applied to the first layer FL
  • the hole may be injected into the first area A 1 of the second semiconductor layer 13 which is in contact with the first layer FL, and the hole may not be injected into the first area B 1 of the first semiconductor layer 11 .
  • the above-described first layer FL may function as a hole injection layer for selectively injecting the hole into the second semiconductor layer 13 of each of the light emitting elements LD.
  • the interlayer insulating layer ILD may be provided and/or formed on the first layer FL.
  • the interlayer insulating layer ILD may have the same configuration as the interlayer insulating layer ILD described with reference to FIG. 4 .
  • the interlayer insulating layer ILD may be disposed on the first layer FL and may be in contact with the both ends EP 1 and EP 2 of each of the light emitting elements LD.
  • the interlayer insulating layer ILD may be in direct contact with the second area B 2 of the first semiconductor layer 11 of each light emitting element LD, and may be in direct contact with the second area A 2 of the second semiconductor layer 13 of each light emitting element LD.
  • the second layer SL may be provided and/or formed on the interlayer insulating layer ILD.
  • the second layer SL may be formed of a transparent oxide semiconductor material such as a-IGZO.
  • the second layer SL may be provided and/or formed on the interlayer insulating layer ILD and the light emitting elements LD.
  • the second layer SL may be provided and/or formed on one area of the bank pattern BNK and the first bridge pattern BRP 1 .
  • the present disclosure is not limited thereto, and according to an embodiment, the second layer SL may not be provided and/or formed on the first bridge pattern BRP 1 .
  • the second layer SL may be in contact with the both ends EP 1 and EP 2 of each of the light emitting elements LD.
  • the second layer SL may be in direct contact with the third area B 3 of the first semiconductor layer 11 of each light emitting element LD, and may be in direct contact with the third area A 3 of the second semiconductor layer 13 .
  • the second layer SL may be disposed on the first conductive line CL 1 to be connected to the first conductive line CL 1 . Accordingly, the second driving power VSS applied to the first conductive line CL 1 may be transferred to the second layer SL.
  • the electron may be selectively injected into one of the first and second semiconductor layers 11 and 13 .
  • the electron may be selectively injected into only one area of the first semiconductor layer 11 .
  • the electron when a predetermined signal (or voltage), for example, the second driving power VSS is applied to the second layer SL, the electron may be injected into only the third area B 3 of the first semiconductor layer 11 that is in contact with the second layer SL, and the electron may not be injected into the third area A 3 of the second semiconductor layer 13 .
  • a predetermined signal for example, the second driving power VSS
  • the above-described second layer SL may function as an electron injection layer that selectively injects the electron into the first semiconductor layer 11 of each of the light emitting elements LD.
  • the first layer FL and the second layer SL may be electrically and/or physically separated by the interlayer insulating layer ILD disposed therebetween.
  • the first area A 1 of the second semiconductor layer 13 that is in contact with the first layer FL, the second area A 2 of the second semiconductor layer 13 that in contact with the interlayer insulating layer ILD, and the third area A 3 of the second semiconductor layer 13 that is in contact with the second layer SL may be the upper surface 13 b of the second semiconductor layer 13 .
  • a value obtained by summing a thickness of the first area A 1 of the second semiconductor layer 13 , the second area A 2 , and a thickness of the third area A 3 of the second semiconductor layer 13 may be the same as the diameter D of each light emitting element LD.
  • the first area B 1 of the first semiconductor layer 11 that is in contact with the first layer FL, the second area B 2 of the first semiconductor layer 11 that is in contact with the interlayer insulating layer ILD, and the third area B 3 of the first semiconductor layer 11 that is in contact with the second layer SL may be the lower surface 11 a of the first semiconductor layer 11 .
  • a value obtained by summing a thickness of the first area B 1 of the first semiconductor layer 11 , a thickness of the second area B 2 of the first semiconductor layer 11 , and a thickness of the third area B 3 of the first semiconductor layer 11 may be the same as the diameter D of each light emitting element LD.
  • the second insulating layer INS 2 may be provided and/or formed on the second layer SL.
  • the second insulating layer INS 2 may include the same material as the first insulating layer INS 1 .
  • the second insulating layer INS 2 may be formed of an inorganic insulating layer such as silicon oxide (SiO x ).
  • SiO x silicon oxide
  • the second insulating layer INS 2 may cover the second layer SL so that the second layer SL is not exposed to the outside.
  • the second conductive line CL 2 may be provided and/or formed on the second insulating layer INS 2 .
  • the second conductive line CL 2 may include the same material as the first conductive line CL 1 .
  • the second conductive line CL 2 may include indium tin oxide (ITO).
  • the second conductive line CL 2 may be provided and/or formed on another area of the bank pattern BNK on which the second layer SL is not provided, and although not illustrated, the second conductive line CL 2 may be connected to the first bridge pattern BRP 1 .
  • the second conductive line CL 2 may be electrically connected to a partial configuration of the pixel circuit part PCL, for example, the driving transistor Tdr, through the first bridge pattern BRP 1 . Accordingly, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transferred to the second conductive line CL 2 .
  • the second conductive line CL 2 may be positioned on each light emitting element LD, and the first conductive line CL 1 may be positioned under each light emitting element LD.
  • the first conductive line CL 1 and the second conductive line CL 2 may be respectively positioned on and under each light emitting element LD interposed therebetween.
  • the second driving power VSS may be applied to the first conductive line CL 1 through the second power line PL 2
  • the predetermined signal (or voltage) applied to the driving transistor Tdr may be applied to the second conductive line CL 2 through the first bridge pattern BRP 1
  • the predetermined signal (or voltage) applied to the driving transistor Tdr may be potential power higher than that of the second driving power VSS.
  • an electric field may be formed between the first conductive line CL 1 and the second conductive line CL 2 .
  • the electric field may be formed in a direction from the first conductive line CL 1 to the second conductive line CL 2 .
  • the HE11 mode of the light emitted from the active layer 12 of each light emitting element LD may be strengthened. Accordingly, the amount (or intensity) of the light proceeding from the active layer 12 of each light emitting element LD to each of the first semiconductor layer 11 and the second semiconductor layer 13 may increase, and thus the light output efficiency of each light emitting element LD may be further improved.
  • the cover layer CVL may be provided and/or formed on the second conductive line CL 2 .
  • the cover layer CVL may be disposed on the uppermost layer among configurations provided in each pixel area PXA, and may cover the light emitting elements LD when viewed in a plan view.
  • the cover layer CVL may function as a light guide member for guiding the light emitted from each of the light emitting elements LD to be concentrated in a specific direction of the pixel area PXA.
  • the cover layer CVL may be formed of a conductive material (or substance) having a constant reflectance.
  • the conductive material (or substance) may include an opaque metal advantageous for guiding the light emitted from the light emitting elements LD in a specific direction (for example, a desired direction) by reflecting or scattering the light.
  • the cover layer CVL may not overlap the bank pattern BNK in the pixel area PXA, and may overlap an inner area surrounded by the bank pattern BNK, for example, an area where the light emitting elements LD are disposed.
  • the light emitted from each of the light emitting elements LD positioned under the cover layer CVL may be reflected or scattered by the cover layer CVL and may proceed in the specific direction. Accordingly, light may be intensively emitted only from a specific area of the pixel area PXA. For example, as shown in FIG. 13 , an area between the bank pattern BNK and the cover layer CVL in the pixel area PXA may become the emission area EMA from which the light is emitted.
  • a position of the emission area EMA from which the light is emitted in the pixel area PXA may be finally determined by the cover layer CVL.
  • the cover layer CVL when the cover layer CVL is disposed in the pixel area PXA in which each pixel PXL is provided, the light emitted from the light emitting elements LD may be intensively guided in the specific direction (for example, a desired direction).
  • the position of the cover layer CVL provided in the pixel area PXA of each pixel PXL is the same as the position of the cover layer CVL provided to the pixels PXL adjacent to each pixel PXL
  • positions of the emission areas EMA from which the light is emitted in each of the pixels PXL may be substantially the same. Accordingly, a light output deviation between each pixel PXL and the pixel PXL adjacent thereto may be reduced, and the display device according to an embodiment of the present disclosure may have a uniform light output distribution over the entire area.
  • the cover layer CVL does not overlap the bank pattern BNK in the pixel area PXA, but the present disclosure is not limited thereto.
  • the cover layer CVL may overlap one area of the bank pattern BNK.
  • the light emitted from each of the light emitting elements LD may proceed to a specific area of the pixel area PXA, for example, another area of the bank pattern BNK spaced apart from the cover layer CVL by a predetermined distance without overlapping the cover layer CVL.
  • a separation space between the other area of the bank pattern BNK (for example, the area spaced apart from the cover layer CVL without overlapping the cover layer CVL) and the cover layer CVL may be determined as the emission area EMA from which the light is emitted.
  • An overcoat layer OC may be provided and/or formed on the cover layer CVL.
  • the overcoat layer OC may be a planarization layer that relieves a step difference generated by configurations disposed thereunder, the light emitting elements LD, the bank pattern BNK, the first and second layers FL and SL, and the first and second conductive lines CL 1 and CL 2 , the first and second insulating layers INS 1 and INS 2 , and the like.
  • the overcoat layer OC may be an encapsulation layer that prevents oxygen and moisture from penetrating into the light emitting elements LD.
  • FIGS. 17 a to 17 k are schematic plan views sequentially illustrating a method of manufacturing one pixel shown in FIG. 13
  • FIGS. 18 a to 18 k are cross-sectional views sequentially illustrating a method of manufacturing one pixel shown in FIG. 14 .
  • FIGS. 13 and 14 the pixel according to an embodiment of the present disclosure shown in FIGS. 13 and 14 is sequentially described according to a manufacturing method in conjunction with FIGS. 17 a to 17 k and 18 a to 18 k .
  • a partial configuration of the pixel circuit part PCL is formed on a substrate SUB.
  • the partial configuration of the pixel circuit part PCL may include the driving transistor Tdr, the first and second power lines PL 1 and PL 2 , and at least one insulating layer.
  • the at least one insulating layer may include the buffer layer BFL and the first and second gate insulating layers GI 1 and GI 2 sequentially formed on the substrate SUB.
  • a first insulating material layer (not shown) is applied on the driving transistor Tdr and the first and second power lines PL 1 and PL 2 , and then a photo process, a curing process, and a descum process (a process of removing a remainder (or a residue) generated when a process is progressed) are sequentially performed, to form the protective layer PSV.
  • the protective layer PSV may include the third contact hole CH 3 exposing a portion of the driving transistor Tdr, the first contact hole CH 1 exposing a portion of the first power line PL 1 , the second contact hole CH 2 exposing a portion of the second power line PL 2 , and the fourth contact hole CH 4 exposing another portion of the second power line PL 2 .
  • a transparent metal oxide such as indium tin oxide (ITO) may be deposited on the protective layer PSV, and a photo process, an etching process, and a strip process are sequentially performed, to form the first bridge pattern BRP 1 , the second bridge pattern BRP 2 , and the first conductive line CL 1 spaced apart from each other on the protective layer PSV.
  • the etching process may be a wet etching process, but the present disclosure is not limited thereto.
  • the first bridge pattern BRP 1 may be electrically and/or physically connected to the driving transistor Tdr through the third contact hole CH 3 passing through the protective layer PSV.
  • the second bridge pattern BRP 2 may be electrically and/or physically connected to the first power line PL 1 through the first contact hole CH 1 passing through the protective layer PSV.
  • the first conductive line CL 1 may be electrically and/or physically connected to the second power line PL 2 through the second and fourth contact holes CH 2 and CH 4 passing through the protective layer PSV.
  • a second insulating material layer (not shown) formed of silicon oxide (SiO x ) is applied on the first bridge pattern BRP 1 , the second bridge pattern BRP 2 , and the first conductive line CL 1 , and then a photo process, an etching process, and a strip process are sequentially performed, to form the first insulating layer INS 1 .
  • the etching process may be a dry etching process, but the present disclosure is not limited thereto.
  • the first insulating layer INS 1 may be formed on a portion of the first conductive line CL 1 .
  • a third insulating material layer (not shown) is applied on the protective layer PSV on which the first insulating layer INS 1 is formed, and then a photo process, a curing process, and a descum process are sequentially performed, to form the bank pattern BNK.
  • a mixed solution including the light emitting elements LD is input to the pixel area PXA of each of the pixels PXL using an inkjet printing method or the like.
  • an inkjet nozzle may be disposed on the first insulating layer INS 1 , and a solvent mixed with the plurality of light emitting elements LD may be input into the pixel area PXA of each of the pixels PXL through the inkjet nozzle.
  • the solvent may be any one or more of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto.
  • the solvent may be in a form of an ink or paste.
  • a method of inputting the light emitting elements LD into the pixel area PXA of each of the pixels PXL is not limited to the above-described embodiment, and the method of inputting the light emitting elements LD may be variously changed.
  • the solvent may be removed.
  • the light emitting elements LD may be positioned on one area of the pixel area PXA of each of the pixels PXL, for example, on the first insulating layer INS 1 of an inner area surrounded by the bank pattern BNK without overlapping the bank pattern BNK.
  • an hydrogenated amorphous silicon (a-Si:H) semiconductor material is applied on the light emitting elements LD and the first insulating layer INS 1 , and a PHT process, an etching process, a strip process, and a process of injecting a p-type dopant are sequentially performed, to form the first layer FL.
  • the etching process may be a dry etching process, but the present disclosure is not limited thereto.
  • the first layer FL may be formed of a p-type hydrogenated amorphous silicon semiconductor material and may be formed on the first insulating layer INS 1 . In addition, the first layer FL may be disposed on each light emitting element LD.
  • the first layer FL may contact one area of the both ends EP 1 and EP 2 of each light emitting element LD.
  • the first layer FL may be in contact with the first area B 1 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD and the first area A 1 of the upper surface 13 b of the second semiconductor layer 13 .
  • a fourth insulating material layer (not shown) formed of silicon oxide (SiO x ) is applied on the first layer FL, and then a photo process, an etching process, and a strip process are sequentially performed, to form the interlayer insulating layer ILD.
  • the etching process may be a dry etching process, but the present disclosure is not limited thereto.
  • the interlayer insulating layer ILD may be formed on the first layer FL and may be in contact with another area of the both ends EP 1 and EP 2 of each light emitting element LD.
  • the interlayer insulating layer ILD may be in contact with the second area B 2 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD and the second area A 2 of the upper surface 13 b of the second semiconductor layer 13 .
  • a transparent metal oxide formed of a-IGZO is applied on the interlayer insulating layer ILD, and then a photo process, an etching process, and a strip process are sequentially performed, to form the second layer SL.
  • the etching process may be a wet etching process, but the present disclosure is not limited thereto.
  • the second layer SL may be formed on the interlayer insulating layer ILD.
  • the second layer SL may be formed on the first conductive line CL 1 exposed to the outside without being covered by the first insulating layer INS 1 in which the bank pattern BNK is formed on one area. Accordingly, the second layer SL may be electrically and/or physically connected to the second power line PL 2 through the first conductive line CL 1 . Additionally, the second layer SL may be formed on the first bridge pattern BRP 1 .
  • the second layer SL may be in contact with still another area of the both ends EP 1 and EP 2 of each light emitting element LD.
  • the second layer SL may be in contact with each of the third area B 3 of the lower surface 11 a of the first semiconductor layer 11 of each light emitting element LD and the third area A 3 of the upper surface 13 b of the second semiconductor layer 13 .
  • a fifth insulating material layer (not shown) formed of silicon oxide (SiO x ) is applied on the second layer SL, and then a photo process, an etching process, and a strip process are sequentially performed, to form the second insulating layer INS 2 .
  • the etching process may be a dry etching process, but the present disclosure is not limited thereto.
  • the second insulating layer INS 2 may be formed on the second layer SL to protect the second layer SL.
  • a transparent metal oxide such as indium tin oxide (ITO) is deposited on the second insulating layer INS 2 , and a photo process, an etching process, and a strip process are sequentially performed, to form the second conductive line CL 2 .
  • ITO indium tin oxide
  • the etching process may be a wet etching process, but the present disclosure is not limited thereto.
  • the second conductive line CL 2 may be formed on the second insulating layer INS 2 and may be formed on the first bridge pattern BRP 1 . Accordingly, the second conductive line CL 2 may be electrically and/or physically connected to the driving transistor Tdr through the first bridge pattern BRP 1 .
  • the cover layer CVL is formed on the second conductive line CL 2 .
  • the cover layer CVL may be formed in an area of the pixel area PXA surrounded by the bank pattern BNK without overlapping the bank pattern BNK, for example, in the center (or middle) of the pixel area PXA.
  • the cover layer CVL may be formed on the second conductive line CL 2 to correspond to an area in which the light emitting elements LD are positioned.
  • the present disclosure is not limited thereto, and according to an embodiment, the position of the cover layer CVL may be variously changed.
  • the overcoat layer OC is formed on the cover layer CVL.

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KR102605335B1 (ko) * 2018-06-27 2023-11-27 삼성디스플레이 주식회사 발광 표시 장치 및 그의 제조 방법
KR102585158B1 (ko) * 2018-07-04 2023-10-05 삼성디스플레이 주식회사 표시 장치
KR102606922B1 (ko) * 2018-07-06 2023-11-27 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR102552602B1 (ko) * 2018-07-10 2023-07-10 삼성디스플레이 주식회사 발광 장치, 그의 제조 방법, 및 이를 구비한 표시 장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230206843A1 (en) * 2021-12-29 2023-06-29 Lg Display Co., Ltd. Display device

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