US20220320215A1 - Display apparatus - Google Patents
Display apparatus Download PDFInfo
- Publication number
- US20220320215A1 US20220320215A1 US17/570,270 US202217570270A US2022320215A1 US 20220320215 A1 US20220320215 A1 US 20220320215A1 US 202217570270 A US202217570270 A US 202217570270A US 2022320215 A1 US2022320215 A1 US 2022320215A1
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- United States
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Images
Classifications
-
- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H01L27/3262—
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- H01L27/3276—
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- a connection area from among the plurality of connection areas may connect a pixel area in the i th row and the (j ⁇ 1)th column to a pixel area in the i th row and the j th column from among the plurality of pixel areas; and a contact area from among the plurality of contact areas may connect the pixel area in the i th row and the j th column to a pixel area in the i th row and the (j+1) th column from among the plurality of pixel areas.
- FIG. 7 is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment
- FIG. 8 is an equivalent circuit diagram of a plurality of pixels according to another embodiment
- At least one of the first voltage line VL1 and the second voltage line VL2 may include horizontal lines extending in the second direction DR2, and the horizontal lines may be connected to the vertical lines.
- the timing controller 140 receives the image source data RGB and a control signal CONT from the outside.
- the timing controller 140 may convert the image source data RGB into image data DATA based on features of the display 110 and the pixels PX.
- the timing controller 140 may provide the image data DATA to the data driver 130 .
- the gate driver 120 may use the first and second gate voltages VGH and VGL provided from the voltage generator 150 , and may sequentially generate the first scan signals GW_1 to GW_m, the second scan signals GI_1 to GI_m, and the third scan signals GB_1 to GB_m in response to the gate timing control signal GDC provided from the timing controller 140 .
- the data driver 130 may sample and latch the image data DATA provided from the timing controller 140 in response to the data timing control signal DDC provided from the timing controller 140 , thus converting the image data DATA into data in a parallel data system.
- the data driver 130 may convert the image data DATA into a gamma reference voltage, and may then convert the gamma reference voltage into a data voltage of an analog type.
- the data driver 130 provides the data voltages Dm_1 to Dm_n to the pixels PX through the data lines DL_1 to DL_n.
- the pixels PX receive the data voltages Dm_1 to Dm_n in response to the first scan signals GW_1 to GW_m.
- the data lines DL_j-1, DL_j, and DL_J+1 may each extend in the first direction DR1, and may be configured to deliver the data voltages Dm_j ⁇ 1, Dm_j, and Dm_j+1 to the pixels PX arranged in the same column, respectively.
- the data lines DL_j-1, DL_j, and DL_J+1 may be connected to the first to third pixels PXi(j ⁇ 1), PXij, and PXi(j+1) by thirteenth contact plugs CP13, respectively.
- the second voltage lines VL2 may include second vertical lines VL2v and second horizontal lines VL2h.
- the second vertical lines VL2v may each extend in the first direction DR1, and may be configured to deliver the second initialization voltage VINT2 to the pixels PX in the same column.
- the second horizontal lines VL2h may each extend in the second direction DR2, and may be configured to deliver the second initialization voltage VINT2 to the pixels PX in the same row.
- FIGS. 3A and 3B illustrate that the second voltage lines VL2 include the second vertical lines VL2v and the second horizontal lines VL2h. In another example, however, one of the second vertical lines VL2v or the second horizontal lines VL2h may be omitted. In another embodiment, some of the second vertical lines VL2v may be omitted, or some of the second horizontal lines VL2h may be omitted.
- the third scan line GBL_i may surround (e.g., around a periphery of) at least part of the third contact plug CP3.
- a portion GBLp of the third scan line GBL_i, which is adjacent to the third contact plug CP3, may be bent at least once.
- a planar shape of the portion GBLp of the third scan line GBL_i may be an omega (0) shape.
- the second pixel PXij includes a light-emitting element OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst.
- the light-emitting element OLED may be an organic light-emitting diode including an anode and a cathode.
- the cathode may be a common electrode to which the second driving voltage ELVSS is applied.
- the light-emitting element OLED is omitted in FIG. 3B .
- the storage capacitor Cst is connected between the power line PL and a gate of the driving transistor T1.
- the storage capacitor Cst may include an upper electrode CE 2 connected to the power line PL, and a lower electrode CE 1 connected to the gate of the driving transistor T1.
- the storage capacitor Cst is connected between a horizontal power line PLh of the power line PL and the gate of the driving transistor T1.
- the storage capacitor Cst may include the upper electrode CE 2 connected to the horizontal power line PLh of the power line PL, and the lower electrode CE 1 connected to the gate of the driving transistor T1.
- the driving transistor T1 may control a value of a current Id flowing from the power line PL to the light-emitting element OLED, according to the gate-source voltage thereof.
- the driving transistor T1 may include the gate connected to the lower electrode CE 1 of the storage capacitor Cst, a source connected to the power line PL through the first emission control transistor T5, and a drain connected to the light-emitting element OLED through the second emission control transistor T6.
- the driving transistor T1 may output the driving current Id to the light-emitting element OLED according to the gate-source voltage thereof.
- the value of the driving current Id is determined based on a difference between the gate-source voltage of the driving transistor T1 and a threshold voltage.
- the light-emitting element OLED may receive the driving current Id from the driving transistor T1, and may emit light having a brightness corresponding to the value of the driving current Id.
- the scan transistor T2 may be configured to deliver the data voltage Dm_j to the driving transistor T1 in response to the first scan signal GW_i.
- the scan transistor T2 may include a gate connected to the first scan line GWL_i, a source connected to the data line GL_J, and a drain connected to the source of the driving transistor T1.
- the second emission control transistor T6 may connect the drain of the driving transistor T1 to the anode of the light-emitting element OLED in response to the emission control signal EM_i.
- the second emission control transistor T6 may include a gate connected to the emission control line EML_i, a source connected to the drain of the driving transistor T1, and a drain connected to the anode of the light-emitting element OLED.
- the drain of the second emission control transistor T6 may be connected to the anode of the light-emitting element OLED through the connection line CML, a fifteenth contact plug CP15, and a sixteenth contact plug CP16.
- the scan transistor T2 and the compensation transistor T3 are turned on, and the data voltage Dm_j is received through the source of the driving transistor T1.
- the driving transistor T1 is diode-connected through the compensation transistor T3, and is biased in a forward direction.
- a gate voltage of the driving transistor T1 increases from the first initialization voltage VINT1.
- which is obtained by subtracting a threshold voltage Vth of the driving transistor T1 from the data voltage Dm_j
- the driving transistor T1 is turned off, and an increase in the gate voltage of the driving transistor T1 stops. Accordingly, in the storage capacitor Cst, a difference ELVDD— Dm_j+
- the anode initialization transistor T7 is turned on, and the second initialization voltage VINT2 is applied to the anode of the light-emitting element OLED.
- the second initialization voltage VINT2 is applied to the anode of the light-emitting element OLED.
- a level of the second initialization voltage VINT2 may be higher than a level of the first initialization voltage VINT1, and may be lower than a level of a portion of the second driving voltage ELVSS that is as high as the threshold voltage of the light-emitting element OLED. Because the light-emitting element OLED has a relatively large size, the light-emitting element OLED may significantly have a great capacitance. Furthermore, because the level of the first initialization voltage VINT1 is too low, the light-emitting element OLED may start to emit light in a next frame after a considerable delay.
- the anode of the light-emitting element OLED is initialized according to the second initialization voltage VINT2 having a higher level than that of the first initialization voltage VINT1, and thus, the light-emitting element OLED may start emitting light faster in a next frame. In other words, an emission delay may be reduced.
- the first emission control transistor T5 and the second emission control transistor T6 may be turned on, and the driving transistor T1 may output a driving current Id corresponding to a voltage ELVDD— Dm_j, which is obtained by subtracting the threshold voltage
- the light-emitting element OLED may emit light having a brightness corresponding to a value of the driving current Id.
- a display apparatus may include a semiconductor pattern Act.
- the semiconductor pattern Act may extend (e.g., may continuously extend) in the second direction DR2.
- the semiconductor pattern Act may be integrally formed by extending in the second direction DR2 without any disconnection therein.
- the semiconductor pattern Act of FIG. 4 may partially extend in the first direction DR1, but may generally extend in the second direction DR2 overall.
- the semiconductor pattern Act includes a portion microscopically extending in the first direction DR1, but may generally extend in the second direction DR2 overall.
- the semiconductor pattern Act may include pixel areas Ai(j ⁇ 1), Aij, and Ai(j+1), connection areas Aca arranged between the pixel areas Ai(j ⁇ 1), Aij, and Ai(j+1), and contact areas Acp.
- connection areas Aca and the contact areas Acp may be alternately arranged along the second direction DR2.
- the static electricity generated (or introduced) from the outside may not be isolated, and may be distributed (or moved) in the second direction DR2. Therefore, because the static electricity may not be isolated in the semiconductor pattern Act and may be distributed in the second direction DR2, the damage to the semiconductor pattern Act may be prevented or reduced.
- the first pixel PXi(j ⁇ 1) may include a first emission control transistor T5i(j ⁇ 1).
- the second pixel PXij may include a driving transistor T1ij, a first emission control transistor T5ij, and an anode initialization transistor T7ij.
- the third pixel PXi(j+1) may include an anode initialization transistor T7i(j+1).
- the anode initialization transistor T7i(j+1) of the third pixel PXi(j+1) may include an active area A7i(j+1), and a gate electrode G.
- the active area A7i(j+1) of the anode initialization transistor T7i(j+1) of the third pixel PXi(j+1) may correspond to a portion of the pixel area Ai(j+1) (e.g., see FIG. 4 ) of the third pixel PXi(j+1).
- the substrate 200 may have a single-layer structure or a multilayered structure including one or more of the above materials. When the substrate 200 has a multilayered structure, the substrate 200 may further include an inorganic layer. In some embodiments, the substrate 200 may have a structure of an organic material/an inorganic material/an organic material.
- a barrier layer may be further included between the substrate 200 and the buffer layer 211 .
- the barrier layer may prevent or decrease the penetration of the impurities from the substrate 200 and/or the like, into the active areas A5i(j ⁇ 1), A1ij, A5ij, A7ij, and A7i(j+1), the connection area Aca, and the contact area Acp.
- the barrier layer may include an inorganic material, for example, such as an oxide or a nitride, an organic material, or a composite of organic/inorganic materials, and may have a single-layer structure or a multilayered structure including one or more organic and inorganic materials.
- the active areas A5i(j ⁇ 1), A1ij, A5ij, A7ij, and A7i(j+1), the connection area Aca, and the contact area Acp may each include an oxide semiconductor material.
- the active areas A5i(j ⁇ 1), A1ij, A5ij, A7ij, and A7i(j+1), the connection area Aca, and the contact area Acp may each include, for example, at least one oxide selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).
- a first gate insulating layer 213 and a second gate insulating layer 215 may be stacked to cover the active areas A5i(j ⁇ 1), A1ij, A5ij, A7ij, and A7i(j+1), the connection area Aca, and the contact area Acp.
- connection line CML, the first vertical power line PLv1, the second vertical power line PLv2, and the second voltage line VL2 may be connected to the active areas A5i(j ⁇ 1), A1ij, A5ij, A7ij, and A7i(j+1), the connection area Aca, and the contact area Acp through contact holes formed in insulating layers.
- a pixel electrode 310 of the light-emitting element 300 may be connected to the connection line CML through a contact hole formed in a planarization layer 219 .
- Part of the pixel electrode 310 may be buried in (e.g., may extend through) the contact hole, and the buried part (e.g., a penetrating part) of the pixel electrode 310 may be referred to as the sixteenth contact plug CP16. Because the pixel electrode 310 is connected to the connection line CML, and the connection line CML is connected to the anode initialization transistor T7ij of the second pixel PXij, the connection line CML may connect the light-emitting element 300 to the anode initialization transistor T7ij of the second pixel PXij.
- the second first vertical power line PLv2 may be connected to the connection area Aca through a second contact hole CNT2 formed in the first gate insulating layer 213 , the second gate insulating layer 215 , and the interlayer insulating layer 217 .
- Part of the second vertical power line PLv2 may be buried in (e.g., may extend through) the second contact hole CNT2, and the buried part (e.g., a penetrating part) of the second vertical power line PLv2 may be referred to as the second contact plug CP2.
- the second vertical power line PLv2 may be integrally formed with the second contact plug CP2.
- the pixel-defining layer 221 may include at least one organic insulating material selected from the group consisting of polyimide, polyamide, acryl resin, BCB, and phenol resin.
- the intermediate layer 320 may be individually disposed to corresponding to each of the pixel electrodes 310 .
- the present disclosure is not limited thereto, and various modifications may be made to the intermediate layer 320 .
- the intermediate layer 320 may include a layer that is integrally formed over the pixel electrodes 310 .
- the opposite electrode 330 may be a light-transmissive electrode or a reflection electrode.
- the opposite electrode 330 may be transparent or translucent, and may be a metallic thin film having a low work function including, for example, Li, Ca, LiF/Ca, LiF/AI, Al, Ag, Mg, and/or a combination thereof.
- a transparent conductive oxide (TCO) film for example, such as ITO, IZO, ZnO x , or In 2 O 3 , may be further disposed on the metallic thin film.
- the opposite electrode 330 may be disposed over the display, and on upper portions of the intermediate layer 320 and the pixel-defining layer 221 .
- the opposite electrode 330 may be integrally formed (e.g., commonly formed) for the light-emitting elements 300 , and may correspond to the pixel electrodes 310 .
- FIG. 7 is a schematic cross-sectional view of a portion of a display apparatus according to an embodiment.
- the first voltage line VL1 may include a first vertical line VL1v and a first horizontal line VL1h.
- the second voltage line VL2 may include a second vertical line VL2v and a second horizontal line VL2h.
- the power line PL may include the first vertical power line PLv1 and a horizontal power line PLh.
- the power line PL may include the second vertical power line PLv2.
- the first vertical power line PLv1 is mainly described with reference to FIG. 7 , but the second vertical power line PLv2 may have the same or substantially the same structure as that of the first vertical power line PLv1, and thus, redundant description thereof may not be repeated.
- the interlayer insulating layer 217 may be arranged between the first vertical power line PLv1 and the horizontal power line PLh.
- the first vertical power line PLv1 may be connected to the horizontal power line PLh through the tenth contact hole CNT10 formed in the interlayer insulating layer 217 .
- Part of the first vertical power line PLv1 may be buried in (e.g., may extend through) the tenth contact hole CNT10, and the buried part (e.g., the penetrating part) of the first vertical power line PLv1 may be referred to as the tenth contact plug CP10.
- the tenth contact plug CP10 may penetrate the insulating layer, and may connect the first vertical power line PLv1 to the horizontal power line PLh.
- FIG. 7 illustrates that the horizontal power line PLh may be arranged on the second gate insulating layer 215 , and the first vertical power line PLv1 may be arranged on the interlayer insulating layer 217 , but the present disclosure is not limited thereto.
- the horizontal power line PLh may be arranged on the interlayer insulating layer 217
- the first vertical power line PLv1 may be arranged on the second gate insulating layer 215
- the horizontal power line PLh may be arranged on the first gate insulating layer 213 .
- the horizontal power line PLh and the first vertical power line PLv1 may be at (e.g., in or on) the same layer as each other.
- the horizontal power line PLh may contact (e.g., may directly contact) the first vertical power line PLv1.
- the tenth contact plug CP10 may correspond to a portion where the horizontal power line PLh may contact (e.g., may directly contact) the first vertical power line PLv1.
- the tenth contact plug CP10 may correspond to a portion where the horizontal power line PLh may cross the first vertical power line PLv1.
- the first contact plug CP1′ and the second contact plug CP2′ may correspond to portions of a conductive layer.
- the first contact plug CP1′ and the second contact plug CP2′ may correspond to portions of the conductive layer buried in (e.g., extending through) contact holes formed in an insulating layer.
- the vertical power lines PLv of the power line PL and the second vertical lines VL2v of the second voltage line VL2 may be alternately arranged along the second direction DR2.
- a display apparatus may include the semiconductor pattern Act.
- first contact areas Acp1 and the second contact areas Acp2 may be alternately arranged along the second direction DR2.
- the first pixel PXi(j ⁇ 1) may include the first emission control transistor T5i(j-1).
- the second pixel PXij may include the driving transistor T1ij, the first emission control transistor T5ij, and the anode initialization transistor T7ij.
- the third pixel PXi(j+1) may include the anode initialization transistor T7i(j+1).
- the power line PL may be connected to the first contact area Acp1 of the semiconductor pattern Act through the first contact hole CNT1′ formed in the first gate insulating layer 213 , the second gate insulating layer 215 , and the interlayer insulating layer 217 .
- Part of the power line PL may be buried in (e.g., may extend through) the first contact hole CNT1′, and the buried part (e.g., the penetrating part) of the power line PL may be referred to as the first contact plug CP1′.
- the first contact plug CP1′ may penetrate the insulating layers, and may connect the power line PL to the first contact area Acp1 of the semiconductor pattern Act.
- the insulating layers may be arranged between the second contact area Acp2 of the semiconductor pattern Act and the second voltage line VL2.
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US11783793B1 (en) * | 2022-06-30 | 2023-10-10 | Xiamen Tianma Micro-Electronics Co., Ltd. | Display panel and display device |
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KR102637791B1 (ko) | 2018-02-13 | 2024-02-19 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
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US20230225160A1 (en) * | 2022-01-12 | 2023-07-13 | Samsung Display Co., Ltd. | Display panel |
US11783793B1 (en) * | 2022-06-30 | 2023-10-10 | Xiamen Tianma Micro-Electronics Co., Ltd. | Display panel and display device |
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KR20220138499A (ko) | 2022-10-13 |
US12048198B2 (en) | 2024-07-23 |
CN115206943A (zh) | 2022-10-18 |
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