US20220279656A1 - Method of making a molded interconnect device - Google Patents
Method of making a molded interconnect device Download PDFInfo
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- US20220279656A1 US20220279656A1 US17/749,137 US202217749137A US2022279656A1 US 20220279656 A1 US20220279656 A1 US 20220279656A1 US 202217749137 A US202217749137 A US 202217749137A US 2022279656 A1 US2022279656 A1 US 2022279656A1
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- copper film
- palladium
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- plating
- metallic
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- 238000004519 manufacturing process Methods 0.000 title description 58
- 238000007747 plating Methods 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000000465 moulding Methods 0.000 claims abstract description 16
- 238000009713 electroplating Methods 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract 2
- 239000007924 injection Substances 0.000 claims abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 70
- 229910052802 copper Inorganic materials 0.000 claims description 70
- 239000010949 copper Substances 0.000 claims description 70
- 229910000679 solder Inorganic materials 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000001746 injection moulding Methods 0.000 claims description 9
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- -1 for example Substances 0.000 description 4
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0236—Plating catalyst as filler in insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09118—Moulded substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/51—Plural diverse manufacturing apparatus including means for metal shaping or assembling
- Y10T29/5193—Electrical connector or terminal
Definitions
- MIDs Molded interconnect devices
- a plastic substrate or housing is created and electrical circuits and devices are plated, layered, or implanted upon the plastic substrate.
- MIDs typically have fewer parts than conventionally manufactured devices, which results in space and weight savings.
- Applications for MIDs include mobile telephones, automated teller machines, steering wheel components for automobiles, RFID components, lighting, medical devices and many other consumer and/or commercial products.
- MIDs Current processes for manufacturing MIDs include two-shot molding, laser direct structuring technology (LDS), microscopic integrated processing technology (MIPTEC), and a laser developed additive technology.
- LDS laser direct structuring technology
- MIPTEC microscopic integrated processing technology
- Two-shot molding involves the use of two separate plastic parts, typically one platable and one non-platable.
- the platable part forms the circuitry, and the non-platable part fulfills mechanical functions and completes the molding.
- the two parts are fused together and circuits are created through use of electroless plating.
- the platable plastic is metallized, while the non-platable plastic remains non-conductive.
- LDS technology involves the steps of injection molding (using any of a variety of dielectric thermoplastic materials, including polyamide, polycarbonate, and liquid crystal polymer), laser activation of the thermoplastic material, and then metallization (electroless plating). The laser etches a wiring pattern onto the part and prepares it for metallization. With LDS, only a single thermoplastic material is required thereby making the molding step a one-shot process, and generally preferable as compared to the two-shot molding process.
- MIPTEC technology which is offered by Panasonic Corporation, involves a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- the molding stage includes injection-molding the intended shape using a thermoplastic resin, such as polyphthalamide (PPA).
- a thermoplastic resin such as polyphthalamide (PPA).
- the circuit forming stage includes two steps, namely: (1) metallization; and (2) patterning. Thin copper film is formed in the base metallization process (copper-strike). A laser is then used to remove the copper and outline the circuit pattern, with the wavelength and exposure time of the laser optimized to achieve copper removal without damaging the substrate.
- the plating stage includes two or three steps, namely: (1) electrolytic copper plating; (2) optional soft etching; and (3) electrolytic nickel and gold plating.
- copper is electrically plated to form the circuit pattern.
- soft etching is applied to remove unnecessary copper-strike that was not removed by the laser in the circuit forming stage.
- nickel and gold are plated on the electrolytically-plated copper, forming the circuit pattern to help prevent oxidation and corrosion.
- An optional cutting stage then includes dicing the sheet form into individual MIDs.
- MIPTEC technology like LDS technology, has only a one-shot molding process, but also provides MIDs which can be fine patterned and bare chip mounted.
- thermoplastic materials such as polyamide (PA), polycarbonate (PC) and acrylonitrile butadiene styrene (ABS) or liquid crystal polymer (LCP), to be used in the process.
- PA polyamide
- PC polycarbonate
- ABS acrylonitrile butadiene styrene
- LCP liquid crystal polymer
- FIGS. 25 and 26 a through-hole type via 60 is illustrated.
- Plating of the through-hole type via 60 could not be achieved with a MIPTEC technology process because the chemical applied to the surface of the plastic would also need to be applied to the vertical walls of the via 60 .
- Plating of the through-hole type via 60 could not be achieved with a LDS technology process because vertical walls could not be achieved due to laser activation required angle of incidence.
- FIG. 27 illustrates a different line-of-sight feature 70 , referred to herein as an overhang or an undercut, which likely is not possible with a MIPTEC and/or LDS technology process.
- a first preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film to form metallic-plated first, second and third portions; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- a palladium-catalyzed material such as, for example, resins or epoxy molding compounds into
- a second preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide first, second and optional third portions of the copper film; electrolytic copper plating; soft etching to remove any unnecessary copper; electrolytic nickel plating; electrolytic gold plating; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of the MID, and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- a palladium-catalyzed material such as, for example, resins or epoxy molding compounds into a palladium-catalyzed
- a third preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide ablated sections and first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film with copper plating; non-selectively adding solder resist; selectively removing the solder resist from parts of the first portion which will form contact points for connection of the MID to an associated device or assembly, such as a printed circuit board, and from the ablated sections; electrolytically plating the contact points with nickel plating and gold plating to form metallic-plated first, second and third portions; and ablating or removing the second portion in order to isolate the metallic-
- a fourth preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide ablated sections and first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film with copper plating, nickel plating and gold plating; non-selectively adding solder resist; selectively removing the solder resist from parts of the first portion which will form contact points for connection of the MID to an associated device or assembly, such as a printed circuit board, and from the ablated sections; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises
- Each manufacturing process results in an MID having a palladium-catalyzed substrate, a circuit portion, and an optional Faraday cage portion, where the Faraday cage portion and the circuit portion may be isolated from one another.
- FIG. 1 is a flow chart showing the steps of a first embodiment of a process of manufacturing a molded interconnect device (MID);
- FIG. 2 is a flow chart showing the sub-steps of an electrolytic plating step of the first embodiment of the manufacturing process
- FIG. 3 is a perspective view of a sheet
- FIG. 4 is a perspective view of one of the substrates separated from the sheet
- FIG. 5 is a top plan view of the substrate of FIG. 4 ;
- FIG. 6 is a bottom plan view of the substrate of FIG. 4 ;
- FIG. 7 is a cross-sectional view of a first assembly
- FIG. 8 is a perspective view of a second assembly
- FIG. 9 is a top plan view of the second assembly of FIG. 8 ;
- FIG. 10 is a bottom plan view of the second assembly of FIG. 8 ;
- FIG. 11 is a perspective view of a third assembly
- FIG. 12 is a top plan view of the third assembly of FIG. 11 ;
- FIG. 13 is a bottom plan view of the third assembly of FIG. 11 ;
- FIG. 14 is a cross-sectional view, shown in perspective, of the third assembly of FIG. 11 , in accordance with an embodiment
- FIG. 15 is an enlarged view of a portion of FIG. 14 ;
- FIG. 16 is a perspective view of a fourth assembly
- FIG. 17 is a flow chart showing the steps of a second embodiment of a process of manufacturing a molded interconnect device (MID);
- FIG. 18 is a flow chart showing the steps of a third embodiment of a process of manufacturing a molded interconnect device (MID);
- FIG. 19 is a partial perspective, cross-sectional view of the MID during formation in accordance with the third embodiment.
- FIG. 20 is a perspective view of the MID during formation in accordance with the third embodiment.
- FIG. 21 is a perspective view of the MID during formation in accordance with the third embodiment.
- FIG. 22 is a flow chart showing the steps of a fourth embodiment of a process of manufacturing a molded interconnect device (MID);
- FIG. 23 is a partial perspective, cross-sectional view of the MID during formation in accordance with the fourth embodiment.
- FIG. 24 is a perspective view of the MID during formation in accordance with the fourth embodiment.
- FIGS. 25-27 illustrate cross-sectional views of prior art line-of-sight features, such as through-hole type vias and overhangs or undercuts which can be plated by any of the embodiments of the process.
- the present disclosure is directed to novel manufacturing processes 100 , 200 , 300 , 400 for forming a molded interconnect device (MID) 50 .
- the manufacturing processes 100 , 200 , 300 , 400 are useful for the creation of MIDs, such as printed circuit boards, flex circuits, connectors, thermal management features, electromagnetic interference (EMI) shielding, high current conductors, radio frequency identification (RFID) apparatuses, antennas, wireless power, sensors, MEMS apparatuses, LEDs, microprocessors and memory, ASICs, passives, and other electrical and electro-mechanical apparatuses.
- EMI electromagnetic interference
- RFID radio frequency identification
- FIGS. 1-16 relating to a first embodiment of the manufacturing process 100 used to form the MID 50 .
- FIG. 1 illustrates a flow chart depicting the steps of the manufacturing process 100 .
- FIG. 2 illustrates a flow chart depicting the steps of a sub-process of the manufacturing process 100 .
- the manufacturing process 100 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- Step 110 is an injection-molding step where a palladium-catalyzed material (sometimes called palladium-doped in the art), such as, for example, resins or epoxy molding compounds, is injection-molded in the form of a sheet 112 containing a plurality of connected substrates 114 (each formed in the intended shape) for production purposes.
- a palladium-catalyzed material sometimes called palladium-doped in the art
- Each substrate 114 may be formed in a desired three-dimensional shape.
- each substrate 114 is formed of the same three-dimensional shape.
- FIG. 3 illustrates the formation of the MID 50 after the completion of step 110 , where the sheet 112 contains the plurality of substrates 114 .
- the material which is injection-molded is a palladium-catalyzed resin, but is intended to be inclusive of materials where the palladium (or any comparable material that does not need to be surface treated to accept metallization) is provided within, or infused within, the material itself.
- the circuit forming stage of the manufacturing process 100 includes two steps, which steps will be referred to as steps 120 and 130 .
- Step 120 is a metallization step where a thin copper film 122 is formed over the exterior and exposed surfaces of the palladium-catalyzed substrates 114 to form a first assembly 123 .
- Metallization step 120 is commonly referred to as copper-striking.
- FIG. 7 illustrates the formation of the MID 50 after the completion of step 120 , where the substrate 114 has the copper film 122 formed thereon (the first assembly 123 is shown in cross-section for clarity to show the substrate 114 ).
- Sections 124 (shown with shading for clarity) which do not have the copper film 122 formed thereon are where the substrate 114 is connected to the adjacent substrate 114 in the sheet 112 . Sections 124 are illustrative only and do not denote required locations for the connection points.
- Step 130 is a circuit patterning step where a laser (not shown) ablates or removes portions of the copper film 122 from the first assembly 123 to expose portions 131 , 132 of the substrate 114 and form a second assembly 133 . This action defines and outlines a circuit pattern within the remaining copper film 122 to be provided for the MID 50 .
- FIGS. 8-10 illustrate the formation of the MID 50 after the completion of step 130 , where the non-ablated/removed copper film 122 preferably includes first, second and optional and selectively sized/shaped third portions 134 , 136 , 138 which are to be subject to the plating stage, as will be described further below.
- the first portion 134 forms the circuit pattern
- the second portion(s) 136 forms a bus portion(s) which connects the first portion 134 to the third portion(s) 138 , if provided
- the third portion(s) 138 is/are generally a Faraday cage portion (hereinafter, the second portion(s) 136 is referred to in the singular, but more than one second portion 136 may be provided; hereinafter, the third portion(s) 138 is referred to in the singular, but more than one third portion 138 may be provided).
- the remaining steps will be described and illustrated showing the third portion(s) 138 with the understanding that the size/shape of the third portion(s) 138 could be changed as desired, and also with the understanding that the third portion(s) 138 could not be provided at all.
- the plating stage of the manufacturing process 100 includes two steps, which steps will be referred to as steps 140 and 150 .
- Step 140 is an electrolytic plating step where a probe (not shown) is attached/connected to one of the first, second and third portions 134 , 136 , 138 and electricity is run through the first, second and third portions 134 , 136 , 138 and desired metallic molecules from a desired metallic bath are drawn to and secured to the first, second and third portions 134 , 136 , 138 , until the desired metallic plating of the first, second and third portions 134 , 136 , 138 is built up to the desired thickness, thus forming metallic-plated first, second and third portions 144 , 146 , 148 (it is to be understood that metallic-plated third portion 148 will only be formed if third portion 138 is provided), thereby forming a third assembly 143 .
- FIGS. 11-13 illustrate the formation of the MID 50 after the completion of step 140 .
- the electrolytic plating step 140 can include the electrolytic plating of any metal(s) as desired.
- the electrolytic plating step 140 begins with a step 141 wherein a copper material is electrolytic plated onto the first, second and third portions 144 , 146 , 148 to form a copper plating 173 , followed by a step 171 wherein a nickel material is electrolytic plated onto the copper material 173 to form a nickel plating 174 , followed by a step 172 wherein a gold material is electrolytic plated onto the nickel material 147 to form a gold plating 175 , as illustrated in FIGS. 14 and 15 .
- Step 150 is a circuit isolation step where a laser (not shown) ablates or removes the formed second (bus) portion(s) 136 / 146 , beginning with second portion 146 , and finishing with second portion 136 , until the surface of the substrate 114 is provided between the first and third portions 144 , 148 , thereby providing portions 152 of the substrate 114 which are visible, and thereby forming a fourth assembly 153 .
- the ablated sections 152 are connected to or continuous with the ablated sections 132 such that the first portion 144 (namely the circuit pattern) is isolated from the third portion 148 (namely the Faraday cage portion).
- FIG. 16 illustrates the MID 50 that is formed after the completion of step 150 .
- Step 160 is a cutting step where the sheet 112 is diced in order to separate each of the MIDs 50 .
- the sheet 112 can be diced along saw streets 162 (the saw streets 162 are not shown in FIGS. 4-16 ), thereby exposing the sections 124 .
- one or more of the MIDs 50 can then be inspected, as desired and in any of a number of known manners, to ensure that the MIDs 50 are suitable for their intended use.
- the MIDs 50 may then be packaged and shipped. If desired, further electronic components may be electrically connected and secured to the first portion 144 , namely the circuit portions, before the MIDs 50 are packaged and shipped. It is to be understood that the sheet 112 of MIDs 50 could be packaged and shipped prior to the cutting step 160 being performed.
- FIG. 17 illustrates a flow chart depicting the steps of the manufacturing process 200 .
- manufacturing process 200 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- Manufacturing process 200 includes each of the same steps 110 , 120 , 130 , 140 (including steps 141 , 142 , 143 ), 150 , 160 from manufacturing process 100 , but also includes a further step 245 that would preferably be a part of the plating stage.
- Step 245 is a soft etching step which would preferably be performed after step 141 , but before step 142 .
- soft etching would be applied in order to remove any unnecessary copper from areas that are not part of the first, second or third portions 144 , 146 , 148 of the MID 50 and to prevent any unnecessary nickel and/or gold plating.
- FIG. 18 illustrates a flow chart depicting the steps of the manufacturing process 300 .
- manufacturing process 300 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- Manufacturing process 300 includes each of the same steps 110 , 120 , 130 , 141 , 142 , 143 , 150 , 160 from manufacturing process 100 , also includes steps 380 , 381 after step 141 and before step 142 .
- the soft etching step 245 may be included after step 141 .
- Step 380 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the copper plating 173 and the ablated sections 131 , 132 as shown in FIG. 19 .
- Step 380 is a solder resist removal step where a laser (not shown) ablates or removes the solder resist 337 from one or more sections 339 of the copper plating 173 overlaying the first portion 134 which will form contact point(s) for connection of the MID 50 to an associated device or assembly, such as a printed circuit board, as shown in FIG. 20 .
- the solder resist 337 on the ablated section 131 , 132 and on the second portion 136 is also removed in step 380 .
- all of the solder resist 337 overlaying the ablated sections 131 , 132 is removed. In some embodiments, only a portion of the solder resist 337 overlaying the ablated sections 131 , 132 is removed.
- the solder resist 337 on the second portion 136 and the solder resist 337 that remains on the ablated sections 131 , 132 that prevents the isolation of the first portion 144 is removed. Thereafter, in steps 142 and 143 , the nickel plating 174 and the gold plating 175 are only electrolytic plated onto the sections 339 as shown in FIG. 21 . This manufacturing process 300 reduces the amount of precious metal used and provides for limiting solder flow once the resulting MID 50 is soldered to another component.
- FIG. 22 illustrates a flow chart depicting the steps of the manufacturing process 400 .
- manufacturing process 400 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- Manufacturing process 300 includes each of the same steps 110 , 120 , 130 , 141 , 142 , 143 , 150 , 160 from manufacturing process 100 , also includes steps 490 , 491 after step 143 and before step 150 .
- the soft etching step 245 may be included after step 141 .
- Step 490 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the gold plating 175 and the ablated sections 131 , 132 as shown in FIG. 23 .
- Step 491 is a solder resist removal step where a laser (not shown) ablates or removes the solder resist 337 from one or more sections 439 of the gold plating 175 overlaying the first portion 134 which will form contact point(s) for connection of the MID 50 to an associated device or assembly, such as a printed circuit board, as shown in FIG. 24 .
- the solder resist 337 on the ablated section 131 , 132 and on the second portion 136 is also removed in step 491 .
- all of the solder resist 337 overlaying the ablated sections 131 , 132 is removed. In some embodiments, only a portion of the solder resist 337 overlaying the ablated sections 131 , 132 is removed. Alternatively, or additionally, during step 150 , the solder resist 337 on the second portion 136 and the solder resist 337 that remains on the ablated sections 131 , 132 that prevents the isolation of the first portion 144 is removed.
- This manufacturing process 400 provides for limiting solder flow once the resulting MID 50 is soldered to another component.
- the manufacturing processes 100 , 200 , 300 , 400 of forming the MIDs 50 are advantageous as compared to the prior-known MID manufacturing processes, especially as compared to the MIPTEC and laser developed additive technology processes. More specifically, as the injection-molded material is infused with palladium, it is then unnecessary to perform any type of surface activation treatment to the substrate 114 of the type which is required in all prior-known MID manufacturing processes. Thus, the manufacturing processes 100 , 200 , 300 , 400 removes a step which is needed in all prior-known MID manufacturing processes, thereby saving both manufacturing costs and manufacturing time.
- MIPTEC and LDS technology processes also have limitations, and in some circumstances even impossibilities, in connection with plating features that are not within a line-of-sight.
- a through-hole type via 60 is illustrated.
- Plating of the through-hole type via 60 could not be achieved with a MIPTEC technology process because the chemical applied to the surface of the plastic would also need to be applied to the vertical walls of the via 60 .
- Plating of the through-hole type via 60 as illustrated in FIG. 26 , could not be achieved with a LDS technology process because vertical walls could not be achieved due to laser activation required angle of incidence.
- FIGS. 25 - 27 illustrates a different line-of-sight feature 70 , referred to herein as an overhang or an undercut, which likely is not possible with a MIPTEC and/or LDS technology process.
- the through-hole type vias 60 and overhang/undercut 70 of FIGS. 25 - 27 can be easily plated with the manufacturing processes 100 , 200 , 300 , 400 described and illustrated herein.
- the manufacturing processes 100 , 200 , 300 , 400 provide for improved plating adhesion as compared to the prior-known MID manufacturing processes, thereby making the MIDs 50 formed from the manufacturing processes 100 , 200 , 300 , 400 more robust and reliable than the MIDs formed from the prior-known MID manufacturing processes.
- each of the manufacturing processes 100 , 200 , 300 , 400 may provide an MID 50 having a Faraday cage configuration, where the third portions 148 provide the Faraday cage configuration which is useful in providing better EMI shielding for any packaged integrated circuit application.
- each substrate 114 provided in the sheet 112 may have one or more vias (not shown) formed along saw street, namely where the sheet 112 is diced during step 160 to provide the individual MIDs 50 . These vias allow for the metallization and electrolytic plating, of steps 120 and 140 / 140 a , respectively, of all sides of the MIDs 50 . It is to be understood that the size/shape of the Faraday cage configuration, if provided, may vary as desired.
Abstract
A method of forming a molded interconnect device (MID) is provided. The method includes the steps of performing a molding stage, performing a circuit forming stage, and performing a plate stage. As a part of the molding stage, a palladium-catalyzed material is injection molded into a palladium-catalyzed substrate of a desired shape. As a part of the circuit forming stage, both a metallization step and a circuit patterning step are performed. As a part of the plating stage, both an electrolytic plating step and a circuit isolation step are performed.
Description
- This application is a continuation of U.S. patent application Ser. No. 16/315,244, filed on Jan. 4, 2019, which is a national stage of International Application No. PCT/US2017/040721, filed Jul. 5, 2017, which claims priority to both U.S. Provisional Patent Application Ser. No. 62/359,365, filed on Jul. 7, 2016, and U.S. Provisional Patent Application Ser. No. 62/435,305, filed on Dec. 16, 2016, the contents of all of which are incorporated herein in their entireties.
- Molded interconnect devices (“MIDs”) are three-dimensional manufactured parts that typically include plastic components and electronic circuit traces. A plastic substrate or housing is created and electrical circuits and devices are plated, layered, or implanted upon the plastic substrate. MIDs typically have fewer parts than conventionally manufactured devices, which results in space and weight savings. Applications for MIDs include mobile telephones, automated teller machines, steering wheel components for automobiles, RFID components, lighting, medical devices and many other consumer and/or commercial products.
- Current processes for manufacturing MIDs include two-shot molding, laser direct structuring technology (LDS), microscopic integrated processing technology (MIPTEC), and a laser developed additive technology. Each of these manufacturing processes have been known in the art for some time, yet each has its own drawbacks such that many individuals believe that further improvements to manufacturing MIDs would be beneficial.
- Two-shot molding involves the use of two separate plastic parts, typically one platable and one non-platable. The platable part forms the circuitry, and the non-platable part fulfills mechanical functions and completes the molding. The two parts are fused together and circuits are created through use of electroless plating. The platable plastic is metallized, while the non-platable plastic remains non-conductive.
- LDS technology involves the steps of injection molding (using any of a variety of dielectric thermoplastic materials, including polyamide, polycarbonate, and liquid crystal polymer), laser activation of the thermoplastic material, and then metallization (electroless plating). The laser etches a wiring pattern onto the part and prepares it for metallization. With LDS, only a single thermoplastic material is required thereby making the molding step a one-shot process, and generally preferable as compared to the two-shot molding process.
- MIPTEC technology, which is offered by Panasonic Corporation, involves a molding stage, a circuit forming stage, a plating stage, and a cutting stage.
- The molding stage includes injection-molding the intended shape using a thermoplastic resin, such as polyphthalamide (PPA).
- The circuit forming stage includes two steps, namely: (1) metallization; and (2) patterning. Thin copper film is formed in the base metallization process (copper-strike). A laser is then used to remove the copper and outline the circuit pattern, with the wavelength and exposure time of the laser optimized to achieve copper removal without damaging the substrate.
- The plating stage includes two or three steps, namely: (1) electrolytic copper plating; (2) optional soft etching; and (3) electrolytic nickel and gold plating. First, copper is electrically plated to form the circuit pattern. Then, if desired, soft etching is applied to remove unnecessary copper-strike that was not removed by the laser in the circuit forming stage. Finally, nickel and gold are plated on the electrolytically-plated copper, forming the circuit pattern to help prevent oxidation and corrosion.
- An optional cutting stage then includes dicing the sheet form into individual MIDs.
- Thus, MIPTEC technology, like LDS technology, has only a one-shot molding process, but also provides MIDs which can be fine patterned and bare chip mounted.
- The laser developed additive technology is similar to the MIPTEC technology, but allows for other thermoplastic materials, such as polyamide (PA), polycarbonate (PC) and acrylonitrile butadiene styrene (ABS) or liquid crystal polymer (LCP), to be used in the process. Like polyphthalamide (PPA), however, these thermoplastic materials are all dielectric materials and require the separate and extra step of surface activation treatment prior to the circuit forming stage. This extra step adds both time and expense to these technologies.
- MIPTEC and LDS technology processes have limitations, and in some circumstances even impossibilities, in connection with plating features that are not within a line-of-sight. For instance, as illustrated in
FIGS. 25 and 26 , a through-hole type via 60 is illustrated. Plating of the through-hole type via 60, as illustrated inFIG. 25 , could not be achieved with a MIPTEC technology process because the chemical applied to the surface of the plastic would also need to be applied to the vertical walls of thevia 60. Plating of the through-hole type via 60, as illustrated inFIG. 26 , could not be achieved with a LDS technology process because vertical walls could not be achieved due to laser activation required angle of incidence.FIG. 27 illustrates a different line-of-sight feature 70, referred to herein as an overhang or an undercut, which likely is not possible with a MIPTEC and/or LDS technology process. - A first preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film to form metallic-plated first, second and third portions; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of portion of a molded interconnect device (MID), and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- A second preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide first, second and optional third portions of the copper film; electrolytic copper plating; soft etching to remove any unnecessary copper; electrolytic nickel plating; electrolytic gold plating; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of the MID, and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- A third preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide ablated sections and first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film with copper plating; non-selectively adding solder resist; selectively removing the solder resist from parts of the first portion which will form contact points for connection of the MID to an associated device or assembly, such as a printed circuit board, and from the ablated sections; electrolytically plating the contact points with nickel plating and gold plating to form metallic-plated first, second and third portions; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of the MID, and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- A fourth preferred embodiment of a manufacturing process includes the steps of: injection molding a palladium-catalyzed material, such as, for example, resins or epoxy molding compounds into a palladium-catalyzed substrate of a desired shape; forming a thin copper film over exterior and exposed surfaces of the palladium-catalyzed substrate; ablating or removing some of the copper film from the palladium-catalyzed substrate to provide ablated sections and first, second and optional third portions of the copper film; electrolytically plating each of the first, second and third portions of the copper film with copper plating, nickel plating and gold plating; non-selectively adding solder resist; selectively removing the solder resist from parts of the first portion which will form contact points for connection of the MID to an associated device or assembly, such as a printed circuit board, and from the ablated sections; and ablating or removing the second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion, where the metallic-plated first portion comprises a circuit portion of the MID, and where the metallic-plated third portion comprises a Faraday cage portion of the MID.
- Each manufacturing process results in an MID having a palladium-catalyzed substrate, a circuit portion, and an optional Faraday cage portion, where the Faraday cage portion and the circuit portion may be isolated from one another.
- These and other aspects and features of the disclosure are described in further detail below.
-
FIG. 1 is a flow chart showing the steps of a first embodiment of a process of manufacturing a molded interconnect device (MID); -
FIG. 2 is a flow chart showing the sub-steps of an electrolytic plating step of the first embodiment of the manufacturing process; -
FIG. 3 is a perspective view of a sheet; -
FIG. 4 is a perspective view of one of the substrates separated from the sheet; -
FIG. 5 is a top plan view of the substrate ofFIG. 4 ; -
FIG. 6 is a bottom plan view of the substrate ofFIG. 4 ; -
FIG. 7 is a cross-sectional view of a first assembly; -
FIG. 8 is a perspective view of a second assembly; -
FIG. 9 is a top plan view of the second assembly ofFIG. 8 ; -
FIG. 10 is a bottom plan view of the second assembly ofFIG. 8 ; -
FIG. 11 is a perspective view of a third assembly; -
FIG. 12 is a top plan view of the third assembly ofFIG. 11 ; -
FIG. 13 is a bottom plan view of the third assembly ofFIG. 11 ; -
FIG. 14 is a cross-sectional view, shown in perspective, of the third assembly ofFIG. 11 , in accordance with an embodiment; -
FIG. 15 is an enlarged view of a portion ofFIG. 14 ; -
FIG. 16 is a perspective view of a fourth assembly; -
FIG. 17 is a flow chart showing the steps of a second embodiment of a process of manufacturing a molded interconnect device (MID); -
FIG. 18 is a flow chart showing the steps of a third embodiment of a process of manufacturing a molded interconnect device (MID); -
FIG. 19 is a partial perspective, cross-sectional view of the MID during formation in accordance with the third embodiment; -
FIG. 20 is a perspective view of the MID during formation in accordance with the third embodiment; -
FIG. 21 is a perspective view of the MID during formation in accordance with the third embodiment; -
FIG. 22 is a flow chart showing the steps of a fourth embodiment of a process of manufacturing a molded interconnect device (MID); -
FIG. 23 is a partial perspective, cross-sectional view of the MID during formation in accordance with the fourth embodiment; -
FIG. 24 is a perspective view of the MID during formation in accordance with the fourth embodiment; -
FIGS. 25-27 illustrate cross-sectional views of prior art line-of-sight features, such as through-hole type vias and overhangs or undercuts which can be plated by any of the embodiments of the process. - The present disclosure is directed to novel manufacturing processes 100, 200, 300, 400 for forming a molded interconnect device (MID) 50. The manufacturing processes 100, 200, 300, 400 are useful for the creation of MIDs, such as printed circuit boards, flex circuits, connectors, thermal management features, electromagnetic interference (EMI) shielding, high current conductors, radio frequency identification (RFID) apparatuses, antennas, wireless power, sensors, MEMS apparatuses, LEDs, microprocessors and memory, ASICs, passives, and other electrical and electro-mechanical apparatuses.
- Attention is directed to
FIGS. 1-16 relating to a first embodiment of themanufacturing process 100 used to form theMID 50.FIG. 1 illustrates a flow chart depicting the steps of themanufacturing process 100.FIG. 2 illustrates a flow chart depicting the steps of a sub-process of themanufacturing process 100. Themanufacturing process 100 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage. - The molding stage of the
manufacturing process 100 advantageously includes only a single step, which step will be referenced byreference numeral 110. Step 110 is an injection-molding step where a palladium-catalyzed material (sometimes called palladium-doped in the art), such as, for example, resins or epoxy molding compounds, is injection-molded in the form of a sheet 112 containing a plurality of connected substrates 114 (each formed in the intended shape) for production purposes. Eachsubstrate 114 may be formed in a desired three-dimensional shape. In some embodiments, eachsubstrate 114 is formed of the same three-dimensional shape.FIG. 3 illustrates the formation of theMID 50 after the completion ofstep 110, where the sheet 112 contains the plurality ofsubstrates 114.FIGS. 4-6 illustrate asingulated substrate 114. The material which is injection-molded is a palladium-catalyzed resin, but is intended to be inclusive of materials where the palladium (or any comparable material that does not need to be surface treated to accept metallization) is provided within, or infused within, the material itself. - The circuit forming stage of the
manufacturing process 100 includes two steps, which steps will be referred to assteps - Step 120 is a metallization step where a
thin copper film 122 is formed over the exterior and exposed surfaces of the palladium-catalyzedsubstrates 114 to form afirst assembly 123.Metallization step 120 is commonly referred to as copper-striking.FIG. 7 illustrates the formation of theMID 50 after the completion ofstep 120, where thesubstrate 114 has thecopper film 122 formed thereon (thefirst assembly 123 is shown in cross-section for clarity to show the substrate 114). Sections 124 (shown with shading for clarity) which do not have thecopper film 122 formed thereon are where thesubstrate 114 is connected to theadjacent substrate 114 in the sheet 112.Sections 124 are illustrative only and do not denote required locations for the connection points. - Step 130 is a circuit patterning step where a laser (not shown) ablates or removes portions of the
copper film 122 from thefirst assembly 123 to exposeportions substrate 114 and form asecond assembly 133. This action defines and outlines a circuit pattern within the remainingcopper film 122 to be provided for theMID 50.FIGS. 8-10 illustrate the formation of theMID 50 after the completion ofstep 130, where the non-ablated/removedcopper film 122 preferably includes first, second and optional and selectively sized/shapedthird portions first portion 134 forms the circuit pattern, the second portion(s) 136 forms a bus portion(s) which connects thefirst portion 134 to the third portion(s) 138, if provided, and the third portion(s) 138, if provided, is/are generally a Faraday cage portion (hereinafter, the second portion(s) 136 is referred to in the singular, but more than one second portion 136 may be provided; hereinafter, the third portion(s) 138 is referred to in the singular, but more than onethird portion 138 may be provided). The remaining steps will be described and illustrated showing the third portion(s) 138 with the understanding that the size/shape of the third portion(s) 138 could be changed as desired, and also with the understanding that the third portion(s) 138 could not be provided at all. - The plating stage of the
manufacturing process 100 includes two steps, which steps will be referred to assteps 140 and 150. - Step 140 is an electrolytic plating step where a probe (not shown) is attached/connected to one of the first, second and
third portions third portions third portions third portions third portions 144, 146, 148 (it is to be understood that metallic-platedthird portion 148 will only be formed ifthird portion 138 is provided), thereby forming athird assembly 143.FIGS. 11-13 illustrate the formation of theMID 50 after the completion of step 140. - It is to be understood that the electrolytic plating step 140 can include the electrolytic plating of any metal(s) as desired. In a preferred embodiment, the electrolytic plating step 140 begins with a
step 141 wherein a copper material is electrolytic plated onto the first, second andthird portions copper plating 173, followed by a step 171 wherein a nickel material is electrolytic plated onto thecopper material 173 to form anickel plating 174, followed by astep 172 wherein a gold material is electrolytic plated onto the nickel material 147 to form agold plating 175, as illustrated inFIGS. 14 and 15 . - Step 150 is a circuit isolation step where a laser (not shown) ablates or removes the formed second (bus) portion(s) 136/146, beginning with second portion 146, and finishing with second portion 136, until the surface of the
substrate 114 is provided between the first andthird portions portions 152 of thesubstrate 114 which are visible, and thereby forming a fourth assembly 153. Theablated sections 152 are connected to or continuous with theablated sections 132 such that the first portion 144 (namely the circuit pattern) is isolated from the third portion 148 (namely the Faraday cage portion).FIG. 16 illustrates theMID 50 that is formed after the completion ofstep 150. - Step 160 is a cutting step where the sheet 112 is diced in order to separate each of the
MIDs 50. The sheet 112 can be diced along saw streets 162 (the saw streets 162 are not shown inFIGS. 4-16 ), thereby exposing thesections 124. - Either before or after
step 160 of themanufacturing process 100 is performed, one or more of the MIDs 50 can then be inspected, as desired and in any of a number of known manners, to ensure that theMIDs 50 are suitable for their intended use. TheMIDs 50 may then be packaged and shipped. If desired, further electronic components may be electrically connected and secured to thefirst portion 144, namely the circuit portions, before theMIDs 50 are packaged and shipped. It is to be understood that the sheet 112 ofMIDs 50 could be packaged and shipped prior to the cuttingstep 160 being performed. - Attention is directed to
FIG. 17 relating to a second embodiment of the manufacturing process 200 used to form theMID 50.FIG. 17 illustrates a flow chart depicting the steps of the manufacturing process 200. Likemanufacturing process 100, manufacturing process 200 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage. Manufacturing process 200 includes each of thesame steps steps manufacturing process 100, but also includes afurther step 245 that would preferably be a part of the plating stage. Step 245 is a soft etching step which would preferably be performed afterstep 141, but beforestep 142. As a part of thesoft etching step 245, soft etching would be applied in order to remove any unnecessary copper from areas that are not part of the first, second orthird portions MID 50 and to prevent any unnecessary nickel and/or gold plating. - Attention is directed to
FIGS. 18-21 relating to a third embodiment of themanufacturing process 300 used to form theMID 50.FIG. 18 illustrates a flow chart depicting the steps of themanufacturing process 300. Likemanufacturing process 100,manufacturing process 300 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.Manufacturing process 300 includes each of thesame steps manufacturing process 100, also includessteps 380, 381 afterstep 141 and beforestep 142. Thesoft etching step 245 may be included afterstep 141. - Step 380 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the copper plating 173 and the
ablated sections FIG. 19 . Step 380 is a solder resist removal step where a laser (not shown) ablates or removes the solder resist 337 from one ormore sections 339 of the copper plating 173 overlaying thefirst portion 134 which will form contact point(s) for connection of theMID 50 to an associated device or assembly, such as a printed circuit board, as shown inFIG. 20 . In some embodiments, the solder resist 337 on theablated section step 380. In some embodiments, all of the solder resist 337 overlaying theablated sections ablated sections step 150, the solder resist 337 on the second portion 136 and the solder resist 337 that remains on theablated sections first portion 144 is removed. Thereafter, insteps gold plating 175 are only electrolytic plated onto thesections 339 as shown inFIG. 21 . Thismanufacturing process 300 reduces the amount of precious metal used and provides for limiting solder flow once the resultingMID 50 is soldered to another component. - Attention is directed to
FIGS. 22-24 relating to a fourth embodiment of themanufacturing process 400 used to form theMID 50.FIG. 22 illustrates a flow chart depicting the steps of themanufacturing process 400. Likemanufacturing process 100,manufacturing process 400 includes a molding stage, a circuit forming stage, a plating stage, and a cutting stage.Manufacturing process 300 includes each of thesame steps manufacturing process 100, also includessteps step 143 and beforestep 150. Thesoft etching step 245 may be included afterstep 141. - Step 490 is a solder resist addition step where solder resist 337 is added non-selectively onto the entire assembly, including the
gold plating 175 and theablated sections FIG. 23 . Step 491 is a solder resist removal step where a laser (not shown) ablates or removes the solder resist 337 from one ormore sections 439 of thegold plating 175 overlaying thefirst portion 134 which will form contact point(s) for connection of theMID 50 to an associated device or assembly, such as a printed circuit board, as shown inFIG. 24 . In some embodiments, the solder resist 337 on theablated section step 491. In some embodiments, all of the solder resist 337 overlaying theablated sections ablated sections step 150, the solder resist 337 on the second portion 136 and the solder resist 337 that remains on theablated sections first portion 144 is removed. Thismanufacturing process 400 provides for limiting solder flow once the resultingMID 50 is soldered to another component. - The manufacturing processes 100, 200, 300, 400 of forming the
MIDs 50 are advantageous as compared to the prior-known MID manufacturing processes, especially as compared to the MIPTEC and laser developed additive technology processes. More specifically, as the injection-molded material is infused with palladium, it is then unnecessary to perform any type of surface activation treatment to thesubstrate 114 of the type which is required in all prior-known MID manufacturing processes. Thus, the manufacturing processes 100, 200, 300, 400 removes a step which is needed in all prior-known MID manufacturing processes, thereby saving both manufacturing costs and manufacturing time. - MIPTEC and LDS technology processes also have limitations, and in some circumstances even impossibilities, in connection with plating features that are not within a line-of-sight. For instance, as illustrated in
FIGS. 25 and 26 , a through-hole type via 60 is illustrated. Plating of the through-hole type via 60, as illustrated inFIG. 25 , could not be achieved with a MIPTEC technology process because the chemical applied to the surface of the plastic would also need to be applied to the vertical walls of the via 60. Plating of the through-hole type via 60, as illustrated inFIG. 26 , could not be achieved with a LDS technology process because vertical walls could not be achieved due to laser activation required angle of incidence.FIG. 27 illustrates a different line-of-sight feature 70, referred to herein as an overhang or an undercut, which likely is not possible with a MIPTEC and/or LDS technology process. The through-hole type vias 60 and overhang/undercut 70 of FIGS. 25-27, however, can be easily plated with the manufacturing processes 100, 200, 300, 400 described and illustrated herein. - Furthermore, it has been determined that the manufacturing processes 100, 200, 300, 400 provide for improved plating adhesion as compared to the prior-known MID manufacturing processes, thereby making the
MIDs 50 formed from the manufacturing processes 100, 200, 300, 400 more robust and reliable than the MIDs formed from the prior-known MID manufacturing processes. - Advantageously, each of the manufacturing processes 100, 200, 300, 400 may provide an
MID 50 having a Faraday cage configuration, where thethird portions 148 provide the Faraday cage configuration which is useful in providing better EMI shielding for any packaged integrated circuit application. To aid in the provision of the Faraday cage configuration, eachsubstrate 114 provided in the sheet 112 may have one or more vias (not shown) formed along saw street, namely where the sheet 112 is diced duringstep 160 to provide theindividual MIDs 50. These vias allow for the metallization and electrolytic plating, ofsteps 120 and 140/140 a, respectively, of all sides of theMIDs 50. It is to be understood that the size/shape of the Faraday cage configuration, if provided, may vary as desired. - All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
- The use of the terms “a” and “an” and “the” and “at least one” and similar referents in the context of describing the disclosure (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the disclosure, and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.
- Preferred embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the disclosure. Variations of those preferred embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the disclosure to be practiced otherwise than as specifically described herein. Accordingly, this disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.
Claims (22)
1. A method of forming a molded interconnect device (MID), the method comprising the steps of:
a) performing a molding stage, wherein a palladium-catalyzed material is injection molded into a palladium-catalyzed substrate of a desired shape;
b) performing a circuit forming stage, wherein
b1) a metallization step is performed, and
b2) a circuit patterning step is performed; and
c) performing a plating stage, wherein
c1) an electrolytic plating step is performed, and
c2) a circuit isolation step is performed to provide the MID.
2. The method as defined in claim 1 , wherein the metallization step of step b1) comprises forming a thin copper film over an exposed surface of the palladium-catalyzed substrate.
3. The method as defined in claim 1 , wherein the circuit pattering step of step b2) comprises removing some of the copper film from the palladium-catalyzed substrate to provide first and second portions of the copper film which are separated from one another.
4. The method as defined in claim 3 , wherein the removal of some of the copper film in step b2) is performed by a laser.
5. The method as defined in claim 3 , wherein the at least first and second portions of the copper film provided in step b2) are separated from one another by at least one exposed portion of the palladium-catalyzed substrate.
6. The method as defined in claim 3 , wherein the electrolytic plating step of step c1) comprises electrolytic copper plating, electrolytic nickel plating, and electrolytic gold plating.
7. The method as defined in claim 3 , wherein the electrolytic plating step of step c1) comprises electrolytically plating the first portion of the copper film to form a metallic-plated first portion.
8. The method as defined in claim 7 , wherein the current isolation step of step c2) comprises removing the second portion of the copper film.
9. The method as defined in claim 8 , wherein the removal of the second portion of the copper film in step c2) is performed by a laser.
10. The method as defined in claim 8 , wherein the removal of the second portion of the copper film in step c2) is performed by soft etching.
11. The method as defined in claim 8 , wherein step c) further comprises steps c3) and c4), wherein in step c3) a solder resist addition step is performed, wherein in step c4) a solder resist removal step is performed, and wherein step c4) is performed after step c3) is performed.
12. The method as defined in claim 11 , wherein steps c3) and c4) are performed before step c2) is performed.
13. The method as defined in claim 3 , wherein the circuit patterning step of step b2) further provides a third portion of the copper film which separates the first portion of the copper film from the second portion of the copper film, the third portion of the copper film connecting the first portion of the copper film to the second portion of the copper film.
14. The method as defined in claim 13 , wherein the first portion of the copper film forms a circuit patter, wherein the second portion of the copper film is a Faraday cage portion, and wherein the third portion of the copper film is a bus portion.
15. The method as defined in claim 13 , wherein the electrolytic plating step of step c1) comprises electrolytically plating the first, second and third portions of the copper film to form metallic-plated first, second and third portions.
16. The method as defined in claim 15 , wherein the current isolation step of step c2) comprises removing the metallic-plated third portion to electrically isolate the metallic-plated first portion from the metallic-plated third portion.
17. The method as defined in claim 16 , wherein the removal of the metallic-plated third portion in step c2) is performed by a laser.
18. The method as defined in claim 16 , wherein the removal of the metallic-plated third portion in step c2) is performed by soft etching.
19. The method as defined in claim 16 , wherein step c) further comprises steps c3) and c4), wherein in step c3) a solder resist addition step is performed, wherein in step c4) a solder resist removal step is performed, and wherein step c4) is performed after step c3) is performed.
20. The method as defined in claim 19 , wherein steps c3) and c4) are performed before step c2) is performed.
21. A method of forming a molded interconnect device (MID), the method comprising the steps of:
a) injection molding a palladium-catalyzed material into a palladium-catalyzed substrate of a desired shape;
b) forming a thin copper film over exposed surfaces of the palladium-catalyzed substrate;
c) removing some of the copper film from the palladium-catalyzed substrate to provide first and second portions of the copper film and at least one exposed portion of the palladium-catalyzed substrate, the first and second portions of the copper film being separated from one another by the at least one exposed portion of the palladium-catalyzed substrate;
d) electrolytically plating the first portion of the copper film to form a metallic-plated first portion; and
e) removing the second portion of the copper film to provide the MID.
22. A method of forming a molded interconnect device (MID), the method comprising the steps of:
a) injection molding a palladium-catalyzed material into a palladium-catalyzed substrate of a desired shape;
b) forming a thin copper film over exposed surfaces of the palladium-catalyzed substrate;
c) removing some of the copper film from the palladium-catalyzed substrate to provide first, second and third portions of the copper film, the second portion of the copper film connecting the first portion of the copper film to the third portion of the copper film;
d) electrolytically plating the first, second and third portions of the copper film to form metallic-plated first, second and third portions; and
e) removing the metallic-plated second portion in order to isolate the metallic-plated first portion from the metallic-plated third portion to provide the MID.
Priority Applications (1)
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US17/749,137 US20220279656A1 (en) | 2016-07-07 | 2022-05-20 | Method of making a molded interconnect device |
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US201662359365P | 2016-07-07 | 2016-07-07 | |
US201662435305P | 2016-12-16 | 2016-12-16 | |
PCT/US2017/040721 WO2018009543A1 (en) | 2016-07-07 | 2017-07-05 | Molded interconnect device and method of making same |
US201916315244A | 2019-01-04 | 2019-01-04 | |
US17/749,137 US20220279656A1 (en) | 2016-07-07 | 2022-05-20 | Method of making a molded interconnect device |
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US16/315,244 Continuation US11357112B2 (en) | 2016-07-07 | 2017-07-05 | Molded interconnect device |
PCT/US2017/040721 Continuation WO2018009543A1 (en) | 2016-07-07 | 2017-07-05 | Molded interconnect device and method of making same |
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US17/749,137 Abandoned US20220279656A1 (en) | 2016-07-07 | 2022-05-20 | Method of making a molded interconnect device |
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JP (1) | JP6771837B2 (en) |
KR (1) | KR102221083B1 (en) |
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TW (1) | TWI678953B (en) |
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TWI678953B (en) | 2016-07-07 | 2019-12-01 | 美商莫仕有限公司 | Molded interconnect element and method for manufacturing the same |
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US11357112B2 (en) | 2022-06-07 |
KR102221083B1 (en) | 2021-02-26 |
KR20190016592A (en) | 2019-02-18 |
CN109479373A (en) | 2019-03-15 |
JP6771837B2 (en) | 2020-10-21 |
TW201813473A (en) | 2018-04-01 |
TWI678953B (en) | 2019-12-01 |
JP2019526168A (en) | 2019-09-12 |
WO2018009543A1 (en) | 2018-01-11 |
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