JP4798000B2 - LED package - Google Patents

LED package Download PDF

Info

Publication number
JP4798000B2
JP4798000B2 JP2007006203A JP2007006203A JP4798000B2 JP 4798000 B2 JP4798000 B2 JP 4798000B2 JP 2007006203 A JP2007006203 A JP 2007006203A JP 2007006203 A JP2007006203 A JP 2007006203A JP 4798000 B2 JP4798000 B2 JP 4798000B2
Authority
JP
Japan
Prior art keywords
main body
body portion
package
led chip
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007006203A
Other languages
Japanese (ja)
Other versions
JP2008172167A (en
Inventor
正博 佐藤
淳 立田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Electric Works Co Ltd
Original Assignee
Panasonic Corp
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Works Ltd filed Critical Panasonic Corp
Priority to JP2007006203A priority Critical patent/JP4798000B2/en
Publication of JP2008172167A publication Critical patent/JP2008172167A/en
Application granted granted Critical
Publication of JP4798000B2 publication Critical patent/JP4798000B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features

Description

本発明は、発光ダイオード（Light Emitting Diode；以下、ＬＥＤという。）チップをパッケージ本体に実装したＬＥＤパッケージに関する。   The present invention relates to an LED package in which a light emitting diode (hereinafter referred to as LED) chip is mounted on a package body.

従来から、ＬＥＤチップを所定のパッケージ本体に実装し、これをプリント回路基板等の実装基板に実装するＬＥＤパッケージが提案されている。かかるＬＥＤパッケージは、ハンダによってＬＥＤチップを実装基板に実装する際に、電極間でハンダ量に差があると、ハンダが溶融したときの表面張力の差やハンダが固化するときの収縮応力等に起因して、一方の電極が浮き上がる、いわゆる、マンハッタン現象を生じるという問題がある。これを解決するために、特許文献１に記載された技術が提案されている。   Conventionally, an LED package in which an LED chip is mounted on a predetermined package body and mounted on a mounting board such as a printed circuit board has been proposed. Such an LED package has a difference in surface tension when the solder is melted or a shrinkage stress when the solder is solidified when there is a difference in the amount of solder between the electrodes when the LED chip is mounted on the mounting substrate by solder. As a result, there is a problem that a so-called Manhattan phenomenon occurs in which one electrode floats. In order to solve this, the technique described in Patent Document 1 has been proposed.

この特許文献１には、一方の面が素子取付面とされて素子用電極が設けられ他方の面が取付面とされて端子用電極が設けられる板状基板を有する発光ダイオードが開示されている。特に、この発光ダイオードは、板状基板に一方の面から他方の面に達するスルーホール電極を設け、このスルーホール電極によって素子用電極と端子用電極との電気的接続を行うことにより、ハンダ量に不均一を生じているときであっても、板状基板に一方の端部を浮き上がらせるような応力を生じることをなくし、導通不良を防止することができるとしている。
特開２０００−２１６４４０号公報 This Patent Document 1 discloses a light emitting diode having a plate-like substrate in which one surface is an element mounting surface and an element electrode is provided, and the other surface is a mounting surface and a terminal electrode is provided. . In particular, this light-emitting diode is provided with a through-hole electrode that extends from one surface to the other surface on a plate-like substrate, and by making electrical connection between the element electrode and the terminal electrode by this through-hole electrode, the amount of solder Even when non-uniformity occurs, stress that lifts one end of the plate-like substrate is eliminated, and poor conduction can be prevented.
JP 2000-216440 A

ところで、ＬＥＤパッケージにおいては、実装基板にハンダ実装した場合には、実装基板の線膨張率がＬＥＤパッケージの線膨張率よりも大きく、熱履歴によってＬＥＤパッケージと実装基板上の配線パターンとの接続部分に応力が集中することに起因して、ヒートサイクル試験等の際にハンダが破壊することがあり、導通不良を起こすという問題があった。この問題は、パッケージ本体がセラミックス材などで形成されていることに起因し、使用時のみならず、はんだ実装時においても問題になることがある。   By the way, in the LED package, when solder mounting is performed on the mounting substrate, the linear expansion coefficient of the mounting substrate is larger than the linear expansion coefficient of the LED package, and the connection portion between the LED package and the wiring pattern on the mounting substrate due to thermal history. Due to the stress concentration in the solder, the solder may be broken during a heat cycle test or the like, causing a problem of poor conduction. This problem is caused by the fact that the package body is formed of a ceramic material or the like, and may become a problem not only during use but also during solder mounting.

そこで、本発明は、上述したような問題を解決するために案出されたものであり、実装基板との線膨張率の違いに起因して発生する応力を有効に緩和することによってハンダの破壊を防止し、導通不良を防止することができるＬＥＤパッケージを提供することを目的とする。   Therefore, the present invention has been devised to solve the above-described problems, and breaks down the solder by effectively relieving the stress generated due to the difference in linear expansion coefficient with the mounting board. An object of the present invention is to provide an LED package that can prevent the occurrence of continuity failure.

本発明は、ＬＥＤチップをパッケージ本体に実装したＬＥＤパッケージにおいて、前記パッケージ本体は、複数箇所に形成されたハンダを介して実装基板上に実装されるものであり、上述の課題を解決するために、パッケージ本体は、ＬＥＤチップが設けられた第１本体部と、ＬＥＤチップが設けられていない第２本体部とを分割されて構成され、当該第１本体部と第２本体部とが間隙を設けて実装基板上に配設されている。   The present invention provides an LED package in which an LED chip is mounted on a package body, and the package body is mounted on a mounting board via solder formed at a plurality of locations. The package body is configured by dividing a first main body part provided with LED chips and a second main body part not provided with LED chips, and the first main body part and the second main body part have a gap. It is provided and disposed on the mounting substrate.

本発明に係るＬＥＤパッケージによれば、パッケージ本体を第１本体部と第２本体部とに分割し且つ第１本体部と第２本体部とを間隙を介して配置したので、パッケージ本体に与えられた熱膨張に応じて第１本体部、第２本体部のそれぞれの基板が動くので、パッケージ本体と実装基板との線膨張率の違いに起因して発生する応力を有効に緩和することによってハンダの破壊を防止し、導通不良を防止することができる。   According to the LED package of the present invention, the package main body is divided into the first main body portion and the second main body portion, and the first main body portion and the second main body portion are arranged with a gap therebetween. Since the respective substrates of the first main body portion and the second main body portion move in accordance with the thermal expansion, the stress generated due to the difference in the linear expansion coefficient between the package main body and the mounting substrate is effectively reduced. Solder breakage can be prevented and conduction failure can be prevented.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１に、ＬＥＤチップを実装するパッケージ本体１０の外観構成を示す斜視図を示し、図２に、ＬＥＤチップ１１をパッケージ本体１０に実装したＬＥＤパッケージを実装基板２０上に実装した状態を示す断面図を示す。   FIG. 1 is a perspective view illustrating an external configuration of a package body 10 on which an LED chip is mounted, and FIG. 2 is a cross-sectional view illustrating a state in which an LED package having the LED chip 11 mounted on the package body 10 is mounted on a mounting substrate 20. The figure is shown.

パッケージ本体１０は、例えばセラミック焼結体からなる第１本体部１２Ａ、第２本体部１２Ｂを有する。第１本体部１２Ａ、第２本体部１２Ｂは、所定の厚みをもった角柱体を形成する一の主面の中央部分に頭切円錐状の窪みが形成されたＬＥＤパッケージが分割されて構成されている。第１本体部１２Ａ、第２本体部１２Ｂのセラミック焼結体の製造方法としては、射出成形、圧縮成形（プレス成形）、鋳込み成形等があるが、パッケージ本体１０を製造するにあたっては、いずれの方法を用いてもよい。この第１本体部１２Ａの頭切円錐状の窪みの底面は、ＬＥＤチップ１１を実装するＬＥＤチップ実装部１３として用いられる。   The package main body 10 includes a first main body portion 12A and a second main body portion 12B made of, for example, a ceramic sintered body. The first main body portion 12A and the second main body portion 12B are configured by dividing an LED package in which a truncated cone-shaped depression is formed in the central portion of one main surface forming a prismatic body having a predetermined thickness. ing. There are injection molding, compression molding (press molding), casting molding, and the like as methods for manufacturing the ceramic sintered bodies of the first main body 12A and the second main body 12B. A method may be used. The bottom surface of the truncated cone-shaped depression of the first main body portion 12A is used as an LED chip mounting portion 13 for mounting the LED chip 11.

したがって、パッケージ本体１０は、このＬＥＤチップ実装部１３から第１本体部１２Ａの側面にかけて所定の回路パターン１４Ａが設けられた立体回路基板（Molded Interconnect Device;MID）として機能することになる。一方、第２本体部１２Ｂは、ＬＥＤチップ実装部１３が設けられていない。第２本体部１２Ｂには、側面に掛けて所定の回路パターン１４Ｂが設けられており、立体回路基板（ＭＩＤ）として機能する。   Accordingly, the package main body 10 functions as a three-dimensional circuit board (Molded Interconnect Device; MID) provided with a predetermined circuit pattern 14A from the LED chip mounting portion 13 to the side surface of the first main body portion 12A. On the other hand, the LED chip mounting portion 13 is not provided in the second main body portion 12B. A predetermined circuit pattern 14B is provided on the side surface of the second main body portion 12B, and functions as a three-dimensional circuit board (MID).

第１本体部１２Ａ、第２本体部１２Ｂの頭切円錐状の窪みの円錐面は、ＬＥＤチップ１１から放射された光を反射する反射板１５Ａ、反射板１５Ｂとして機能する。ＬＥＤパッケージにおいては、反射板１５Ａ、反射板１５Ｂをこのような円錐面とすることにより、高い信頼性及び光取り出し効率を実現することができる。なお、パッケージ本体１０は、反射板１５Ａ、反射板１５Ｂの部分に高反射率の金属膜を形成するようにしてもよい。これにより、ＬＥＤパッケージは、より高い信頼性及び光取り出し効率を実現することができる。   The truncated cone-shaped conical surfaces of the first main body portion 12A and the second main body portion 12B function as the reflecting plate 15A and the reflecting plate 15B that reflect the light emitted from the LED chip 11. In the LED package, high reliability and light extraction efficiency can be realized by making the reflecting plate 15A and the reflecting plate 15B have such a conical surface. The package body 10 may be formed with a highly reflective metal film on the portions of the reflecting plate 15A and the reflecting plate 15B. Thereby, the LED package can achieve higher reliability and light extraction efficiency.

このようなＬＥＤパッケージは、薄膜輪郭除去法により、ＬＥＤチップ実装部１３と反射板１５Ａ、反射板１５Ｂとを一体化したような立体回路基板を容易に形成することができる。この薄膜輪郭除去法は、以下のようなプロセスからなる。   Such an LED package can easily form a three-dimensional circuit board in which the LED chip mounting portion 13, the reflecting plate 15A, and the reflecting plate 15B are integrated by a thin film outline removing method. This thin film outline removing method includes the following processes.

まず、薄膜輪郭除去法は、加熱処理プロセスを実行し、焼結体を温度１０００℃、保持時間１時間の条件で加熱処理し、表面を清浄化する。   First, in the thin film contour removal method, a heat treatment process is performed, and the sintered body is heat treated under the conditions of a temperature of 1000 ° C. and a holding time of 1 hour to clean the surface.

続いて、薄膜輪郭除去法においては、導電性薄膜形成プロセスを実行する。この導電性薄膜形成プロセスは、真空蒸着装置やＤＣマグネトロンスパッタリング装置等を使用した物理的蒸着法や無電解めっき等の湿式法等により、導電性薄膜を試験体表面に形成するものである。具体的には、試験体をプラズマ処理装置のチャンバ内にセットし、チャンバ内を１０−４Ｐａ程度に減圧した後、温度１５０℃で３分間程度、試験体を予備加熱する。その後、チャンバ内に酸素ガスを流通させるとともに、チャンバ内のガス圧を１０Ｐａ程度に制御する。そして、電極間に１ｋＷの高周波電圧（ＲＦ：１３．５６ＭＨｚ）を３００秒間印加することにより、プラズマ処理を行う。続いて、チャンバ内の圧力を１０−４Ｐａ以下に制御し、この状態でチャンバ内にアルゴンガスをガス圧が０．６Ｐａ程度になるように導入した後、さらに５００Ｖの直流電圧を印加することにより、金属ターゲットをボンバートし、試験体表面に膜厚が３００ｎｍ程度の導電性薄膜を形成する。なお、導電性材料としては、銅、ニッケル、クロム、チタン等が用いられる。 Subsequently, in the thin film outline removing method, a conductive thin film forming process is executed. In this conductive thin film formation process, a conductive thin film is formed on the surface of a specimen by a physical vapor deposition method using a vacuum vapor deposition apparatus, a DC magnetron sputtering apparatus or the like, or a wet method such as electroless plating. Specifically, the test specimen is set in the chamber of the plasma processing apparatus, the pressure in the chamber is reduced to about 10 −4 Pa, and then the specimen is preheated at a temperature of 150 ° C. for about 3 minutes. Thereafter, oxygen gas is circulated in the chamber, and the gas pressure in the chamber is controlled to about 10 Pa. Then, plasma treatment is performed by applying a high-frequency voltage of 1 kW (RF: 13.56 MHz) between the electrodes for 300 seconds. Subsequently, the pressure in the chamber is controlled to 10 −4 Pa or less, and in this state, argon gas is introduced into the chamber so that the gas pressure is about 0.6 Pa, and then a DC voltage of 500 V is applied. Thus, the metal target is bombarded to form a conductive thin film having a thickness of about 300 nm on the surface of the test body. Note that copper, nickel, chromium, titanium, or the like is used as the conductive material.

続いて、薄膜輪郭除去法においては、回路パターン形成プロセスを実行し、大気中でＹＡＧレーザーの第３高調波（ＴＨＧ−ＹＡＧレーザー）を使用して回路パターンの輪郭に沿ってレーザーを走査し、アルミナ基板上に形成された導電性薄膜のうち、回路パターンの輪郭部の薄膜のみを除去した薄膜除去部を形成する。   Subsequently, in the thin film contour removal method, a circuit pattern forming process is executed, and a laser is scanned along the contour of the circuit pattern using the third harmonic of a YAG laser (THG-YAG laser) in the atmosphere. Of the conductive thin film formed on the alumina substrate, a thin film removal portion is formed by removing only the thin film at the contour portion of the circuit pattern.

続いて、薄膜輪郭除去法においては、めっきプロセスを実行し、焼結体表面の電気回路部のみに電解めっきによって銅めっきを施して厚膜化し、厚さが約１５μｍの銅膜を形成する。その後、非電気回路部に残存している導電性薄膜をエッチングによって除去する。このとき、銅めっきは、導電性薄膜よりも厚く形成されているために、残存する。そして、電気回路部に電気めっきによってニッケルめっきや金めっきを施す。   Subsequently, in the thin film contour removal method, a plating process is executed, and only the electric circuit portion on the surface of the sintered body is subjected to copper plating by electrolytic plating to form a thick film, thereby forming a copper film having a thickness of about 15 μm. Thereafter, the conductive thin film remaining in the non-electric circuit portion is removed by etching. At this time, since the copper plating is formed thicker than the conductive thin film, it remains. Then, nickel plating or gold plating is applied to the electric circuit portion by electroplating.

ＬＥＤパッケージは、このような薄膜輪郭除去法によって容易に形成することができる。なお、反射板１５Ａ、反射板１５Ｂに金属膜を形成したＬＥＤパッケージを薄膜輪郭除去法によって製造する場合には、上述した銅めっき、エッチング、ニッケルめっきまでのプロセスについては同様に行った上で、電気回路部のみに給電して金めっきを施すとともに、反射板１５Ａ、反射板１５Ｂのみに給電して例えば銀めっきを施せばよい。   The LED package can be easily formed by such a thin film outline removing method. In addition, when manufacturing the LED package in which the metal film is formed on the reflection plate 15A and the reflection plate 15B by the thin film outline removal method, after performing the processes up to the above-described copper plating, etching, and nickel plating in the same manner, Power is supplied to only the electric circuit portion and gold plating is performed, and power is supplied only to the reflection plate 15A and the reflection plate 15B and silver plating is performed, for example.

このようにして形成されるＬＥＤパッケージは、図２に示したように、ハンダ２１Ａ、２１Ｂを介して所定の回路パターン２２Ａ、２２Ｂが形成された実装基板２０上に実装される。第１本体部１２Ａは、回路パターン１４Ａと実装基板２０の回路パターン２２Ａとがハンダ２１Ａによって接続されて、実装基板２０上の回路パターン２２Ａと電気的に導通している。また、ハンダ２１Ａによって第１本体部１２Ａは実装基板２０上に固定されている。第２本体部１２Ｂは、回路パターン１４Ｂと実装基板２０の回路パターン２２Ｂとがハンダ２１Ｂによって接続されて、実装基板２０上の回路パターン２２Ｂと電気的に導通している。また、ハンダ２１Ｂによって第２本体部１２Ｂは実装基板２０上に固定されている。   As shown in FIG. 2, the LED package thus formed is mounted on a mounting substrate 20 on which predetermined circuit patterns 22A and 22B are formed via solders 21A and 21B. In the first main body portion 12A, the circuit pattern 14A and the circuit pattern 22A of the mounting substrate 20 are connected by solder 21A, and are electrically connected to the circuit pattern 22A on the mounting substrate 20. Further, the first main body 12A is fixed on the mounting substrate 20 by the solder 21A. In the second main body 12B, the circuit pattern 14B and the circuit pattern 22B of the mounting substrate 20 are connected by solder 21B, and are electrically connected to the circuit pattern 22B on the mounting substrate 20. Further, the second main body portion 12B is fixed on the mounting substrate 20 by the solder 21B.

実装基板２０上の回路パターン２２Ａ、２２Ｂには、図示しないＬＥＤチップ１１の駆動回路が接続されている。このＬＥＤの駆動回路は、回路パターン１４Ａ、１４Ｂを介してＬＥＤチップ１１に駆動電力を供給して、ＬＥＤチップ１１を発光させる。   A drive circuit for the LED chip 11 (not shown) is connected to the circuit patterns 22A and 22B on the mounting substrate 20. This LED drive circuit supplies drive power to the LED chip 11 via the circuit patterns 14A and 14B, and causes the LED chip 11 to emit light.

ここで、第１本体部１２Ａと第２本体部１２Ｂとが分離されて構成されており、第１本体部１２Ａと第２本体部１２Ｂとが間隙を介して配設されている。ＬＥＤチップ１１と回路パターン１４Ｂとの導通は、ワイヤ１６をＬＥＤチップ１１及び回路パターン１４Ｂに接続するワイヤボンディングにより実現している。   Here, the first main body portion 12A and the second main body portion 12B are separated from each other, and the first main body portion 12A and the second main body portion 12B are disposed with a gap therebetween. The conduction between the LED chip 11 and the circuit pattern 14B is realized by wire bonding for connecting the wire 16 to the LED chip 11 and the circuit pattern 14B.

このようなＬＥＤパッケージは、第１本体部１２Ａと第２本体部１２Ｂとを分離して構成して、当該第１本体部１２Ａと第２本体部１２Ｂとを離間して配置する事により、ＬＥＤチップ１１の発熱によって当該ＬＥＤパッケージと実装基板２０とが熱膨張した場合に、両者の線膨張率の違いから界面に応力が発生したとしても、第１本体部１２Ａと第２本体部１２Ｂとが離間した間隙に向かって変形することになる。これにより、ハンダ２１Ａ，２１Ｂへの応力集中を緩和するため、ハンダ２１Ａ、２１Ｂの部分が破壊してしまうような不良発生を低減することができる。   In such an LED package, the first main body portion 12A and the second main body portion 12B are separately configured, and the first main body portion 12A and the second main body portion 12B are arranged apart from each other. When the LED package and the mounting substrate 20 are thermally expanded due to the heat generated by the chip 11, the first main body 12 </ b> A and the second main body 12 </ b> B are not affected even if stress is generated at the interface due to the difference between the linear expansion coefficients of the two. It will be deformed towards the spaced gap. Thereby, since stress concentration on the solders 21A and 21B is relaxed, it is possible to reduce the occurrence of defects such that the parts of the solders 21A and 21B are destroyed.

例えば、複数のＬＥＤチップ１１を搭載し、且つ実装基板２０がエポキシ基板からなりパッケージ本体１０の幅が５ｍｍといった大型なものとなると、ＬＥＤチップ１１の発熱時の熱膨張幅が大きくなり、第１本体部１２Ａ及び第２本体部１２Ｂと実装基板２０との間で生じる応力が大きくなる。これに対し、ＬＥＤパッケージによれば、第１本体部１２Ａと第２本体部１２Ｂとの間隙を設けることにより、確実に熱膨張の差による応力がハンダ２１Ａ，２１Ｂに加わることを抑制できる。   For example, when a plurality of LED chips 11 are mounted and the mounting substrate 20 is made of an epoxy substrate and the package body 10 has a large width of 5 mm, the thermal expansion width of the LED chip 11 during heat generation increases. The stress generated between the main body portion 12A and the second main body portion 12B and the mounting substrate 20 is increased. On the other hand, according to the LED package, by providing the gap between the first main body portion 12A and the second main body portion 12B, it is possible to reliably prevent the stress due to the difference in thermal expansion from being applied to the solders 21A and 21B.

また、第１本体部１２Ａと第２本体部１２Ｂとは、図３に示すように、第１本体部１２Ａと第２本体部１２Ｂとが嵌合するように構成されていても良い。第１本体部１２Ａには、凹部３１が設けられ、第２本体部１２Ｂには、凸部３２が設けられている。また、第１本体部１２Ａには、第２本体部１２Ｂが挿入されて配置されるように所定のオーバーラップ幅が形成されている。   Further, the first main body portion 12A and the second main body portion 12B may be configured such that the first main body portion 12A and the second main body portion 12B are fitted, as shown in FIG. A concave portion 31 is provided in the first main body portion 12A, and a convex portion 32 is provided in the second main body portion 12B. The first main body 12A has a predetermined overlap width so that the second main body 12B is inserted and disposed.

このＬＥＤパッケージは、第１本体部１２Ａの凹部３１と第２本体部１２Ｂの凸部３２とが嵌合するように第１本体部１２Ａと第２本体部１２Ｂとを実装基板２０上に配置する。このように第１本体部１２Ａと第２本体部１２Ｂとを嵌合させる場合であっても、凹部３１と凸部３２との間には、変形を吸収する間隙を設けて第１本体部１２Ａと第２本体部１２Ｂとを配置することになる。なお、この例では、第２本体部１２Ｂ上にＬＥＤチップ１１を配置して、ＬＥＤチップ１１と回路パターン１４Ａとをワイヤ１６により導通させている。   In this LED package, the first main body portion 12A and the second main body portion 12B are arranged on the mounting substrate 20 so that the concave portion 31 of the first main body portion 12A and the convex portion 32 of the second main body portion 12B are fitted. . Even when the first main body portion 12A and the second main body portion 12B are fitted in this manner, a gap for absorbing deformation is provided between the concave portion 31 and the convex portion 32 to provide the first main body portion 12A. And the second main body 12B. In this example, the LED chip 11 is disposed on the second main body 12B, and the LED chip 11 and the circuit pattern 14A are electrically connected by the wire 16.

このようなＬＥＤパッケージによれば、図２に示したＬＥＤパッケージのように、第１本体部１２Ａと第２本体部１２Ｂとの間隙から、ＬＥＤチップ１１から発光した光が漏れることが無い。また、第１本体部１２Ａと第２本体部１２Ｂとが所定の嵌合深さとなるオーバーラップ幅だけオーバーラップして嵌合されているので、第１本体部１２Ａと第２本体部１２Ｂの配置時における第１本体部１２Ａと第２本体部１２Ｂとの位置決めが容易となる。   According to such an LED package, the light emitted from the LED chip 11 does not leak from the gap between the first main body 12A and the second main body 12B as in the LED package shown in FIG. Further, since the first main body portion 12A and the second main body portion 12B are fitted so as to overlap each other by an overlap width having a predetermined fitting depth, the arrangement of the first main body portion 12A and the second main body portion 12B. The positioning of the first main body portion 12A and the second main body portion 12B at the time becomes easy.

また、上述したＬＥＤパッケージは、回路パターン１４Ａ又は回路パターン１４ＢとＬＥＤチップ１１とをワイヤ１６で接続する構成について説明したが、これに限らず、回路パターン１４Ａと回路パターン１４Ｂの一方とＬＥＤチップ１１とを導通させる構成であっても良い。この場合、第１本体部１２Ａと第２本体部１２Ｂの一方には回路パターンを設けなくても良いが、回路パターンを設けていない本体部には回路パターン２２との間でハンダ付けするためのダミーの導体部を設ける必要がある。   Moreover, although the LED package mentioned above demonstrated the structure which connects the circuit pattern 14A or the circuit pattern 14B, and the LED chip 11 with the wire 16, it is not restricted to this, One of the circuit pattern 14A and the circuit pattern 14B, and the LED chip 11 It is also possible to have a configuration in which the two are electrically connected. In this case, one of the first body portion 12A and the second body portion 12B may not be provided with a circuit pattern, but the body portion not provided with the circuit pattern may be soldered with the circuit pattern 22. It is necessary to provide a dummy conductor.

なお、上述の実施の形態は本発明の一例である。このため、本発明は、上述の実施形態に限定されることはなく、この実施の形態以外であっても、本発明に係る技術的思想を逸脱しない範囲であれば、設計等に応じて種々の変更が可能であることは勿論である。   The above-described embodiment is an example of the present invention. For this reason, the present invention is not limited to the above-described embodiment, and various modifications can be made depending on the design and the like as long as the technical idea according to the present invention is not deviated from this embodiment. Of course, it is possible to change.

本発明を適用したＬＥＤパッケージの斜視図である。It is a perspective view of the LED package to which this invention is applied. 本発明を適用したＬＥＤパッケージの断面図である。It is sectional drawing of the LED package to which this invention is applied. 本発明を適用した他のＬＥＤパッケージの断面図である。It is sectional drawing of the other LED package to which this invention is applied.

符号の説明Explanation of symbols

１０ パッケージ本体
１１ ＬＥＤチップ
１２Ａ 第１本体部
１２Ｂ 第２本体部
１３ ＬＥＤチップ実装部
１４Ａ，１４Ｂ 回路パターン
１５Ａ，１５Ｂ 反射板
１６ ワイヤ
２０ 実装基板
２１Ａ，２１Ｂ ハンダ
２２Ａ 回路パターン
２２Ｂ 回路パターン
３１ 凹部
３２ 凸部 DESCRIPTION OF SYMBOLS 10 Package main body 11 LED chip 12A 1st main body part 12B 2nd main body part 13 LED chip mounting part 14A, 14B Circuit pattern 15A, 15B Reflector 16 Wire 20 Mounting board 21A, 21B Solder 22A Circuit pattern 22B Circuit pattern 31 Concave 32 Convex Part

Claims (4)

ＬＥＤチップをパッケージ本体に実装したＬＥＤパッケージにおいて、
前記パッケージ本体は、複数箇所に形成されたハンダを介して実装基板上に実装されるものであり、
前記パッケージ本体は、前記ＬＥＤチップが設けられた第１本体部と、前記ＬＥＤチップが設けられていない第２本体部とが分割されて構成され、当該第１本体部と第２本体部とが間隙を設けて前記実装基板上に配設され、
前記第１本体部及び前記第２本体部には、所定の厚みをもった角柱体を形成する一の主面の頭切円錐状の窪みが形成され、前記第１本体部における窪みの側面及び前記第２本体部における窪みの側面に反射板が形成され、前記第１本体部に形成された反射板及び前記第２本体部に形成された反射板によって前記ＬＥＤチップから放射された光を反射すること
を特徴とするＬＥＤパッケージ。 In the LED package in which the LED chip is mounted on the package body,
The package body is mounted on a mounting substrate via solder formed in a plurality of locations,
The package main body is configured by dividing a first main body portion provided with the LED chip and a second main body portion not provided with the LED chip, and the first main body portion and the second main body portion include Provided on the mounting substrate with a gap ;
The first main body part and the second main body part are formed with a truncated cone-shaped depression of one main surface forming a prismatic body having a predetermined thickness, and the side surface of the depression in the first main body part and A reflection plate is formed on the side surface of the recess in the second main body, and the light emitted from the LED chip is reflected by the reflection plate formed on the first main body and the reflection plate formed on the second main body. An LED package characterized by: ＬＥＤチップをパッケージ本体に実装したＬＥＤパッケージにおいて、
前記パッケージ本体は、複数箇所に形成されたハンダを介して実装基板上に実装されるものであり、
前記パッケージ本体は、前記ＬＥＤチップが設けられた第１本体部と、前記ＬＥＤチップが設けられていない第２本体部とが分割されて構成され、当該第１本体部と第２本体部とが間隙を設けて前記実装基板上に配設されており、
前記第１本体部に設けられた前記ＬＥＤチップと前記実装基板とを電気的に接続するように当該第１本体部に形成され、前記実装基板とハンダにより接続される第１回路パターンと、前記第２本体部に形成され前記実装基板とハンダにより接続される第２回路パターンとを備え、前記第１回路パターンと前記第２回路パターンとがワイヤボンディングにより導通されていることを特徴とするＬＥＤパッケージ。

In the LED package in which the LED chip is mounted on the package body,
The package body is mounted on a mounting substrate via solder formed in a plurality of locations,
The package main body is configured by dividing a first main body portion provided with the LED chip and a second main body portion not provided with the LED chip, and the first main body portion and the second main body portion include Provided on the mounting substrate with a gap,
A first circuit pattern formed on the first main body so as to electrically connect the LED chip provided on the first main body and the mounting substrate, and connected to the mounting substrate by solder; and a second circuit pattern connected by the mounting board and the solder is formed on the second main body portion, and said first circuit pattern and said second circuit pattern you characterized in that it is conducted by wire bonding L ED package.

前記第１本体部と前記第２本体部とが間隙を介して嵌合するように前記実装基板上に実装されていることを特徴とする請求項１又は請求項２に記載のＬＥＤパッケージ。   3. The LED package according to claim 1, wherein the first main body portion and the second main body portion are mounted on the mounting substrate so as to be fitted through a gap. 前記第１本体部と前記第２本体部とが所定の嵌合深さで嵌合されていることを特徴とする請求項３に記載のＬＥＤパッケージ。   The LED package according to claim 3, wherein the first main body portion and the second main body portion are fitted with a predetermined fitting depth.
JP2007006203A 2007-01-15 2007-01-15 LED package Expired - Fee Related JP4798000B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007006203A JP4798000B2 (en) 2007-01-15 2007-01-15 LED package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007006203A JP4798000B2 (en) 2007-01-15 2007-01-15 LED package

Publications (2)

Publication Number Publication Date
JP2008172167A JP2008172167A (en) 2008-07-24
JP4798000B2 true JP4798000B2 (en) 2011-10-19

Family

ID=39699954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007006203A Expired - Fee Related JP4798000B2 (en) 2007-01-15 2007-01-15 LED package

Country Status (1)

Country Link
JP (1) JP4798000B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101055081B1 (en) * 2010-01-15 2011-08-08 엘지이노텍 주식회사 Light emitting device, light emitting device manufacturing method and backlight unit
EP3416202B1 (en) * 2016-02-12 2021-04-07 LG Innotek Co., Ltd. Light emitting device package and lighting apparatus comprising same
CN109479373A (en) 2016-07-07 2019-03-15 莫列斯有限公司 Mold interconnecting device and the method for manufacturing it
JP6897640B2 (en) * 2018-08-02 2021-07-07 日亜化学工業株式会社 Manufacturing method of light emitting device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2825387B2 (en) * 1992-02-14 1998-11-18 シャープ株式会社 Light emitting element
JP3923817B2 (en) * 2002-02-14 2007-06-06 シチズン電子株式会社 Manufacturing method of light emitting diode
JP4651008B2 (en) * 2005-02-01 2011-03-16 シチズン電子株式会社 Light emitting diode
DE102005017527A1 (en) * 2005-04-15 2006-11-02 Osram Opto Semiconductors Gmbh Surface-mountable optoelectronic component
JP4674487B2 (en) * 2005-04-25 2011-04-20 パナソニック電工株式会社 Surface mount light emitting device

Also Published As

Publication number Publication date
JP2008172167A (en) 2008-07-24

Similar Documents

Publication Publication Date Title
JP5864742B2 (en) SUPPORT DEVICE, ELECTRIC DEVICE EQUIPPED WITH SUPPORT DEVICE, AND SUPPORT DEVICE AND METHOD FOR MANUFACTURING ELECTRIC DEVICE
KR20090104860A (en) Led package and structure for mounting three-dimensional circuit component
JP6400928B2 (en) Wiring board and electronic device
KR20030097673A (en) Method of plugging through-holes in silicon substrate
JP4798000B2 (en) LED package
KR20040097899A (en) Method of production of semiconductor device
JP4582100B2 (en) LED package
JP4687665B2 (en) LED package
US20120267674A1 (en) Mounting substrate, light emitting body, and method for manufacturing mounting substrate
KR100626845B1 (en) Manufacturing method of radiant heat circuit board
JP2015195309A (en) Manufacturing method of metal-ceramics circuit board
JP2008053621A (en) Led package
JP4100685B2 (en) Semiconductor device
JP2008016507A (en) Process for producing electric wiring
JP4107003B2 (en) Wiring board manufacturing method and board used in the manufacturing method
JP2012182210A (en) Method for manufacturing lead frame substrate for led element
JP5081418B2 (en) LED package
JP2006308413A (en) Probe card
JP4496793B2 (en) Circuit board and manufacturing method thereof
JP4151503B2 (en) Circuit board manufacturing method
JP2011044559A (en) Circuit board, method of manufacturing circuit board, circuit module, and method of manufacturing the same
JP2022095118A (en) Wiring board
JP4360285B2 (en) Semiconductor package and manufacturing method thereof
JP2005302957A (en) Multiple wiring board
CN115152040A (en) Electronic component mounting package and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080603

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110104

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110510

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110602

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110705

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110718

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140812

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees