US20220165753A1 - Semiconductor memory device and method for manufacturing same - Google Patents
Semiconductor memory device and method for manufacturing same Download PDFInfo
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- US20220165753A1 US20220165753A1 US17/669,875 US202217669875A US2022165753A1 US 20220165753 A1 US20220165753 A1 US 20220165753A1 US 202217669875 A US202217669875 A US 202217669875A US 2022165753 A1 US2022165753 A1 US 2022165753A1
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Images
Classifications
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- H01L27/11582—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L27/11565—
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- H01L27/11568—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.
- a nonvolatile memory based on the vertical MONOS (metal-oxide-nitride-oxide-silicon) structure has been proposed.
- conductive films and insulating films are alternately stacked to form a stacked body. Holes extending in the stacking direction are formed in the stacked body. A charge accumulation layer is formed on the inner surface of this hole. Then, a silicon pillar is buried in the hole. Thus, a memory transistor is formed at each closest point between the conductive film and the silicon pillar.
- the packing density of memory devices will be further increased.
- the number of stacked conductive films is increased.
- the diameter of the hole is reduced, and the aspect ratio of the hole is increased. This makes it very difficult to form the hole with a vertical side surface, and causes the diameter of the hole to decrease downward. In this case, the upper portion and the lower portion of the hole have different diameters. This causes variations in the characteristics of the memory transistors.
- FIGS. 1A and 1B are sectional views illustrating a semiconductor memory device according to a first embodiment
- FIG. 2 is a sectional view illustrating a silicon pillar and its neighborhood in the semiconductor memory device according to the first embodiment
- FIGS. 3A to 13B are process views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment
- FIGS. 14A to 15B are process views illustrating a method for manufacturing a semiconductor memory device according to a comparative example
- FIGS. 16A and 16B are sectional views illustrating a semiconductor memory device according to the comparative example
- FIGS. 17A and 17B are sectional views illustrating a semiconductor memory device according to a second embodiment
- FIGS. 18A and 18B are process views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment
- FIGS. 19A and 19B are sectional views illustrating a semiconductor memory device according to a third embodiment.
- FIGS. 20A to 21B are process views illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.
- a semiconductor memory device includes a stacked body, a plurality of semiconductor pillars, charge accumulation layers and an insulating member.
- the stacked body includes an insulating film and a conductive film alternately stacked therein.
- a trench is formed in the stacked body. The trench extends in one direction.
- the conductive film is divided by the trench.
- the plurality of semiconductor pillars are provided in the trench.
- the semiconductor pillars extend in a stacking direction of the insulating film and the conductive film.
- Each of the charge accumulation layers is provided around each of the semiconductor pillars.
- the insulating member is provided between the charge accumulation layers in the trench.
- a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film.
- the method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film.
- the method includes burying a diblock copolymer in the trench.
- the method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film.
- the method includes forming a plurality of holes by removing the first blocks.
- the method includes forming charge accumulation layers on inner surfaces of the holes.
- the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
- FIGS. 1A and 1B are sectional views illustrating a semiconductor memory device according to the embodiment.
- FIG. 1A shows a cross section parallel to the upper surface of the silicon substrate.
- FIG. 1B shows a cross section perpendicular to the upper surface of the silicon substrate.
- FIG. 2 is a sectional view illustrating a silicon pillar and its neighborhood in the semiconductor memory device according to the embodiment.
- FIG. 1B is a sectional view taken along line A-A′ shown in FIG. 1A .
- the semiconductor memory device 1 includes a silicon substrate 10 .
- a memory cell region populated with memory cells, and a peripheral circuit region (not shown) populated with driver circuits are established.
- the peripheral circuit region is located around the memory cell region.
- an insulating film 11 is provided on the silicon substrate 10 .
- a conductive film 12 is provided on the insulating film 11 .
- a plurality of insulating films 14 and conductive films 15 are alternately stacked to constitute a stacked body ML.
- the number of insulating films 14 and conductive films 15 depicted in FIG. 1B is only three for each. However, in practice, more insulating films 14 and conductive films 15 may be stacked.
- an insulating film 16 , a conductive film 17 , and an insulating film 18 are formed in this order.
- the conductive films 12 , 15 , and 17 are formed from a conductive material such as impurity-containing polysilicon.
- the insulating films 11 , 14 , 16 , and 18 are formed from an insulating material such as silicon oxide.
- an XYZ orthogonal coordinate system is herein introduced.
- the two directions parallel to the upper surface of the silicon substrate 10 and orthogonal to each other are referred to as X and Y directions.
- the direction orthogonal to both the X and Y directions, i.e., the stacking direction of the layers, is referred to as Z direction.
- Trenches 20 and 21 extending in the Y direction are alternately formed in the stacked body ML, the insulating film 16 , and the conductive film 17 .
- the trench 20 penetrates through the insulating film 18 , the conductive film 17 , the insulating film 16 , and the stacked body ML to the conductive film 12 .
- the trench 21 penetrates through the lower portion of the insulating film 18 , the conductive film 17 , the insulating film 16 , and the portion of the stacked body ML except the lowermost insulating film 14 . However, the trench 21 does not penetrate through the upper portion of the insulating film 18 and the lowermost insulating film 14 .
- the conductive film 15 is divided by the trenches 20 and 21 into a plurality of control gate electrodes CG extending in the Y direction.
- the conductive film 17 is divided by the trenches 20 and 21 into a plurality of select gate electrodes SG extending in the Y direction.
- the trench 20 is shaped like a generally rectangular solid.
- the trench 20 is longest along its depth d, i.e., the length in the Z direction.
- the trench 20 is second longest along its longitudinal length l, i.e., the length in the Y direction.
- the trench 20 is shortest along its width w, i.e., the length in the X direction. That is, these dimensions satisfy d>l>w.
- a plurality of silicon pillars SP extending in the Z direction (stacking direction) are provided.
- the silicon pillar SP is formed from impurity-doped polysilicon.
- the silicon pillars SP are equally spaced in a line along the Y direction.
- the number of silicon pillars SP provided in each trench 20 is e.g. three.
- the silicon pillar SP is shaped like a circular column with the central axis extending in the Z direction in which the two side portions of this circular column opposed to the inner surface of the trench 20 are trimmed along the YZ plane. That is, the region 25 of the side surface of the silicon pillar SP opposed to the inner surface of the trench 20 is parallel to the YZ plane and parallel to the side surface of the trench 20 .
- the outer edge of the silicon pillar SP includes a pair of circular arcs and a pair of line segments.
- a recess 12 a shaped like a generally rectangular solid with the longitudinal direction aligned with the X direction is formed.
- a coupling member 26 made of impurity-doped polysilicon is provided inside the recess 12 a.
- the coupling member is shaped like a generally rectangular solid with the longitudinal direction aligned with the X direction. Both end portions of the coupling member 26 are exposed at the bottom surface of two adjacent trenches 20 .
- the central portion of the coupling member 26 is located immediately below the trench 21 .
- the lower ends of two silicon pillars SP adjacent in the X direction are coupled.
- the coupling member 26 is formed integrally with these two silicon pillars SP. Hence, these two silicon pillars SP are connected to each other via the coupling member 26 .
- One of the two silicon pillars SP connected to both ends of one coupling member 26 is connected to a source line (not shown), and the other is connected to a bit line (not shown).
- the source line is provided on the select gate electrode SG and extends in the Y direction.
- the bit line is provided on the source line and extends in the X direction.
- a memory film 30 is provided around the silicon pillar SP, i.e., on the entire region of the side surface, and around the coupling member 26 .
- a tunnel layer 31 In the memory film 30 , a tunnel layer 31 , a charge accumulation layer 32 , and a block layer 33 are stacked sequentially from inside, i.e., from the side of the silicon pillar SP and the coupling member 26 .
- the tunnel layer 31 is a layer which is normally insulative, but passes a tunnel current under application of a prescribed voltage in the range of the driving voltage of the semiconductor memory device 1 .
- the tunnel layer 31 is formed from e.g. silicon oxide.
- the charge accumulation layer 32 is a layer capable of trapping charge, and is formed from e.g. silicon nitride.
- the block layer 33 is a layer which substantially blocks the flow of current even under application of voltage in the range of the driving voltage of the semiconductor memory device 1 .
- the block layer 33 is formed from e.g. silicon oxide.
- the memory film 30 is an ONO (oxide-nitride-oxide) film.
- the control gate electrode CG, the memory film 30 , and the silicon pillar SP constitute a MONOS structure.
- the silicon pillar SP is insulated from the conductive film 12 , the control gate electrode CG, and the select gate electrode SG by the memory film 30 .
- an insulating member 28 is provided between the memory films 30 in the trench 20 .
- the insulating member 28 is formed primarily from silicon oxide.
- the insulating member 28 is a member formed by a method different from that for the insulating films 11 , 14 , 16 , and 18 .
- the composition of the insulating member 28 is slightly different from the composition of these insulating films.
- the insulating member 28 contains a trace amount of organic residual components besides silicon oxide. As described later, for instance, the insulating member 28 is formed by heat treatment of polyethylene oxide in a diblock copolymer of polystyrene and polyethylene oxide.
- an insulating member 29 shaped like a plate along the YZ plane is provided in the trench 21 .
- the insulating member 29 is formed from e.g. silicon nitride.
- the silicon pillar SP functions as a channel
- the control gate electrode CG functions as a gate electrode
- the charge accumulation layer 32 accumulates electrons.
- a vertical memory transistor MT is formed at each closest point between the silicon pillar SP and the control gate electrode CG.
- a plurality of memory transistors MT are arranged three-dimensionally along the X, Y, and Z directions.
- FIGS. 3A to 13B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment.
- the figures labeled with “A” are plan views.
- the figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”.
- a silicon substrate 10 is prepared.
- transistors and wirings, for instance, constituting driver circuits are formed.
- an insulating film 11 made of silicon oxide is formed on the silicon substrate 10 .
- a conductive film 12 made of impurity-containing polysilicon is formed on the insulating film 11 .
- a resist film 41 is formed on the conductive film 12 .
- a plurality of strip-shaped openings 41 a with the longitudinal direction aligned with the X direction are formed in the resist film 41 .
- the openings 41 a are arranged in a matrix configuration along the X and Y directions.
- the resist film 41 (see FIGS. 4A and 4B ) is used as a mask to perform dry etching.
- a recess 12 a shaped like a rectangular solid with the longitudinal direction aligned with the X direction is formed in the upper portion of the conductive film 12 .
- ashing is performed to remove the resist film 41 .
- silicon nitride is deposited on the entire surface.
- dry etching is performed to remove the portion of the silicon nitride deposited on the upper surface of the conductive film 12 .
- a sacrificial material 42 made of silicon nitride is buried in the recess 12 a.
- insulating films 14 made of silicon oxide and conductive films 15 made of polysilicon are alternately formed on the conductive film 12 and the sacrificial material 42 .
- a stacked body ML is formed.
- an insulating film 16 made of silicon oxide, a conductive film 17 made of polysilicon, and an insulating film 18 a made of silicon oxide are deposited in this order.
- a resist film 43 is formed on the insulating film 18 a.
- a plurality of groove-shaped openings 43 a extending in the Y direction are formed in the resist film 43 .
- the resist film 43 (see FIGS. 6A and 6B ) is used as a mask to perform dry etching to selectively remove the insulating film 18 a, the conductive film 17 , the insulating film 16 , and the stacked body ML.
- the lowermost insulating film 14 of the stacked body ML is left unetched.
- a trench 21 extending in the Y direction is formed in the portion of the stacked body ML except the lowermost insulating film 14 , the insulating film 16 , the conductive film 17 , and the insulating film 18 a.
- the trench 21 is formed immediately below the opening 43 a at a position linking the immediately overlying regions of the X-direction central portions of the sacrificial materials 42 .
- ashing is performed to remove the resist film 43 .
- silicon nitride is deposited by the CVD process.
- dry etching is performed to remove the portion of the silicon nitride deposited on the insulating film 18 a.
- an insulating member 29 made of silicon nitride is buried in the trench 21 .
- silicon oxide is deposited by the CVD process to form an insulating film 18 b on the insulating film 18 a.
- the insulating films 18 a and 18 b constitute an insulating film 18 .
- a resist film 44 is formed on the insulating film 18 .
- an opening 44 a extending in the Y direction is formed in the resist film 44 .
- the opening 44 a is formed at a position linking the immediately overlying regions of both X-direction end portions of the sacrificial materials 42 .
- the resist film 44 (see FIGS. 9A and 9B ) is used as a mask to perform dry etching to selectively remove the insulating film 18 , the conductive film 17 , the insulating film 16 , and the stacked body ML.
- a trench 20 extending in the Y direction is formed immediately below the opening 44 a.
- the trench 20 is shaped like a generally rectangular solid.
- the length l is made longer than the width w
- the depth d is made longer than the length l. That is, these dimensions are set to satisfy d>l>w.
- the conductive films 12 and the sacrificial materials 42 are exposed and alternately arranged along the Y direction.
- the conductive film 17 is divided by the trenches 20 and 21 into a plurality of select gate electrodes SG.
- each conductive film 15 is divided by the trenches 20 and 21 into a plurality of control gate electrodes CG. Subsequently, ashing is performed to remove the resist film 44 .
- a cylindrical (circular columnar) hole is formed in the trench 20 .
- a method for this is specifically described below.
- a diblock copolymer is applied and buried in the trench 20 .
- the diblock copolymer is a polymer of two kinds of macromolecules which are phase-separated under an appropriate condition.
- Various materials can be used as the diblock copolymer.
- a polymer of polystyrene (PS) and polyethylene oxide (PEO) is used (this polymer is hereinafter referred to as “PS-PEO polymer”).
- PS-PEO polymer polystyrene (PS) groups and polyethylene oxide (PEO) groups are coupled in a straight chain.
- the diblock copolymer is phase-separated.
- the PS-PEO polymer as the diblock copolymer is separated into a block 46 a resulting from polystyrene (PS) groups and a block 46 b resulting from polyethylene oxide (PEO) groups.
- the block 46 a is made of an organic material.
- the block 46 b is made of silicon oxide in which a small amount of organic residual material is left behind. That is, the block 46 b is substantially made of an inorganic material.
- the inner surface of the trench 20 includes the insulating films 14 , 16 , and 18 made of silicon oxide, the conductive films 12 , 15 , 17 made of silicon, and the sacrificial material 42 made of silicon nitride.
- the inner surface of the trench 20 is entirely hydrophilic.
- polyethylene oxide (PEO) is hydrophilic
- polystyrene (PS) is hydrophobic. That is, the diblock copolymer used in the embodiment is a copolymer having hydrophobic first molecules and hydrophilic second molecules.
- the interfacial energy between the hydrophilic inner surface of the trench 20 and hydrophilic polyethylene oxide (PEO) is lower than the interfacial energy between the hydrophilic inner surface of the trench 20 and hydrophobic polystyrene (PS).
- the polyethylene oxide (PEO) group is coupled to the inner surface of the trench 20
- the polystyrene (PS) group is located at a position spaced from the inner surface of the trench 20 by the length of the PEO group.
- the block 46 b resulting from polyethylene oxide (PEO) groups is aggregated along the inner surface of the trench 20 .
- the block 46 a resulting from polystyrene (PS) groups is aggregated at a position spaced by a fixed distance from the inner surface of the trench 20 .
- the shape and position of the blocks 46 a and 46 b can be controlled by selecting e.g. the size and shape of the trench 20 , the total molecular weight of the PS-PEO polymer, the ratio between PEO groups and PS groups, and the heat treatment condition for phase separation.
- the shape of the block 46 a can be controlled by selecting the ratio between PS groups and PEO groups in the PS-PEO polymer. For instance, the ratio between PS groups and PEO groups being approximately 1:1 produces a lamellar structure in which the blocks 46 a and the blocks 46 b are alternately arranged. If the ratio of PS groups is lower, the block 46 a is shaped like a cylinder (circular column). If the ratio of PS groups is still lower, the block 46 a is shaped like a ball. Furthermore, the formation position of the block 46 a can be controlled by selecting e.g. the size and shape of the trench 20 .
- the blocks 46 a can be aggregated like a cylinder extending in the Z direction immediately above both X-direction end portions of the sacrificial material 42 .
- the block 46 a can be shaped like a cylinder by making the ratio of PS groups lower than the ratio of PEO groups.
- the diameter of the cylindrical block 46 a has a fixed value resulting from the molecular structure of the PS-PEO polymer, such as the length of the PS group.
- the diameter of the block 46 a is made uniform. By adjusting the molecular structure of the PS-PEO polymer, the diameter of the block 46 a can be controlled to an arbitrary value.
- a plurality of blocks 46 a are formed, and the block 46 b is packed in the trench 20 so as to enclose this plurality of blocks 46 a. Hence, the blocks 46 a are not in contact with the inner surface of the trench 20 .
- the depth d of the trench 20 is 300 nm (nanometers), the length l is 70 nm, and the width w is 20 nm.
- the total molecular weight of the PS-PEO polymer is set to approximately 10000, the ratio between PS groups and PEO groups is set to approximately 1:2, the temperature of heat treatment for phase separation is set to approximately 150-250° C., and the time of this heat treatment is set to several minutes. Then, the block 46 a resulting from PS groups can be shaped like a cylinder with a diameter of approximately 10 nm.
- the block 46 b resulting from polyethylene oxide (PEO) is etched back to expose the upper surface of the block 46 a (see FIGS. 11A and 11B ).
- the exposed surface of the insulating film 18 made of silicon oxide is etched to some extent.
- polystyrene PS
- PEO polyethylene oxide
- silicon oxide silicon oxide
- the block 46 b is etched through the hole 47 .
- the side surface of each hole 47 is set back and partly reaches the inner surface of the trench 20 , and the bottom surface of the hole 47 is lowered and reaches the bottom surface of the trench 20 .
- This increases the diameter and depth of the hole 47 , and changes the shape of the hole 47 . That is, as viewed in the Z direction, the shape of the hole 47 includes a pair of circular arcs made of the side surface of the block 46 b, and a pair of line segments made of the side surfaces of the trench 20 .
- the bottom surface of the hole 47 includes the sacrificial material 42 .
- each U-shaped hole 48 includes one recess 12 a and two holes 47 communicating with both end portions of the recess 12 a.
- a block layer 33 made of silicon oxide, a charge accumulation layer 32 made of silicon nitride, and a tunnel layer 31 made of silicon oxide are deposited in this order on the inner surface of the U-shaped hole 48 .
- the stacked film made of the block layer 33 , the charge accumulation layer 32 , and the tunnel layer 31 constitutes a memory film 30 .
- polysilicon is deposited on the entire surface.
- dry etching is performed to remove the portion of the deposited polysilicon located on the upper surface of the insulating film 18 .
- polysilicon is buried in the U-shaped hole 48 to form a coupling member 26 in the recess 12 a and a silicon pillar SP in the hole 47 .
- the block 46 b constitutes an insulating member 28 .
- an upper wiring structure including source lines (not shown) and bit lines (not shown) is formed on the insulating film 18 .
- the semiconductor memory device 1 according to the embodiment is manufactured.
- a trench 20 is formed in the stacked body ML.
- a diblock copolymer is buried in the trench 20 and phase-separated to form a cylindrical block 46 a and a block 46 b surrounding the block 46 a in the trench 20 .
- a hole 47 is formed by removing only the block 46 a.
- a memory film 30 is formed on the inner surface of the hole 47 , and a silicon pillar SP is formed inside the hole 47 .
- memory transistors MT are formed.
- the shape of the block 46 a is determined by the molecular structure of the diblock copolymer.
- the diameter of the block 46 a is made uniform throughout the vertical direction.
- the diameter of the hole 47 is also made uniform throughout the vertical direction. That is, the taper angle of the side surface of the hole 47 is made nearly equal to 90°.
- the diameter of the silicon pillar SP is made uniform, and the curvature of the memory film 30 is also made uniform.
- the holes 47 are formed by the self-organization technique.
- the holes 47 have high shape stability. This also contributes to the uniform characteristics of memory transistors MT.
- the shape of the blocks 46 a and 46 b after phase separation depends on the ratio of macromolecules composing the diblock copolymer.
- the PS-PEO polymer is used as the diblock copolymer, and the ratio of PS groups is made lower than the ratio of PEO groups.
- the block 46 a is shaped like a cylinder.
- the phase separation of the diblock copolymer is affected by the inner surface of the trench 20 .
- the formation position of the block 46 a depends on the shape of the trench 20 .
- the trench 20 is shaped like a generally rectangular solid, with the depth d of the trench 20 made larger than the length l and the width w, and the length l made larger than the width w.
- the phase separation of the diblock copolymer buried in the trench 20 is made less likely to be affected by the bottom surface of the trench 20 , and provided with no structure in the vertical direction (Z direction).
- the cylindrical block 46 a extends in the vertical direction.
- the blocks 46 a are arranged in a line along the longitudinal direction of the trench 20 (Y direction).
- the block 46 a can be located immediately above the sacrificial material 42 by appropriately selecting the relative position of the trench 20 with respect to the recess 12 a.
- the conductive film 15 is divided into a plurality of control gate electrodes CG. Then, a hole 47 is formed in part of the trench 20 , a memory film 30 is formed on the inner surface of the hole 47 , and a silicon pillar SP is provided on the memory film 30 .
- the memory film 30 is located between the silicon pillar SP and the control gate electrode CG (conductive film 15 ) to constitute a memory transistor MT.
- two memory transistors MT are located at each intersection between one silicon pillar SP and one conductive film 15 , enabling storage of at least two bits of information. Furthermore, these two memory transistors MT share the silicon pillar SP. Hence, the packing density can be made higher than that in the case of providing a silicon pillar SP for each memory transistor MT.
- the outer edge of the silicon pillar SP includes a pair of circular arcs and a pair of line segments.
- the region 25 of the side surface of the silicon pillar SP opposed to the inner surface of the trench 20 constitutes a plane parallel to the side surface of the trench 20 .
- the silicon pillar SP and the control gate electrode CG have a positional relationship of parallel plates.
- the electric field is made less likely to concentrate on one location.
- the electric field is applied uniformly in the film thickness direction. This stabilizes the operation of the memory transistor MT.
- FIGS. 14A to 15B are process views illustrating a method for manufacturing a semiconductor memory device according to the comparative example.
- the figures labeled with “A” are plan views.
- the figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”.
- FIGS. 16A and 16B are sectional views illustrating a semiconductor memory device according to the comparative example.
- FIG. 16A shows a cross section parallel to the upper surface of the silicon substrate.
- FIG. 16B shows a cross section taken along line A-A′ shown in FIG. 16A , i.e., a cross section perpendicular to the upper surface of the silicon substrate.
- a resist film 91 is formed on the insulating film 18 .
- an opening 91 a shaped like e.g. a circle is formed immediately above each of both X-direction end portions of the sacrificial material 42 in the resist film 91 .
- a hole pattern is formed in the resist film 91 .
- the resist film 91 (see FIGS. 14A and 14B ) is used as a mask to perform dry etching to selectively remove the insulating film 18 , the conductive film 17 , the insulating film 16 , and the stacked body ML.
- a hole 92 reaching the sacrificial material 42 (see FIGS. 14A and 14B ) is formed immediately below the opening 91 a.
- the insulating films 18 , 16 , and 14 made of silicon oxide, in particular are difficult to process vertically.
- the side surface of the hole 92 is inevitably inclined.
- the hole 92 is tapered downward.
- ashing is performed to remove the resist film 91 .
- the sacrificial material 42 (see FIGS. 14A and 14B ) is removed through the hole 92 .
- two holes 92 adjacent in the X direction are coupled through the recess 12 a of the conductive film 12 to form a U-shaped hole 93 .
- a block layer 33 , a charge accumulation layer 32 , and a tunnel layer 31 are deposited on the inner surface of the U-shaped hole 93 .
- a memory film 30 is formed.
- polysilicon is buried in the U-shaped hole 93 to form a silicon pillar SP and a coupling member 26 .
- the semiconductor memory device according to the comparative example is manufactured.
- holes 92 are formed by dry etching.
- the side surface of the hole 92 is inevitably inclined, and the diameter of the hole 92 decreases downward.
- the diameter of the opening 91 a of the resist film 91 is set to 30 nm (nanometers), and consider the case of forming a hole 92 with a depth of 1 ⁇ m (micron). Then, the aspect ratio exceeds 30 . In this case, for the above-mentioned reason, etching is made difficult, and the hole 92 is tapered downward.
- the silicon pillar SP is made slimmer, and the curvature of the memory film 30 is made larger. This causes the amount of charge accumulated in the memory transistor MT to vary with the formation position.
- the characteristics of memory transistors MT are varied with the formation position. This degrades the overall characteristics of the semiconductor memory device.
- the holes 47 are formed by the self-organization technique. Hence, even if the aspect ratio of the hole 47 is increased, the diameter can be made uniform. As a result, the characteristics of memory transistors MT can be made uniform. This improves the overall characteristics of the semiconductor memory device 1 .
- the variation in the taper angle of the hole required in the semiconductor memory device having the three-dimensional structure as described above can be calculated as follows.
- the variation in the diameter of the hole also needs to be limited to 10% or less.
- the diameter of the upper end portion of the hole is 30 nm
- the diameter of the lower end portion needs to be set to 27 nm or more.
- Such processing is very difficult to realize by etching, but easy by using the self-organization technique.
- the hole 92 is formed by lithography and dry etching. Hence, the shape of the hole 92 as viewed in the Z direction may be deviated from a perfect circle. If the shape of the hole 92 is deviated from a perfect circle, a portion having a high curvature may occur at the inner surface of the hole 92 and the outer surface of the memory film 30 and the silicon pillar SP. The electric field may concentrate on this portion. This increases the operational variation at the time of writing and reading data. Furthermore, because the memory film 30 is formed cylindrically, the electric field applied to the inner tunnel layer 31 is made stronger than that applied to the outer block layer 33 .
- the shape of the hole 47 is determined by the molecular structure of the diblock copolymer, and hence made uniform at the molecular level. This suppresses the operational variation at the writing/reading time. Furthermore, the portion of the memory transistor MT subjected to the electric field has a planar structure. Hence, the electric field is less likely to concentrate on this portion.
- the trench 20 (see FIGS. 1A and 1B ) is not formed.
- the conductive film 15 is not divided by the trench 20 to both sides of the silicon pillar SP.
- only one memory transistor MT is formed at each intersection between one silicon pillar SP and one conductive film 15 .
- the information storage density is halved as compared with the above first embodiment.
- FIGS. 17A and 17B are sectional views illustrating a semiconductor memory device according to the embodiment.
- FIG. 17A shows a cross section parallel to the upper surface of the silicon substrate.
- FIG. 17B shows a cross section taken along line A-A′ shown in FIG. 17A , i.e., a cross section perpendicular to the upper surface of the silicon substrate.
- the semiconductor memory device 2 according to the embodiment is different from the semiconductor memory device 1 (see FIGS. 1A and 1B ) according to the above first embodiment in that a guide 51 projected toward the inside of the trench 20 is formed at both side surfaces of the trench 20 .
- the guide 51 is formed from the stacked body ML, the insulating film 16 , the conductive film 17 , and the insulating film 18 left behind.
- the guides 51 are periodically arranged along the Y direction. The phase of the arrangement is equal at both side surfaces of the trench 20 .
- the portion of the trench 20 provided with the guide 51 constitutes a narrow width portion 52 a having a relatively narrow width.
- the portion of the trench 20 not provided with the guide 51 constitutes a wide width portion 52 b having a relatively wide width.
- the narrow width portions 52 a and the wide width portions 52 b are alternately arranged along the Y direction.
- the silicon pillar SP and the memory film 30 are located in the wide width portion 52 b.
- FIGS. 18A and 18B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment.
- FIG. 18A is a plan view.
- FIG. 18B is a sectional view taken along line A-A′ shown in FIG. 18A .
- the pattern of the resist film 44 is adjusted so that a guide 51 projected toward the inside of the trench 20 is formed at both side surfaces of the trench 20 .
- the guides 51 are periodically arranged along the longitudinal direction of the trench 20 (Y direction). Furthermore, the phase of the arrangement is matched between both side surfaces of the trench 20 .
- narrow width portions 52 a where the guides 51 are formed on both sides and the width is relatively narrow
- wide width portions 52 b where the guides 51 are not formed and the width is relatively wide
- a diblock copolymer is buried inside the trench 20 and phase-separated.
- the hydrophilic block 46 b is formed along the inner surface of the trench 20 including the guide 51
- the hydrophobic block 46 a is formed at a position spaced by a prescribed distance from the inner surface of the trench 20 including the guide 51 .
- the block 46 a is formed like a cylinder extending in the Z direction in the central portion of the wide width portion 52 b.
- the process shown in FIGS. 12A to 13B is performed.
- the silicon pillar SP and the memory film 30 are located in the wide width portion 52 b of the trench 20 .
- the guide 51 is provided at the inner surface of the trench 20 . This can reliably control the shape and position of the block 46 a. Thus, the shape and position of the silicon pillar SP and the memory film 30 can be reliably controlled.
- the configuration, the manufacturing method, and the operation and effect of the embodiment other than the foregoing are similar to those of the above first embodiment.
- FIGS. 19A and 19B are sectional views illustrating a semiconductor memory device according to the embodiment.
- FIG. 19A shows a cross section parallel to the upper surface of the silicon substrate.
- FIG. 19B shows a cross section taken along line A-A′ shown in FIG. 19A , i.e., a cross section perpendicular to the upper surface of the silicon substrate.
- the semiconductor memory device 3 according to the embodiment is different from the semiconductor memory device 1 (see FIGS. 1A and 1B ) according to the above first embodiment in that as viewed in the Z direction, the silicon pillar SP is shaped like a rectangle, and the memory film 30 is shaped like a frame. Between the memory films 30 in the trench 20 , an insulating member 28 including e.g. silicon oxide is provided.
- FIGS. 20A to 21B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment.
- the figures labeled with “A” are plan views.
- the figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”.
- a diblock copolymer is applied and buried in the trench 20 .
- a diblock copolymer for instance, a PS-PEO polymer is used.
- the ratio between PS groups and PEO groups is set to approximately 1:1.
- the PS-PEO polymer is phase-separated.
- the phase structure after separation is a lamellar structure in which blocks 46 a resulting from PS groups and blocks 46 b resulting from PEO groups are alternately arranged along the longitudinal direction of the trench 20 (Y direction).
- the blocks 46 a and 46 b are both shaped like a rectangular column extending in the Z direction.
- the blocks 46 a and 46 b are both shaped like a rectangle.
- each size of the blocks 46 a and 46 b is uniform.
- the blocks 46 a and 46 b are both in contact with the side surface and bottom surface of the trench 20 . The upper surface of the blocks 46 a and 46 b is exposed.
- the block 46 a is removed.
- a hole 61 is formed.
- the hole 61 extends in the Z direction.
- the upper surface of the hole 61 is opened.
- the sacrificial material 42 is exposed.
- the side surface of the trench 20 is exposed.
- the shape of the hole 61 is determined by the shape of the block 46 a.
- the hole 61 is shaped like a rectangular column with a vertical inner surface and a uniform width.
- each U-shaped hole 62 includes one recess 12 a and two holes 61 communicating with both end portions of the recess 12 a.
- a block layer 33 (see FIGS. 2A and 2B ), a charge accumulation layer 32 (see FIGS. 2A and 2B ), and a tunnel layer 31 (see FIGS. 2A and 2B ) are deposited in this order on the inner surface of the U-shaped hole 62 to form a memory film 30 .
- the memory film 30 is shaped like a frame.
- polysilicon is buried inside the U-shaped hole 62 to form a coupling member 26 in the recess 12 a and a silicon pillar SP in the hole 61 .
- the silicon pillar SP is shaped like a rectangle.
- the block 46 b left behind constitutes an insulating member 28 .
- an upper structure including source lines (not shown) and bit lines (not shown) is formed.
- the semiconductor memory device 3 according to the embodiment is manufactured.
- the block structure of the phase-separated PS-PEO polymer is set to a lamellar structure.
- the block 46 a can be formed in contact with the side surface and bottom surface of the trench 20 , with the upper surface of the block 46 a exposed.
- the hole 61 can be formed simply by removing the block 46 a. This eliminates the need to etch the block 46 b before and after the step of removing the block 46 a. As a result, the process for manufacturing the semiconductor memory device 3 can be simplified.
- a copolymer of polystyrene (PS) and polyethylene oxide (PEO) is used as a diblock copolymer.
- PS polystyrene
- PEO polyethylene oxide
- the diblock copolymer can be made of any material as long as it is separated into two or more kinds of blocks by phase separation, at least one kind of blocks have a shape extending in the Z direction with uniform thickness, and this block extending in the Z direction can be removed by a suitable method.
- this block left behind is insulative and stable as a device material, this block can be directly used as an insulating member for separation between the memory films.
- the block to be removed is made of an organic material
- the block to be left behind is made of an inorganic material.
- this block can be replaced by another insulating material after forming the memory film and the silicon pillar.
- the embodiments described above can realize a semiconductor memory device with uniform characteristics of memory transistors, and a method for manufacturing the same.
Abstract
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
Description
- This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 16/809,735 filed Mar. 5, 2020, which is a divisional of U.S. application Ser. No. 15/635,398 filed Jun. 28, 2017, which is a division of U.S. application Ser. No. 14/981,526 filed Dec. 28, 2015 (now U.S. Pat. No. 9,728,550 issued Aug. 8, 2017), which is a continuation of U.S. application Ser. No. 13/344,757 filed Jan. 6, 2012 (now U.S. Pat. No. 9,385,137 issued Jul. 5, 2016), and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2011-138387 filed Jun. 22, 2011, the entire contents of each of which are incorporated herein by reference.
- Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.
- Recently, as a new memory device, a nonvolatile memory based on the vertical MONOS (metal-oxide-nitride-oxide-silicon) structure has been proposed. In manufacturing this memory device, conductive films and insulating films are alternately stacked to form a stacked body. Holes extending in the stacking direction are formed in the stacked body. A charge accumulation layer is formed on the inner surface of this hole. Then, a silicon pillar is buried in the hole. Thus, a memory transistor is formed at each closest point between the conductive film and the silicon pillar.
- However, in the future, the packing density of memory devices will be further increased. Then, the number of stacked conductive films is increased. Furthermore, the diameter of the hole is reduced, and the aspect ratio of the hole is increased. This makes it very difficult to form the hole with a vertical side surface, and causes the diameter of the hole to decrease downward. In this case, the upper portion and the lower portion of the hole have different diameters. This causes variations in the characteristics of the memory transistors.
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FIGS. 1A and 1B are sectional views illustrating a semiconductor memory device according to a first embodiment; -
FIG. 2 is a sectional view illustrating a silicon pillar and its neighborhood in the semiconductor memory device according to the first embodiment; -
FIGS. 3A to 13B are process views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment; -
FIGS. 14A to 15B are process views illustrating a method for manufacturing a semiconductor memory device according to a comparative example; -
FIGS. 16A and 16B are sectional views illustrating a semiconductor memory device according to the comparative example; -
FIGS. 17A and 17B are sectional views illustrating a semiconductor memory device according to a second embodiment; -
FIGS. 18A and 18B are process views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment; -
FIGS. 19A and 19B are sectional views illustrating a semiconductor memory device according to a third embodiment; and -
FIGS. 20A to 21B are process views illustrating a method for manufacturing a semiconductor memory device according to the third embodiment. - In general, a semiconductor memory device includes a stacked body, a plurality of semiconductor pillars, charge accumulation layers and an insulating member. The stacked body includes an insulating film and a conductive film alternately stacked therein. A trench is formed in the stacked body. The trench extends in one direction. The conductive film is divided by the trench. The plurality of semiconductor pillars are provided in the trench. The semiconductor pillars extend in a stacking direction of the insulating film and the conductive film. Each of the charge accumulation layers is provided around each of the semiconductor pillars. The insulating member is provided between the charge accumulation layers in the trench.
- In general, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
- Embodiments of the invention will now be described with reference to the drawings.
- First, a first embodiment is described.
-
FIGS. 1A and 1B are sectional views illustrating a semiconductor memory device according to the embodiment.FIG. 1A shows a cross section parallel to the upper surface of the silicon substrate.FIG. 1B shows a cross section perpendicular to the upper surface of the silicon substrate. -
FIG. 2 is a sectional view illustrating a silicon pillar and its neighborhood in the semiconductor memory device according to the embodiment. - Here,
FIG. 1B is a sectional view taken along line A-A′ shown inFIG. 1A . - As shown in
FIGS. 1A and 1B and 2 , thesemiconductor memory device 1 according to the embodiment includes asilicon substrate 10. On thesilicon substrate 10, a memory cell region populated with memory cells, and a peripheral circuit region (not shown) populated with driver circuits are established. The peripheral circuit region is located around the memory cell region. - In the memory cell region, an insulating
film 11 is provided on thesilicon substrate 10. Aconductive film 12 is provided on the insulatingfilm 11. On theconductive film 12, a plurality of insulatingfilms 14 andconductive films 15 are alternately stacked to constitute a stacked body ML. Here, the number of insulatingfilms 14 andconductive films 15 depicted inFIG. 1B is only three for each. However, in practice, more insulatingfilms 14 andconductive films 15 may be stacked. On the stacked body ML, an insulatingfilm 16, aconductive film 17, and an insulatingfilm 18 are formed in this order. Theconductive films films - In the following, for convenience of description, an XYZ orthogonal coordinate system is herein introduced. In this coordinate system, the two directions parallel to the upper surface of the
silicon substrate 10 and orthogonal to each other are referred to as X and Y directions. The direction orthogonal to both the X and Y directions, i.e., the stacking direction of the layers, is referred to as Z direction. -
Trenches film 16, and theconductive film 17. Thetrench 20 penetrates through the insulatingfilm 18, theconductive film 17, the insulatingfilm 16, and the stacked body ML to theconductive film 12. Thetrench 21 penetrates through the lower portion of the insulatingfilm 18, theconductive film 17, the insulatingfilm 16, and the portion of the stacked body ML except the lowermost insulatingfilm 14. However, thetrench 21 does not penetrate through the upper portion of the insulatingfilm 18 and the lowermost insulatingfilm 14. - The
conductive film 15 is divided by thetrenches conductive film 17 is divided by thetrenches trench 20 is shaped like a generally rectangular solid. Thetrench 20 is longest along its depth d, i.e., the length in the Z direction. Thetrench 20 is second longest along its longitudinal length l, i.e., the length in the Y direction. Thetrench 20 is shortest along its width w, i.e., the length in the X direction. That is, these dimensions satisfy d>l>w. - In the
trench 20, a plurality of silicon pillars SP extending in the Z direction (stacking direction) are provided. The silicon pillar SP is formed from impurity-doped polysilicon. In eachtrench 20, the silicon pillars SP are equally spaced in a line along the Y direction. The number of silicon pillars SP provided in eachtrench 20 is e.g. three. - The silicon pillar SP is shaped like a circular column with the central axis extending in the Z direction in which the two side portions of this circular column opposed to the inner surface of the
trench 20 are trimmed along the YZ plane. That is, theregion 25 of the side surface of the silicon pillar SP opposed to the inner surface of thetrench 20 is parallel to the YZ plane and parallel to the side surface of thetrench 20. Hence, as viewed in the Z direction, the outer edge of the silicon pillar SP includes a pair of circular arcs and a pair of line segments. - In the upper surface of the
conductive film 12, arecess 12 a shaped like a generally rectangular solid with the longitudinal direction aligned with the X direction is formed. Inside therecess 12 a, acoupling member 26 made of impurity-doped polysilicon is provided. The coupling member is shaped like a generally rectangular solid with the longitudinal direction aligned with the X direction. Both end portions of thecoupling member 26 are exposed at the bottom surface of twoadjacent trenches 20. The central portion of thecoupling member 26 is located immediately below thetrench 21. To the upper surfaces of both end portions of thecoupling member 26, the lower ends of two silicon pillars SP adjacent in the X direction are coupled. Thecoupling member 26 is formed integrally with these two silicon pillars SP. Hence, these two silicon pillars SP are connected to each other via thecoupling member 26. One of the two silicon pillars SP connected to both ends of onecoupling member 26 is connected to a source line (not shown), and the other is connected to a bit line (not shown). The source line is provided on the select gate electrode SG and extends in the Y direction. The bit line is provided on the source line and extends in the X direction. - A
memory film 30 is provided around the silicon pillar SP, i.e., on the entire region of the side surface, and around thecoupling member 26. In thememory film 30, atunnel layer 31, acharge accumulation layer 32, and ablock layer 33 are stacked sequentially from inside, i.e., from the side of the silicon pillar SP and thecoupling member 26. Thetunnel layer 31 is a layer which is normally insulative, but passes a tunnel current under application of a prescribed voltage in the range of the driving voltage of thesemiconductor memory device 1. Thetunnel layer 31 is formed from e.g. silicon oxide. Thecharge accumulation layer 32 is a layer capable of trapping charge, and is formed from e.g. silicon nitride. Theblock layer 33 is a layer which substantially blocks the flow of current even under application of voltage in the range of the driving voltage of thesemiconductor memory device 1. Theblock layer 33 is formed from e.g. silicon oxide. In this case, thememory film 30 is an ONO (oxide-nitride-oxide) film. Thus, the control gate electrode CG, thememory film 30, and the silicon pillar SP constitute a MONOS structure. The silicon pillar SP is insulated from theconductive film 12, the control gate electrode CG, and the select gate electrode SG by thememory film 30. - Between the
memory films 30 in thetrench 20, an insulatingmember 28 is provided. The insulatingmember 28 is formed primarily from silicon oxide. However, the insulatingmember 28 is a member formed by a method different from that for the insulatingfilms member 28 is slightly different from the composition of these insulating films. The insulatingmember 28 contains a trace amount of organic residual components besides silicon oxide. As described later, for instance, the insulatingmember 28 is formed by heat treatment of polyethylene oxide in a diblock copolymer of polystyrene and polyethylene oxide. - On the other hand, in the
trench 21, an insulatingmember 29 shaped like a plate along the YZ plane is provided. The insulatingmember 29 is formed from e.g. silicon nitride. - In the
semiconductor memory device 1, the silicon pillar SP functions as a channel, the control gate electrode CG functions as a gate electrode, and thecharge accumulation layer 32 accumulates electrons. Thus, a vertical memory transistor MT is formed at each closest point between the silicon pillar SP and the control gate electrode CG. In thesemiconductor memory device 1, a plurality of memory transistors MT are arranged three-dimensionally along the X, Y, and Z directions. - Next, a method for manufacturing a semiconductor memory device according to the embodiment is described.
-
FIGS. 3A to 13B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment. Here, the figures labeled with “A” are plan views. The figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”. - First, as shown in
FIGS. 3A and 3B , asilicon substrate 10 is prepared. Next, in the peripheral circuit region (not shown) of thissilicon substrate 10, transistors and wirings, for instance, constituting driver circuits are formed. - Next, by e.g. the CVD (chemical vapor deposition) process, an insulating
film 11 made of silicon oxide is formed on thesilicon substrate 10. Then, aconductive film 12 made of impurity-containing polysilicon is formed on the insulatingfilm 11. - Next, as shown in
FIGS. 4A and 4B , a resistfilm 41 is formed on theconductive film 12. Next, by the lithography technique, a plurality of strip-shapedopenings 41 a with the longitudinal direction aligned with the X direction are formed in the resistfilm 41. Theopenings 41 a are arranged in a matrix configuration along the X and Y directions. - Next, as shown in
FIGS. 5A and 5B , the resist film 41 (seeFIGS. 4A and 4B ) is used as a mask to perform dry etching. Thus, arecess 12 a shaped like a rectangular solid with the longitudinal direction aligned with the X direction is formed in the upper portion of theconductive film 12. Subsequently, ashing is performed to remove the resistfilm 41. - Next, by the CVD process, silicon nitride is deposited on the entire surface. Next, dry etching is performed to remove the portion of the silicon nitride deposited on the upper surface of the
conductive film 12. Thus, asacrificial material 42 made of silicon nitride is buried in therecess 12 a. - Next, as shown in
FIGS. 6A and 6B , insulatingfilms 14 made of silicon oxide andconductive films 15 made of polysilicon are alternately formed on theconductive film 12 and thesacrificial material 42. Thus, a stacked body ML is formed. Next, on the stacked body ML, an insulatingfilm 16 made of silicon oxide, aconductive film 17 made of polysilicon, and an insulatingfilm 18 a made of silicon oxide are deposited in this order. Next, a resistfilm 43 is formed on the insulatingfilm 18 a. Next, by the lithography technique, a plurality of groove-shapedopenings 43 a extending in the Y direction are formed in the resistfilm 43. - Next, as shown in
FIGS. 7A and 7B , the resist film 43 (seeFIGS. 6A and 6B ) is used as a mask to perform dry etching to selectively remove the insulatingfilm 18 a, theconductive film 17, the insulatingfilm 16, and the stacked body ML. At this time, the lowermost insulatingfilm 14 of the stacked body ML is left unetched. Thus, atrench 21 extending in the Y direction is formed in the portion of the stacked body ML except the lowermost insulatingfilm 14, the insulatingfilm 16, theconductive film 17, and the insulatingfilm 18 a. Thetrench 21 is formed immediately below the opening 43 a at a position linking the immediately overlying regions of the X-direction central portions of thesacrificial materials 42. Subsequently, ashing is performed to remove the resistfilm 43. - Next, as shown in
FIGS. 8A and 8B , silicon nitride is deposited by the CVD process. Next, dry etching is performed to remove the portion of the silicon nitride deposited on the insulatingfilm 18 a. Thus, an insulatingmember 29 made of silicon nitride is buried in thetrench 21. Next, silicon oxide is deposited by the CVD process to form an insulatingfilm 18 b on the insulatingfilm 18 a. The insulatingfilms film 18. - Next, as shown in
FIGS. 9A and 9B , a resistfilm 44 is formed on the insulatingfilm 18. Next, by the lithography technique, an opening 44 a extending in the Y direction is formed in the resistfilm 44. The opening 44 a is formed at a position linking the immediately overlying regions of both X-direction end portions of thesacrificial materials 42. - Next, as shown in
FIGS. 10A and 10B , the resist film 44 (seeFIGS. 9A and 9B ) is used as a mask to perform dry etching to selectively remove the insulatingfilm 18, theconductive film 17, the insulatingfilm 16, and the stacked body ML. Thus, atrench 20 extending in the Y direction is formed immediately below the opening 44 a. Thetrench 20 is shaped like a generally rectangular solid. In thetrench 20, the length l is made longer than the width w, and the depth d is made longer than the length l. That is, these dimensions are set to satisfy d>l>w. At the bottom surface of thetrench 20, theconductive films 12 and thesacrificial materials 42 are exposed and alternately arranged along the Y direction. Thus, theconductive film 17 is divided by thetrenches conductive film 15 is divided by thetrenches film 44. - Next, by a self-organization technique, a cylindrical (circular columnar) hole is formed in the
trench 20. A method for this is specifically described below. - First, as shown in
FIGS. 11A and 11B , as a block copolymer, a diblock copolymer is applied and buried in thetrench 20. The diblock copolymer is a polymer of two kinds of macromolecules which are phase-separated under an appropriate condition. Various materials can be used as the diblock copolymer. In the embodiment, a polymer of polystyrene (PS) and polyethylene oxide (PEO) is used (this polymer is hereinafter referred to as “PS-PEO polymer”). In the PS-PEO polymer, polystyrene (PS) groups and polyethylene oxide (PEO) groups are coupled in a straight chain. - Next, by e.g. heat treatment, the diblock copolymer is phase-separated. Thus, in the
trench 20, the PS-PEO polymer as the diblock copolymer is separated into ablock 46 a resulting from polystyrene (PS) groups and ablock 46 b resulting from polyethylene oxide (PEO) groups. Theblock 46 a is made of an organic material. Theblock 46 b is made of silicon oxide in which a small amount of organic residual material is left behind. That is, theblock 46 b is substantially made of an inorganic material. - The inner surface of the
trench 20 includes the insulatingfilms conductive films sacrificial material 42 made of silicon nitride. Thus, the inner surface of thetrench 20 is entirely hydrophilic. On the other hand, polyethylene oxide (PEO) is hydrophilic, whereas polystyrene (PS) is hydrophobic. That is, the diblock copolymer used in the embodiment is a copolymer having hydrophobic first molecules and hydrophilic second molecules. Hence, the interfacial energy between the hydrophilic inner surface of thetrench 20 and hydrophilic polyethylene oxide (PEO) is lower than the interfacial energy between the hydrophilic inner surface of thetrench 20 and hydrophobic polystyrene (PS). Thus, in each PS-PEO polymer, the polyethylene oxide (PEO) group is coupled to the inner surface of thetrench 20, whereas the polystyrene (PS) group is located at a position spaced from the inner surface of thetrench 20 by the length of the PEO group. As a result, theblock 46 b resulting from polyethylene oxide (PEO) groups is aggregated along the inner surface of thetrench 20. On the other hand, theblock 46 a resulting from polystyrene (PS) groups is aggregated at a position spaced by a fixed distance from the inner surface of thetrench 20. - Here, the shape and position of the
blocks trench 20, the total molecular weight of the PS-PEO polymer, the ratio between PEO groups and PS groups, and the heat treatment condition for phase separation. For instance, the shape of theblock 46 a can be controlled by selecting the ratio between PS groups and PEO groups in the PS-PEO polymer. For instance, the ratio between PS groups and PEO groups being approximately 1:1 produces a lamellar structure in which theblocks 46 a and theblocks 46 b are alternately arranged. If the ratio of PS groups is lower, theblock 46 a is shaped like a cylinder (circular column). If the ratio of PS groups is still lower, theblock 46 a is shaped like a ball. Furthermore, the formation position of theblock 46 a can be controlled by selecting e.g. the size and shape of thetrench 20. - Thus, by appropriately selecting these parameters, the
blocks 46 a can be aggregated like a cylinder extending in the Z direction immediately above both X-direction end portions of thesacrificial material 42. For instance, theblock 46 a can be shaped like a cylinder by making the ratio of PS groups lower than the ratio of PEO groups. Here, the diameter of thecylindrical block 46 a has a fixed value resulting from the molecular structure of the PS-PEO polymer, such as the length of the PS group. Furthermore, in the vertical direction (Z direction), the diameter of theblock 46 a is made uniform. By adjusting the molecular structure of the PS-PEO polymer, the diameter of theblock 46 a can be controlled to an arbitrary value. In onetrench 20, a plurality ofblocks 46 a are formed, and theblock 46 b is packed in thetrench 20 so as to enclose this plurality ofblocks 46 a. Hence, theblocks 46 a are not in contact with the inner surface of thetrench 20. - By way of example, the depth d of the
trench 20 is 300 nm (nanometers), the length l is 70 nm, and the width w is 20 nm. In this case, the total molecular weight of the PS-PEO polymer is set to approximately 10000, the ratio between PS groups and PEO groups is set to approximately 1:2, the temperature of heat treatment for phase separation is set to approximately 150-250° C., and the time of this heat treatment is set to several minutes. Then, theblock 46 a resulting from PS groups can be shaped like a cylinder with a diameter of approximately 10 nm. - Next, as shown in
FIGS. 12A and 12B , by wet etching with hydrofluoric acid or dry etching, theblock 46 b resulting from polyethylene oxide (PEO) is etched back to expose the upper surface of theblock 46 a (seeFIGS. 11A and 11B ). At this time, the exposed surface of the insulatingfilm 18 made of silicon oxide is etched to some extent. - Next, by dry etching with an etching gas containing oxygen or hydrogen and not containing halogens, polystyrene (PS) is selectively etched relative to polyethylene oxide (PEO) and silicon oxide to remove the
block 46 a (seeFIGS. 12A and 12B ). Thus, after theblock 46 a is removed, ahole 47 is formed. Thehole 47 extends in the Z direction. The upper surface of thehole 47 is opened. At the bottom surface of thehole 47, theblock 46 b is left behind. Thehole 47 is formed for eachblock 46 a. Hence, a plurality ofholes 47 are formed in eachtrench 20. Here, the shape of thehole 47 is determined by the shape of theblock 46 a. Hence, thehole 47 is shaped like a cylinder (circular column) with a vertical inner surface and a uniform diameter. - Next, as shown in
FIGS. 13A and 13B , by wet etching with hydrofluoric acid, theblock 46 b is etched through thehole 47. Thus, the side surface of eachhole 47 is set back and partly reaches the inner surface of thetrench 20, and the bottom surface of thehole 47 is lowered and reaches the bottom surface of thetrench 20. This increases the diameter and depth of thehole 47, and changes the shape of thehole 47. That is, as viewed in the Z direction, the shape of thehole 47 includes a pair of circular arcs made of the side surface of theblock 46 b, and a pair of line segments made of the side surfaces of thetrench 20. Furthermore, the bottom surface of thehole 47 includes thesacrificial material 42. - Next, by wet etching with high temperature phosphoric acid, the
sacrificial material 42 made of silicon nitride is removed through thehole 47. Thus, the inside of therecess 12 a of theconductive film 12 is made hollow to form aU-shaped hole 48 made of therecess 12 a and theholes 47. EachU-shaped hole 48 includes onerecess 12 a and twoholes 47 communicating with both end portions of therecess 12 a. - Next, as shown in
FIGS. 1A and 1B and 2 , by the CVD process, ablock layer 33 made of silicon oxide, acharge accumulation layer 32 made of silicon nitride, and atunnel layer 31 made of silicon oxide are deposited in this order on the inner surface of theU-shaped hole 48. The stacked film made of theblock layer 33, thecharge accumulation layer 32, and thetunnel layer 31 constitutes amemory film 30. Next, polysilicon is deposited on the entire surface. Next, dry etching is performed to remove the portion of the deposited polysilicon located on the upper surface of the insulatingfilm 18. Thus, polysilicon is buried in theU-shaped hole 48 to form acoupling member 26 in therecess 12 a and a silicon pillar SP in thehole 47. Here, theblock 46 b constitutes an insulatingmember 28. Next, on the insulatingfilm 18, an upper wiring structure including source lines (not shown) and bit lines (not shown) is formed. Thus, thesemiconductor memory device 1 according to the embodiment is manufactured. - Next, the operation and effect of the embodiment are described.
- In the embodiment, in manufacturing the
semiconductor memory device 1, atrench 20 is formed in the stacked body ML. A diblock copolymer is buried in thetrench 20 and phase-separated to form acylindrical block 46 a and ablock 46 b surrounding theblock 46 a in thetrench 20. Then, ahole 47 is formed by removing only theblock 46 a. Amemory film 30 is formed on the inner surface of thehole 47, and a silicon pillar SP is formed inside thehole 47. Thus, memory transistors MT are formed. - Here, the shape of the
block 46 a is determined by the molecular structure of the diblock copolymer. Thus, the diameter of theblock 46 a is made uniform throughout the vertical direction. Hence, the diameter of thehole 47 is also made uniform throughout the vertical direction. That is, the taper angle of the side surface of thehole 47 is made nearly equal to 90°. Thus, throughout the vertical direction, the diameter of the silicon pillar SP is made uniform, and the curvature of thememory film 30 is also made uniform. As a result, even if the aspect ratio of thehole 47 is increased, the characteristics are made uniform between the memory transistor MT formed in the upper end portion of thehole 47 and the memory transistor MT formed in the lower end portion of thehole 47. Furthermore, in the embodiment, theholes 47 are formed by the self-organization technique. Hence, theholes 47 have high shape stability. This also contributes to the uniform characteristics of memory transistors MT. - The shape of the
blocks block 46 a is shaped like a cylinder. Furthermore, the phase separation of the diblock copolymer is affected by the inner surface of thetrench 20. Hence, the formation position of theblock 46 a depends on the shape of thetrench 20. In the embodiment, thetrench 20 is shaped like a generally rectangular solid, with the depth d of thetrench 20 made larger than the length l and the width w, and the length l made larger than the width w. That is, these dimensions are set to satisfy d>l>w. Thus, the phase separation of the diblock copolymer buried in thetrench 20 is made less likely to be affected by the bottom surface of thetrench 20, and provided with no structure in the vertical direction (Z direction). As a result, thecylindrical block 46 a extends in the vertical direction. Furthermore, because the length l of thetrench 20 is made longer than the width w, theblocks 46 a are arranged in a line along the longitudinal direction of the trench 20 (Y direction). Moreover, theblock 46 a can be located immediately above thesacrificial material 42 by appropriately selecting the relative position of thetrench 20 with respect to therecess 12 a. - Furthermore, in the
semiconductor memory device 1 according to the embodiment, by formingtrenches 20 in the stacked body ML, theconductive film 15 is divided into a plurality of control gate electrodes CG. Then, ahole 47 is formed in part of thetrench 20, amemory film 30 is formed on the inner surface of thehole 47, and a silicon pillar SP is provided on thememory film 30. Thus, thememory film 30 is located between the silicon pillar SP and the control gate electrode CG (conductive film 15) to constitute a memory transistor MT. As a result, two memory transistors MT are located at each intersection between one silicon pillar SP and oneconductive film 15, enabling storage of at least two bits of information. Furthermore, these two memory transistors MT share the silicon pillar SP. Hence, the packing density can be made higher than that in the case of providing a silicon pillar SP for each memory transistor MT. - Moreover, in the
semiconductor memory device 1 according to the embodiment, as viewed in the stacking direction (Z direction), the outer edge of the silicon pillar SP includes a pair of circular arcs and a pair of line segments. Thus, theregion 25 of the side surface of the silicon pillar SP opposed to the inner surface of thetrench 20 constitutes a plane parallel to the side surface of thetrench 20. Hence, in each memory transistor MT, the silicon pillar SP and the control gate electrode CG have a positional relationship of parallel plates. Thus, the electric field is made less likely to concentrate on one location. Furthermore, also in thememory film 30, the electric field is applied uniformly in the film thickness direction. This stabilizes the operation of the memory transistor MT. - Next, a comparative example of the embodiment is described.
-
FIGS. 14A to 15B are process views illustrating a method for manufacturing a semiconductor memory device according to the comparative example. Here, the figures labeled with “A” are plan views. The figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”. -
FIGS. 16A and 16B are sectional views illustrating a semiconductor memory device according to the comparative example.FIG. 16A shows a cross section parallel to the upper surface of the silicon substrate.FIG. 16B shows a cross section taken along line A-A′ shown inFIG. 16A , i.e., a cross section perpendicular to the upper surface of the silicon substrate. - First, the process shown in
FIGS. 3A to 8B is performed. - Next, as shown in
FIGS. 14A and 14B , a resistfilm 91 is formed on the insulatingfilm 18. Next, by using the lithography technique, an opening 91 a shaped like e.g. a circle is formed immediately above each of both X-direction end portions of thesacrificial material 42 in the resistfilm 91. Thus, a hole pattern is formed in the resistfilm 91. - Next, as shown in
FIGS. 15A and 15B , the resist film 91 (seeFIGS. 14A and 14B ) is used as a mask to perform dry etching to selectively remove the insulatingfilm 18, theconductive film 17, the insulatingfilm 16, and the stacked body ML. As a result, ahole 92 reaching the sacrificial material 42 (seeFIGS. 14A and 14B ) is formed immediately below the opening 91 a. In this etching step, the insulatingfilms hole 92 is inevitably inclined. Hence, thehole 92 is tapered downward. Subsequently, ashing is performed to remove the resistfilm 91. - Next, by wet etching with high temperature phosphoric acid, the sacrificial material 42 (see
FIGS. 14A and 14B ) is removed through thehole 92. Thus, twoholes 92 adjacent in the X direction are coupled through therecess 12 a of theconductive film 12 to form aU-shaped hole 93. - Next, as shown in
FIGS. 16A and 16B , like the above first embodiment, by the CVD process, ablock layer 33, acharge accumulation layer 32, and atunnel layer 31 are deposited on the inner surface of theU-shaped hole 93. Thus, amemory film 30 is formed. Next, polysilicon is buried in theU-shaped hole 93 to form a silicon pillar SP and acoupling member 26. Thus, the semiconductor memory device according to the comparative example is manufactured. - In the comparative example, in the step shown in
FIGS. 15A and 15B , holes 92 are formed by dry etching. However, in this case, the side surface of thehole 92 is inevitably inclined, and the diameter of thehole 92 decreases downward. One reason for this is the variation in the incident angle of ions used for dry etching. For instance, consider the case where the incident angle of ions is inclined 5° with respect to the vertical direction (Z direction). In this case, if the aspect ratio of thehole 92 exceeds 11.5 (=1/tan(5°)), no ions directly reach the bottom surface of thehole 92. Then, only the ions once reflected by impingement on the side surface of thehole 92 reach the bottom surface of thehole 92. Thus, in the subsequent etching, the number of ions directly reaching the bottom surface of thehole 92 decreases, and makes vertical processing difficult. - For instance, the diameter of the opening 91 a of the resist
film 91 is set to 30 nm (nanometers), and consider the case of forming ahole 92 with a depth of 1 μm (micron). Then, the aspect ratio exceeds 30. In this case, for the above-mentioned reason, etching is made difficult, and thehole 92 is tapered downward. As a result, in the memory transistor MT formed in the lower portion of the stacked body ML, as compared with the memory transistor MT formed in the upper portion, the silicon pillar SP is made slimmer, and the curvature of thememory film 30 is made larger. This causes the amount of charge accumulated in the memory transistor MT to vary with the formation position. Hence, in the semiconductor memory device according to the comparative example, the characteristics of memory transistors MT are varied with the formation position. This degrades the overall characteristics of the semiconductor memory device. - In contrast, in the
semiconductor memory device 1 according to the above first embodiment, theholes 47 are formed by the self-organization technique. Hence, even if the aspect ratio of thehole 47 is increased, the diameter can be made uniform. As a result, the characteristics of memory transistors MT can be made uniform. This improves the overall characteristics of thesemiconductor memory device 1. - Here, the variation in the taper angle of the hole required in the semiconductor memory device having the three-dimensional structure as described above can be calculated as follows. To limit the variation in the surface area of the
charge accumulation layer 32 to 10% or less, the variation in the diameter of the hole also needs to be limited to 10% or less. Hence, for instance, in the case where the diameter of the upper end portion of the hole is 30 nm, the diameter of the lower end portion needs to be set to 27 nm or more. With the depth of the hole set to 1 μm, the taper angle of the side surface of the hole needs to be 89.9° (=tan−1(1000/1.5)) or more. That is, the side surface of the hole needs to be nearly vertical. Such processing is very difficult to realize by etching, but easy by using the self-organization technique. - In the comparative example, the
hole 92 is formed by lithography and dry etching. Hence, the shape of thehole 92 as viewed in the Z direction may be deviated from a perfect circle. If the shape of thehole 92 is deviated from a perfect circle, a portion having a high curvature may occur at the inner surface of thehole 92 and the outer surface of thememory film 30 and the silicon pillar SP. The electric field may concentrate on this portion. This increases the operational variation at the time of writing and reading data. Furthermore, because thememory film 30 is formed cylindrically, the electric field applied to theinner tunnel layer 31 is made stronger than that applied to theouter block layer 33. - In contrast, in the first embodiment, the shape of the
hole 47 is determined by the molecular structure of the diblock copolymer, and hence made uniform at the molecular level. This suppresses the operational variation at the writing/reading time. Furthermore, the portion of the memory transistor MT subjected to the electric field has a planar structure. Hence, the electric field is less likely to concentrate on this portion. - Furthermore, in the comparative example, the trench 20 (see
FIGS. 1A and 1B ) is not formed. Hence, theconductive film 15 is not divided by thetrench 20 to both sides of the silicon pillar SP. Thus, only one memory transistor MT is formed at each intersection between one silicon pillar SP and oneconductive film 15. As a result, the information storage density is halved as compared with the above first embodiment. - Next, a second embodiment is described.
-
FIGS. 17A and 17B are sectional views illustrating a semiconductor memory device according to the embodiment.FIG. 17A shows a cross section parallel to the upper surface of the silicon substrate.FIG. 17B shows a cross section taken along line A-A′ shown inFIG. 17A , i.e., a cross section perpendicular to the upper surface of the silicon substrate. - As shown in
FIGS. 17A and 17B , thesemiconductor memory device 2 according to the embodiment is different from the semiconductor memory device 1 (seeFIGS. 1A and 1B ) according to the above first embodiment in that aguide 51 projected toward the inside of thetrench 20 is formed at both side surfaces of thetrench 20. Theguide 51 is formed from the stacked body ML, the insulatingfilm 16, theconductive film 17, and the insulatingfilm 18 left behind. Theguides 51 are periodically arranged along the Y direction. The phase of the arrangement is equal at both side surfaces of thetrench 20. Thus, the portion of thetrench 20 provided with theguide 51 constitutes anarrow width portion 52 a having a relatively narrow width. On the other hand, the portion of thetrench 20 not provided with theguide 51 constitutes awide width portion 52 b having a relatively wide width. In eachtrench 20, thenarrow width portions 52 a and thewide width portions 52 b are alternately arranged along the Y direction. The silicon pillar SP and thememory film 30 are located in thewide width portion 52 b. - Next, a method for manufacturing a semiconductor memory device according to the embodiment is described.
-
FIGS. 18A and 18B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment.FIG. 18A is a plan view.FIG. 18B is a sectional view taken along line A-A′ shown inFIG. 18A . - First, the process shown in
FIGS. 3A to 10B is performed. Here, as shown inFIGS. 18A and 18B , the pattern of the resistfilm 44 is adjusted so that aguide 51 projected toward the inside of thetrench 20 is formed at both side surfaces of thetrench 20. Theguides 51 are periodically arranged along the longitudinal direction of the trench 20 (Y direction). Furthermore, the phase of the arrangement is matched between both side surfaces of thetrench 20. Thus, in thetrench 20, along its longitudinal direction (Y direction),narrow width portions 52 a where theguides 51 are formed on both sides and the width is relatively narrow, andwide width portions 52 b where theguides 51 are not formed and the width is relatively wide, are alternately arranged. - Next, like the above first embodiment, a diblock copolymer is buried inside the
trench 20 and phase-separated. At this time, thehydrophilic block 46 b is formed along the inner surface of thetrench 20 including theguide 51, whereas thehydrophobic block 46 a is formed at a position spaced by a prescribed distance from the inner surface of thetrench 20 including theguide 51. Thus, theblock 46 a is formed like a cylinder extending in the Z direction in the central portion of thewide width portion 52 b. Subsequently, like the above first embodiment, the process shown inFIGS. 12A to 13B is performed. Thus, the silicon pillar SP and thememory film 30 are located in thewide width portion 52 b of thetrench 20. - According to the embodiment, the
guide 51 is provided at the inner surface of thetrench 20. This can reliably control the shape and position of theblock 46 a. Thus, the shape and position of the silicon pillar SP and thememory film 30 can be reliably controlled. The configuration, the manufacturing method, and the operation and effect of the embodiment other than the foregoing are similar to those of the above first embodiment. - Next, a third embodiment is described.
-
FIGS. 19A and 19B are sectional views illustrating a semiconductor memory device according to the embodiment.FIG. 19A shows a cross section parallel to the upper surface of the silicon substrate.FIG. 19B shows a cross section taken along line A-A′ shown inFIG. 19A , i.e., a cross section perpendicular to the upper surface of the silicon substrate. - As shown in
FIGS. 19A and 19B , thesemiconductor memory device 3 according to the embodiment is different from the semiconductor memory device 1 (seeFIGS. 1A and 1B ) according to the above first embodiment in that as viewed in the Z direction, the silicon pillar SP is shaped like a rectangle, and thememory film 30 is shaped like a frame. Between thememory films 30 in thetrench 20, an insulatingmember 28 including e.g. silicon oxide is provided. - Next, a method for manufacturing a semiconductor memory device according to the embodiment is described.
-
FIGS. 20A to 21B are process views illustrating the method for manufacturing a semiconductor memory device according to the embodiment. The figures labeled with “A” are plan views. The figures labeled with “B” are sectional views taken along line A-A′ shown in the corresponding figures labeled with “A”. - First, the process shown in
FIGS. 3A to 10B is performed. - Next, as shown in
FIGS. 20A and 20B , as a block copolymer, a diblock copolymer is applied and buried in thetrench 20. As the diblock copolymer, for instance, a PS-PEO polymer is used. In the embodiment, the ratio between PS groups and PEO groups is set to approximately 1:1. - Next, by heat treatment, the PS-PEO polymer is phase-separated. Here, the phase structure after separation is a lamellar structure in which blocks 46 a resulting from PS groups and blocks 46 b resulting from PEO groups are alternately arranged along the longitudinal direction of the trench 20 (Y direction). The
blocks blocks blocks blocks trench 20. The upper surface of theblocks - Next, as shown in
FIGS. 21A and 21B , by dry etching with an etching gas containing oxygen or hydrogen and not containing halogens, theblock 46 a is removed. Thus, after theblock 46 a is removed, ahole 61 is formed. Thehole 61 extends in the Z direction. The upper surface of thehole 61 is opened. At the bottom surface of thehole 61, thesacrificial material 42 is exposed. At part of the side surface of thehole 61, the side surface of thetrench 20 is exposed. The shape of thehole 61 is determined by the shape of theblock 46 a. Hence, thehole 61 is shaped like a rectangular column with a vertical inner surface and a uniform width. - Next, by wet etching with high temperature phosphoric acid, the
sacrificial material 42 is removed through thehole 61. Thus, the inside of therecess 12 a of theconductive film 12 is made hollow to form aU-shaped hole 62 made of therecess 12 a and theholes 61. EachU-shaped hole 62 includes onerecess 12 a and twoholes 61 communicating with both end portions of therecess 12 a. - Next, as shown in
FIGS. 19A and 19B , by the CVD process, a block layer 33 (seeFIGS. 2A and 2B ), a charge accumulation layer 32 (seeFIGS. 2A and 2B ), and a tunnel layer 31 (seeFIGS. 2A and 2B ) are deposited in this order on the inner surface of theU-shaped hole 62 to form amemory film 30. As viewed in the Z direction, thememory film 30 is shaped like a frame. Next, polysilicon is buried inside theU-shaped hole 62 to form acoupling member 26 in therecess 12 a and a silicon pillar SP in thehole 61. As viewed in the Z direction, the silicon pillar SP is shaped like a rectangle. Theblock 46 b left behind constitutes an insulatingmember 28. Next, on the insulatingfilm 18, an upper structure including source lines (not shown) and bit lines (not shown) is formed. Thus, thesemiconductor memory device 3 according to the embodiment is manufactured. - According to the embodiment, the block structure of the phase-separated PS-PEO polymer is set to a lamellar structure. Thus, the
block 46 a can be formed in contact with the side surface and bottom surface of thetrench 20, with the upper surface of theblock 46 a exposed. Hence, thehole 61 can be formed simply by removing theblock 46 a. This eliminates the need to etch theblock 46 b before and after the step of removing theblock 46 a. As a result, the process for manufacturing thesemiconductor memory device 3 can be simplified. - The configuration, the manufacturing method, and the operation and effect of the embodiment other than the foregoing are similar to those of the above first embodiment.
- In the examples illustrated in the above embodiments, a copolymer of polystyrene (PS) and polyethylene oxide (PEO) is used as a diblock copolymer. However, the invention is not limited thereto. The diblock copolymer can be made of any material as long as it is separated into two or more kinds of blocks by phase separation, at least one kind of blocks have a shape extending in the Z direction with uniform thickness, and this block extending in the Z direction can be removed by a suitable method. Here, if the block left behind is insulative and stable as a device material, this block can be directly used as an insulating member for separation between the memory films. In view of these points, preferably, the block to be removed is made of an organic material, and the block to be left behind is made of an inorganic material. However, if the block to be left behind is unsuitable as a device material, this block can be replaced by another insulating material after forming the memory film and the silicon pillar.
- The embodiments described above can realize a semiconductor memory device with uniform characteristics of memory transistors, and a method for manufacturing the same.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
Claims (21)
1. (canceled)
2. A semiconductor memory device, comprising:
a stacked body including a plurality of insulating portions and a plurality of conductive films, each of the insulating portions and each of the conductive films being alternately stacked in a stacking direction above a substrate, trenches extending in the stacked body in a first direction intersecting with the stacking direction and dividing each of the conductive films in a second direction intersecting with the stacking direction and the first direction;
an underlying conductive layer provided between the substrate and the stacked body in the stacking direction;
a plurality of semiconductor pillars provided in the trenches and extending in the stacking direction, lower portions of a first semiconductor pillar and a second semiconductor pillar of the semiconductor pillars being coupled to the underlying conductive layer;
a plurality of insulating layers provided around the semiconductor pillars; and
an insulating member provided between the insulating layers around the semiconductor pillars in the trenches, the semiconductor pillars and the insulating member being alternately arranged in the first direction in the trenches,
a pair of memory transistors being provided so as to correspond to regions of each of the semiconductor pillars, the regions facing a pair of side surfaces of one of the trenches, the side surfaces extending along the first direction, the pair of memory transistors being disposed at an intersection between one of the semiconductor pillars and one of the conductive films, the pair of memory transistors being arranged in the second direction.
3. The device according to claim 2 , wherein each of the regions includes a plane parallel to the side surfaces of one of the trenches.
4. The device according to claim 2 , wherein each of the insulating layers includes a tunnel layer.
5. The device according to claim 2 , wherein each of the trenches has a first portion and second portions, a first dividing distance between divided parts of one of the conductive films at the first portion is shorter than a second dividing distance between the divided parts at the second portions, and the semiconductor pillars are located in the second portions.
6. The device according to claim 2 , wherein the trenches are arranged in the second direction, and the first semiconductor pillar is provided in a first one of the trenches and the second semiconductor pillar is provided in a second one of the trenches.
7. The device according to claim 2 , wherein the underlying conductive layer includes polysilicon.
8. A semiconductor memory device, comprising:
a stacked body including a plurality of conductive films stacked and insulated from each other in a stacking direction;
a plurality of first trenches extending in the stacked body in a first direction intersecting with the stacking direction and dividing each of the conductive films in a second direction intersecting with the stacking direction and the first direction;
a second trench extending in the stacking direction between the first trenches and being filled with an insulator;
a plurality of pillars provided in each of the first trenches and arranged spaced from each other in the first direction, each of the pillars including:
a silicon channel extending in the stacking direction, and
an insulating layer provided on a first direction side and on a second direction side of the silicon channel; and
an insulating member provided between the pillars in the first trenches, the pillars and the insulating member being alternately arranged in the first direction in each of the first trenches, wherein
a pair of memory transistors are provided so as to correspond to regions of each of the pillars, the regions facing to one of the conductive films at both sides of the second direction.
9. The device according to claim 8 , wherein regions of side surfaces of the pillars include planes parallel to side surfaces of the first trenches, the side surfaces of the pillars facing to the side surfaces of the first trenches.
10. The device according to claim 8 , wherein neither any silicon channel nor any semiconductor pillar is provided in the second trench.
11. The device according to claim 8 , wherein the insulating layer includes a tunnel layer.
12. The device according to claim 8 , wherein the insulating member includes a portion having a length in the second direction shorter than a dividing distance in the second direction between divided parts of one of the conductive films via one of the first trenches at places where the pillars are located.
13. The device according to claim 8 , wherein each of the pillars includes an outer edge consisting of a pair of first sides including circular arcs and a pair of second sides of line segments as viewed in the stacking direction.
14. The device according to claim 8 , further comprising:
a charge accumulation layer provided between the insulating layer and one of the conductive films; and
a block layer provided between the charge accumulation layer and the one of the conductive films,
the insulating layer being a tunnel layer.
15. The device according to claim 14 , wherein
the tunnel layer includes silicon and oxygen,
the charge accumulation layer includes silicon, and
the block layer includes silicon and oxygen.
16. A method for manufacturing a semiconductor memory device according to claim 2 , the method comprising:
forming the stacked body above the underlying conductive layer by alternately stacking a plurality of first films and a plurality of second films;
forming the trenches in the stacked body, the trenches extending in a first direction and dividing the stacked body in a second direction, the second direction intersecting with the first direction and a stacking direction of the first films and the second films;
burying the insulating member in the trenches;
forming a plurality of holes by removing selectively the insulating member, the holes being spaced from each other in the first direction in each of the trenches; and
forming the plurality of semiconductor pillars extending in the stacking direction in the holes via the insulating layers.
17. The method according to claim 16 , further comprising setting back side surfaces of the holes by etching after forming the holes.
18. The method according to claim 16 , wherein one of the semiconductor pillars is formed in one of the holes via a charge accumulation layer.
19. The method according to claim 16 , wherein one of the semiconductor pillars is formed in one of the holes via a block layer, a charge accumulation layer, and a tunnel layer, each of the insulating layers being a tunnel layer.
20. The method according to claim 16 , wherein
a length of each of the trenches in the first direction is made longer than a length of each of the trenches in the second direction.
21. The method according to claim 16 , further comprising dividing the stacked body in the second direction at a position differing from the trenches.
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US17/669,875 US20220165753A1 (en) | 2011-06-22 | 2022-02-11 | Semiconductor memory device and method for manufacturing same |
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JP2011138387A JP5603834B2 (en) | 2011-06-22 | 2011-06-22 | Semiconductor memory device and manufacturing method thereof |
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US13/344,757 US9385137B2 (en) | 2011-06-22 | 2012-01-06 | Semiconductor memory device and method for manufacturing same |
US14/981,526 US9728550B2 (en) | 2011-06-22 | 2015-12-28 | Semiconductor memory device and method for manufacturing same |
US15/635,398 US20170301691A1 (en) | 2011-06-22 | 2017-06-28 | Semiconductor memory device and method for manufacturing same |
US16/809,735 US11289506B2 (en) | 2011-06-22 | 2020-03-05 | Semiconductor memory device and method for manufacturing same |
US17/669,875 US20220165753A1 (en) | 2011-06-22 | 2022-02-11 | Semiconductor memory device and method for manufacturing same |
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US20160079266A1 (en) * | 2014-09-11 | 2016-03-17 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
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JP2019220534A (en) * | 2018-06-18 | 2019-12-26 | キオクシア株式会社 | Semiconductor storage device and manufacturing method thereof |
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US9385137B2 (en) | 2016-07-05 |
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US20170301691A1 (en) | 2017-10-19 |
US9728550B2 (en) | 2017-08-08 |
JP2013008712A (en) | 2013-01-10 |
US11289506B2 (en) | 2022-03-29 |
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