TWI631682B - Semiconductor structure and method for manufacturing the same - Google Patents

Semiconductor structure and method for manufacturing the same Download PDF

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TWI631682B
TWI631682B TW106128660A TW106128660A TWI631682B TW I631682 B TWI631682 B TW I631682B TW 106128660 A TW106128660 A TW 106128660A TW 106128660 A TW106128660 A TW 106128660A TW I631682 B TWI631682 B TW I631682B
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Taiwan
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layer
conductive
layers
stack
conductive layer
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TW106128660A
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Chinese (zh)
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TW201913943A (en
Inventor
吳冠緯
劉注雍
張耀文
楊怡箴
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旺宏電子股份有限公司
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Abstract

A semiconductor structure includes a substrate, a stack, a hole, and an active structure. The stack is placed on the substrate. The stack is composed of a plurality of conductive layers and a plurality of insulating layers alternating with each other. The conductive layer comprises an ith conductive layer and a j-th conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness t i , and the j-th conductive layer has a thickness t j , where t j is greater than t i . The holes pass through the stack. The holes have diameters D i and diameters D j corresponding to the i-th conductive layer and the j-th conductive layer, respectively, and D j is greater than D i . The active structure is placed in the hole. The active structure includes a channel layer. The channel layer is disposed along one of the sidewalls of the hole and is isolated from the stacked conductive layers.

Description

Semiconductor structure and method of manufacturing same
The present disclosure relates to a semiconductor structure and a method of fabricating the same. The present disclosure relates in particular to a semiconductor structure including a compensatory stack structure and a method of fabricating the same.
Three-dimensional (3D) semiconductor structures have been developed for reasons of volume reduction, weight reduction, increased power density, and improved portability. In a typical process of some three-dimensional semiconductor structures, a stack comprising a plurality of layers can be formed on a substrate and then one or more holes and/or trenches are formed through the stack. Due to process limitations, the holes and/or trenches may have sloping sidewalls such that the size and area gradually change along a vertical direction of the holes and/or trenches. This may further lead to deviations in the characteristics of some devices, especially in terms of electrical properties. As the number of layers in the stack increases, this deviation may become a problem that will affect device performance and operation.
The present disclosure is directed to the provision of a compensatory stack structure that compensates for different sizes and areas along a vertical direction of the holes and/or trenches. Impact.
According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, a hole, and an active structure. The stack is placed on the substrate. The stack is composed of a plurality of conductive layers and a plurality of insulating layers alternating with each other. The conductive layer comprises an ith conductive layer and a j-th conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness t i , and the j-th conductive layer has a thickness t j , t j Greater than t i . The holes pass through the stack. The holes have diameters D i and diameters D j corresponding to the i-th conductive layer and the j-th conductive layer, respectively, and D j is greater than D i . The active structure is placed in the hole. The active structure includes a channel layer. The channel layer is disposed along one of the sidewalls of the hole and is isolated from the stacked conductive layers.
In accordance with some embodiments, a method of fabricating a semiconductor structure is provided. This manufacturing method includes the following steps. First, a stack is formed on a substrate. The stack is composed of a plurality of sacrificial layers and a plurality of insulating layers alternating with each other. The sacrificial layer includes an ith sacrificial layer and a j-th sacrificial layer formed over the ith sacrificial layer, the ith sacrificial layer has a thickness t i , and the j-th sacrificial layer has a thickness t j , t j Greater than t i . A hole is formed through the stack. The holes have diameters D i and diameters D j corresponding to the i-th sacrificial layer and the j-th sacrificial layer, respectively, and D j is greater than D i . An active structure is formed in the hole. The active structure includes a channel layer. The channel layer is formed along one of the sidewalls of the hole and is separated from the stacked sacrificial layer.
In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
100, 200‧‧‧ semiconductor structure
102‧‧‧Substrate
104, 204‧‧‧ Stacking
106, 106 (0), 106 (1), 106 (2), 106 (3), ..., 106 (i), ..., 106 (j), ..., 106 (n-2) , 106(n-1), 206(0), 206(1), 206(2), 206(3), ..., 206(i), ..., 206(j), ..., 206(n-2), 206(n-1)‧‧‧ conductive layer
108‧‧‧Insulation
110‧‧‧ Coverage
112‧‧‧ hole
114‧‧‧Active structure
116‧‧‧Channel layer
118‧‧‧ memory layer
120‧‧‧Insulation materials
122‧‧‧Conductive components
304‧‧‧Stacking
306(0), 306(1), 306(2), 306(3), ..., 306(i), ..., 306(j), ..., 306(n-2), 306 (n-1)‧‧‧ Sacrifice layer
352‧‧‧Ion implantation process
354‧‧‧ openings
356‧‧‧Metal materials
358‧‧‧High dielectric constant material
360‧‧‧Ion Implantation Process
362‧‧‧Conductive components
A i , A j ‧‧‧ conductive area
D i , D j ‧‧‧ diameter
G(1), G(2), ..., G( )‧‧‧Group
L 0 , L 1 , L 2 , L 3 , ..., L i , ..., L j , ..., L n-2 , L n-1 , L' 0 , L' 1 , L' 2 , L' 3 , ..., L' i , ..., L' j , ..., L' n-2 , L' n-1 ‧ ‧ channel length
t 0 , t 1 , t 2 , t 3 , ..., t i , ..., t j , ..., t n-2 , t n-1 , t' 0 , t' 1 , t' 2 , t' 3 , ..., t' i , ..., t' j , ..., t' n-2 , t' n-1 ‧ ‧ thickness
Θ‧‧‧ angle
FIG. 1 illustrates an exemplary semiconductor structure in accordance with an embodiment.
FIG. 2 illustrates another exemplary semiconductor structure in accordance with an embodiment.
Figure 3 shows the effect of the diameter of the hole and the length of the channel on the one hand.
4A-4B illustrate the effect of the diameter of the hole on the other hand.
5A to 5H illustrate an exemplary manufacturing method of a semiconductor structure according to an embodiment.
Various embodiments will be described in more detail below in conjunction with the drawings. The drawings are for illustrative purposes only and are not intended to be limiting. For the sake of clarity, the components may not be shown in actual scale. In addition, some elements and/or component symbols may be omitted from the drawings. In the present disclosure, when an element is described in the singular, it is also the case that the more than one element is included. It is contemplated that elements and features of one embodiment can be advantageously included in another embodiment without further elaboration.
Referring to FIG. 1, an exemplary semiconductor structure 100 is illustrated in accordance with an embodiment. The semiconductor structure 100 includes a substrate 102, a stack 104, a via 112, and an active structure 114. The stack 104 is disposed on the substrate 102. The stack 104 is composed of a plurality of conductive layers 106 (106(0)-106(n-1)) and a plurality of insulating layers 108 that alternate with each other. The conductive layer 106 includes an ith conductive layer 106(i) and a j-th conductive layer 106(j) disposed over the ith conductive layer 106(i), and the ith conductive layer 106(i) has a thickness t i , the j-th conductive layer 106(j) has a thickness t j , and t j is greater than t i . The holes 112 pass through the stack 104. The hole 112 has a diameter D i and a diameter D j corresponding to the i-th conductive layer 106 (i) and the j-th conductive layer 106 (j), respectively, and D j is greater than D i . The active structure 114 is disposed in the bore 112. The active structure 114 includes a channel layer 116. The channel layer 116 is disposed along one of the sidewalls of the hole 112 and is isolated from the conductive layer 106 of the stack 104.
In some embodiments, the stack 104 is disposed on the substrate 102, a cover layer 110 is further disposed on the stack 104, and the holes 112 pass through the cover layer 110 and the stack 104. In some embodiments, the angle θ between the substrate 102 and the sidewall of the aperture 112 is less than 90°, such as about 87°. The hole 112 may have a diameter that gradually becomes larger from the bottom to the top. In some embodiments, the diameter of the holes 112 is between 80 nm and 130 nm. For example, the aperture 112 can have a diameter of 80 nanometers at the bottom and a diameter of 130 nanometers at the top end. Correspondingly, the conductive layer 106 can have a thickness that gradually thickens from bottom to top, the details of which will be described in subsequent paragraphs. In some embodiments, conductive layer 106 can comprise a metallic material and a high dielectric constant material. According to some embodiments, the semiconductor structure 100 can be a memory structure. In such embodiments, the active structure 114 can further include a memory layer 118. A memory layer 118 is disposed between the channel layer 116 and the stack 104. Memory layer 118 can include a capture layer (not shown). More specifically, in some embodiments, the memory layer 118 may include a barrier layer (not shown), a capture layer (not shown), and a tunneling layer (s) formed sequentially from the sidewalls of the holes 112. Not shown) and may be formed by a single oxide-nitride-oxide (ONO) stack. A plurality of memory cell lines are defined by the intersection between the active structure 114 and the conductive layer 106 of the stack 104, which form part of a three dimensional memory cell array. In some embodiments, the active structure 114 can further include an insulating material 120. The insulating material 120 is filled into the remaining space of the hole 112. In some embodiments, a conductive element 122 can be disposed on the insulating material 120. In some embodiments, the conductive layers 106 are a plurality of word lines, and the active structure 114 is coupled to the one bit line by the conductive elements 122.
The configuration details of the conductive layer 106 will now be described. Specifically, the conductive layer 106 may be a 0th conductive layer 106(0) to an n-1th conductive layer 106(n-1) from bottom to top. The 0th conductive layer 106(0) to the n-1th conductive layer 106(n-1) have thicknesses t 0 to t n-1 , t 0 , respectively t 1 ... t n-2 t n-1 . Further, in addition, the first conductive layers 106 0 (0) to the n-1 layer, conductive layer 106 (n-1) can be provided to a channel length L 0 L n-1, L 0, respectively L 1 ... L n-2 L n-1 . According to some embodiments, the channel lengths L 0 to L n-1 are defined in a vertical direction, and throughout the disclosure, the vertical direction means substantially perpendicular to a direction of the substrate 102. Thus, each channel length (L 0 to L n-1 ) is substantially equal to the corresponding thickness (t 0 to t n-1 ). In some embodiments, the thickness t 0 to t n-1 , with the channel lengths L 0 to L n-1 , is between 20 nm and 60 nm. For example, the thickness t 0 and the channel length L 0 may be 20 nm, and the thickness t n-1 and the channel length L n-1 may be 60 nm.
As long as the compensation function can be provided such that the deviation falls within an acceptable range, the thickness t 0 to t n-1 , together with the channel lengths L 0 to L n-1 , can be configured in any suitable manner. In some embodiments, as shown in FIG. 1, each of the conductive layers 106 is thicker than the conductive layers 106 underlying the respective conductive layers 106. In other words, t 0 <t 1 <...<t n-2 <t n-1 . In other words, L 0 <L 1 <...<L n-2 <L n-1 .
In other embodiments, the conductive layer 106 is divided into a plurality of groups, and the conductive layers 106 in each group have the same thickness and are thicker than the conductive layers in the groups below the respective groups. 106. In such an embodiment, for at least one integer i from 0 to n-2, t i = t i+1 . In other words, for at least one integer i from 0 to n-2, L i = L i+1 .
Please refer to Figure 2, which shows a particular category of such embodiments. In this particular category, the conductive layer 106 is equally divided into a plurality of groups, and the conductive layers 106 in each group have the same thickness and are thicker than the conductive layers in the groups below the respective groups. Layer 106. For example, the conductive layer 106 can be equally divided Groups, that is, each group includes m conductive layers, t' 0 = t' 1 =...=t' m-1 <t' m ...<t' nm =...=t' N-2 = t' n-1 . In other words, the conductive layer 106 can be equally divided Groups, L' 0 = L' 1 =...=L' m-1 <...<L' nm =...=L' n-2 =L' n-1 . In the semiconductor structure 200 shown in FIG. 2, m is 2. In other words, in the stack 204, the conductive layers 206(0) to 206(n-1) are equally divided. Groups G(1) to G( ), group G(1) to G() Each of the conductive layers 206(0) to 206(n-1), t' 0 = t' 1 <t' 2 = t' 3 <... <t' n-2 =t' n-1 , L' 0 = L' 1 <L' 2 = L' 3 <... <L' n-2 = L' n-1 .
The stack according to the above embodiments, such as stack 104 or 204, is referred to as a compensating stack structure in the present disclosure. On the one hand, a larger hole diameter means a smaller electric field, resulting in lower programming/erasing speeds and poorer programming/erasing capabilities. This is reflected in the trend shown in Figure 3. In contrast, larger channel lengths result in larger electric fields, resulting in higher programming/erasing speeds and better programming/ Wipe the ability. Thus, in a semiconductor structure in accordance with an embodiment, the effect of a larger hole diameter on the programming/erasing operation of the device can be compensated for by a larger channel length, which is achieved by a thicker conductive layer. Thereby, better stability can be provided.
In addition, a larger hole diameter means that the conductive area of the corresponding conductive layer is smaller, thereby reducing conductance. For example, as shown in Figures 4A and 4B, the hole 1122 has a larger diameter Dj corresponding to the conductive layer 106(j). Accordingly, the conductive layer 106 (j) of the conductive area A j is less than the conductive layer 106 (i) of the conductive area A i. This is not conducive to the passage of current in the conductive layer disposed at a higher (higher position) as shown in Figs. 4A and 4B. For example, in the case where the conductive layer is a word line, degradation of the word line resistance may occur. However, this situation can be compensated by the thickness of the conductive layer. In other words, the effect of the larger hole diameter on the conductance of the conductive layer can be compensated for by the thicker conductive layer thickness.
Referring now to FIGS. 5A-5H, an exemplary method of fabricating a semiconductor structure in accordance with an embodiment is shown. FIGS. 5A-5H illustrate a semiconductor structure as shown in FIG. 1 by a process of replacing the sacrificial layer. However, other processes can also be used to form semiconductor structures in accordance with embodiments. For example, a stack of a plurality of conductive layers and a plurality of insulating layers alternated with each other can be directly formed without forming a sacrificial layer. Further, other semiconductor structures according to the embodiment, such as the semiconductor structure shown in FIG. 2, can also be formed.
As shown in FIG. 5A, a substrate 102 is provided. The substrate 102 can be a germanium substrate. The ion implantation process can be performed. A stack 304 is formed on the substrate 102, for example by a deposition process, and the stack 304 is composed of a plurality of sacrificial layers (306(0) to 306(n-1)) and a plurality of insulating layers 108 alternating with each other. The insulating layer 108 may be formed of an oxide having the same thickness. The sacrificial layers 306(0) through 306(n-1) may be formed of nitride. The sacrificial layers 306(0) to 306(n-1) include an ith sacrificial layer 306(i) and a jth sacrificial layer 306(j) formed over the ith sacrificial layer 306(i), i sacrificial layer 306 (i) having a thickness t i, j-th sacrificial layer 306 (j) having a thickness t j, t j is greater than t i. More specifically, the sacrificial layers 306(0) through 306(n-1) may have thicknesses t 0 to t n-1 , t 0 , respectively. t 1 ... t n-2 t n-1 . In FIG. 5A, sacrificial layers 306(0) through 306(n-1) are depicted with sacrificial layers 306(0) through 306(n-1) being thicker in the sacrificial layer 306. (0) The sacrificial layers below each of 306(n-1), that is, t 0 <t 1 <...<t n-2 <t n-1 . However, in other embodiments, the sacrificial layers 306(0) through 306(n-1) may have a thickness that gradually changes in a group manner. In such an embodiment, for at least one integer i from 0 to n-2, t i = t i+1 . For example, the sacrificial layer can be divided equally Groups, that is, each group includes m sacrificial layers, t 0 = t 1 =...=t m-1 <t m ...<t nm =...=t n-2 =t n -1 . In some embodiments, the thickness t 0 to t n-1 is between 20 nm and 60 nm. For example, the thickness t 0 can be 20 nanometers and the thickness t n-1 can be 60 nanometers. In some embodiments, a cap layer 110 can be formed on the stack 304. The cover layer 110 may be formed of an oxide.
As shown in FIG. 5B, a hole 112 is formed to form a stack 304, such as by an etching process. For example, the aperture 112 can have a sidewall that is inclined at an angle of approximately 87°. The hole 112 has a diameter D i and a diameter D j corresponding to the i-th sacrificial layer 306 (i) and the j-th sacrificial layer 306 (j), respectively, and D j is greater than D i . In some embodiments, the diameter of the holes 112 is between 80 nm and 130 nm. For example, the aperture 112 can have a diameter of 80 nanometers at the bottom and a diameter of 130 nanometers at the top end.
As shown in FIG. 5C, an active structure 114 is formed in the hole 112. The active structure 114 includes a channel layer 116. Channel layer 116 is formed along the sidewalls of hole 112 and is separated from sacrificial layers 306(0) through 306(n-1) of stack 304. Channel layer 116 can be isolated from stack 304 by any suitable insulating material. In some embodiments, a memory layer 118 provides an isolation function. Memory layer 118 can include a capture layer (not shown). More specifically, in some embodiments, the memory layer 118 may include a barrier layer (not shown), a capture layer (not shown), and a tunneling layer (s) formed sequentially from the sidewalls of the holes 112. Not shown) and may be formed by a single oxide-nitride-oxide (ONO) stack. According to some embodiments, the active structure 114 may be formed on the sidewall of the hole 112 by first forming an ONO stack (ie, the memory layer 118). Next, a polysilicon layer is formed thereon as the channel layer 116. An insulating material 120, such as an oxide, may be filled into the remaining space of the holes 112. Thus, a gate-all-around structure is formed. In some embodiments, a conductive element 122 can be further formed on the insulating material 120. Next, as shown in FIG. 5D, an ion implantation process 352 can be performed to provide a connection to the bit lines. The dopant can be arsenic.
Next, the sacrificial layers 306(0) to 306(n-1) are replaced with a plurality of conductive layers 106. As shown in FIG. 5E, an opening 354 is formed through the stack 304, such as by an etching process. As shown in FIG. 5F, the sacrificial layers 306(0) through 306(n-1) are removed through the opening 354, for example, by an etching process. Next, a conductive layer 106 is formed. According to some embodiments, the conductive layer 106 may include a metal material 356 and a high dielectric constant material 358. As shown in FIG. 5G, in some embodiments, a high dielectric constant material 358 can be formed on the upper and lower sides of the insulating layer 108 and surround the active structure 114. The high dielectric constant material 358 can be Al 2 O 3 . Next, the metal material 356 is filled into the remaining portion of the space created by the sacrificial layers 306(0) through 306(n-1). Metal material 356 can be tungsten. In some embodiments, word lines are thus provided.
In some embodiments, opening 354 provides a source region for the semiconductor structure and an ion implantation process 360 can be performed to form the source region. The dopant can be arsenic. Next, as shown in FIG. 5H, a conductive element 362 (ie, a source conductive element) can be formed in the opening 354.
In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (9)

  1. A semiconductor structure comprising: a substrate; a stack disposed on the substrate, the stack being composed of a plurality of conductive layers and a plurality of insulating layers alternating with each other, the conductive layers including an ith conductive layer and disposed thereon a j-th conductive layer above the i-th conductive layer, the i-th conductive layer having a thickness t i , the j-th conductive layer having a thickness t j , t j greater than t i ; a hole passing through the stack The hole has a diameter D i and a diameter D j corresponding to the ith conductive layer and the j-th conductive layer respectively, and D j is greater than D i ; and an active structure is disposed in the hole, the active structure includes: a channel layer disposed along a sidewall of the hole and isolated from the conductive layers of the stack; wherein the hole has a diameter that gradually increases from bottom to top, and the conductive layers have a thickness that gradually increases from bottom to top thickness of.
  2. The semiconductor structure of claim 1, wherein each of the conductive layers is thicker than the conductive layers under the respective conductive layers.
  3. The semiconductor structure of claim 1, wherein the conductive layers are divided into a plurality of groups, and the conductive layers in each group have the same thickness and are thicker than the groups. The conductive layers in the groups below the group.
  4. The semiconductor structure of claim 1, wherein the conductive layers are equally divided into a plurality of groups, and the conductive layers in each group have the same The thickness is thicker than the conductive layers in the groups below the respective groups.
  5. The semiconductor structure of claim 1, wherein the conductive layer is a 0th conductive layer from bottom to top to an n-1th conductive layer, and the 0th conductive layer reaches the nth - 1 layer of conductive layer provides channel length L 0 to L n-1 , L 0 L 1 ... L n-2 L n-1 .
  6. The semiconductor structure of claim 5, wherein L 0 <L 1 <...<L n-2 <L n-1 .
  7. The semiconductor structure of claim 5, wherein for at least one integer i from 0 to n-2, L i = L i+1 .
  8. The semiconductor structure of claim 5, wherein the conductive layers are equally divided Groups, L 0 = L 1 =...=L m-1 <...<L nm =...=L n-2 = L n-1 .
  9. A method of fabricating a semiconductor structure, comprising: forming a stack on a substrate, the stack being composed of a plurality of sacrificial layers and a plurality of insulating layers alternating with each other, the sacrificial layers including an ith sacrificial layer and formed in the a j-th sacrificial layer above the sa-layer sacrificial layer, the ith sacrificial layer having a thickness t i , the j-th sacrificial layer having a thickness t j , t j greater than t i , the sacrificial layers having a bottom-up a thickness that gradually becomes thicker; forming a hole through the stack, the hole having a diameter D i and a diameter D j corresponding to the ith layer sacrificial layer and the j-th sacrificial layer, respectively, D j being greater than D i , the hole having a diameter that gradually increases from bottom to top; and an active structure is formed in the hole, the active structure comprising: a channel layer formed along a sidewall of the hole and separated from the sacrificial layers of the stack.
TW106128660A 2017-08-23 2017-08-23 Semiconductor structure and method for manufacturing the same TWI631682B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201607045A (en) * 2014-08-13 2016-02-16 愛思開海力士有限公司 Semiconductor device and method of manufacturing the same
TW201640614A (en) * 2015-05-05 2016-11-16 旺宏電子股份有限公司 Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201607045A (en) * 2014-08-13 2016-02-16 愛思開海力士有限公司 Semiconductor device and method of manufacturing the same
TW201640614A (en) * 2015-05-05 2016-11-16 旺宏電子股份有限公司 Semiconductor device and manufacturing method thereof

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