TW201640614A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device including a substrate, a bottom insulating layer disposed on the substrate, two stacked structure disposed on the bottom insulating layer, a charge trapping structure and a channel layer disposed on the charge trapping structure is provided. Each of the stacked structures includes a plurality of semiconductor layers and insulating layers, a top insulating layer disposed on the semiconductor layers and the insulating layers and a high-doped semiconductor layer disposed on the top insulating layer. The semiconductor layers and the insulating layers are alternately stacked on the bottom insulating layer. The charge trapping layer is disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. The channel layer is directly contacted the high-doped semiconductor layer.

Description

Semiconductor device and method of manufacturing same 【0001】

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a vertical channel semiconductor device and a method of fabricating the same.

【0002】

Memory devices are used in many products, such as storage components such as MP3 players, digital cameras, computer files, and the like. With the advancement of memory manufacturing technology, the demand for memory devices has also tended to be smaller in size and larger in memory capacity.

[0003]

Therefore, a vertical channel memory device capable of achieving a large storage capacity, a small volume, and having good performance and stability has become an important direction for research and development. However, in the vertical channel memory device, a thin polysilicon is used as the channel layer. This thin channel layer cannot avoid the contact landing risk, and the additional lithography process is also prone to overlap problems ( Overlap issue).

[0004]

The present invention relates to a semiconductor device and a method of fabricating the same, which is formed by etching a portion of a charge trapping structure to form a highly doped semiconductor layer to form a thick pad for stably connecting a conductive plug.

[0005]

According to the present invention, a semiconductor device is provided comprising a substrate, a bottom insulating layer, a two-stack structure, a charge trapping structure, and a channel layer. The bottom insulating layer is disposed on the substrate. The stack structure is disposed on the bottom insulating layer. The stacked structure includes a plurality of semiconductor layers and insulating layers, a top insulating layer, and a highly doped semiconductor layer. The semiconductor layer and the insulating layer are alternately stacked on the bottom insulating layer. The top insulating layer is disposed on the semiconductor layer and the insulating layer. The highly doped semiconductor layer is disposed on the top insulating layer. The charge trapping structure is disposed on one of the side surfaces of each of the stacked structures and the upper surface of the bottom insulating layer. The channel layer is disposed on the charge trapping structure and directly contacts the highly doped semiconductor layer.

[0006]

According to the present invention, a method of fabricating a semiconductor device is provided, comprising the following steps. A bottom insulating layer is formed on a substrate. A plurality of semiconductor layers and an insulating layer are alternately stacked on the bottom insulating layer. A top insulating layer and a tantalum nitride layer are formed on the semiconductor layer and the insulating layer to form a plurality of stacked structures. A charge trapping structure and a channel layer are sequentially deposited on the surface of the stacked structure and a portion of the upper surface of the bottom insulating layer. Part of the channel layer is removed to expose the top surface of the structure with bare charge. The charge trapping structure and the tantalum nitride layer on top of the tantalum nitride layer are removed. A highly doped semiconductor layer is deposited on each of the stacked structures, and the highly doped semiconductor layer directly contacts the channel layer. Etching to separate the highly doped semiconductor layers on top of each stacked structure.

【0007】

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

[0036]

100‧‧‧Semiconductor device
1‧‧‧Substrate
10‧‧‧Bottom insulation
10a‧‧‧ upper surface
21, 22‧‧‧Stack structure
21a, 22a‧‧‧ side surface
23‧‧‧Insulation
23(1)‧‧‧Top insulation
24, 24 (1), 24 (2) ‧ ‧ semiconductor layer
25‧‧‧矽 nitride layer
30, 31‧‧‧ trench
32‧‧‧Tongkong
40‧‧‧Charge trapping structure
40a‧‧‧ Upper surface of the charge trapping structure
50‧‧‧Channel layer
50a‧‧‧ surface above the channel layer
70‧‧‧Highly doped semiconductor layer
80‧‧‧conductive plug
91, 92, 93, 94‧‧‧ oxide
92a‧‧‧ upper surface of oxide
300‧‧‧Photomask
X, Y, Z‧‧‧ axes

[0008]

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
2 to 14B are views showing a manufacturing embodiment of the semiconductor device of the present invention.

【0009】

Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.

[0010]

FIG. 1 is a cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention. It is to be noted that FIG. 1 is only a partial schematic view of the semiconductor device 100 of the embodiment of the present invention, and some elements of the semiconductor device 100 may be omitted. As shown in FIG. 1, the semiconductor device 100 includes a substrate 1, a bottom insulating layer 10, two stacked structures 21 and 22, a charge trapping structure 40, and a channel layer 50. The bottom insulating layer 10 is disposed on the substrate 1, and the stacked structures 21 and 22 are disposed on the bottom insulating layer 10. The charge trapping structure 40 is disposed on the side surface 21a of the stacked structure 21, the side surface 22a of the stacked structure 22, and the bottom insulating layer 10. On the upper surface 10a, the channel layer 50 is disposed on the charge trapping structure 40.

[0011]

In the present embodiment, the stacked structure 21 includes a plurality of semiconductor layers 24 and an insulating layer 23, a top insulating layer 23(1), and a highly doped semiconductor layer 70. The semiconductor layer 24 and the insulating layer 23 are alternately stacked on the bottom insulating layer 10, the top insulating layer 23(1) is disposed on the semiconductor layer 24 and the insulating layer 23, and the highly doped semiconductor layer 70 is disposed on the top insulating layer 23(1). . Further, the channel layer 50 may directly contact the highly doped semiconductor layer 70.

[0012]

As shown in FIG. 1, the top of the channel layer 50 is higher than the top of the charge trapping structure 40. The highly doped semiconductor layer 70 can also directly contact the charge trapping structure 40, and the top of the highly doped semiconductor layer 70 is higher than the top of the channel layer 50 and the top of the charge trapping structure 40. Further, the thickness of the highly doped semiconductor layer 70 is greater than the thickness of the channel layer 50.

[0013]

In the embodiment of the present invention, the charge trapping structure 40 can be a multilayer structure including a plurality of first dielectric layers and a plurality of second dielectric layers (not shown). For example, the charge trapping structure 40 can be, for example, a hafnium oxide/tantalum nitride/yttria (ONO) structure or a niobium oxide/tantalum nitride/yttria/tantalum nitride/anthracene oxide (ONONO) structure, That is, the material of the first dielectric layer may be tantalum nitride, and the material of the second dielectric layer may be tantalum oxide. However, the invention is not limited thereto.

[0014]

In addition, the heights of the first dielectric layer and the second dielectric layer of the charge trapping structure 40 may be different due to the manufacturing method, which will be described later.

[0015]

In the embodiment of the present invention, the material of the highly doped semiconductor layer 70 and the material of the channel layer 50 may be the same. For example, the material of the highly doped semiconductor layer 70 and the channel layer 50 is, for example, an N-type doped polysilicon, and the material of the semiconductor layer 24 is a P-type doped polysilicon. However, the invention is not limited thereto.

[0016]

In the embodiment of the present invention, the stacked structure 22 has a structure similar to that of the stacked structure 21, and details are not described herein. As shown in FIG. 1, the charge trapping structure 40 and the channel layer 50 may be formed in the trench 30 between the stacked structure 21 and the stacked structure 22, and the shape of the charge trapping structure 40 and the channel layer 50 is, for example, U-shaped. Further, after the charge trapping structure 40 and the channel layer 50 are formed, the trenches 30 may be filled with the oxide 94.

[0017]

In one embodiment, the topmost semiconductor layer 24(1) of the stacked structure 21 can serve as a ground select line (GSL), and the topmost semiconductor layer 24(2) of the stacked structure 22 can serve as a string. Column select line (SSL). In addition, as shown in FIG. 1, the semiconductor device 100 may include a plurality of stacked structures 21 and a stacked structure 22, and the oxide layers 94 may be isolated from each other between the plurality of stacked structures 21 and the stacked structures 22.

[0018]

2 to 14B illustrate a manufacturing embodiment of the semiconductor device 100 of the present invention. First, as shown in Fig. 2, a bottom insulating layer 10 is formed on the substrate 1. Then, a plurality of semiconductor layers 24 and an insulating layer 23 are alternately stacked on the bottom insulating layer 10, and a top insulating layer 23(1) and a tantalum nitride layer 25 are formed on the semiconductor layer 24 and the insulating layer 23 to form a plurality Stacked structure.

[0019]

In the present embodiment, the insulating layer 23 and the top insulating layer 23 (1) are, for example, a hafnium oxide layer, and the tantalum nitride layer 25 is disposed on the top insulating layer 23 (1), and the material of the tantalum nitride layer 25 Strong stress can be used to stabilize each stack structure.

[0020]

As shown in FIG. 3, the charge trapping structure 40 and the channel layer 50 are sequentially deposited on the surface of the stacked structure and a portion of the upper surface 10a of the bottom insulating layer 10. In the present embodiment, the charge trapping structure 40 can be, for example, a multilayer structure including a first dielectric layer and a second dielectric layer, and the channel layer 50 has a thickness of, for example, 8 nm. For example, the charge trapping structure 40 is a hafnium oxide/tantalum nitride/yttria (ONO) structure or a tantalum oxide/tantalum nitride/yttria/tantalum nitride/anthracene oxide (ONONO) structure, that is, The material of the first dielectric layer is, for example, tantalum nitride, and the material of the second dielectric layer is, for example, tantalum oxide. Here, the trenches 30 are included between the stacked structures.

[0021]

As shown in FIG. 4, the oxide 91 is filled so that the oxide 91 fills the remaining portion of the trench 30. Next, as shown in Fig. 5, the oxide 91 of the upper surface 50a of the channel layer 50 is removed, and an oxide 92 is formed. For example, an etching tool or a chemical mechanical polish (CMP) process can be used, and the channel layer 50 can function as a stop layer.

[0022]

As shown in FIG. 6, a portion of the channel layer 50 is removed to expose the upper surface 40a of the charge trapping structure 40. Next, as shown in FIG. 7, the charge trapping structure 40 and the tantalum nitride layer 25 on the top of the tantalum nitride layer 25 are sequentially removed.

[0023]

For example, the charge trapping layer 40 on top of the tantalum nitride layer 25 is first removed using an etch tool, at which point a portion of the via layer 50 is also removed. Next, phosphoric acid can be used _{(phosphoric acid) (H 3 PO} 4) silicon nitride layer 25 is removed. Since the phosphoric acid is highly selective to the oxide, the tantalum nitride layer 25 can be removed, but stopped at the top insulating layer 23(1). That is, the tantalum nitride layer 25 can serve as a sacrificial layer, and after the tantalum nitride layer 25 is removed, each stacked structure can be self-aligned to the upper surface of the top insulating layer 23(1).

[0024]

Since the charge trapping structure 40 can include, for example, a first dielectric layer formed of tantalum nitride and a second dielectric layer formed of tantalum oxide, the first dielectric layer can be removed by phosphoric acid while the second dielectric layer is not. It will be removed, that is, the height of the first dielectric layer and the second dielectric layer are different (not shown in Figure 7).

[0025]

As shown in FIG. 8, a highly doped semiconductor layer 70 is deposited on each of the stacked structures, and the highly doped semiconductor layer 70 is in direct contact with the via layer 50 and the top insulating layer 23(1). Here, the highly doped semiconductor layer 70 is, for example, an N-type doping polysilicon.

[0026]

As shown in FIG. 9, a portion of the highly doped semiconductor layer 70 is removed to expose the upper surface 92a of the oxide 92. Similarly, an etch tool or a CMP process can be used to remove a portion of the highly doped semiconductor layer 70.

[0027]

As shown in FIGS. 10A to 10C, a plurality of trenches 31 are etched and formed to form a plurality of stacked structures 21 and stacked structures 22 such that the charge trapping structure 40 and the channel layer 50 between the stacked structure 21 and the stacked structure 22 are formed. The shape is U-shaped. Next, an oxide may be filled in the plurality of trenches 31 to separate the plurality of stacked structures 21 from the stacked structure 22. Here, FIG. 10A is a cross-sectional view of each stack structure at this stage, and FIG. 10B is a top view of each stack structure at this stage, and FIG. 10C is a perspective view of each stack structure at this stage.

[0028]

Next, an oxide 93 is deposited in the plurality of trenches 31 and on the upper surface of the highly doped semiconductor layer 70 to form a structure as shown in FIG.

[0029]

Next, as shown in FIGS. 12A to 12C, etching is performed using the photomask 300 to separate the respective stacked structures 21 and the highly doped semiconductor layer 70 on top of the stacked structure 22. Here, FIG. 12A is a cross-sectional view of each stack structure at this stage, and FIG. 12B is a top view of each stack structure at this stage, and FIG. 12C is a perspective view of each stack structure at this stage.

[0030]

Finally, the semiconductor device 100 as shown in FIG. 1 is formed by filling the oxide 94 between the separated highly doped semiconductor layers 70 and the top of each doped semiconductor layer 70.

[0031]

In the embodiment of the present invention, the semiconductor device 100 further includes a conductive plug 80 disposed on the highly doped semiconductor layer 70 to electrically connect the highly doped semiconductor layer 70 and the channel layer 50.

[0032]

13 through 14B illustrate a fabrication example of forming a conductive plug 80 on the highly doped semiconductor layer 70. As shown in Fig. 13, a plurality of through holes 32 are formed which expose the upper surface of the highly doped semiconductor layer 70.

[0033]

Next, as shown in FIGS. 14A and 14B, a conductive material is filled in the through holes 32 to form a plurality of conductive plugs 80. It should be noted that the position of the conductive plug 80 in the embodiment of the present invention is not limited to the configuration illustrated in FIGS. 14A and 14B.

[0034]

The memory device 100 of the embodiment of the present invention is a vertical gate structure, which can be applied, for example, to a NAND flash. The highly doped semiconductor layer 70 formed using the fabrication method of the present invention is self-aligned and does not require an additional lithography etching step. In addition, the risk and overlap of landings can be effectively avoided.

[0035]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor device

1‧‧‧Substrate

10‧‧‧Bottom insulation

10a‧‧‧ upper surface

21, 22‧‧‧Stack structure

21a, 22a‧‧‧ side surface

23‧‧‧Insulation

23(1)‧‧‧Top insulation

24, 24 (1), 24 (2) ‧ ‧ semiconductor layer

30‧‧‧ trench

40‧‧‧Charge trapping structure

50‧‧‧Channel layer

70‧‧‧Highly doped semiconductor layer

94‧‧‧Oxide

X, Y‧‧‧ axes

Claims (10)

[Item 1] A semiconductor device comprising:
a substrate;
a bottom insulating layer disposed on the substrate;
The second stack structure is disposed on the bottom insulating layer, and each of the stack structures comprises:
a plurality of semiconductor layers and an insulating layer are alternately stacked on the bottom insulating layer;
a top insulating layer disposed on the semiconductor layers and the insulating layers; and a highly doped semiconductor layer disposed on the top insulating layer;
A charge trapping structure is disposed on one side surface of each of the stacked structures and an upper surface of the bottom insulating layer; and a channel layer disposed on the charge trapping structure and directly contacting the highly doped semiconductor layer. [Item 2] The semiconductor device according to claim 1, further comprising:
a conductive plug disposed on the highly doped semiconductor layer to electrically connect the highly doped semiconductor layer and the via layer,
Wherein the top of the channel layer is higher than the top of the charge trapping structure, the highly doped semiconductor layer directly contacts the charge trapping structure, and the top of the highly doped semiconductor layer is higher than the top of the channel layer and the charge trapping structure top. [Item 3] The semiconductor device of claim 1, wherein the highly doped semiconductor layer has a thickness greater than a thickness of the channel layer. [Item 4] The semiconductor device of claim 1, wherein the charge trapping structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers, the first dielectric layers and the second dielectric layers The height of each of the first dielectric layers is tantalum nitride, and the material of each of the second dielectric layers is yttrium oxide. [Item 5] The semiconductor device of claim 1, wherein the charge trapping structure and the channel layer are U-shaped, and the material of the highly doped semiconductor layer and the material of the channel layer are the same. [Item 6] The semiconductor device according to claim 1, wherein the material of each of the semiconductor layers is a P-type doped polysilicon, and the material of the highly doped semiconductor layer and the channel layer is an N-type doped polysilicon. [Item 7] A method of fabricating a semiconductor structure, comprising:
Forming a bottom insulating layer on a substrate;
Stacking a plurality of semiconductor layers and an insulating layer on the bottom insulating layer;
Forming a top insulating layer and a tantalum nitride layer on the semiconductor layers and the insulating layers to form a plurality of stacked structures;
Depositing a charge trapping structure and a channel layer on the surface of the stacked structure and a portion of the upper surface of the bottom insulating layer;
Removing a portion of the channel layer to expose the upper surface of the charge trapping structure;
Removing the charge trapping structure and the tantalum nitride layer on top of the tantalum nitride layer;
Depositing a highly doped semiconductor layer on each of the stacked structures, the highly doped semiconductor layer directly contacting the via layer; and etching to separate the highly doped semiconductor layer on top of each stacked structure. [Item 8] The manufacturing method described in claim 7 of the patent scope further includes:
Forming a conductive plug on the highly doped semiconductor layer,
The conductive plug is electrically connected to the highly doped semiconductor layer and the channel layer, and the tantalum nitride layer is removed by using phosphoric acid. [Item 9] The manufacturing method of claim 7, wherein the charge trapping structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers, and the first dielectric layers and the second dielectric layers The height of the layers is different. [Item 10] For example, the manufacturing method described in claim 7 includes:
Etching and forming a plurality of trenches; and filling oxides in the trenches to separate the stacked structures,
Wherein the top of the highly doped semiconductor layer is higher than the top of the channel layer and the top of the charge trapping structure, the shape of the charge trapping structure and the channel layer is U-shaped, and the highly doped semiconductor layer and the channel layer The material is an N-type doped polysilicon.