US20220028473A1 - Ground bounce generator in device under test, automatic test equipment, and method of testing with ground noise - Google Patents
Ground bounce generator in device under test, automatic test equipment, and method of testing with ground noise Download PDFInfo
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- US20220028473A1 US20220028473A1 US16/939,047 US202016939047A US2022028473A1 US 20220028473 A1 US20220028473 A1 US 20220028473A1 US 202016939047 A US202016939047 A US 202016939047A US 2022028473 A1 US2022028473 A1 US 2022028473A1
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- generator
- device under
- under test
- ground bounce
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56012—Timing aspects, clock generation, synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
Abstract
A ground bounce generator includes a resistor and at least one switch coupled in parallel with the resistor. The ground bounce generator is in a device under test circuit including a source, at least one ground bounce generator, at least one device under test, and a ground. The device under test is coupled in series between the source and the ground bounce generator. The device under test and the ground bounce generator are coupled in series between the source and the ground.
Description
- The present invention relates to the ground bounce generator. More particularly, the present invention relates to the structure and the method of the ground bounce generator for generating the ground noise.
- An automatic test equipment (ATE) is generally used in the device development to test the performance of the device, for example, a dynamic random accesory memory (DRAM). A platform is a component of the ATE, and a device under test (DUT) is designed on the platform for placement of the testing device. The purpose of the ATE is to simulate a real application environment for the testing device and screen out the cases of disqualification.
- The invention provides a ground bounce generator including a resistor and at least one switch coupled in parallel with the resistor. The ground bounce generator is in a device under test circuit including a source, at least one ground bounce generator, at least one device under test, and a ground. The device under test is coupled in series between the source and the ground bounce generator. The device under test and the ground bounce generator are coupled in series between the source and the ground.
- The invention also provides an automatic test equipment, which includes a devices under test and at least one ground bounce generator. The device under test includes a printed circuit board in which the ground bounce generator is arranged and a socket on the printed circuit board that is connected to the printed circuit board.
- The invention also provides a method of testing a testing device with a ground noise. The method includes coupling a device under test in series between a source and a ground, coupling a ground bounce generator in series between the device under test and the ground, coupling a testing device to the device under test, providing a current by the source through the device under test and the ground bounce generator, controlling the ground bounce generator to generate the ground noise, and collecting a performance result of the testing device.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
-
FIG. 1A is a schematic block view of an automatic test equipment with a plurality of device under tests according to some embodiments; -
FIG. 1B is a schematic block view of a device under test in an automatic test equipment according to some embodiments; -
FIG. 2 is a schematic diagram of a circuit including a device under test and a ground bounce generator according to some embodiments of the present disclosure; -
FIGS. 3A-3B are line graphs of time dependent voltage VA and VDUT, respectively, in the circuit ofFIG. 2 ; -
FIG. 4 is a line graph of a time dependent voltage VB in the circuit which a ground bounce generator is not working according to some embodiments; -
FIG. 5 is a schematic diagram of a circuit including more than one device under test and one ground bounce generator according to some embodiments of the present disclosure; -
FIG. 6 is a schematic diagram of a circuit including one device under test and more than one ground bounce generator according to some embodiments of the present disclosure; -
FIG. 7 is a line graph of a time dependent voltage VC in the circuit ofFIG. 6 ; and -
FIG. 8 is a schematic diagram of a circuit including a device under test and a ground bounce generator according to some embodiments of the present disclosure. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1A illustrates a schematic block view of an automatice test equipment (ATE) in accordance with some embodiments of the present disclosure. As shown inFIG. 1A , an ATE 120 may include aplatform 110 which is designed as a part of a jig. A plurality of device under tests (DUT) 100 may be arranged in theplatform 110 for the placement of testing devices, for example, dynamic random accesory memories (DRAM). The number and the arrangement of theDUT 100 may be any suitable design to meet the purpose of device quality test, and those modifications are within the scope of the present disclosure. -
FIG. 1B illustrates a schematic block view of aDUT 100 related toFIG. 1A in accordance with some embodiments of the present disclosure. InFIG. 1B , theDUT 100 includes a printed circuit board (PCB) 102 and asocket 104 on the PCB 102. The PCB 102 may be designed to contain circuits for different purposes which include power supply, data transmission, or the like. As shown inFIG. 1B , thePCB 102 may be connected to lines such as anaddress input 122, acontrol input 124, or a data input/output 126 in the ATE 120. Therefore, additional tester components may be added in thePCB 102, such as the following descripted ground bounce generator of the present disclosure. Thesocket 104 may be connected to the PCB 102, which becomes the connector between thePCB 102 and thetesting device 106. When a current is provided to theDUT 100, the ATE 120 works to simulate an application environment and collects a performance result of thetesting device 106 by aprocessor 130 connecting to theDUT 100. As designed as the above mentioned, the ATE 120 is able to perform various tests on thetesting device 106 by the PCB 102 and thesocket 104 of theDUT 100 and examine the product quality. In some embodiments, there may be other layers or devices included in theDUT 100 or the ATE 120, and those modifications are within the scope of the present disclosure. - The purpose of an ATE is to simulate an application environment close to the real life. For example, a ground noise exists in real application of devices, and a commercial device should have resistance to the ground noise. In other words, an ATE with the ability to generate the ground noise to the DUT is preferable for the device performance test. Therefore, a ground bounce generator is disclosed herein to generate artificial and controllable ground noise which occurs in the real life.
FIG. 2 illustrates a schematic diagram of a circuit including a DUT and a ground bounce generator in accordance with some embodiments of the present disclosure. As shown inFIG. 2 , the illustrated DUT is aDUT 200 which is similar to theDUT 100 ofFIGS. 1A-1B . However, the DUT included in the circuit ofFIG. 2 and the other circuits mentioned in the following description may be theDUT 200 or any other suitable DUT. TheDUT 200 may be coupled in serious between a source VDD and a ground G. The source VDD and the ground G may provide power to theDUT 200 to simulate a working condition for testing devices. In addition, theDUT 200 may be connected to other lines including, but not limited to,address input 222,control input 224, and data input/output 226 similar to those inFIG. 1B to provide signals for device performance test in an ATE. In some embodiments, there may be other lines or devices connected to theDUT 200, and those modifications are within the scope of the present disclosure. - A
ground bounce generator 300 may be coupled in series between theDUT 200 and the ground G to generate ground noise to theDUT 200. Referring toFIG. 1B andFIG. 2 , in some embodiments, theground bounce generator 300 may be added into thePCB 102 of theDUT 100 and thus coupled in series with thesocket 104. However, for clearity of discussion, theground bounce generator 300 is illustrated as a component separated from theDUT 200 inFIG. 2 . In some embodiments, theground bounce generator 300 may be positioned at different places in an ATE, and those modifications are within the scope of the present disclosure. - In some embodiments, the
ground bounce generator 300 may include a resistor R and aswitch 302 coupling in parallel. In some embodiments, theswitch 302 may have a relay controlled by the ATE. Theswitch 302 may be controlled by other ways or elements of the ATE, and those modifications are within the scope of the present disclosure. When theswitch 302 is turned “on” and forms a closed circuit on theswitch 302, the current from the source VDD passes through theDUT 200 and theswitch 302. As a result, theDUT 200 is directly connected to the ground G and the voltage from the source VDD may be mainly provided to theDUT 200. In this case, the ground noise may be regarded as the smallest during the operation of the ATE. When theswitch 302 is turned “off” and theswitch 302 forms an open circuit, the current from the source VDD passes through theDUT 200 and the resistor R, which generates a voltage drop across the resistor R. Therefore, the voltage from the source VDD may be shared by theDUT 200 and the resistor R. The voltage drop may be considered as the largest ground noise provided to theDUT 200 by theground bounce generator 300. The ATE having theground bounce generator 300 may be able to generate a group of artificial ground noises while repeating turning theswitch 302 on and off. - In one embodiment, for example, the source VDD totally provides 1.2 V, and the current through the
DUT 200 is 300 mA. When theswitch 302 is turned on, the voltage on theDUT 200 is 1.2 V, and the voltage at point A is 0 V in the circuit ofFIG. 2 . When theswitch 302 is turned off, a voltage drop occurs across the resistor R. As the resistor R is 1 Ω, the voltage at point A equals to 0.3 V according to Ohm's law, and the voltage on theDUT 200 correspondly decreases to 0.9 V. According to the above embodiment, the ATE may repeat turning on and off theswitch 302 and generate a ground noise with a maximum amplitude of 0.3 V to theDUT 200. The values in the above mentioned embodiment are only exemplary, and they may be any suitable values for device performance tests. - The ground noise may be illustrated as a line graph for clearer discussion.
FIG. 3A illustrates a time dependent voltage VA at point A in the circuit ofFIG. 2 . Referring toFIG. 2 andFIG. 3A , the rise and the drop of voltage VA respectively correspond to the off and on of theswitch 302, which lead to the peaks shown inFIG. 3A . The maximum amplitude of the peaks is regarded as an amplitude H. The amplitude H of the peaks may be determined by the resistor R. If the resistor R is larger, the amplitude H (or the voltage drop across the resistor R) also becomes larger. In some embodiments, the resistor R may be selected to generate the amplitude H larger than 50 mV so that the ground noise is not neglected. In some embodiments, the resistor R may be selected to generate the amplitude H larger than 300 mV since the real ground noise is generally larger than 300 mV. In some embodiments, the resistor R may be selected to generate the amplitude H with 10% to 30% of the voltage provided by the source VDD. The amplitude H smaller than 10% of the voltage of the source VDD may be too small to simulate the real ground noise, while the amplitude H larger than 30% of the voltage of the source VDD may affect the testing devices much more seriously than the real application. In some embodiments, the ratio of the amplitude H to the voltage provided to the DUT may include other values, and those modifications are within the scope of the present disclosure. In addition, the retention time of the peaks is regarded as a period T. The period T is determined by theswitch 302 controlled by the ATE. In some embodiments, the period T may remain the same during the operation of the ATE, which indicates that the ground noise frequency generated by ground bounce generator is consistent and regular. In some other embodiments, the period T may vary during the operation of ATE, as shown as a period T1 and a period T2 inFIG. 3A , which leads to the irregular ground noise frequency. -
FIG. 3B illustrates a time dependent voltage VDUT on theDUT 200 in the circuit ofFIG. 2 . Referring toFIGS. 2, 3A, and 3B , the voltage VA inFIG. 3A may lead to corresponding changes of the voltage VDUT inFIG. 3B . When the voltage VA increases, the voltage VDUT correspondly decreases, and vice versa. In some embodiments which the voltage provided by the source VDD is not consumed by other components, the sum of the voltage VA and the voltage VDUT equals to the voltage of the source VDD. In some other embodiments, the amplitude H of the voltage VA equals to the drop of the voltage VDUT. As shown inFIGS. 3A and 3B , the amplitude of the voltage VDUT varies between an amplitude Vmax and an amplitude Vmin, and the sum of the amplitude Vmin and the amplitude H inFIG. 3A equals to the amplitude Vmax. The retention times of the peaks of the voltage VDUT also correspond to those of the voltage VA, as shown as the period T1 and T2. - Generally, the source VDD and the groung G in an ATE serve as a power supplier, which indicates that the ground noise is not provided or is small enough to be neglected between the source VDD and the ground G.
FIG. 4 illustrates the time dependent voltage VB at point A in the circuit similar to that ofFIG. 2 , without introducing theground bounce generator 300. As shown inFIG. 4 , voltage VB is nearly zero during the operation of the ATE. In some embodiments, a ground noise smaller than 50 mV may be neglected. As a result, no ground noise is provided to theDUT 200, and the ATE fails to simulate a real application environment for testing devices. -
FIG. 5 illustrates a schematic diagram of a circuit similar toFIG. 2 , except the circuit includes more than oneDUT 200 and oneground bounce generator 300 in accordance with some embodiments of the present disclosure. As shown inFIG. 5 , more than oneDUT 200 may be coupled in parallel and collectively coupled in series with theground bounce generator 300. As such, the ground noise generated by theground bounce generator 300 is delivered to allDUTs 200 under this arrangement. TwoDUTs 200 are illustrated inFIG. 5 , however, a circuit including other numbers of DUTs is within the scope of the present disclosure. - As shown in
FIG. 2 andFIG. 3A , theground bounce generator 300 in the circuit may provide the symmetric waveforms of the artificial ground noise. To simulate the ground noise closer to the real application, a plurality of ground bounce generators may be included in a circuit and generate asymmetric waveforms of the ground noise.FIG. 6 illustrates a schematic diagram of a circuit similar to the circuit ofFIG. 2 , except the circuit ofFIG. 6 includes oneDUT 200 and more than one ground bounce generators in accordance with some embodiments of the present disclosure. More than one ground bounce generators may be coupled in parallel and collectively coupled in series withDUT 200. Twoground bounce generators FIG. 6 , however, a circuit including other number of ground bounce generators is within the scope of the present disclosure. Twoground bounce generators ground bounce generators ground bounce generators DUT 200.FIG. 7 illustrates a time dependent voltage VC at point C in the circuit ofFIG. 6 which the amplitude and the frequency of the ground noise from theground bounce generators -
FIG. 8 illustrates a schematic diagram of a circuit similar toFIG. 2 , except the circuit ofFIG. 8 includes aDUT 200 and aground bounce generator 800 in accordance with some embodiments of the present disclosure. Theground bounce generator 800 is similar to theground bounce generator 300, except theground bounce generator 800 may include more than one switch. As shown inFIG. 8 , theground bounce generator 800 includes two switches, 302 and 304. It should be noted that a ground bounce generator including other number of switches is within the scope of the present disclosure. Theswitches switches ground bounce generator 800 may be used in other circuits such as those illustrated inFIG. 5 andFIG. 6 . For example, at least one of the ground bounce generator inFIG. 6 may be theground bounce generator 800. - With at least one ground bounce generator in an ATE as mentioned above, the ATE is able to test a testing device with a ground noise. After the testing device is coupled to the device under test in the ATE, the current and the voltage is provided through the device under test and the ground bounce generator. While the ground bounce generator is controlled by turning on and off, a group of artificial ground noises is generated that affects the device under test, which further affects the lines connected to the device under test, for example, the address input, the control input, or the data input/output. A performance result of the testing device which closer reflects application in real life is then collected by the processor of the ATE.
- Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (19)
1. A device under test circuit, comprising:
a source;
at least one ground bounce generator, wherein each ground bounce generator comprises:
a resistor; and
at least one switch coupled in parallel with the resistor;
at least one device under test, wherein the device under test is coupled in series between the source and the ground bounce generator; and
a ground, wherein the device under test and the ground bounce generator are coupled in series between the source and the ground.
2. The device under test circuit of claim 1 , further comprising:
an address input;
a control input; and
a data input/output, wherein the address input, the control input, and the data input/out are connected to the device under test.
3. The device under test circuit of claim 1 , wherein the switch comprises a relay.
4. The device under test circuit of claim 1 , wherein the at least one ground bounce generator is plural, and the ground bounce generators are coupled in parallel and collectively coupled in series with the device under test.
5. The device under test circuit of claim 1 , wherein the at least one device under test is plural, and the device under tests are coupled in parallel and collectively coupled in series with the ground bounce generator.
6. An automatic test equipment, comprising:
a device under test comprising:
a printed circuit board; and
a socket on the printed circuit board, wherein the socket is connected to the printed circuit board; and
at least one ground bounce generator on the printed circuit board of the device under test, wherein the socket of the device under tests is coupled in series with the ground bounce generator, and wherein the ground bounce generator comprises a resistor and at least one switch coupled in parallel with the resistor; and
a processor connecting to the device under test.
7. The automatic test equipment of claim 6 , further comprising:
an address input;
a control input; and
a data input/output, wherein the address input, the control input, and the data input/out are connected to the device under test.
8. The automatic test equipment of claim 6 , wherein the ground bounce generator comprises a switch, and the switch comprises a relay.
9. A method of testing a testing device with a ground noise, comprising:
coupling a device under test in series between a source and a ground in an automatic test equipment;
coupling a ground bounce generator in series between the device under test and the ground;
coupling the testing device to the device under test;
providing a current by the source through the device under test and the ground bounce generator;
controlling the ground bounce generator to generate the ground noise; and
collecting a performance result of the testing device in the automatic test equipment.
10. The method of claim 9 , wherein controlling the ground bounce generator further comprising:
forming a closed circuit on a switch in the ground bounce generator to minimize the ground noise;
forming an open circuit on the switch in the ground bounce generator to maximize the ground noise; and
repeating forming the closed circuit and the open circuit on the switch in the ground bounce generator to generate the ground noise.
11. The method of claim 9 , wherein controlling the ground bounce generator comprises generating a voltage drop across a resistor in the ground bounce generator.
12. The method of claim 11 , wherein the voltage drop equals to an amplitude of the ground noise.
13. The method of claim 9 , wherein an amplitude of the ground noise is determined by a resistor in the ground bounce generator.
14. The method of claim 9 , wherein an amplitude of the ground noise is between 10% to 30% of a voltage of the source.
15. The method of claim 9 , wherein an amplitude of the ground noise is larger than 300 mV.
16. The method of claim 9 , wherein the ground noise comprises symmetric or asymmetric waveforms.
17. The method of claim 9 , wherein the ground noise comprises regular or irregular waveforms.
18. The method of claim 9 , wherein the testing device comprises a dynamic random accesory memory.
19. The method of claim 9 , wherein the ground noise affects an address input, a control input, or a data input/output coupled to the device under test.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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US16/939,047 US11250925B1 (en) | 2020-07-26 | 2020-07-26 | Ground bounce generator in device under test, automatic test equipment, and method of testing with ground noise |
CN202110807548.7A CN113990381A (en) | 2020-07-26 | 2021-07-16 | Circuit of device under test, automatic test device and method for testing by using grounding noise |
TW110126297A TWI779725B (en) | 2020-07-26 | 2021-07-16 | Device under test circuit, automatic test equipment, and method of testing with ground noise |
US17/643,188 US11551773B2 (en) | 2020-07-26 | 2021-12-08 | Method of testing with ground noise |
Applications Claiming Priority (1)
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US16/939,047 US11250925B1 (en) | 2020-07-26 | 2020-07-26 | Ground bounce generator in device under test, automatic test equipment, and method of testing with ground noise |
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US17/643,188 Division US11551773B2 (en) | 2020-07-26 | 2021-12-08 | Method of testing with ground noise |
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US20220028473A1 true US20220028473A1 (en) | 2022-01-27 |
US11250925B1 US11250925B1 (en) | 2022-02-15 |
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US16/939,047 Active US11250925B1 (en) | 2020-07-26 | 2020-07-26 | Ground bounce generator in device under test, automatic test equipment, and method of testing with ground noise |
US17/643,188 Active US11551773B2 (en) | 2020-07-26 | 2021-12-08 | Method of testing with ground noise |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US6674677B2 (en) * | 1999-09-02 | 2004-01-06 | Micron Technology, Inc. | Memory device tester and method for testing reduced power states |
US7518424B2 (en) * | 2004-11-08 | 2009-04-14 | Elite Semiconductor Memory Technology Inc. | Slew rate controlled output circuit |
US8461858B1 (en) * | 2008-12-11 | 2013-06-11 | Altera Corporation | Adjustable power supply sag and bounce generator |
US10127127B2 (en) * | 2015-06-04 | 2018-11-13 | Qualcomm Incorporated | Systems and methods for pre-warning a monitoring tool for a communication bus |
US10666044B2 (en) * | 2016-05-25 | 2020-05-26 | Nec Corporation | Grounding circuit, electrical device, grounding control method, and grounding control program |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000043490A (en) * | 1998-12-29 | 2000-07-15 | 윤종용 | Test system of semiconductor chip and tester |
-
2020
- 2020-07-26 US US16/939,047 patent/US11250925B1/en active Active
-
2021
- 2021-07-16 CN CN202110807548.7A patent/CN113990381A/en active Pending
- 2021-07-16 TW TW110126297A patent/TWI779725B/en active
- 2021-12-08 US US17/643,188 patent/US11551773B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6674677B2 (en) * | 1999-09-02 | 2004-01-06 | Micron Technology, Inc. | Memory device tester and method for testing reduced power states |
US7518424B2 (en) * | 2004-11-08 | 2009-04-14 | Elite Semiconductor Memory Technology Inc. | Slew rate controlled output circuit |
US8461858B1 (en) * | 2008-12-11 | 2013-06-11 | Altera Corporation | Adjustable power supply sag and bounce generator |
US10127127B2 (en) * | 2015-06-04 | 2018-11-13 | Qualcomm Incorporated | Systems and methods for pre-warning a monitoring tool for a communication bus |
US10666044B2 (en) * | 2016-05-25 | 2020-05-26 | Nec Corporation | Grounding circuit, electrical device, grounding control method, and grounding control program |
Also Published As
Publication number | Publication date |
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CN113990381A (en) | 2022-01-28 |
TWI779725B (en) | 2022-10-01 |
US11551773B2 (en) | 2023-01-10 |
TW202205297A (en) | 2022-02-01 |
US11250925B1 (en) | 2022-02-15 |
US20220101935A1 (en) | 2022-03-31 |
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