US20210287723A1 - Self-biased sense amplification circuit - Google Patents

Self-biased sense amplification circuit Download PDF

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US20210287723A1
US20210287723A1 US17/131,802 US202017131802A US2021287723A1 US 20210287723 A1 US20210287723 A1 US 20210287723A1 US 202017131802 A US202017131802 A US 202017131802A US 2021287723 A1 US2021287723 A1 US 2021287723A1
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terminal
coupled
bit line
sense
control
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US11139006B1 (en
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Chih-Chun Chen
Chun-Hung Lin
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eMemory Technology Inc
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/10—Floating gate memory cells with a single polysilicon layer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Definitions

  • the pre-amplifier 1201 can generate a read current IR 1 on the main bit line MBL 1 according to the voltage of the local bit line LBL 1 during sample operations and sense operations of the memory cells MC( 1 , 1 ) to MC(M, 1 ), and the pre-amplifier 120 N can generate a read current on the main bit line MBLN according to a voltage of the local bit line LBLN during sample operations and sense operations of the memory cells MC( 1 ,N) to MC(M,N).
  • the path selector 240 can have a first terminal for receiving a second system voltage VDD, and second terminals coupled to the pre-amplifiers 2101 to 210 N.
  • the path selector 240 can form an electrical connection between the first terminal and one of the second terminals of the path selector 240 during the sample operation and the sense operation.
  • the second terminals of the pre-amplifiers 2201 to 220 N can be coupled to the same main bit line MBL, and main bit line MBL can be coupled to the data bit line DL directly. That is, the connection of the path selector 140 can be adjusted as the path selector 240 according to the system requirement.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This non-provisional application claims priority of U.S. provisional application No. 62/988,403, filed on Mar. 12, 2020, included herein by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is related to a sense amplification circuit, and more particularly, to a self-biased sense amplification circuit.
  • 2. Description of the Prior Art
  • The data stored in a memory cell is often read by sensing the cell current generated by the memory cells. For example, if the cell current is greater than a reference current, then it implies that the data stored in the memory cell has a first type of value. However, if the cell current is not greater than the reference current, then it implies that the data stored in the memory cell has a second type of value. That is, the reference current can be critical for the read operation of the memory cell.
  • However, it can be difficult to provide an un-biased reference current source due to the uncontrollable variance caused during the manufacturing process. Furthermore, if an inappropriate reference current is used, then the read margin would be rather small, and the small read margin can not only slow down the read process but also affect the accuracy of the read operation.
    • SUMMARY OF THE INVENTION
  • One embodiment of the present invention discloses a self-biased sense amplification circuit. The sense amplification circuit includes a local bit line, a reset unit, a main bit line, a pre-amplifier, a data line, a sample reference circuit, and a second amplifier.
  • The local bit line is coupled to a memory cell, and receives a cell current generated by the memory cell during a sense operation. The reset unit is coupled to the local bit line, and resets the local bit line to a first system voltage during a sample operation. The pre-amplifier is coupled to the local bit line and the main bit line. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line during the sample operation and the sense operation. The sample reference unit is coupled to the data line. The sample reference unit generates a first reference current and a second reference current and records a reference control voltage during the sample operation, and generates the first reference current according to the reference control voltage during the sense operation. The sense amplifier is coupled to the data line, and senses a voltage of the data line during the sense operation.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a sense amplification circuit according to one embodiment of the present invention.
  • FIG. 2 shows the timing diagram of the signals received by the sense amplification circuit in FIG. 1 for reading the data stored in a memory cell.
  • FIG. 3 shows a sense amplification circuit according to another embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • FIG. 1 shows a sense amplification circuit 100 according to one embodiment of the present invention. The sense amplification circuit 100 includes local bit lines LBL1 to LBLN, main bit lines MBL1 to MBLN, a data line DL, reset units 1101 to 110N, pre-amplifiers 1201 to 120N, a sample reference unit 130, a path selector 140, and a sense amplifier 150.
  • In some embodiments, the sense amplification circuit 100 can be used to read data from the cell array CA1. In FIG. 1, the cell array CA1 can include memory cells MC(1,1) to MC(M,N), where M and N are positive integers. In the cell array CA1, the memory cells MC(1,1) to MC (M,N) are arranged as M different words, and each word can include N bits of data. In this case, the memory cells MC(1,1) to MC(M,1) may be coupled to the same local bit line LBL1, the memory cells MC (1,2) to MC(M,2) may be coupled to the same local bit line LBL2, and so on.
  • In the prior art, when a memory cell is selected to be read, the cell current generated by the memory cell has to charge all local bit lines that are coupled to the same sense amplifier, making the read operation very time consuming.
  • However, in the sense amplification circuit 100, each of the local bit lines LBL1 to LBLN can be coupled to a corresponding pre-amplifier of the pre-amplifiers 1201 to 120N. Each of the pre-amplifiers 1201 to 120N can generate a read current according to the voltage of a corresponding local bit line of the local bit lines LBL1 to LBLN. Therefore, in FIG. 1, the local bit lines LBL1 to LBLN are not coupled to the same node directly. Also, the pre-amplifiers 1201 to 120N can help to amplify the cell currents generated by the memory cells MC(1,1) to MC(M,N), thereby increasing the reading speed.
  • Each of the pre-amplifiers 1201 to 120N can be coupled to a corresponding local bit line and a corresponding main bit line. For example, the pre-amplifier 1201 can be coupled to the local bit line LBL1 and the main bit line MBL1 while the pre-amplifier 120N can be coupled to the local bit line LBLN and the main bit line MBLN. In this case, the pre-amplifier 1201 can generate a read current IR1 on the main bit line MBL1 according to the voltage of the local bit line LBL1 during sample operations and sense operations of the memory cells MC(1,1) to MC(M,1), and the pre-amplifier 120N can generate a read current on the main bit line MBLN according to a voltage of the local bit line LBLN during sample operations and sense operations of the memory cells MC(1,N) to MC(M,N).
  • In addition, the reset units 1101 to 110N can each be coupled to a corresponding local bit line of the local bit lines LBL1 to LBLN. For example, the reset unit 1101 can be coupled to the local bit line LBL1, and the reset unit 110N can be coupled to the local bit line LBLN. The reset units 1101 to 110N can reset the local bit lines LBL1 to LBLN to a first system voltage VS1 during the sample operations before the sense operations, allowing the sense amplification circuit 100 to generate suitable reference currents during the sense operations according to the self-biased voltages obtained during the sample operations.
  • Furthermore, in order to sense the read currents generated by the pre-amplifiers 1201 to 120N with the same sense amplifier 150, the path selector 140 can be coupled between the main bit lines MBL1 to MBLN and the data line DL. In some embodiments, during the sample operations and the sense operations of the memory cells MC(1,1) to MC(M,1), the path selector 140 can form an electrical connection between the main bit line MBL1 and the data line DL, and during the sample operations and the sense operations of the memory cells MC(1,N) to MC(M,N), the path selector 140 can form an electrical connection between the main bit line MBLN and the data line DL. Consequently, the data line DL will be coupled to the corresponding main bit line of the main bit lines MBL1 to MBLN during the sample operation and the sense operation of the corresponding memory cell of the memory cells MC(1,1) to MC(M,N).
  • In FIG. 1, the sample reference unit 130 and the sense amplifier 150 can be coupled to the data line DL. In some embodiments, when the memory cell MC(1,1) is requested to be read, a sample operation and a sense operation can be performed. During the sample operation, the reset unit 1101 can reset the local bit line LBL1 to the first system voltage VS1, and the pre-amplifier 1201 would generate the read current IR1. In this case, the sample reference unit 130 can generate the first reference current Iref1 and the second reference current Iref2 according to the read current IR1 and the self-biased reference control voltage VC.
  • Also, the sample reference unit 130 can also record the reference control voltage VC during the sample operation, so during the sense operation after the sample operation, the sample reference unit 130 can generate the first reference current Iref1 according to the reference control voltage VC. In addition, during the sense operation, the reset unit 1101 can stop resetting the local bit line LBL1, so the cell current IC1 generated by the memory cell MC(1,1) may charge the local bit line LBL1. In some embodiments, if the memory cell MC(1,1) is, for example but not limited to, in a programmed state, then the memory cell MC(1,1) would generate a significant cell current IC1 and the voltage of the local bit line LBL1 would be raised. However, if the memory cell MC(1,1) is not programmed (namely, in an erased state), then the cell current IC1 generated by the memory cell MC(1,1) would be zero or insignificant, so the voltage of the local bit line LBL1 would remain close to the first system voltage VS1. In this case, the pre-amplifier 1201 can generate the read current IR1 according to the voltage of the local bit line LBL1, and the voltage of the data line DL would be determined by the competition between the read current IR1 and the first reference current Iref1. Consequently, the sense amplifier 150 can sense the voltage of the data line DL and output a data signal SIGD accordingly during the sense operation. Since the reference control voltage VC used for generating the first reference current Iref1 during the sense operation is obtained in a self-biased condition during the sample operation, the reference current Iref1 generated by the sample reference unit 130 should be a good reference for identifying the data stored in the memory cell MC(1,1).
  • In FIG. 1, each of the pre-amplifiers 1201 to 120N can include an amplifying transistor TA1. The amplifying transistor TA1 has a first terminal for receiving a second system voltage VDD, a second terminal coupled to a corresponding main bit line of the main bit lines MBL1 to MBLN, and a control terminal coupled to a corresponding local bit line of the local bit lines LBL1 to LBLN.
  • Also, the sample reference unit 130 includes a switch unit 132, a capacitor 134, a first control transistor TC1, at least one first reference transistor TR1, a second control transistor TC2, and at least one second reference transistor TR2.
  • The switch unit 132 has a first terminal coupled to the data line DL, and a second terminal. In FIG. 1, the switch unit 132 can include an N-type transistor TN1 and a P-type transistor TP1. The N-type transistor TN1 has a first terminal coupled to the first terminal of the switch unit 132, a second terminal coupled to the second terminal of the switch unit 132, and a control terminal for receiving a first switch signal SIGSW1. The P-type transistor TP1 has a first terminal coupled to the first terminal of the switch unit 132, a second terminal coupled to the second terminal of the switch unit 132, and a control terminal for receiving a second switch signal SIGSW2. In some embodiments, the first switch signal SIGSW1 and the second switch signal SIGSW2 can be complementary so that the N-type transistor TN1 and the P-type transistor TP1 can be turned on and turned off in a synchronous manner. However, in some embodiments, the switch unit 132 may omit the N-type transistor TN1 or the P-type transistor TP1 according to the system requirement.
  • The capacitor 134 has a first terminal A1 coupled to the second terminal of the switch unit 132, and a second terminal for receiving the first system voltage VS1. The first control transistor TC1 has a first terminal coupled to the data line DL, a second terminal, and a control terminal for receiving a first control signal SIGC1. Each of the at least one first reference transistor TR1 has a first terminal coupled to the second terminal of the first control transistor TC1, a second terminal for receiving the first system voltage VS1, and a control terminal coupled to the first terminal A1 of the capacitor 134. The second control transistor TC2 has a first terminal coupled to the data line DL, a second terminal, and a control terminal for receiving a second control signal SIGC2. Each of the at least one second reference transistor TR2 has a first terminal coupled to the second terminal of the second control transistor TC2, a second terminal for receiving the first system voltage VS1, and a control terminal coupled to the first terminal A1 of the capacitor 134.
  • Furthermore, the sample reference unit 130 can further include a reset transistor TRS1 . The reset transistor TRS1 has a first terminal coupled to the data line DL, a second terminal for receiving a reset voltage VRST, and a control terminal for receiving a reset signal SIGRST0. The reset signal SIGRST0 can turn on the reset transistor TRS1 during a reset operation, so that the data line DL can be reset to the reset voltage VRST after the reset operation is performed. In some embodiments, the reset voltage VRST can be, for example but not limited to, substantially equal to the first system voltage VS1. Also, the reset signal SIGRST0 can turn off the reset transistor TRS1 during the sample operation and the sense operation.
  • In FIG. 1, each of the reset units 1101 to 110N can include a reset transistor TRS2. The reset transistor TRS2 has a first terminal coupled to a corresponding local bit line of the local bit lines LBL1 to LBLN, a second terminal for receiving the first system voltage VS1, and a control terminal for receiving a corresponding reset signal of the reset signal SIGRST1 to SIGRSTN.
  • FIG. 2 shows the timing diagram of the signals received by the sense amplification circuit for reading the data stored in the memory cell MC(1,1) . In FIG. 2, the reset operation can be performed during a period S0 before the sample operation and the sense operation. During the reset operation, the reset signal SIGRST0 can be at a high voltage, for example but not limited to the second system voltage VDD, for turning on the reset transistor TRS1 to reset the data line DL.
  • During a period S1, the sample operation is performed. During the sample operation, the reset signal SIGRST1 is at a high voltage for turning on the reset transistor TRS2 of the reset unit 1101, so the local bit line LBL1 can be reset to the first system voltage VS1 and the pre-amplifier 1201 can generate the read current IR1, simulating the condition of zero cell current, that is, the erased state. Also, the first control signal SIGC1 and the second control signal SIGC2 can be at the high voltage for turning on the first control transistor TC1 and the second control transistor TC2. Furthermore, the first switch signal SIGSW1 can be at the high voltage and the second switch signal SIGSW2 can be at a low voltage, so the switch unit 132 can form an electrical connection between the data line DL and the first terminal A1 of the capacitor 134.
  • In this case, the read current IR1 can charge the capacitor 134 during the sample operation. Also, as the voltage of the first terminal A1 of the capacitor 134 is raised, the at least one first reference transistor TR1 and the at least one second reference transistor TR2 will be turned on. Since the first control transistor TC1 and the second control transistor TC2 are also turned on, the read current IR1 will mainly flow through a low impedance path formed by the first control transistor TC1 and the at least one first reference transistor TR1 and another low impedance path formed by the second control transistor TC2 and the at least one second reference transistor TR2. In this case, the at least one first reference transistor TR1 and the at least one second reference transistor TR2 can be self-biased by the end of the sample operation, and the self-biased reference control voltage VC can be recorded by the capacitor 134. Since the reference control voltage VC is obtained under a self-biased condition, the variations of the pre-amplifiers 1201 to 120N and the control transistors TC1 and TC2 can all be compensated automatically during the sample operations, making the reference control voltage VC suitable for generating the reference current Iref1 for the sense operation.
  • During a period S2, the sense operation is performed. During the sense operation, the second reset signal SIGRST1 is at the low voltage for turning off the reset transistor TRS2, so the reset unit 1101 would stop resetting the local bit line LBL1 to the first system voltage VS1. In this case, the cell current IC1 generated by the memory cell MC(1,1) will start to charge the local bit line LBL1, and the pre-amplifier 1201 would generate the read current IR1 accordingly. For example, if the memory cell MC(1,1) is in a programmed state, then the local bit line LBL1 may be charged to a higher voltage by the cell current IC1, and the read current IR1 generated by pre-amplifier 1201 would decrease. However, if the memory cell MC(1,1) is in the erased state, then the current cell IC1 generated by the memory cell MC(1,1) would be rather small, so the local bit line LBL1 would be at the first system volte VS1 or remain close to the first system volte VS1, and the read current IR1 generated by pre-amplifier 1201 would remain high.
  • Also, the first control signal SIGC1 can be at the high voltage for turning on the first control transistor TC1 while the second control signal SIGC2 can be at the low voltage for turning off the second control transistor TC2. Furthermore, the first switch signal SIGSW1 can be at the low voltage and the second switch signal SIGSW2 can be at the high voltage, so the switch unit 132 can cut off the electrical connection between the data line DL and the first terminal Al of the capacitor 134. In this case, the at least one first reference transistor TR1 can be turned on according to the reference control voltage VC recorded by the capacitor 134, so the first reference current Iref1 can be generated during the sense operation. In this case, the voltage of the data line DL would be determined by the competition between the read current IR1 generated by the pre-amplifier 1201 and the first reference current Iref1 generated by the at least one first reference transistor TR1.
  • In some embodiments, since the sum of the first reference current Iref1 and the second reference current Iref2 should be substantially equal to the read current IR1 by the end of the sample operation, the first reference current Iref1 generated according to the same reference control voltage VC during sense operation should be smaller than the read current IR1 if the memory cell MC(1,1) is in the erased state. Also, the first reference current Iref1 should be greater than the read current IR1 if the memory cell MC(1,1) is in the programmed state. Therefore, by sensing the voltage at the data line DL, the state of the memory cell MC(1,1) can be determined, and the data stored in the memory cell MC(1,1) can be read.
  • For example, if the memory cell MC(1,1) is in the programmed state, then the read current IR1 should be smaller than the first reference current Iref1, so the voltage of the data line DL will drop to the first system voltage VS1. However, if the memory cell MC(1,1) is in the erased state, then the read current IR1 should be greater than the first reference current Iref1, so the voltage of the data line DL will be raised to the second system voltage VDD.
  • That is, by obtaining the reference control voltage VC for the at least one first reference transistor TR1 and the at least one second reference transistor TR2 under the condition of zero cell current during the sample operation, the reference current Iref1 generated according to the same reference control voltage VC during the sense operation would be a good comparing basis for determining the state of the memory cell MC(1,1).
  • Furthermore, in some embodiments, the ratio between the first reference current Iref1 and the second reference current Iref2 can be adjusted according to the system requirement by adjusting the number of the first reference transistor TR1 and the second reference transistor TR2. For example, in one embodiment, the sample reference unit 130 may include nine first reference transistors TR1 and one second reference transistor TR2. In this case, the first reference current Iref1 used for the sense operation would be substantially equal to 90% of the read current IR1 obtained during the sample operation under the zero cell current condition, allowing the sense amplifier 150 to determine the result with a higher speed and better accuracy. However, in some other embodiments, the number of the first reference transistors TR1 and the number of the second reference transistors TR2 can be determined according to the system requirement.
  • In FIG. 1, the sense amplifier 150 can be a single ended amplifier. In this case, the input terminal of the sense amplifier 150 can be coupled to the data line DL, and the output terminal of the sense amplifier 150 can output a data signal SIGD. However, in some other embodiments, the sense amplifier 150 can be a differential amplifier.
  • FIG. 3 shows a sense amplification circuit 200 according to one embodiment of the present invention. The sense amplification circuit 200 and the sense amplification circuit 100 have similar structures and can be operated with similar principles. However, the sense amplifier 250 of the sense amplification circuit 200 is a differential amplifier. In this case, the first input terminal of the sense amplifier 250 can be coupled to the data line DL, the second input terminal of the sense amplifier 250 can be coupled to the first terminal A1 of the capacitor 134, and an output terminal of the sense amplifier 250 can output a data signal SIGD.
  • In addition, in FIG. 3, the path selector 240 can have a first terminal for receiving a second system voltage VDD, and second terminals coupled to the pre-amplifiers 2101 to 210N. The path selector 240 can form an electrical connection between the first terminal and one of the second terminals of the path selector 240 during the sample operation and the sense operation. In this case, the second terminals of the pre-amplifiers 2201 to 220N can be coupled to the same main bit line MBL, and main bit line MBL can be coupled to the data bit line DL directly. That is, the connection of the path selector 140 can be adjusted as the path selector 240 according to the system requirement.
  • In summary, the sense amplification circuits provided by the embodiments of the present invention can obtain the reference control voltage for generating the reference currents in a self-biased condition during the sample operation, so the variations of the pre-amplifiers and the control transistors can be compensated automatically during the sample operations. Therefore, the reference current generated by the sample reference unit during the sample operation can be a good reference for identifying the data stored in the memory cells, allowing the sense amplification circuits to read the data of the memory cells with a higher speed and better accuracy.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (13)

What is claimed is:
1. A self-biased sense amplification circuit comprising:
a local bit line coupled to a memory cell, and configured to receive a cell current generated by the memory cell during a sense operation;
a reset unit coupled to the local bit line, and configured to reset the local bit line to a first system voltage during a sample operation;
a main bit line;
a pre-amplifier coupled to the local bit line and the main bit line, and configured to generate a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation;
a data line coupled to the main bit line during the sample operation and the sense operation;
a sample reference unit coupled to the data line, and configured to generate a first reference current and a second reference current and record a reference control voltage during the sample operation and generate the first reference current according to the reference control voltage during the sense operation; and
a sense amplifier coupled to the data line, and configured to sense a voltage of the data line during the sense operation.
2. The self-biased sense amplification circuit of claim 1, wherein the sample reference unit comprises:
a switch unit having a first terminal coupled to the data line, and a second terminal;
a capacitor having a first terminal coupled to the second terminal of the switch unit, and a second terminal configured to receive the first system voltage;
a first control transistor having a first terminal coupled to the data line, a second terminal, and a control terminal configured to receive a first control signal;
at least one first reference transistor each having a first terminal coupled to the second terminal of the first control transistor, a second terminal configured to receive the first system voltage, and a control terminal coupled to the first terminal of the capacitor;
a second control transistor having a first terminal coupled to the data line, a second terminal, and a control terminal configured to receive a second control signal; and
at least one second reference transistor each having a first terminal coupled to the second terminal of the second control transistor, a second terminal configured to receive the first system voltage, and a control terminal coupled to the first terminal of the capacitor.
3. The self-biased sense amplification circuit of claim 2, wherein during the sample operation:
the first control signal is configured to turn on the first control transistor;
the second control signal is configured to turn on the second control transistor; and
the switch unit is configured to form an electrical connection between the data line and the first terminal of the capacitor.
4. The self-biased sense amplification circuit of claim 2, wherein during the sense operation:
the first control signal is configured to turn on the first control transistor;
the second control signal is configured to turn off the second control transistor;
the switch unit is configured to cut off the electrical connection between the data line and the first terminal of the capacitor; and
the reset unit is further configured to stop resetting the local bit line to the first system voltage.
5. The self-biased sense amplification circuit of claim 2, wherein the switch unit comprises:
an N-type transistor having a first terminal coupled to the first terminal of the switch unit, a second terminal coupled to the second terminal of the switch unit, and a control terminal configured to receive a first switch signal.
6. The self-biased sense amplification circuit of claim 5, wherein the switch unit further comprises:
a P-type transistor having a first terminal coupled to the first terminal of the switch unit, a second terminal coupled to the second terminal of the switch unit, and a control terminal configured to receive a second switch signal;
wherein the first switch signal and the second switch signal are complementary.
7. The self-biased sense amplification circuit of claim 2, wherein the sample reference unit further comprises a first reset transistor having a first terminal coupled to the data line, a second terminal configured to receive a reset voltage, and a control terminal configured to receive a first reset signal, and the first reset signal is configured to turn on the first reset transistor during a reset operation and turn off the first reset transistor during the sample operation and the sense operation.
8. The self-biased sense amplification circuit of claim 2, wherein the sense amplifier is a differential amplifier having a first input terminal coupled to the data line, a second input terminal coupled to the first terminal of the capacitor, and an output terminal configured to output a data signal.
9. The self-biased sense amplification circuit of claim 1, wherein the sense amplifier is a single ended amplifier having an input terminal coupled to the data line, and an output terminal configured to output a data signal.
10. The self-biased sense amplification circuit of claim 1 further comprising a path selector coupled between the main bit line and the data line, and configured to form an electrical connection between the main bit line and the data line during the sample operation and the sense operation.
11. The self-biased sense amplification circuit of claim 1 further comprising a path selector having a first terminal configured to receive a second system voltage, and a second terminal coupled to the pre-amplifier, and configured to form an electrical connection between the first terminal and the second terminal of the path selector during the sample operation and the sense operation;
wherein the main bit line and the data bit line are directly coupled.
12. The self-biased sense amplification circuit of claim 1, wherein the pre-amplifier comprises an amplifying transistor having a first terminal configured to receive a second system voltage during the sample operation and the sense operation, a second terminal coupled to the main bit line, and a control terminal coupled to the local bit line.
13. The self-biased sense amplification circuit of claim 1, wherein the reset unit comprises a second reset transistor having a first terminal coupled to the local bit line, a second terminal configured to receive the first system voltage, and a control terminal configured to receive a second reset signal.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit
KR20220145223A (en) * 2021-04-21 2022-10-28 삼성전자주식회사 Processing element and electronic device including processing element
KR20230045690A (en) * 2021-09-27 2023-04-05 삼성전자주식회사 Semiconductor memory device of 2T-1C structure and method of fabricating the same
US12014796B2 (en) 2022-02-11 2024-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method of operating the same
US11901004B2 (en) * 2022-04-08 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array, memory structure and operation method of memory array

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2968906B2 (en) * 1992-04-07 1999-11-02 三菱電機株式会社 Nonvolatile semiconductor memory device
JPH06325582A (en) * 1993-05-12 1994-11-25 Rohm Co Ltd Non-volatile storage device
TW336319B (en) * 1997-05-12 1998-07-11 Powerchip Semiconductor Corp Method for reducing cell plate noises and circuit thereof
KR100335767B1 (en) * 1999-12-29 2002-05-09 박종섭 Flash memory device
US8164362B2 (en) 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6445216B1 (en) 2001-05-14 2002-09-03 Intel Corporation Sense amplifier having reduced Vt mismatch in input matched differential pair
US6590807B2 (en) * 2001-08-02 2003-07-08 Intel Corporation Method for reading a structural phase-change memory
US7263001B2 (en) * 2005-03-17 2007-08-28 Impinj, Inc. Compact non-volatile memory cell and array system
US7443708B2 (en) * 2006-03-09 2008-10-28 Texas Instruments Incorporated Low resistance plate line bus architecture
US7269056B1 (en) * 2006-04-27 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Power grid design for split-word line style memory cell
US7436710B2 (en) * 2007-03-12 2008-10-14 Maxim Integrated Products, Inc. EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well
US7995397B1 (en) * 2007-05-03 2011-08-09 Cypress Semiconductor Corporation Power supply tracking single ended sensing scheme for SONOS memories
US8472251B2 (en) * 2008-02-11 2013-06-25 Aplus Flash Technology, Inc. Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device
US7885110B2 (en) * 2008-03-25 2011-02-08 Rao G R Mohan Random access memory with CMOS-compatible nonvolatile storage element and parallel storage capacitor
US7885101B2 (en) 2008-12-29 2011-02-08 Numonyx B.V. Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory
WO2011135999A1 (en) * 2010-04-27 2011-11-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US8355282B2 (en) * 2010-06-17 2013-01-15 Ememory Technology Inc. Logic-based multiple time programming memory cell
US8958245B2 (en) * 2010-06-17 2015-02-17 Ememory Technology Inc. Logic-based multiple time programming memory cell compatible with generic CMOS processes
US8339831B2 (en) * 2010-10-07 2012-12-25 Ememory Technology Inc. Single polysilicon non-volatile memory
KR20130067687A (en) 2011-12-14 2013-06-25 에스케이하이닉스 주식회사 Data sensing circuit and memory device including the same
US8787092B2 (en) * 2012-03-13 2014-07-22 Ememory Technology Inc. Programming inhibit method of nonvolatile memory apparatus for reducing leakage current
US9208826B2 (en) * 2012-03-30 2015-12-08 Sharp Kabushiki Kaisha Semiconductor storage device with two control lines
KR101983274B1 (en) * 2012-05-18 2019-05-30 삼성전자주식회사 PCRAM : Phase Change Random Access Memory device and Method for sensing threrof
US9312014B2 (en) * 2013-04-01 2016-04-12 SK Hynix Inc. Single-layer gate EEPROM cell, cell array including the same, and method of operating the cell array
US9041089B2 (en) * 2013-06-07 2015-05-26 Ememory Technology Inc. Nonvolatile memory structure
US9236453B2 (en) * 2013-09-27 2016-01-12 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
US9171856B2 (en) * 2013-10-01 2015-10-27 Ememory Technology Inc. Bias generator for flash memory and control method thereof
US9275702B2 (en) * 2013-11-29 2016-03-01 The Regents Of The University Of Michigan Memory circuitry including read voltage boost
US9214203B2 (en) * 2014-02-12 2015-12-15 Ememory Technology Inc. Sensing apparatus and data sensing method thereof
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
US9847133B2 (en) * 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation
TWI630623B (en) * 2017-04-07 2018-07-21 力旺電子股份有限公司 Erasable programmable non-volatile memory
US10090309B1 (en) * 2017-04-27 2018-10-02 Ememory Technology Inc. Nonvolatile memory cell capable of improving program performance
US11063772B2 (en) * 2017-11-24 2021-07-13 Ememory Technology Inc. Multi-cell per bit nonvolatile memory unit
KR102167831B1 (en) * 2018-06-21 2020-10-21 윈본드 일렉트로닉스 코포레이션 Memory device and method for test reading and writing thereof
US11282844B2 (en) * 2018-06-27 2022-03-22 Ememory Technology Inc. Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate
US11017862B2 (en) * 2018-12-13 2021-05-25 Ememory Technology Inc. Multi-time programming memory cell and memory cell array with erase inhibit capability
US11152383B2 (en) * 2020-03-03 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory (NVM) cell structure to increase reliability
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit

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