US20210119058A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20210119058A1 US20210119058A1 US17/114,598 US202017114598A US2021119058A1 US 20210119058 A1 US20210119058 A1 US 20210119058A1 US 202017114598 A US202017114598 A US 202017114598A US 2021119058 A1 US2021119058 A1 US 2021119058A1
- Authority
- US
- United States
- Prior art keywords
- work function
- layer
- ferroelectric material
- gate stack
- function layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 247
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000010936 titanium Substances 0.000 claims description 11
- 239000002135 nanosheet Substances 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011777 magnesium Substances 0.000 claims description 6
- 239000010955 niobium Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 4
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052582 BN Inorganic materials 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 2
- QDMRQDKMCNPQQH-UHFFFAOYSA-N boranylidynetitanium Chemical compound [B].[Ti] QDMRQDKMCNPQQH-UHFFFAOYSA-N 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 332
- 238000010586 diagram Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 11
- 150000001875 compounds Chemical class 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- -1 titanium aluminum silicon Chemical compound 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 2
- PTXMVOUNAHFTFC-UHFFFAOYSA-N alumane;vanadium Chemical compound [AlH3].[V] PTXMVOUNAHFTFC-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000004964 aerogel Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium atom Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
Definitions
- the present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor having negative capacitance (NC) using a ferroelectric material.
- NC negative capacitance
- MOSETs metal-oxide semiconductor field-effect transistors
- These semiconductor technologies may include a high dielectric constant (high-k) metal gate (HKMG) technology and a fin field-effect transistor (FinFET) technology.
- HKMG high dielectric constant metal gate
- FinFET fin field-effect transistor
- the HKMG technology improves gate capacitance and reduces leakage current
- the FinFET technology improves a short channel effect (SCE) in which the electric potential of a channel region is affected by a drain voltage.
- SCE short channel effect
- CMOS complementary metal-oxide-semiconductor
- a semiconductor device comprising a first transistor which comprises a first gate stack on a substrate; and a second transistor which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer comprises the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
- a semiconductor device comprising a first transistor which comprises a first gate stack on a substrate; and a second transistor which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first ferroelectric material layer disposed on the substrate, a first work function layer contacting the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second ferroelectric material layer disposed on the substrate, a second work function layer contacting the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first ferroelectric material layer and the second ferroelectric material layer comprise the same material, wherein a thickness of the first ferroelectric material layer is equal to a thickness of the second ferroelectric material layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
- a semiconductor device comprising a first negative capacitance field-effect transistor (NCFET) which comprises a first gate stack on a substrate; and a second NCFET which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first interfacial layer disposed on the substrate, a first gate insulating layer disposed on the first interfacial layer, a first work function layer disposed on the first gate insulating layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second interfacial layer disposed on the substrate, a second gate insulating layer disposed on the second interfacial layer, a second work function layer disposed on the second gate insulating layer and a second upper gate electrode disposed on the second work function layer, and wherein a structure of the first gate stack is different from a structure of the second gate stack, and wherein an effective work function of the first gate stack is different from an effective work function of
- FIG. 1 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 2 is a perspective view of a first fin transistor illustrated in FIG. 1 ;
- FIG. 3 is a diagram for explaining an effect of the semiconductor device of FIG. 1 ;
- FIG. 4 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIGS. 5 and 6 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept
- FIGS. 7 and 8 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept.
- FIG. 9 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept.
- FIGS. 10 and 11 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept
- FIGS. 12 and 13 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept
- FIGS. 14 and 15 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept.
- FIG. 16 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept.
- a fin field-effect transistor including a fin pattern-shaped channel region is illustrated by way of example.
- the present inventive concept is not limited to the FinFET.
- the exemplary embodiments of the present inventive concept disclosed herein are applicable to a transistor including a nanowire, a transistor including a nanosheet or a three-dimensional (3D) transistor, in addition, the exemplary embodiments of the present inventive concept disclosed herein are applicable to a planar transistor. It is to be understood that in the drawings, like reference numerals may refer to like elements.
- FIG. 1 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept.
- FIG. 2 is a perspective view of a first fin transistor NF 1 illustrated in FIG. 1 .
- FIG. 3 is a for explaining an effect of the semiconductor device of FIG. 1 .
- first, second and third fin transistors NF 1 , NF 2 and NF 3 are not illustrated in FIGS. 1 and 2 , this is merely for ease of description, and the present inventive concept is not limited thereto.
- the cross section of the first fin transistor NF 1 of FIG. 1 may be a cross section taken along A-A of FIG. 2 .
- the semiconductor device may include the first fin transistor NF 1 , the second fin transistor NF 2 and the third fin transistor NF 3 formed on a substrate 100 .
- Each of the first through third fin transistors NF 1 through NF 3 may be a FinFET using a three-dimensional (3D) channel.
- the first through third fin transistors NF 1 through NF 3 may be transistors of the same conductivity type (e.g., an N type or P type).
- at least one of the first through third fin transistors NF 1 through NF 3 may be a P-type transistor, and the other may be an N-type transistor.
- Each of the first through third fin transistors NF 1 through NF 3 may be a negative capacitance (NC) FET using a negative capacitor.
- the negative capacitor is a capacitor having negative capacitance and may be connected in series to a positive capacitor to increase its capacitance.
- the first through third fin transistors NF 1 through NF 3 which are NCFETs may include an insulating layer having ferroelectric characteristics.
- Each of the first through third fin transistors NF 1 through NF 3 may have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.
- SS subthreshold swing
- first through third fin transistors NF 1 through NF 3 are illustrated as being formed on the substrate 100 , this is merely for ease of description, and the present inventive concept is not limited thereto.
- at least two of the first through third fin transistors NF 1 through NF 3 may be formed on the substrate 100 .
- the first fin transistor NF 1 may include a first fin pattern F 1 , a first gate stack 110 , and first gate spacers 140 .
- the first gate stack 110 may include a first interfacial layer 115 , a first ferroelectric material layer 120 , a first work function layer 125 , a first interposing conductive layer 130 , and a first filling layer 135 .
- the substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Additionally, the substrate 100 may be, but is not limited to, a silicon substrate or a substrate made of another material such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.
- SOI silicon-on-insulator
- the first fin pattern F 1 may protrude from the substrate 100 .
- the first fin pattern F 1 may extend along a first direction X on the substrate 100 .
- the first fin pattern F 1 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100 .
- the first fin pattern F 1 may include an elemental semiconductor material such as silicon or germanium.
- the first fin pattern F 1 may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.
- the group IV-IV compound semiconductor may be, e.g., a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn) or a compound obtained by doping the binary or ternary compound with a group IV element.
- the group III-V compound semiconductor may be, e.g., a binary, ternary, or quaternary compound composed of aluminum (Al), gallium (Ga) or indium (In) (e.g., group III elements) bonded with phosphorus (P), arsenic (As) or antimony (Sb) (e.g., group V elements).
- a field insulating layer 105 may be formed on the substrate 100 .
- the field insulating layer 105 may be formed on part of sidewalls of the first fin pattern F 1 .
- a top surface of the first fin pattern F 1 may protrude above a top surface of the field insulating layer 105 .
- the field insulating layer 105 may include, e.g., a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
- An interlayer insulating film 190 may be disposed on the field insulating layer 105 .
- a first gate trench 140 t may be formed in the interlayer insulating film 190 .
- the first gate trench 1401 may be defined by the first gate spacers 140 .
- the first gate spacers 140 may include, e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), or silicon oxycarbonitride (SiOCN).
- the interlayer insulating film 190 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), toner silazen (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethylorthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO)), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), polyimide, a porous polymeric material, or a combination of the same.
- the first gate stack 110 may be formed in the first gate trench 140 .
- the first gate stack 110 entirely fills the first gate trench 140 t.
- a top surface of the first gate stack 110 lies in the same plane with a top surface of the interlayer insulating film 190 in the drawings, the present inventive concept is not limited thereto.
- a capping pattern may also be formed on the first gate slack 110 to partially fill the first gate trench 140 t.
- a top surface of the capping pattern may lie in the same plane with the top surface of the interlayer insulating film 190 .
- the first interfacial layer 115 may be formed on the substrate 100 .
- the first interfacial layer 115 may be formed on the first fin pattern F 1 .
- the first interfacial layer 115 may directly contact the first fin pattern F 1 .
- the first interfacial layer 115 may be formed in the first gate trench 140 t. Although the first interfacial layer 115 is illustrated as being formed on a bottom surface of the first gate trench 140 t, the present inventive concept is not limited thereto. The first interfacial layer 115 may also be formed on sidewalls of the first gate trench 140 t depending on a manufacturing method.
- the first interfacial layer 115 may include a silicon oxide layer.
- the first interfacial layer 115 may be formed using, but not limited to, a chemical oxidation method, an ultraviolet (UV) oxidation method, or a dual plasma oxidation method.
- the first ferroelectric material layer 120 may be formed on the first interfacial layer 115 .
- the first interfacial layer 115 may be disposed between the first ferroelectric material layer 120 and the first fin pattern F 1 .
- the first ferroelectric material layer 120 may be formed along inner walls of the first gate trench 140 t.
- the first ferroelectric material layer 120 may be formed along the sidewalk and bottom surface of the first gate trench 140 t.
- the first ferroelectric material layer 120 may be formed using, but not limited to, chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the first ferroelectric material layer 120 may have ferroelectric characteristics.
- the first ferroelectric material layer 120 may have a thickness sufficient to have the ferroelectric characteristics.
- the thickness of the first ferroelectric material layer 120 may be, but is not limited to, 3 to 10 nm. Since a critical thickness exhibiting the ferroelectric characteristics may be different for each ferroelectric material, the thickness of the first ferroelectric material layer 120 may vary according to the ferroelectric material.
- the first ferroelectric material layer 120 may include, e.g., hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide.
- hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr) or may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).
- the first ferroelectric material layer 120 may further include a doping element doped in the above-described materials.
- the doping element may be aluminum (Al), titanium (Ti). niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dv), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn).
- the first interfacial layer 115 and the first ferroelectric material layer 120 may be gate insulating layers of the first fin transistor NF 1 .
- the first interfacial layer 115 may be a lower gate insulating layer having a positive capacitance
- the first ferroelectric material layer 120 may be an upper gate insulating layer having a negative capacitance.
- a conductive layer may also be formed between the first interfacial layer 115 and the first ferroelectric material layer 120 .
- a high dielectric constant (high-k) insulating layer and a conductive layer stacked sequentially may be formed between the first interfacial layer 115 and the first ferroelectric material layer 120 .
- the high dielectric constant (high-k) insulating layer may be directly disposed on the first interfacial layer 115 .
- the first work function layer 125 may be formed on the first ferroelectric material layer 120 .
- the first work function layer 125 may be formed along the sidewalls and bottom surface of the first gate trench 140 t.
- the first work function layer 125 may contact the first ferroelectric material layer 120 .
- the first work function layer 125 may include, e.g., titanium nitride (TiN), titanium carbonitride (TiCN), or tungsten carbonitride (WCN).
- the first interposing conductive layer 130 may be formed on the first work function layer 125 .
- the first interposing conductive layer 130 may be formed along the sidewalls and bottom surface of the first gate trench 140 t.
- the first interposing conductive layer 130 may include, e.g., titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), vanadium aluminum carbide (VAlC), titanium aluminum silicon carbide (TiAlSiC), or tantalum aluminum silicon carbide (TaAlSiC).
- TiAl titanium aluminum
- TiAlC titanium aluminum carbide
- TaAlC tantalum aluminum carbide
- VAlC vanadium aluminum carbide
- TiAlSiC titanium aluminum silicon carbide
- TaAlSiC tantalum aluminum silicon carbide
- the first filling layer 135 may be formed on the first interposing conductive layer 130 .
- the first filling layer 135 may fill the first gate trench 140 t.
- the first filling layer 135 may include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), or titanium nitride (TiN).
- the first interposing conductive layer 130 and the first filling layer 135 may be a first upper gate electrode formed on the first work function layer 125 .
- the second fin transistor NF 2 may include a second fin pattern F 2 , a second gate stack 210 , and second gate spacers 240 .
- the second gate stack 210 is formed in a second gate trench 240 t.
- the second gate stack 210 may include a second interfacial layer 215 , a second ferroelectric material layer 220 , a second work function layer 225 , a second interposing conductive layer 230 , and a second tilling layer 235 .
- the second work function layer 225 may be disposed on the second ferroelectric material layer 220 to contact the second ferroelectric material layer 220 .
- the second work function layer 225 may directly contact the second ferroelectric material layer 220 .
- the third fin transistor NF 3 may include a third fin pattern F 3 , a third gate stack 310 , and third gate spacers 340 .
- the third gate stack 310 is formed in a third gate trench 340 t.
- the third gate stack 310 may include a third interfacial layer 315 , a third ferroelectric material layer 320 , a third work function layer 325 , a third interposing conductive layer 330 , and a third filling layer 335 .
- the third work function layer 325 may be disposed on the third ferroelectric material layer 320 to contact the third ferroelectric material layer 320 .
- the third work function layer 325 may directly contact the third ferroelectric material layer 320 .
- the first through third fin patterns F 1 through F 3 may be, but are not necessarily, made of the same material and have the same thickness.
- the first through third interfacial layers 115 through 315 may be, but are not necessarily, made of the same material.
- the first through third interposing conductive layers 130 through 330 may be, but are not necessarily, made of the same material, and the first through third filling layers 135 through 335 may be, but are not necessarily, made of the same material.
- the first through third ferroelectric material layers 120 through 320 may include the same material.
- the first through third work function layers 125 through 325 may be made of the same material.
- a thickness a t 11 of the first ferroelectric material layer 120 may be equal to a thickness t 12 of the second ferroelectric material layer 220 and a thickness t 13 of the third ferroelectric material layer 320 .
- a thickness t 22 of the second work function layer 225 is greater than a thickness t 21 of the first work function layer 125 and smaller than a thickness t 23 of the third work function layer 325 .
- the upper gate electrodes of the first, second and third gate structures 110 , 210 and 310 may have different sizes.
- an effective work function eWF 1 of the first gate stack 110 may be different from each other.
- an effective work function eWF 2 of the second gate stack 210 may be different from each other.
- an effective work function eWF 3 of the third gate stack 310 may be different from each other.
- the effective work functions eWF 1 through eWF 3 of the first through third agate stacks 110 through 310 may be different from each other.
- gate stacks when gate stacks have different structures, it may mean that materials included (e.g., doped) in ferroelectric material layers of the gate stacks are different from each other or that materials included in work function layers of the gate stacks are different from each other.
- the gate stacks when the gate stacks have different structures, it may mean that thicknesses of the work function layers are different from each other. In other words, if the types and presence or absence of the materials doped in the ferroelectric material layers, the materials included in the work function layers, or the thicknesses of the work function layers are different from each other, it can be said that the gate stacks have different structures.
- the effective work functions eWF 1 through eWF 3 of the first through third gate stacks 110 through 310 can be adjusted by adjusting the thickness t 21 of the first work function layer 125 , the thickness t 22 of the second work function layer 225 and the thickness 123 of the third work function layer 325 .
- the thickness t 21 of the first work function layer 125 and the thickness t 22 of the second work function layer 225 are the same, the effective work functions eWF 1 and eWF 2 of the first and second gate stacks 110 and 210 might be the same.
- first through third fin transistors NF 1 through NF 3 are of the same conductivity type, they may have different threshold voltages.
- the first through third work function layers 125 through 325 may include, for example, a titanium nitride (TiN) layer.
- the effective work function of a gate stack may increase.
- the effective work function eWF 2 of the second gate stack 210 is greater than the effective work function eWF 1 of the first gate stack 110 and smaller than the effective work function eWF 3 of the third gate stack 310 .
- FIG. 4 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 1 through 3 will be mainly described below.
- the semiconductor device may include a first fin transistor NF 1 , a second fin transistor NF 2 , a third fin transistor NF 3 and a fourth fin transistor NF 4 formed on a substrate 100 .
- the fourth fin transistor NF 4 may be an NCFET.
- the fourth fin transistor NF 4 may include a fourth fin pattern F 4 , a fourth gate stack 410 , and fourth gate spacers 440 .
- the fourth gate stack 410 is formed in a fourth gate trench 440 t.
- the fourth gate stack 410 may include a fourth interfacial layer 415 , a fourth ferroelectric material layer 420 , a fourth interposing conductive layer 430 , and a fourth filling layer 435 .
- the fourth gate stack 410 may not include a work function layer like the first through third gate stacks 110 through 310 .
- the fourth ferroelectric material layer 420 may include the same material as a first ferroelectric material layer 120 .
- a thickness t 14 of the fourth ferroelectric material layer 420 may be equal to a thickness t 11 of the first ferroelectric material layer 120 .
- an effective work function of the fourth gate stack 410 may be smaller than that of the first gate stack 110 .
- FIGS. 5 and 6 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 1 through 3 will be mainly described below.
- FIG. 5 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 6 is a diagram for explaining an effect of the semiconductor device of FIG. 5 .
- the semiconductor device may include a first fin transistor NF 1 , a fifth fin transistor NF 5 and a sixth fin transistor NF 6 formed on a substrate 100 .
- the first fin transistor NF 1 , the fifth fin transistor NF 5 and the sixth fin transistor NF 6 may be, but are not necessarily, of the same conductivity type.
- Each of the fifth fin transistor NF 5 and the sixth fin transistor NF 6 may be an NCFET.
- first fin transistor NF 1 , the fifth fin transistor NF 5 and the sixth fin transistor NF 6 are illustrated as being formed on the substrate 100 , this is merely for ease of description, and the present inventive concept is not limited thereto.
- at least two of the first fin transistor NF 1 , the fifth fin transistor NE 5 and the sixth fin transistor NF 6 may be formed on the substrate 100 .
- the fifth fin transistor NF 5 may include a fifth fin pattern F 5 , a fifth gate stack 510 , and fifth gate spacers 540 .
- the fifth gate stack 510 is formed in a fifth gate trench 540 t.
- the fifth gate stack 510 may include a fifth interfacial layer 515 , a fifth ferroelectric material layer 520 , a fifth work function layer 525 , a fifth interposing conductive layer 530 , and a fifth filling layer 535 .
- the fifth work function layer 525 may be disposed on the fifth ferroelectric material layer 520 to contact the fifth ferroelectric material layer 520 .
- the sixth fin transistor NF 6 may include a sixth fin pattern F 6 , a sixth gate stack 610 , and sixth gate spacers 640 .
- the sixth gate stack 610 is formed in a sixth gate trench 640 t.
- the sixth gate stack 610 may include a sixth interfacial layer 615 , a sixth ferroelectric material layer 620 , a sixth work function layer 625 , a sixth interposing conductive layer 630 , and a sixth filling layer 635 .
- the sixth work function layer 625 may be disposed on the sixth ferroelectric material layer 620 to contact the sixth ferroelectric material layer 620 .
- the first fin pattern F 1 , the fifth fin pattern F 5 and the sixth fin pattern F 6 may be, but are not necessarily, made of the same material to have the same thickness.
- a first interfacial layer 115 , the fifth interfacial layer 515 and the sixth interfacial layer 615 may be, but are not necessarily, made of the same material.
- a first interposing conductive layer 130 , the fifth interposing conductive layer 530 and the sixth interposing conductive layer 630 may be, but are not necessarily, made of the same material, and a first filling layer 135 , the fifth filling layer 535 and the sixth filling layer 635 may be, but are not necessarily, made of the same material.
- a first work function layer 125 , the fifth work function layer 525 and the sixth work function layer 625 may include the same material.
- a thickness t 21 of the first work function layer 125 may be equal to a thickness t 25 of the fifth work function layer 525 and a thickness t 26 of the sixth work function layer 625 .
- a first ferroelectric material layer 120 , the fifth ferroelectric material layer 520 and the sixth ferroelectric material layer 620 may include the same metal oxide.
- the first ferroelectric material layer 120 , the fifth ferroelectric material layer 520 and the sixth ferroelectric material layer 620 may include hafnium (Hf).
- the first ferroelectric material layer 120 , the fifth ferroelectric material layer 520 and the sixth ferroelectric material layer 620 may include hafnium oxide.
- the fifth ferroelectric material layer 520 may include a doped first work function material
- the sixth ferroelectric material layer 620 may include a doped second work function material.
- the first ferroelectric material layer 120 may not include the first work function material and the second work function material.
- the first work function material may be a control material that reduces an effective work function.
- the first work function material may include, for example, lanthanum (La), magnesium (Mg), or yttrium (Y).
- the fifth ferroelectric material layer 520 may include doped nitrogen (N) in addition to the first work function material.
- the second work function material may be a control material that increases an effective work function.
- the second work function material may include, for example, aluminum (Al), titanium (Ti), or niobium (Nb).
- the sixth ferroelectric material layer 620 may include doped nitrogen (N) in addition to the second work function material.
- a work function material may form a dipole within a ferroelectric material layer, thereby changing the effective work function of a gate stack including the ferroelectric material layer.
- a work function material supply layer After a work function material supply layer is formed on a ferroelectric material layer, it may be treated with heat to diffuse a work function material into the ferroelectric material layer.
- the thickness of a ferroelectric material layer including a work function material may be equal to or greater than the thickness of a ferroelectric material layer not including the work function material.
- the structure of a first gate stack 110 may be different from the structure of the fifth gate stack 510 and the structure of the sixth gate stack 610 .
- the fifth ferroelectric material layer 520 includes the first work function material and the sixth ferroelectric material layer 620 includes the second work function material, the structure of the fifth gate stack 510 may be different from that of the sixth gate stack 610 .
- an effective work function eWF 1 of the first gate stack 110 may be different from each other.
- the of work function eWF 1 of the first gate stack 110 may be less than the effective work function eWF 6 of the sixth gate stack 610 and greater than the effective work function eWF 5 of the fifth gate stack 510 .
- each of the effective work function eWF 1 of the first gate stack 110 , the effective work function eWF 5 of the fifth gate stack 510 and the effective work function eWF 6 of the sixth gate stack 610 may be adjusted according, to the presence or absence of a work function material doped in the ferroelectric material layer and the type of the work function material doped in the ferroelectric material layer.
- the first fin transistor NF 1 , the fifth fin transistor NF 5 and the sixth fin transistor NF 6 are of the same conductivity type, they may have different threshold voltages.
- the effective work function eWF 1 of the first gate stack 110 is greater than the effective work function eWF 5 of the fifth gate stack 510 and smaller than the effective work function eWF 6 of the sixth gate stack 610 .
- FIGS. 7 and 8 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 1 through 3 will be mainly described below.
- FIG. 7 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 8 is a diagram for explaining an effect of the semiconductor device of FIG. 7 .
- the semiconductor device may include a first fin transistor NF 1 , a seventh fin transistor NF 7 and an eighth fin transistor NF 8 formed on a substrate 100 .
- the first fin transistor NF 1 , the seventh fin transistor NF 7 and the eighth fin transistor NF 8 may be, but are not necessarily, of the same conductivity type.
- Each of the seventh fin transistor NF 7 and the eighth fin transistor NF 8 may be an NCFET.
- first fin transistor NF 1 , the seventh fin transistor NF 7 and the eighth fin transistor NF 8 are illustrated as being formed on the substrate 100 , this is merely for ease of description, and the present inventive concept is not limited thereto.
- at least two of the first fin transistor NF 1 , the seventh fin transistor NF 7 and the eighth fin transistor NF 8 may be formed on the substrate 100 .
- the seventh fin transistor NF 7 may include a seventh fin pattern F 7 , a seventh gate stack 710 , and seventh gate spacers 740 .
- the seventh gate stack 710 is formed in a seventh gate trench 740 t.
- the seventh gate stack 710 may include a seventh interfacial layer 715 , a seventh ferroelectric material layer 720 , a seventh work function layer 725 , a seventh interposing conductive layer 730 , and a seventh filling layer 735 .
- the seventh work function layer 725 may be disposed on the seventh ferroelectric material layer 720 to contact the seventh ferroelectric material layer 720 .
- the eighth fin transistor NF 8 may include an eighth fin pattern F 8 , an eighth gate stack 810 , and eighth gate spacers 840 .
- the eighth gate stack 810 is formed in an eighth gate trench 840 t.
- the eighth gate stack 810 may include an eighth interfacial layer 815 , an eighth ferroelectric material layer 820 , an eighth work function layer 825 , an eighth interposing conductive layer 830 , and an eighth filling layer 835 .
- the eighth work function layer 825 may be disposed on the eighth ferroelectric material layer 820 to contact the eighth ferroelectric material layer 820 .
- the first fin pattern F 1 , the seventh fin pattern F 7 and the eighth fin pattern F 8 may be, but are not necessarily, made of the same material and have the same thickness.
- a first interfacial layer 115 , the seventh interfacial layer 715 and the eighth interfacial layer 815 may be, but are not necessarily, made of the same material.
- a first interposing, conductive layer 130 , the seventh interposing conductive layer 730 and the eighth interposing conductive layer 830 may be, but are not necessarily, made of the same material, and a first filling layer 135 , the seventh filling layer 735 and the eighth filling layer 835 may be, but are not necessarily, made of the same material.
- a first ferroelectric material layer 120 , the seventh ferroelectric material layer 720 and the eighth ferroelectric material layer 820 may include the same material.
- a thickness t 11 of the first ferroelectric material layer 120 may be equal to a thickness t 17 of the seventh ferroelectric material layer 720 and a thickness t 18 of the eighth ferroelectric material layer 820 .
- a first work function layer 125 , the seventh work function layer 725 and the eighth work function layer 825 may include different materials.
- the seventh work function layer 725 may include a material having a work function smaller than that of the first work function layer 125 .
- the eighth work function layer 825 may include a material having a work function greater than that of the first work function layer 125 .
- the seventh work function layer 725 may include, for example, tungsten (W) titanium silicon nitride (TiSiN) titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), or tantalum nitride (TaN).
- W tungsten
- TiSiN titanium silicon nitride
- TiAlN titanium aluminum nitride
- TiBN titanium boron nitride
- TaN tantalum nitride
- the eighth work function layer 82 may include, for example, platinum Pt), iridium (Ir), ruthenium (Ru), molybdenum nitride (MoN), or molybdenum (Mo).
- the structure of a first gate stack 110 , the structure of the seventh gate stack 710 , and the structure of the eighth gate stack 810 may be different from each other.
- an effective work function eWF 1 of the first gate stack 110 may be different from each other.
- the effective work function eWF 1 of the first gate stack 110 may be less than the effective work function eWF 8 of the eighth gate stack 810 and greater than the effective work function eWF 7 of the seventh gate stack 710 .
- each of the effective work function eWF 1 of the first gate stack 110 , the effective work function eWF 7 of the seventh gate stack 710 and the effective work function eWF 8 of the eighth gate stack 810 may be adjusted according to the type of the work function layer.
- the seventh fin transistor NF 7 and the eighth fin transistor NF 8 are of the same conductivity type, they may have different threshold voltages.
- the effective work function eWF 1 of the first gate stack 110 is greater than the effective work function eWF 7 of the seventh gate stack 710 and smaller than the effective work function eWF 8 of the eighth gate stack 810 .
- the thickness of the seventh work function layer 725 or the thickness of the eighth work function layer 825 it is possible to form a gate stack having various effective work functions.
- FIG. 9 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 1 through 3 will be mainly described below.
- the semiconductor device according to the exemplary embodiments of the present inventive concept may further include a fourth fin transistor NF 4 .
- a fourth gate stack 410 may include a fourth interposing conductive layer 430 .
- the fourth interposing conductive layer 430 may be a material having a work function smaller than that of a seventh work function layer 725 .
- an effective work function of the fourth gate stack 410 may be smaller than that of a seventh gate stack 710 .
- the fourth gate stack 410 may also include a fourth work function layer containing a material whose work function is lower than that of the seventh work function layer 725 .
- the fourth work function layer may include, e.g., titanium aluminum (TiAl), titanium aluminum carbide (TiAlC) tantalum aluminum carbide (TaAlC), vanadium aluminum carbide (VAlC) titanium aluminum silicon carbide (TiAlSiC), or tantalum aluminum silicon carbide (TaAlSiC).
- FIGS. 10 and 11 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 5 and 6 will be mainly described below.
- FIG. 10 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 11 is a diagram for explaining an effect of the semiconductor device of FIG. 10 .
- the semiconductor device may include a first fin transistor. NF 1 , a second fin transistor NF 2 , a fifth fin transistor NF 5 and a sixth fin transistor NF 6 formed on a substrate 100 .
- an effective work function eWF 1 of a first gate stack 110 and an effective work function eWF 2 of a second gate stack 210 may be different from each other.
- the effective work function eWF 1 of the first gate stack 110 and the effective work function eWF 2 of the second gate stack 210 can be changed by changing the thickness of the work function layer.
- each of an effective work function eWF 5 of a fifth gate stack 510 and an effective work function eWF 6 of a sixth gate stack 610 may be different from each other.
- the effective work function eWF 5 of the fifth gate stack 510 and the effective work function eWF 6 of the sixth gate stack 610 can be changed by doping each of a fifth ferroelectric material layer 520 and a sixth ferroelectric material layer 620 with a work function material.
- the effective work function of a gate stack can be changed by doping a ferroelectric material layer with a work function material while changing the thickness of a work function layer.
- a change in effective work function due to a change in the thickness of a work function layer is greater than a change in effective work function due to the doping of a work function material.
- the present inventive concept is not limited thereto.
- the effective work function eWF 6 of the sixth gate stack 610 including the sixth ferroelectric material layer 620 doped with the second work function material can be greater than or equal to the effective work function eWF 2 of the second gate stack 210 including the second work function layer 225 with the increased thickness.
- FIGS. 12 and 13 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 5 and 6 will be mainly described below.
- FIG. 12 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 13 is a diagram for explaining an effect of the semiconductor device of FIG. 12 .
- the semiconductor device may include a first fin transistor NF 1 , a fifth fin transistor NF 5 , a sixth fin transistor NF 6 and a seventh fin transistor NF 7 formed on a substrate 100 .
- an effective work function eWF 1 of a first gate stack 110 and an effective work function eWF 7 of a seventh gate stack 710 can be changed.
- the effective work function eWF 7 of the seventh gate stack 710 can be less than the effective work function eWF 1 of the first gate stack 110 .
- each of an effective work function eWF 5 of a fifth gate stack 510 and an effective work function eWF 6 of a sixth gate stack 610 can be changed by doping each of a fifth ferroelectric material layer 520 and a sixth ferroelectric material layer 620 with a work function material.
- the effective work function eWF 6 of the sixth gate stack 610 can be greater than the effective work function eWF 5 of the fifth gate stack 510 .
- the effective work function of a gate stack can be changed by doping a ferroelectric material layer with a work function material while changing the thickness of a work function layer.
- a change in effective work function due to a change in the material of a work function layer is greater than a change in effective work function due to the doping of a work function material.
- the present inventive concept is not limited thereto.
- the effective work function eWF 5 of the fifth gate stack 510 including the fifth ferroelectric material layer 520 doped with the first work function material may be smaller than or equal to the effective work function eWF 7 of the seventh gate stack 710 including the seventh work function layer 725 whose work function is smaller than that of the first work function layer 125 .
- FIGS. 14 and 15 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 7 and 8 will be mainly described below.
- FIG. 14 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept
- FIG. 15 is a diagram for explaining an effect of the semiconductor device of FIG. 14 .
- the semiconductor device may include a first fin transistor NF 1 , a second fin transistor NF 2 , a seventh fin transistor NF 7 and an eighth fin transistor NF 8 formed on a substrate 100 .
- a first work function layer 125 includes a different material from a seventh work function layer 725 and an eighth work function layer 825 , an effective work function eWF 1 of a first gate stack 110 , an effective work function eWF 7 of a seventh gate stack 710 , and an effective work function eWF 8 of an eighth gate stack 810 can be changed to be different from each other.
- a thickness t 21 of the first work function layer 125 is different from a thickness t 22 of a second work function layer 225 , e.g., the thickness t 21 is thinner than the thickness t 22 , each of the effective work function eWF 1 of the first gate stack 110 and an effective work function eWF 2 of a second gate stack 210 are different. Moreover, the effective work function eWF 1 of the first gate stack 110 and an effective work function eWF 2 of the second gate stack 210 can be changed by changing the thickness of the work function layer.
- the effective work function of a gate stack can be changed by changing the material of a work function layer while changing the thickness of the work function layer.
- a change in effective work function due to a change in the material of a work function layer is greater than a change in effective work function due to a change in the thickness of the work function layer.
- the present inventive concept is not limited thereto.
- the effective work function eWF 2 of the second gate stack 210 including the second work function layer 225 with the increased thickness can be greater than or equal to an effective work function eWF 8 of the eighth gate stack 810 including the eighth work function layer 825 whose work function is greater than that of the first work function layer 125 .
- FIG. 16 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences from FIGS. 1 through 3 will be mainly described below.
- the semiconductor device may include a first fin transistor NF 1 , a second fin transistor NF 2 , a third fin transistor NF 3 and a ninth fin transistor NF 9 formed on a substrate 100 .
- the ninth fin transistor NF 9 is not an NCFET.
- the ninth fin transistor NF 9 does not include a gate insulating layer having ferroelectric characteristics.
- the ninth fin transistor NF 9 may include a ninth fin pattern F 9 , a ninth gate stack 910 , and ninth gate spacers 940 .
- the ninth gate stack 910 is formed in a ninth gate trench 940 t.
- the ninth gate stack 910 may include a ninth interfacial layer 915 , a high-k insulating layer 920 , a ninth interposing conductive layer 930 , and a ninth filling layer 935 .
- a first fin pattern F 1 and the ninth fin pattern F 9 may be, but are not necessarily, made of the same material to have the same thickness.
- a first interfacial layer 115 and the ninth interfacial layer 915 may be, but are not necessarily, made of the same material.
- a first interposing conductive layer 130 and the ninth interposing conductive layer 930 may be, but are not necessarily, made of the same material, and a first filling layer 135 and the ninth filling layer 935 may be, but are not necessarily, made of the same material.
- the high-k insulating layer 920 may not have ferroelectric characteristics. Even if a material included in the high-k insulating layer 920 has the ferroelectric characteristics, the high-k insulating layer 920 may have a thickness so as not to exhibit the ferroelectric characteristics.
- the high-k insulating layer 920 may include, but not necessarily, the same material as a first ferroelectric material layer 120 .
- a thickness t 19 of the high-k insulating layer 920 is smaller than a thickness t 11 of the first ferroelectric material layer 120 .
- a ninth work function layer 925 may be, but is not necessarily, the same as a first work function layer 125 .
- Exemplary embodiments of the present inventive concept provide a semiconductor device capable of realizing various threshold voltages in an NCFET including a gate dielectric layer having ferroelectric characteristics.
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 16/451,787 filed on Jun. 25, 2019, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0078126, filed on Jul. 5, 2018, and Korean Patent Application No. 10-2019-0001698, filed on Jan. 7, 2019 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
- The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor having negative capacitance (NC) using a ferroelectric material.
- The development of metal-oxide semiconductor field-effect transistors (MOSETs) has enabled the integration density of integrated circuits to be continuously increased. For example, the integration density of integrated circuits, which is typically defined as a total number of transistors per unit chip area, has doubled every two years. To increase the integration density of integrated circuits, the size of individual transistors has been continuously reduced. Accordingly, semiconductor technologies for improving the performance of miniaturized transistors have been introduced.
- These semiconductor technologies may include a high dielectric constant (high-k) metal gate (HKMG) technology and a fin field-effect transistor (FinFET) technology. The HKMG technology improves gate capacitance and reduces leakage current, and the FinFET technology improves a short channel effect (SCE) in which the electric potential of a channel region is affected by a drain voltage.
- However, a reduction in the driving voltage of transistors has not correlated with a reduction in the transistor size. Accordingly, the power density of complementary metal-oxide-semiconductor (CMOS) transistors is increasing exponentially. To reduce the power density, the driving voltage should be reduced. However, since silicon-based MOSFETs have thermal emission-based physical operating characteristics, very law supply voltages are not common.
- Accordingly, there is a need for a transistor having a subthreshold swing (SS) of less than 60 mV/decade, which is a physical limit of the SS, at room temperature.
- According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device, comprising a first transistor which comprises a first gate stack on a substrate; and a second transistor which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer comprises the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
- According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device, comprising a first transistor which comprises a first gate stack on a substrate; and a second transistor which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first ferroelectric material layer disposed on the substrate, a first work function layer contacting the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second ferroelectric material layer disposed on the substrate, a second work function layer contacting the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first ferroelectric material layer and the second ferroelectric material layer comprise the same material, wherein a thickness of the first ferroelectric material layer is equal to a thickness of the second ferroelectric material layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
- According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device, comprising a first negative capacitance field-effect transistor (NCFET) which comprises a first gate stack on a substrate; and a second NCFET which comprises a second gate stack on the substrate, wherein the first gate stack comprises a first interfacial layer disposed on the substrate, a first gate insulating layer disposed on the first interfacial layer, a first work function layer disposed on the first gate insulating layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack comprises a second interfacial layer disposed on the substrate, a second gate insulating layer disposed on the second interfacial layer, a second work function layer disposed on the second gate insulating layer and a second upper gate electrode disposed on the second work function layer, and wherein a structure of the first gate stack is different from a structure of the second gate stack, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
- The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof, with reference to the accompanying drawings in which:
-
FIG. 1 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIG. 2 is a perspective view of a first fin transistor illustrated inFIG. 1 ; -
FIG. 3 is a diagram for explaining an effect of the semiconductor device ofFIG. 1 ; -
FIG. 4 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIGS. 5 and 6 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIGS. 7 and 8 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIG. 9 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIGS. 10 and 11 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIGS. 12 and 13 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept; -
FIGS. 14 and 15 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept; and -
FIG. 16 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. - In the drawings accompanying this disclosure, a fin field-effect transistor (FinFET) including a fin pattern-shaped channel region is illustrated by way of example. However, the present inventive concept is not limited to the FinFET. The exemplary embodiments of the present inventive concept disclosed herein are applicable to a transistor including a nanowire, a transistor including a nanosheet or a three-dimensional (3D) transistor, in addition, the exemplary embodiments of the present inventive concept disclosed herein are applicable to a planar transistor. It is to be understood that in the drawings, like reference numerals may refer to like elements.
-
FIG. 1 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept.FIG. 2 is a perspective view of a first fin transistor NF1 illustrated inFIG. 1 .FIG. 3 is a for explaining an effect of the semiconductor device ofFIG. 1 . - For reference, although source/drain regions of first, second and third fin transistors NF1, NF2 and NF3 are not illustrated in
FIGS. 1 and 2 , this is merely for ease of description, and the present inventive concept is not limited thereto. In addition, the cross section of the first fin transistor NF1 ofFIG. 1 may be a cross section taken along A-A ofFIG. 2 . - Referring to
FIG. 1 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include the first fin transistor NF1, the second fin transistor NF2 and the third fin transistor NF3 formed on asubstrate 100. - Each of the first through third fin transistors NF1 through NF3 may be a FinFET using a three-dimensional (3D) channel. For example, the first through third fin transistors NF1 through NF3 may be transistors of the same conductivity type (e.g., an N type or P type). For another example, at least one of the first through third fin transistors NF1 through NF3 may be a P-type transistor, and the other may be an N-type transistor.
- Each of the first through third fin transistors NF1 through NF3 may be a negative capacitance (NC) FET using a negative capacitor. Here, the negative capacitor is a capacitor having negative capacitance and may be connected in series to a positive capacitor to increase its capacitance.
- The first through third fin transistors NF1 through NF3 which are NCFETs may include an insulating layer having ferroelectric characteristics. Each of the first through third fin transistors NF1 through NF3 may have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.
- Although the first through third fin transistors NF1 through NF3 are illustrated as being formed on the
substrate 100, this is merely for ease of description, and the present inventive concept is not limited thereto. For example, at least two of the first through third fin transistors NF1 through NF3 may be formed on thesubstrate 100. - Referring first to the first fin transistor NF1 illustrated in
FIGS. 1 and 2 , the first fin transistor NF1 may include a first fin pattern F1, afirst gate stack 110, andfirst gate spacers 140. Thefirst gate stack 110 may include a firstinterfacial layer 115, a firstferroelectric material layer 120, a firstwork function layer 125, a first interposingconductive layer 130, and afirst filling layer 135. - The
substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Additionally, thesubstrate 100 may be, but is not limited to, a silicon substrate or a substrate made of another material such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. - The first fin pattern F1 may protrude from the
substrate 100. The first fin pattern F1 may extend along a first direction X on thesubstrate 100. - The first fin pattern F1 may be a part of the
substrate 100 or may include an epitaxial layer grown from thesubstrate 100. The first fin pattern F1 may include an elemental semiconductor material such as silicon or germanium. In addition, the first fin pattern F1 may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. - The group IV-IV compound semiconductor may be, e.g., a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn) or a compound obtained by doping the binary or ternary compound with a group IV element. The group III-V compound semiconductor may be, e.g., a binary, ternary, or quaternary compound composed of aluminum (Al), gallium (Ga) or indium (In) (e.g., group III elements) bonded with phosphorus (P), arsenic (As) or antimony (Sb) (e.g., group V elements).
- A
field insulating layer 105 may be formed on thesubstrate 100. Thefield insulating layer 105 may be formed on part of sidewalls of the first fin pattern F1. - A top surface of the first fin pattern F1 may protrude above a top surface of the
field insulating layer 105. Thefield insulating layer 105 may include, e.g., a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. - An interlayer insulating
film 190 may be disposed on thefield insulating layer 105. Afirst gate trench 140 t may be formed in theinterlayer insulating film 190. The first gate trench 1401 may be defined by thefirst gate spacers 140. - The
first gate spacers 140 may include, e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), or silicon oxycarbonitride (SiOCN). - The
interlayer insulating film 190 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), toner silazen (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethylorthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO)), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), polyimide, a porous polymeric material, or a combination of the same. - The
first gate stack 110 may be formed in thefirst gate trench 140. Thefirst gate stack 110 entirely fills thefirst gate trench 140 t. Although a top surface of thefirst gate stack 110 lies in the same plane with a top surface of theinterlayer insulating film 190 in the drawings, the present inventive concept is not limited thereto. - A capping pattern may also be formed on the
first gate slack 110 to partially fill thefirst gate trench 140 t. In this ease, a top surface of the capping pattern may lie in the same plane with the top surface of theinterlayer insulating film 190. - The first
interfacial layer 115 may be formed on thesubstrate 100. The firstinterfacial layer 115 may be formed on the first fin pattern F1. For example, the firstinterfacial layer 115 may directly contact the first fin pattern F1. - The first
interfacial layer 115 may be formed in thefirst gate trench 140 t. Although the firstinterfacial layer 115 is illustrated as being formed on a bottom surface of thefirst gate trench 140 t, the present inventive concept is not limited thereto. The firstinterfacial layer 115 may also be formed on sidewalls of thefirst gate trench 140 t depending on a manufacturing method. - When the first tin pattern F1 includes silicon, the first
interfacial layer 115 may include a silicon oxide layer. The firstinterfacial layer 115 may be formed using, but not limited to, a chemical oxidation method, an ultraviolet (UV) oxidation method, or a dual plasma oxidation method. - The first
ferroelectric material layer 120 may be formed on the firstinterfacial layer 115. The firstinterfacial layer 115 may be disposed between the firstferroelectric material layer 120 and the first fin pattern F1. The firstferroelectric material layer 120 may be formed along inner walls of thefirst gate trench 140 t. For example, the firstferroelectric material layer 120 may be formed along the sidewalk and bottom surface of thefirst gate trench 140 t. - The first
ferroelectric material layer 120 may be formed using, but not limited to, chemical vapor deposition (CVD) or atomic layer deposition (ALD). - The first
ferroelectric material layer 120 may have ferroelectric characteristics. The firstferroelectric material layer 120 may have a thickness sufficient to have the ferroelectric characteristics. For example, the thickness of the firstferroelectric material layer 120 may be, but is not limited to, 3 to 10 nm. Since a critical thickness exhibiting the ferroelectric characteristics may be different for each ferroelectric material, the thickness of the firstferroelectric material layer 120 may vary according to the ferroelectric material. - The first
ferroelectric material layer 120 may include, e.g., hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. Here, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr) or may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O). - The first
ferroelectric material layer 120 may further include a doping element doped in the above-described materials. The doping element may be aluminum (Al), titanium (Ti). niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dv), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). - The first
interfacial layer 115 and the firstferroelectric material layer 120 may be gate insulating layers of the first fin transistor NF1. The firstinterfacial layer 115 may be a lower gate insulating layer having a positive capacitance, and the firstferroelectric material layer 120 may be an upper gate insulating layer having a negative capacitance. - A conductive layer may also be formed between the first
interfacial layer 115 and the firstferroelectric material layer 120. Alternatively, a high dielectric constant (high-k) insulating layer and a conductive layer stacked sequentially may be formed between the firstinterfacial layer 115 and the firstferroelectric material layer 120. In this case, the high dielectric constant (high-k) insulating layer may be directly disposed on the firstinterfacial layer 115. - The first
work function layer 125 may be formed on the firstferroelectric material layer 120. The firstwork function layer 125 may be formed along the sidewalls and bottom surface of thefirst gate trench 140 t. The firstwork function layer 125 may contact the firstferroelectric material layer 120. - The first
work function layer 125 may include, e.g., titanium nitride (TiN), titanium carbonitride (TiCN), or tungsten carbonitride (WCN). - The first interposing
conductive layer 130 may be formed on the firstwork function layer 125. The first interposingconductive layer 130 may be formed along the sidewalls and bottom surface of thefirst gate trench 140 t. - The first interposing
conductive layer 130 may include, e.g., titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), vanadium aluminum carbide (VAlC), titanium aluminum silicon carbide (TiAlSiC), or tantalum aluminum silicon carbide (TaAlSiC). - The
first filling layer 135 may be formed on the first interposingconductive layer 130. Thefirst filling layer 135 may fill thefirst gate trench 140 t. Thefirst filling layer 135 may include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), or titanium nitride (TiN). - The first interposing
conductive layer 130 and thefirst filling layer 135 may be a first upper gate electrode formed on the firstwork function layer 125. - The second fin transistor NF2 may include a second fin pattern F2, a
second gate stack 210, andsecond gate spacers 240. Thesecond gate stack 210 is formed in asecond gate trench 240 t. - The
second gate stack 210 may include a secondinterfacial layer 215, a secondferroelectric material layer 220, a secondwork function layer 225, a second interposingconductive layer 230, and asecond tilling layer 235. The secondwork function layer 225 may be disposed on the secondferroelectric material layer 220 to contact the secondferroelectric material layer 220. For example, the secondwork function layer 225 may directly contact the secondferroelectric material layer 220. - The third fin transistor NF3 may include a third fin pattern F3, a
third gate stack 310, andthird gate spacers 340. Thethird gate stack 310 is formed in athird gate trench 340 t. - The
third gate stack 310 may include a thirdinterfacial layer 315, a thirdferroelectric material layer 320, a thirdwork function layer 325, a third interposingconductive layer 330, and athird filling layer 335. The thirdwork function layer 325 may be disposed on the thirdferroelectric material layer 320 to contact the thirdferroelectric material layer 320. For example, the thirdwork function layer 325 may directly contact the thirdferroelectric material layer 320. - The first through third fin patterns F1 through F3 may be, but are not necessarily, made of the same material and have the same thickness. The first through third
interfacial layers 115 through 315 may be, but are not necessarily, made of the same material. The first through third interposingconductive layers 130 through 330 may be, but are not necessarily, made of the same material, and the first through third filling layers 135 through 335 may be, but are not necessarily, made of the same material. - The first through third ferroelectric material layers 120 through 320 may include the same material. The first through third work function layers 125 through 325 may be made of the same material.
- A thickness a t11 of the first
ferroelectric material layer 120 may be equal to a thickness t12 of the secondferroelectric material layer 220 and a thickness t13 of the thirdferroelectric material layer 320. - A thickness t22 of the second
work function layer 225 is greater than a thickness t21 of the firstwork function layer 125 and smaller than a thickness t23 of the thirdwork function layer 325. In this case, the upper gate electrodes of the first, second andthird gate structures - In the semiconductor device according to the exemplary embodiments of the present inventive concept, an effective work function eWF1 of the
first gate stack 110, an effective work function eWF2 of thesecond gate stack 210, and an effective work function eWF3 of thethird gate stack 310 may be different from each other. - Since the first through third gate stacks 110 through 310 have different structures due, for example, to the differing thicknesses of the first to third work function layers 125 to 325, the effective work functions eWF1 through eWF3 of the first through
third agate stacks 110 through 310 may be different from each other. - Here, when gate stacks have different structures, it may mean that materials included (e.g., doped) in ferroelectric material layers of the gate stacks are different from each other or that materials included in work function layers of the gate stacks are different from each other. In addition, when the gate stacks have different structures, it may mean that thicknesses of the work function layers are different from each other. In other words, if the types and presence or absence of the materials doped in the ferroelectric material layers, the materials included in the work function layers, or the thicknesses of the work function layers are different from each other, it can be said that the gate stacks have different structures.
- In the semiconductor device according to the exemplary embodiments of the present inventive concept, the effective work functions eWF1 through eWF3 of the first through third gate stacks 110 through 310 can be adjusted by adjusting the thickness t21 of the first
work function layer 125, the thickness t22 of the secondwork function layer 225 and thethickness 123 of the thirdwork function layer 325. For example, if the thickness t21 of the firstwork function layer 125 and the thickness t22 of the secondwork function layer 225 are the same, the effective work functions eWF1 and eWF2 of the first and second gate stacks 110 and 210 might be the same. - When the first through third fin transistors NF1 through NF3 are of the same conductivity type, they may have different threshold voltages.
- In
FIGS. 1 through 3 , the first through third work function layers 125 through 325 may include, for example, a titanium nitride (TiN) layer. - As the thickness of the TiN layer increases, the effective work function of a gate stack may increase. In other words, the effective work function eWF2 of the
second gate stack 210 is greater than the effective work function eWF1 of thefirst gate stack 110 and smaller than the effective work function eWF3 of thethird gate stack 310. -
FIG. 4 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 1 through 3 will be mainly described below. - Referring to
FIG. 4 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor NF1, a second fin transistor NF2, a third fin transistor NF3 and a fourth fin transistor NF4 formed on asubstrate 100. - For example, the fourth fin transistor NF4 may be an NCFET.
- The fourth fin transistor NF4 may include a fourth fin pattern F4, a
fourth gate stack 410, andfourth gate spacers 440. Thefourth gate stack 410 is formed in afourth gate trench 440 t. - The
fourth gate stack 410 may include a fourthinterfacial layer 415, a fourthferroelectric material layer 420, a fourth interposingconductive layer 430, and afourth filling layer 435. Thefourth gate stack 410 may not include a work function layer like the first through third gate stacks 110 through 310. - The fourth
ferroelectric material layer 420 may include the same material as a firstferroelectric material layer 120. A thickness t14 of the fourthferroelectric material layer 420 may be equal to a thickness t11 of the firstferroelectric material layer 120. - Since the
fourth gate stack 410 does not include a work function layer, an effective work function of thefourth gate stack 410 may be smaller than that of thefirst gate stack 110. -
FIGS. 5 and 6 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 1 through 3 will be mainly described below. - For reference,
FIG. 5 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept, andFIG. 6 is a diagram for explaining an effect of the semiconductor device ofFIG. 5 . - Referring to
FIG. 5 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor NF1, a fifth fin transistor NF5 and a sixth fin transistor NF6 formed on asubstrate 100. - The first fin transistor NF1, the fifth fin transistor NF5 and the sixth fin transistor NF6 may be, but are not necessarily, of the same conductivity type. Each of the fifth fin transistor NF5 and the sixth fin transistor NF6 may be an NCFET.
- Although the first fin transistor NF1, the fifth fin transistor NF5 and the sixth fin transistor NF6 are illustrated as being formed on the
substrate 100, this is merely for ease of description, and the present inventive concept is not limited thereto. For example, at least two of the first fin transistor NF1, the fifth fin transistor NE5 and the sixth fin transistor NF6 may be formed on thesubstrate 100. - The fifth fin transistor NF5 may include a fifth fin pattern F5, a
fifth gate stack 510, andfifth gate spacers 540. Thefifth gate stack 510 is formed in afifth gate trench 540 t. - The
fifth gate stack 510 may include a fifthinterfacial layer 515, a fifthferroelectric material layer 520, a fifthwork function layer 525, a fifth interposingconductive layer 530, and afifth filling layer 535. The fifthwork function layer 525 may be disposed on the fifthferroelectric material layer 520 to contact the fifthferroelectric material layer 520. - The sixth fin transistor NF6 may include a sixth fin pattern F6, a
sixth gate stack 610, andsixth gate spacers 640. Thesixth gate stack 610 is formed in asixth gate trench 640 t. - The
sixth gate stack 610 may include a sixthinterfacial layer 615, a sixthferroelectric material layer 620, a sixthwork function layer 625, a sixth interposingconductive layer 630, and asixth filling layer 635. The sixthwork function layer 625 may be disposed on the sixthferroelectric material layer 620 to contact the sixthferroelectric material layer 620. - The first fin pattern F1, the fifth fin pattern F5 and the sixth fin pattern F6 may be, but are not necessarily, made of the same material to have the same thickness. A first
interfacial layer 115, the fifthinterfacial layer 515 and the sixthinterfacial layer 615 may be, but are not necessarily, made of the same material. A first interposingconductive layer 130, the fifth interposingconductive layer 530 and the sixth interposingconductive layer 630 may be, but are not necessarily, made of the same material, and afirst filling layer 135, thefifth filling layer 535 and thesixth filling layer 635 may be, but are not necessarily, made of the same material. - A first
work function layer 125, the fifthwork function layer 525 and the sixthwork function layer 625 may include the same material. In addition, a thickness t21 of the firstwork function layer 125 may be equal to a thickness t25 of the fifthwork function layer 525 and a thickness t26 of the sixthwork function layer 625. - A first
ferroelectric material layer 120, the fifthferroelectric material layer 520 and the sixthferroelectric material layer 620 may include the same metal oxide. For example, the firstferroelectric material layer 120, the fifthferroelectric material layer 520 and the sixthferroelectric material layer 620 may include hafnium (Hf). The firstferroelectric material layer 120, the fifthferroelectric material layer 520 and the sixthferroelectric material layer 620 may include hafnium oxide. - Alternatively, the fifth
ferroelectric material layer 520 may include a doped first work function material, and the sixthferroelectric material layer 620 may include a doped second work function material. However, the firstferroelectric material layer 120 may not include the first work function material and the second work function material. - The first work function material may be a control material that reduces an effective work function. The first work function material may include, for example, lanthanum (La), magnesium (Mg), or yttrium (Y). The fifth
ferroelectric material layer 520 may include doped nitrogen (N) in addition to the first work function material. - The second work function material may be a control material that increases an effective work function. The second work function material may include, for example, aluminum (Al), titanium (Ti), or niobium (Nb). The sixth
ferroelectric material layer 620 may include doped nitrogen (N) in addition to the second work function material. - A work function material may form a dipole within a ferroelectric material layer, thereby changing the effective work function of a gate stack including the ferroelectric material layer.
- After a work function material supply layer is formed on a ferroelectric material layer, it may be treated with heat to diffuse a work function material into the ferroelectric material layer. The thickness of a ferroelectric material layer including a work function material may be equal to or greater than the thickness of a ferroelectric material layer not including the work function material.
- Since the first
ferroelectric material layer 120 does not include the first and second work function materials, the structure of afirst gate stack 110 may be different from the structure of thefifth gate stack 510 and the structure of thesixth gate stack 610. In addition, since the fifthferroelectric material layer 520 includes the first work function material and the sixthferroelectric material layer 620 includes the second work function material, the structure of thefifth gate stack 510 may be different from that of thesixth gate stack 610. - In the semiconductor device according to the exemplary embodiments of the present inventive concept, since the structure of the
first gate stack 110, the structure of thefifth gate stack 510 and the structure of thesixth gate stack 610 are different from each other, an effective work function eWF1 of thefirst gate stack 110, an effective work function eWF5 of thefifth gate stack 510, and an effective work function eWF6 of thesixth gate stack 610 may be different from each other. For example, the of work function eWF1 of thefirst gate stack 110 may be less than the effective work function eWF6 of thesixth gate stack 610 and greater than the effective work function eWF5 of thefifth gate stack 510. - In the semiconductor device according to the exemplary embodiments of the present inventive concept, each of the effective work function eWF1 of the
first gate stack 110, the effective work function eWF5 of thefifth gate stack 510 and the effective work function eWF6 of thesixth gate stack 610 may be adjusted according, to the presence or absence of a work function material doped in the ferroelectric material layer and the type of the work function material doped in the ferroelectric material layer. - When the first fin transistor NF1, the fifth fin transistor NF5 and the sixth fin transistor NF6 are of the same conductivity type, they may have different threshold voltages.
- In
FIG. 6 , since the fifthferroelectric material layer 520 includes the first work function material that reduces an effective work function and the sixthferroelectric material layer 620 includes the second work function material that increases the effective work function, the effective work function eWF1 of thefirst gate stack 110 is greater than the effective work function eWF5 of thefifth gate stack 510 and smaller than the effective work function eWF6 of thesixth gate stack 610. -
FIGS. 7 and 8 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 1 through 3 will be mainly described below. - For reference,
FIG. 7 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept, andFIG. 8 is a diagram for explaining an effect of the semiconductor device ofFIG. 7 . - Referring to
FIG. 7 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor NF1, a seventh fin transistor NF7 and an eighth fin transistor NF8 formed on asubstrate 100. - The first fin transistor NF1, the seventh fin transistor NF7 and the eighth fin transistor NF8 may be, but are not necessarily, of the same conductivity type. Each of the seventh fin transistor NF7 and the eighth fin transistor NF8 may be an NCFET.
- Although the first fin transistor NF1, the seventh fin transistor NF7 and the eighth fin transistor NF8 are illustrated as being formed on the
substrate 100, this is merely for ease of description, and the present inventive concept is not limited thereto. For example, at least two of the first fin transistor NF1, the seventh fin transistor NF7 and the eighth fin transistor NF8 may be formed on thesubstrate 100. - The seventh fin transistor NF7 may include a seventh fin pattern F7, a
seventh gate stack 710, andseventh gate spacers 740. Theseventh gate stack 710 is formed in aseventh gate trench 740 t. - The
seventh gate stack 710 may include a seventhinterfacial layer 715, a seventhferroelectric material layer 720, a seventhwork function layer 725, a seventh interposingconductive layer 730, and aseventh filling layer 735. The seventhwork function layer 725 may be disposed on the seventhferroelectric material layer 720 to contact the seventhferroelectric material layer 720. - The eighth fin transistor NF8 may include an eighth fin pattern F8, an
eighth gate stack 810, andeighth gate spacers 840. Theeighth gate stack 810 is formed in aneighth gate trench 840 t. - The
eighth gate stack 810 may include an eighthinterfacial layer 815, an eighthferroelectric material layer 820, an eighthwork function layer 825, an eighth interposingconductive layer 830, and aneighth filling layer 835. The eighthwork function layer 825 may be disposed on the eighthferroelectric material layer 820 to contact the eighthferroelectric material layer 820. - The first fin pattern F1, the seventh fin pattern F7 and the eighth fin pattern F8 may be, but are not necessarily, made of the same material and have the same thickness. A first
interfacial layer 115, the seventhinterfacial layer 715 and the eighthinterfacial layer 815 may be, but are not necessarily, made of the same material. A first interposing,conductive layer 130, the seventh interposingconductive layer 730 and the eighth interposingconductive layer 830 may be, but are not necessarily, made of the same material, and afirst filling layer 135, theseventh filling layer 735 and theeighth filling layer 835 may be, but are not necessarily, made of the same material. - A first
ferroelectric material layer 120, the seventhferroelectric material layer 720 and the eighthferroelectric material layer 820 may include the same material. A thickness t11 of the firstferroelectric material layer 120 may be equal to a thickness t17 of the seventhferroelectric material layer 720 and a thickness t18 of the eighthferroelectric material layer 820. - A first
work function layer 125, the seventhwork function layer 725 and the eighthwork function layer 825 may include different materials. The seventhwork function layer 725 may include a material having a work function smaller than that of the firstwork function layer 125. The eighthwork function layer 825 may include a material having a work function greater than that of the firstwork function layer 125. - The seventh
work function layer 725 may include, for example, tungsten (W) titanium silicon nitride (TiSiN) titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), or tantalum nitride (TaN). - The eighth work function layer 82 may include, for example, platinum Pt), iridium (Ir), ruthenium (Ru), molybdenum nitride (MoN), or molybdenum (Mo).
- Since the first
work function layer 125, the seventhwork function layer 725, and the eighthwork function layer 825 include different materials, the structure of afirst gate stack 110, the structure of theseventh gate stack 710, and the structure of theeighth gate stack 810 may be different from each other. - In the semiconductor device according, to the exemplary embodiments of the present inventive concept, since the structure of the
first gate stack 110, the structure of theseventh gate stack 710 and the structure of theeighth gate stack 810 are different from each other, an effective work function eWF1 of thefirst gate stack 110, an effective work function eWF7 of theseventh gate stack 710, and an effective work function eWF8 of theeighth gate stack 810 may be different from each other. For example, the effective work function eWF1 of thefirst gate stack 110 may be less than the effective work function eWF8 of theeighth gate stack 810 and greater than the effective work function eWF7 of theseventh gate stack 710. - In the semiconductor device according to the exemplary embodiments of the present inventive concept, each of the effective work function eWF1 of the
first gate stack 110, the effective work function eWF7 of theseventh gate stack 710 and the effective work function eWF8 of theeighth gate stack 810 may be adjusted according to the type of the work function layer. - When the first fin transistor NF1, the seventh fin transistor NF7 and the eighth fin transistor NF8 are of the same conductivity type, they may have different threshold voltages.
- In
FIG. 8 , since the seventhwork function layer 725 includes a material having a work function smaller than that of the firstwork function layer 125 and the eighthwork function layer 825 includes a material having a work function higher than that of the firstwork function layer 125, the effective work function eWF1 of thefirst gate stack 110 is greater than the effective work function eWF7 of theseventh gate stack 710 and smaller than the effective work function eWF8 of theeighth gate stack 810. - By changing the thickness of the seventh
work function layer 725 or the thickness of the eighthwork function layer 825, it is possible to form a gate stack having various effective work functions. -
FIG. 9 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 1 through 3 will be mainly described below. - Referring to
FIG. 9 , the semiconductor device according to the exemplary embodiments of the present inventive concept may further include a fourth fin transistor NF4. - A
fourth gate stack 410 may include a fourth interposingconductive layer 430. The fourth interposingconductive layer 430 may be a material having a work function smaller than that of a seventhwork function layer 725. - Therefore, an effective work function of the
fourth gate stack 410 may be smaller than that of aseventh gate stack 710. - Although the
fourth gate stack 410 is illustrated as not including a work function layer, the present inventive concept is not limited thereto. Thefourth gate stack 410 may also include a fourth work function layer containing a material whose work function is lower than that of the seventhwork function layer 725. In this case, the fourth work function layer may include, e.g., titanium aluminum (TiAl), titanium aluminum carbide (TiAlC) tantalum aluminum carbide (TaAlC), vanadium aluminum carbide (VAlC) titanium aluminum silicon carbide (TiAlSiC), or tantalum aluminum silicon carbide (TaAlSiC). -
FIGS. 10 and 11 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 5 and 6 will be mainly described below. - For reference,
FIG. 10 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept, andFIG. 11 is a diagram for explaining an effect of the semiconductor device ofFIG. 10 . - Referring to
FIGS. 10 and 11 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor. NF1, a second fin transistor NF2, a fifth fin transistor NF5 and a sixth fin transistor NF6 formed on asubstrate 100. - Since a thickness t21 of a first
work function layer 125 is different from a thickness t22 of a secondwork function layer 225, an effective work function eWF1 of afirst gate stack 110 and an effective work function eWF2 of asecond gate stack 210 may be different from each other. Moreover, the effective work function eWF1 of thefirst gate stack 110 and the effective work function eWF2 of thesecond gate stack 210 can be changed by changing the thickness of the work function layer. - In addition, each of an effective work function eWF5 of a
fifth gate stack 510 and an effective work function eWF6 of asixth gate stack 610 may be different from each other. Moreover, the effective work function eWF5 of thefifth gate stack 510 and the effective work function eWF6 of thesixth gate stack 610 can be changed by doping each of a fifthferroelectric material layer 520 and a sixthferroelectric material layer 620 with a work function material. - Therefore, the effective work function of a gate stack can be changed by doping a ferroelectric material layer with a work function material while changing the thickness of a work function layer.
- In
FIG. 11 , a change in effective work function due to a change in the thickness of a work function layer is greater than a change in effective work function due to the doping of a work function material. However, the present inventive concept is not limited thereto. - In other words, the effective work function eWF6 of the
sixth gate stack 610 including the sixthferroelectric material layer 620 doped with the second work function material can be greater than or equal to the effective work function eWF2 of thesecond gate stack 210 including the secondwork function layer 225 with the increased thickness. -
FIGS. 12 and 13 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 5 and 6 will be mainly described below. - For reference,
FIG. 12 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept, andFIG. 13 is a diagram for explaining an effect of the semiconductor device ofFIG. 12 . - Referring to
FIGS. 12 and 13 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor NF1, a fifth fin transistor NF5, a sixth fin transistor NF6 and a seventh fin transistor NF7 formed on asubstrate 100. - Since a first
work function layer 125 and a seventhwork function layer 725 include different materials, an effective work function eWF1 of afirst gate stack 110 and an effective work function eWF7 of aseventh gate stack 710 can be changed. For example, the effective work function eWF7 of theseventh gate stack 710 can be less than the effective work function eWF1 of thefirst gate stack 110. - In addition, each of an effective work function eWF5 of a
fifth gate stack 510 and an effective work function eWF6 of asixth gate stack 610 can be changed by doping each of a fifthferroelectric material layer 520 and a sixthferroelectric material layer 620 with a work function material. For example, the effective work function eWF6 of thesixth gate stack 610 can be greater than the effective work function eWF5 of thefifth gate stack 510. - Therefore, the effective work function of a gate stack can be changed by doping a ferroelectric material layer with a work function material while changing the thickness of a work function layer.
- In
FIG. 13 , a change in effective work function due to a change in the material of a work function layer is greater than a change in effective work function due to the doping of a work function material. However, the present inventive concept is not limited thereto. - In other words, the effective work function eWF5 of the
fifth gate stack 510 including the fifthferroelectric material layer 520 doped with the first work function material may be smaller than or equal to the effective work function eWF7 of theseventh gate stack 710 including the seventhwork function layer 725 whose work function is smaller than that of the firstwork function layer 125. -
FIGS. 14 and 15 are diagrams for explaining a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 7 and 8 will be mainly described below. - For reference,
FIG. 14 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept, andFIG. 15 is a diagram for explaining an effect of the semiconductor device ofFIG. 14 . - Referring to
FIGS. 14 and 15 , the semiconductor device according to the exemplary embodiments of the inventive concept may include a first fin transistor NF1, a second fin transistor NF2, a seventh fin transistor NF7 and an eighth fin transistor NF8 formed on asubstrate 100. - Since a first
work function layer 125 includes a different material from a seventhwork function layer 725 and an eighthwork function layer 825, an effective work function eWF1 of afirst gate stack 110, an effective work function eWF7 of aseventh gate stack 710, and an effective work function eWF8 of aneighth gate stack 810 can be changed to be different from each other. - In addition, since a thickness t21 of the first
work function layer 125 is different from a thickness t22 of a secondwork function layer 225, e.g., the thickness t21 is thinner than the thickness t22, each of the effective work function eWF1 of thefirst gate stack 110 and an effective work function eWF2 of asecond gate stack 210 are different. Moreover, the effective work function eWF1 of thefirst gate stack 110 and an effective work function eWF2 of thesecond gate stack 210 can be changed by changing the thickness of the work function layer. - Therefore, the effective work function of a gate stack can be changed by changing the material of a work function layer while changing the thickness of the work function layer.
- In
FIG. 15 , a change in effective work function due to a change in the material of a work function layer is greater than a change in effective work function due to a change in the thickness of the work function layer. However, the present inventive concept is not limited thereto. - In other words, the effective work function eWF2 of the
second gate stack 210 including the secondwork function layer 225 with the increased thickness can be greater than or equal to an effective work function eWF8 of theeighth gate stack 810 including the eighthwork function layer 825 whose work function is greater than that of the firstwork function layer 125. -
FIG. 16 is a cross-sectional view of a semiconductor device according to exemplary embodiments of the present inventive concept. For the sake of convenience, differences fromFIGS. 1 through 3 will be mainly described below. - Referring to
FIG. 16 , the semiconductor device according to the exemplary embodiments of the present inventive concept may include a first fin transistor NF1, a second fin transistor NF2, a third fin transistor NF3 and a ninth fin transistor NF9 formed on asubstrate 100. - For example, the ninth fin transistor NF9 is not an NCFET. The ninth fin transistor NF9 does not include a gate insulating layer having ferroelectric characteristics.
- The ninth fin transistor NF9 may include a ninth fin pattern F9, a
ninth gate stack 910, andninth gate spacers 940. Theninth gate stack 910 is formed in aninth gate trench 940 t. - The
ninth gate stack 910 may include a ninth interfacial layer 915, a high-k insulating layer 920, a ninth interposingconductive layer 930, and aninth filling layer 935. - A first fin pattern F1 and the ninth fin pattern F9 may be, but are not necessarily, made of the same material to have the same thickness. A first
interfacial layer 115 and the ninth interfacial layer 915 may be, but are not necessarily, made of the same material. A first interposingconductive layer 130 and the ninth interposingconductive layer 930 may be, but are not necessarily, made of the same material, and afirst filling layer 135 and theninth filling layer 935 may be, but are not necessarily, made of the same material. - The high-
k insulating layer 920 may not have ferroelectric characteristics. Even if a material included in the high-k insulating layer 920 has the ferroelectric characteristics, the high-k insulating layer 920 may have a thickness so as not to exhibit the ferroelectric characteristics. - The high-
k insulating layer 920 may include, but not necessarily, the same material as a firstferroelectric material layer 120. When the high-k insulating layer 920 includes the same material as the firstferroelectric material layer 120, a thickness t19 of the high-k insulating layer 920 is smaller than a thickness t11 of the firstferroelectric material layer 120. - A ninth work function layer 925 may be, but is not necessarily, the same as a first
work function layer 125. - Exemplary embodiments of the present inventive concept provide a semiconductor device capable of realizing various threshold voltages in an NCFET including a gate dielectric layer having ferroelectric characteristics.
- While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present inventive concept as defined by the following claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/114,598 US11949012B2 (en) | 2018-07-05 | 2020-12-08 | Semiconductor device |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2018-0078126 | 2018-07-05 | ||
KR20180078126 | 2018-07-05 | ||
KR10-2019-0001698 | 2019-01-07 | ||
KR1020190001698A KR102557915B1 (en) | 2018-07-05 | 2019-01-07 | Semiconductor device |
US16/451,787 US10879392B2 (en) | 2018-07-05 | 2019-06-25 | Semiconductor device |
US17/114,598 US11949012B2 (en) | 2018-07-05 | 2020-12-08 | Semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/451,787 Continuation US10879392B2 (en) | 2018-07-05 | 2019-06-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210119058A1 true US20210119058A1 (en) | 2021-04-22 |
US11949012B2 US11949012B2 (en) | 2024-04-02 |
Family
ID=69101627
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/451,787 Active US10879392B2 (en) | 2018-07-05 | 2019-06-25 | Semiconductor device |
US17/114,598 Active US11949012B2 (en) | 2018-07-05 | 2020-12-08 | Semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/451,787 Active US10879392B2 (en) | 2018-07-05 | 2019-06-25 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (2) | US10879392B2 (en) |
JP (1) | JP2020010033A (en) |
CN (1) | CN110690177A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11664279B2 (en) | 2020-02-19 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple threshold voltage implementation through lanthanum incorporation |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11114347B2 (en) * | 2017-06-30 | 2021-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-protective layer formed on high-k dielectric layers with different materials |
US10879392B2 (en) | 2018-07-05 | 2020-12-29 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN109980014B (en) * | 2019-03-26 | 2023-04-18 | 湘潭大学 | Back-grid ferroelectric grid field effect transistor and preparation method thereof |
KR20210014017A (en) * | 2019-07-29 | 2021-02-08 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US11069676B2 (en) * | 2019-09-27 | 2021-07-20 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
WO2021091995A1 (en) * | 2019-11-05 | 2021-05-14 | Applied Materials, Inc. | Pmos high-k metal gates |
US11489056B2 (en) * | 2020-02-10 | 2022-11-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multi-threshold gate structure |
US11309398B2 (en) * | 2020-04-01 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method for the semiconductor device |
KR20210140858A (en) | 2020-05-14 | 2021-11-23 | 삼성전자주식회사 | Semiconductor device |
DE102020130401A1 (en) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | DIPOLE MANUFACTURED HIGH-K-GATE DIELECTRIC AND THE PROCESS FOR ITS FORMATION |
US11784052B2 (en) | 2020-05-28 | 2023-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dipole-engineered high-k gate dielectric and method forming same |
WO2022046493A1 (en) * | 2020-08-25 | 2022-03-03 | Applied Materials, Inc. | Multi-metal lateral layer devices with internal bias generation |
US20240014320A1 (en) * | 2022-07-11 | 2024-01-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Structures for a ferroelectric field-effect transistor and related methods |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150126023A1 (en) * | 2013-11-01 | 2015-05-07 | Globalfoundries Inc. | Methods of forming gate structures with multiple work functions and the resulting products |
US20160351569A1 (en) * | 2015-05-28 | 2016-12-01 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20170053996A1 (en) * | 2015-08-20 | 2017-02-23 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices |
US20170062282A1 (en) * | 2015-07-27 | 2017-03-02 | United Microelectronics Corp. | Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate |
US20170213826A1 (en) * | 2016-01-25 | 2017-07-27 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US10134633B1 (en) * | 2017-10-24 | 2018-11-20 | Globalfoundries Inc. | Self-aligned contact with CMP stop layer |
US20200135577A1 (en) * | 2017-09-28 | 2020-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor devices |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20060120952A (en) | 2005-05-23 | 2006-11-28 | 삼성전자주식회사 | Method of forming tacn layer and manufacturing of semiconductor device using the same |
KR100868768B1 (en) | 2007-02-28 | 2008-11-13 | 삼성전자주식회사 | CMOS semiconductor device and fabrication method the same |
EP2112686B1 (en) | 2008-04-22 | 2011-10-12 | Imec | Method for fabricating a dual workfunction semiconductor device made thereof |
US9041082B2 (en) | 2010-10-07 | 2015-05-26 | International Business Machines Corporation | Engineering multiple threshold voltages in an integrated circuit |
US20120256275A1 (en) * | 2011-04-06 | 2012-10-11 | Hsin-Fu Huang | Metal gate structure and manufacturing method thereof |
US8785995B2 (en) | 2011-05-16 | 2014-07-22 | International Business Machines Corporation | Ferroelectric semiconductor transistor devices having gate modulated conductive layer |
US8673758B2 (en) | 2011-06-16 | 2014-03-18 | United Microelectronics Corp. | Structure of metal gate and fabrication method thereof |
KR20150037009A (en) | 2013-09-30 | 2015-04-08 | 에스케이하이닉스 주식회사 | Method for fabricating semiconductor device with high―k dielectric layer and method for fabricating the same |
US10468528B2 (en) | 2014-04-16 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device with high-k metal gate stack |
US9293556B2 (en) * | 2014-07-29 | 2016-03-22 | Globalfoundries Inc. | Semiconductor structure including a ferroelectric transistor and method for the formation thereof |
DE102014221371B4 (en) | 2014-10-21 | 2018-04-19 | Globalfoundries Inc. | A method of forming a semiconductor circuit element and semiconductor circuit element |
KR101701145B1 (en) | 2015-01-19 | 2017-02-01 | 한국과학기술원 | Negative capacitance logic device, clock generator including the same and method of operating the clock generator |
KR102315275B1 (en) * | 2015-10-15 | 2021-10-20 | 삼성전자 주식회사 | Integrated circuit device and method of manufacturing the same |
KR102392991B1 (en) | 2016-03-10 | 2022-04-29 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US20190326284A1 (en) * | 2016-02-11 | 2019-10-24 | Samsung Electronics Co., Ltd. | Semiconductor device including transistors with adjusted threshold voltages |
US20170338350A1 (en) | 2016-05-17 | 2017-11-23 | Globalfoundries Inc. | Semiconductor device and method |
TWI690080B (en) * | 2016-06-08 | 2020-04-01 | 聯華電子股份有限公司 | Semiconductor device |
US20170365719A1 (en) | 2016-06-15 | 2017-12-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative Capacitance Field Effect Transistor |
US9953876B1 (en) * | 2016-09-30 | 2018-04-24 | Globalfoundries Inc. | Method of forming a semiconductor device structure and semiconductor device structure |
US10229921B2 (en) * | 2017-02-03 | 2019-03-12 | International Business Machines Corporation | Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors |
US10879392B2 (en) | 2018-07-05 | 2020-12-29 | Samsung Electronics Co., Ltd. | Semiconductor device |
-
2019
- 2019-06-25 US US16/451,787 patent/US10879392B2/en active Active
- 2019-07-02 JP JP2019123512A patent/JP2020010033A/en active Pending
- 2019-07-04 CN CN201910601851.4A patent/CN110690177A/en active Pending
-
2020
- 2020-12-08 US US17/114,598 patent/US11949012B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150126023A1 (en) * | 2013-11-01 | 2015-05-07 | Globalfoundries Inc. | Methods of forming gate structures with multiple work functions and the resulting products |
US20160351569A1 (en) * | 2015-05-28 | 2016-12-01 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20170062282A1 (en) * | 2015-07-27 | 2017-03-02 | United Microelectronics Corp. | Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate |
US20170053996A1 (en) * | 2015-08-20 | 2017-02-23 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices |
US20170213826A1 (en) * | 2016-01-25 | 2017-07-27 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US20200135577A1 (en) * | 2017-09-28 | 2020-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor devices |
US10134633B1 (en) * | 2017-10-24 | 2018-11-20 | Globalfoundries Inc. | Self-aligned contact with CMP stop layer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11664279B2 (en) | 2020-02-19 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple threshold voltage implementation through lanthanum incorporation |
Also Published As
Publication number | Publication date |
---|---|
US20200013897A1 (en) | 2020-01-09 |
CN110690177A (en) | 2020-01-14 |
US11949012B2 (en) | 2024-04-02 |
US10879392B2 (en) | 2020-12-29 |
JP2020010033A (en) | 2020-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11949012B2 (en) | Semiconductor device | |
US11728332B2 (en) | Semiconductor device and manufacturing method thereof | |
US11894376B2 (en) | Integrated circuit devices and methods of fabricating such devices | |
US10600913B2 (en) | Semiconductor device and method for fabricating the same | |
US11164791B2 (en) | Contact formation for stacked vertical transport field-effect transistors | |
US11063065B2 (en) | Semiconductor device having a negative capacitance using ferroelectrical material | |
KR102557915B1 (en) | Semiconductor device | |
CN114765209A (en) | Semiconductor memory device and method of manufacturing the same | |
US20180301383A1 (en) | Semiconductor device | |
US20220069092A1 (en) | Semiconductor devices | |
US20230326971A1 (en) | Semiconductor device | |
KR20200005419A (en) | Semiconductor device | |
JP7422765B2 (en) | Dual transport orientation for stacked vertical transport field-effect transistors | |
US10930651B2 (en) | Semiconductor device | |
KR20230000235A (en) | Semiconductor device and method for fabricating the same | |
US20230108041A1 (en) | Semiconductor device | |
US20230145260A1 (en) | Semiconductor device | |
US20230402523A1 (en) | Semiconductor device | |
US20230086174A1 (en) | Semiconductor device and method of fabricating the same | |
US20230411529A1 (en) | Semiconductor device and method for fabricating the same | |
US20230163213A1 (en) | Semiconductor device | |
TW202230686A (en) | Semiconductor devices | |
KR20240039740A (en) | Semiconductor device and method of fabricating the same | |
TW202347798A (en) | Semiconductor device | |
TW202412303A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |