US20200303001A1 - Storage device - Google Patents
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- US20200303001A1 US20200303001A1 US16/559,370 US201916559370A US2020303001A1 US 20200303001 A1 US20200303001 A1 US 20200303001A1 US 201916559370 A US201916559370 A US 201916559370A US 2020303001 A1 US2020303001 A1 US 2020303001A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5614—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Definitions
- Embodiments described herein relate generally to a storage device.
- a storage device semiconductor integrated circuit device configured such that resistance change storage elements such as PCM (phase change memory) elements or iPCM (interfacial phase change memory) elements are integrated on a semiconductor substrate has been proposed.
- PCM phase change memory
- iPCM interfacial phase change memory
- FIG. 1 is a circuit diagram depicting a configuration of a storage device according to an embodiment.
- FIG. 2 schematically depicts frequency distributions of resistance values of a resistance change storage element when a PCM element or an iPCM element is used as the resistance change storage element.
- FIG. 3 schematically depicts a resistance distribution characteristic in a case of an attempt to achieve multivalued storage using the resistance change storage element having a characteristic depicted in FIG. 2 .
- FIG. 4 is a chart representing resistance values on a logarithmic scale, as opposed to the frequency distributions of the resistance values of FIG. 2 .
- FIG. 5 schematically depicts a resistance distribution characteristic in a case of an attempt to achieve the multivalued storage using the resistance change storage element having a characteristic depicted in FIG. 4 .
- FIG. 6 is a circuit diagram depicting a configuration of a first modification of the storage device according to the embodiment.
- FIG. 7 is a circuit diagram depicting a configuration of a second modification of the storage device according to the embodiment.
- FIG. 8 is a circuit diagram depicting a configuration of a third modification of the storage device according to the embodiment.
- FIG. 9 is a circuit diagram depicting a configuration of a first modification of a reference voltage generation circuit block in the storage device according to the embodiment.
- FIG. 10 is a circuit diagram depicting a configuration of a second modification of the reference voltage generation circuit block in the storage device according to the embodiment.
- FIG. 11 is a circuit diagram depicting a configuration of a third modification of the reference voltage generation circuit block in the storage device according to the embodiment.
- FIG. 12 is a circuit diagram depicting a configuration of a fourth modification of the reference voltage generation circuit block in the storage device according to the embodiment.
- An embodiment provides appropriate multivalued storage in a storage device using a resistance change storage element.
- a storage device includes: a memory cell including a storage component configured to set a plurality of data values in response to a plurality of resistance values and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage with at least one of a plurality of reference voltages.
- FIG. 1 is a circuit diagram depicting a configuration of a storage device according to the embodiment.
- the storage device includes a memory cell 10 , a word line 20 , a bit line 30 , a conversion circuit (logarithmic amplifier circuit) 40 , and a comparison circuit 50 .
- the memory cell 10 includes a resistance change storage element (or a storage component) 11 to which a plurality of data values can be set in response to resistance values, and a selection element (or a selector) connected in series to the resistance change storage element 11 .
- a resistance change storage element to which a plurality of resistance states in response to falling speeds of an applied voltage can be set, may be used as the resistance change storage element 11 .
- the resistance change storage element 11 can include at least one of: a PCM (phase change memory) element, an iPCM (interfacial phase change memory) element, an ReRAM (resistive random access memory) element, or a CBRAM (conductive bridge random access memory).
- the selection element 12 selects the resistance change storage element 11 , and a two-terminal element or a three-terminal element is used as the selection element 12 .
- a MOS transistor that is the three-terminal element is used as the selection element 12 .
- the word line 20 is connected to the memory cell 10 .
- the word line 20 is connected to a gate of the MOS transistor (selection element 12 ), and a signal for selecting the memory cell 10 is supplied to the word line 20 . That is, when a selection signal VWL is applied to the word line 20 , the MOS transistor (selection element 12 ) is turned on and the resistance change storage element 11 is selected. As a result, data can be written to or read from the resistance change storage element 11 .
- the bit line 30 to which a data signal from the memory cell 10 is input is connected to the memory cell 10 .
- data is written to or read from the selected memory cell 10 via the bit line 30 connected to the selected memory cell 10 .
- the conversion circuit 40 that nonlinearly converts a current in response to the data signal input to the bit line is connected to the bit line 30 .
- the conversion circuit 40 logarithmically converts the current input to the bit line 30 into a voltage.
- the conversion circuit 40 includes an operational amplifier 41 , PMOS transistors 42 and 43 , and a conversion element 44 .
- the conversion element 44 has a nonlinear voltage-current characteristic, nonlinearly converts the input current into the voltage, and outputs the voltage.
- the comparison circuit 50 to be described later, is connected to an input terminal of the conversion element 44 , and the bit line 30 is connected to an output terminal of the conversion element 44 . Turning on the PMOS transistor 43 by a signal VPG enables the conversion circuit 40 to operate as described above.
- a two-terminal element (or two-terminal component) having a nonlinear voltage-current characteristic is used as the conversion element 44 .
- a diode or a selector that contains a chalcogen element may be used as the two-terminal element.
- the selector that contains the chalcogen element turns into a high resistance state when a voltage applied across two terminals is lower than a threshold voltage, and turns into a low resistance state when the voltage applied across the two terminals is higher than the threshold voltage.
- the selector may contain at least one chalcogen element selected from among Te, Se, and S, or a chalcogenide that is a compound containing these chalcogen elements.
- the selector may contain at least one element selected from among B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.
- the comparison circuit 50 is connected to the conversion circuit 40 .
- the comparison circuit 50 compares the voltage into which the current is converted by the conversion circuit 40 with a plurality of reference voltages.
- the comparison circuit 50 includes a reference voltage generation circuit block 51 and an operational amplifier 52 .
- the reference voltage generation circuit block 51 generates a plurality of reference voltages, and includes a voltage-dividing circuit configured with a plurality of resistors (R 1 , R 2 , R 3 , and R 4 ) connected in series and a switch circuit configured with a plurality of switch elements (SW 1 , SW 2 , SW 3 ). Turning on any of the switch elements SW 1 , SW 2 , and SW 3 enables any of voltages V 1 , V 2 , and V 3 obtained by the voltage-dividing circuit to be supplied to an inverting input terminal of the operational amplifier 52 as a reference voltage VREF.
- a voltage Vsense into which the current is converted by the conversion circuit 40 is input to a non-inverting input terminal of the operational amplifier 52 .
- the operational amplifier 52 compares the voltage Vsense input to the non-inverting input terminal with the reference voltage VREF (voltage V 1 , V 2 , or V 3 ) input to the inverting input terminal, and outputs an output signal (output voltage VDOUT) based on a comparison result from an output terminal.
- VREF voltage V 1 , V 2 , or V 3
- the conversion circuit 40 nonlinearly converts the current from the bit line 30 into the voltage and supplies the resultant voltage to the comparison circuit 50 as described above.
- Such a configuration makes it possible to achieve appropriate multivalued storage. The description will be additionally given below.
- FIG. 2 schematically depicts frequency distributions of resistance values of the resistance change storage element when the PCM element or the iPCM element is used as the resistance change storage element.
- a horizontal axis indicates a resistance value and a vertical axis indicates a frequency (appearance frequency).
- the horizontal axis (resistance value) is represented on a linear scale.
- the PCM element and the iPCM element each has two states, for example, a low resistance state (Set state) and a high resistance state (Reset state).
- FIG. 2 schematically depicts the frequency distribution of the resistance value in a case of performing Set write and the frequency distribution of the resistance value in a case of performing Reset write.
- the resistance value of the resistance change storage element relatively has a wider distribution on a low resistance value side in the case of performing each of the Set write and the Reset write. Therefore, in a case of an attempt to achieve multivalued storage using the resistance change storage element 11 having such a resistance distribution characteristic, a resistance distribution characteristic as depicted in FIG. 3 is conceivable. Specifically, in a case of the attempt to achieve the multivalued storage by repeating writing and verification until the resistance value of the resistance change storage element 11 is set in a resistance value range corresponding to a desired data value ((0,0), (0,1), (1,0), or (1,1) in an example of FIG. 3 ), it is conceivable that resistance distribution characteristic as depicted in FIG. 3 is obtained. With such a resistance distribution characteristic, the resistance value range is extremely narrow on the low resistance value side; thus, it is difficult to perform an accurate read operation.
- FIG. 4 represents the horizontal axis (resistance value) on a logarithmic scale, as opposed to the resistance distribution characteristic of FIG. 2 .
- the horizontal axis (resistance value) is represented on a logarithmic scale, it appears that the resistance distribution characteristic (frequency distribution) is averaged, compared with the case of FIG. 2 where the horizontal axis (resistance value) is represented on a linear scale.
- the resistance distribution characteristic of the multivalued storage depicted in FIG. 3 is changed to that depicted in FIG. 5 . That is, it appears that the resistance value ranges (resistance value ranges corresponding to the data values (0,0), (0,1), (1,0), and (1,1), respectively of the resistance distribution characteristic) are equalized.
- the conversion circuit 40 that nonlinearly converting the current from the bit line 30 into the voltage is provided on the basis of a content described above. As depicted in FIG. 5 , it is thereby possible to equalize the resistance value distributions of the resistance distribution characteristic in a logarithmic graph. This also enables the comparison circuit 50 to use the equalized reference voltages (V 1 , V 2 , or V 3 ), so that the comparison circuit 50 can perform a precise comparison operation. In the present embodiment, therefore, it is possible to perform a precise read operation and achieve a nonvolatile storage device capable of appropriate multivalued storage.
- FIG. 6 is a circuit configuration depicting a configuration of a first modification of the storage device according to the present embodiment.
- a diode-connected three-terminal element (or diode-connected three-terminal component) is used as the conversion element 44 .
- a PMOS transistor having a gate and a drain connected to each other is used as the conversion element 44 . Even with such a configuration, similar operations to those in the embodiment can be achieved and similar advantages to those of the embodiment can be obtained.
- FIG. 7 is a circuit configuration depicting a configuration of a second modification of the storage device according to the present embodiment.
- a diode-connected three-terminal element is used as the conversion element 44 .
- a bipolar transistor having a base and a collector connected to each other is used as the conversion element 44 .
- FIG. 8 is a circuit configuration depicting a configuration of a third modification of the storage device according to the present embodiment.
- a two-terminal element is used as the selection element 12 .
- a selector that is the two-terminal element having a nonlinear voltage-current characteristic and that may be a diode or may contain a chalcogen element is used as the switching element.
- the diode or a selector as illustrated with reference to FIG. 1 or the selector that contains the chalcogen element as illustrated in the present modification may be used as the two-terminal element used as the selection element 12 .
- a terminal that is not connected to the resistance change storage element 11 out of two terminals of the selection element 12 is connected to the word line 20 .
- Applying the selection signal VWL to the word line 20 to turn on the selection element 12 makes it possible to select the memory cell 10 and to write or read data to or from the resistance change storage element 11 .
- the reference voltage generation circuit block 51 in the comparison circuit 50 divides a power supply voltage by resistances and generates the reference voltages in the embodiment and the modifications described above.
- the diode, the PMOS transistor, and the bipolar transistor have temperature dependence, the generated reference voltages may be subjected to temperature dependence.
- FIGS. 9, 10, 11, and 12 are circuit diagrams depicting configurations of first, second, third, and fourth modifications of the reference voltage generation circuit block 51 , respectively.
- the reference voltage generation circuit block 51 is configured to generate the reference voltages having the temperature dependence.
- the reference voltage generation circuit block 51 includes a plurality of reference voltage generation circuits 51 a , 51 b , and 51 c.
- the reference voltage generation circuit 51 a includes a reference resistance element (or reference resistor) 111 a , a reference selection element (or reference selector) 112 a connected in series to the reference resistance element 111 a , a reference word line 120 a to which a signal for selecting the reference selection element 112 a is supplied, a reference bit line 130 a to which a reference current is input from the reference resistance element 111 a , and a conversion circuit 140 a that nonlinearly converts the reference current input to the reference bit line 130 a into a reference voltage.
- the conversion circuit 140 a includes an operational amplifier 141 a , PMOS transistors 142 a and 143 a , and a conversion element 144 a.
- the reference voltage generation circuit 51 b includes a reference resistance element 111 b , a reference selection element 112 b , a reference word line 120 b , a reference bit line 130 b , and a conversion circuit 140 b (an operational amplifier 141 b , PMOS transistors 142 b and 143 b , and a conversion element 144 b ).
- the reference voltage generation circuit 51 c includes a reference resistance element 111 c , a reference selection element 112 c , a reference word line 120 c , a reference bit line 130 c , and a conversion circuit 140 c (an operational amplifier 141 c , PMOS transistors 142 c and 143 c , and a conversion element 144 c ).
- the conversion circuits 140 a , 140 b , and 140 c described above have the same circuit configuration and the same circuit characteristic as those of the conversion circuit 40 depicted in FIG. 1 . Any of the reference voltages V 1 , V 2 , and V 3 generated by the conversion circuit 140 a , 140 b , and 140 c is supplied to the inverting input terminal of the operational amplifier 52 depicted in FIG. 1 via any of the switch elements SW 1 , SW 2 , and SW 3 depicted in FIG. 1 .
- a resistance value of the reference resistance element 111 a is Ra
- a resistance value of the reference resistance element 111 b is Rb
- a resistance value of the reference resistance element 111 c is Rc.
- a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (0,0) is R (0,0)
- a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (0,1) is R (0,1)
- a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (1,0) is R (1,0)
- a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (1,1) is R (1,1) .
- the resistance values R (0,0) , R (0,1) , R (1,0) , and R (1,1) are set to satisfy the following equations.
- log Rb (log R (1,0) +log R (0,1) )/2
- log Rc (log R (0,1) +log R (0,0) )/2
- a basic configuration of a second modification depicted in FIG. 10 is similar to that of the first modification described above, and the reference voltage generation circuit block 51 includes the plurality of reference voltage generation circuits 51 a , 51 b , and 51 c .
- PMOS transistors each having a gate and a drain connected to each other are used as the conversion elements 144 a , 144 b , and 144 c .
- the conversion circuits 140 a , 140 b , and 140 c have the same circuit configuration and the same circuit characteristic as those of the conversion circuit 40 depicted in FIG. 6 .
- a basic configuration of a third modification depicted in FIG. 11 is similar to that of the first modification described above, and the reference voltage generation circuit block 51 includes the plurality of reference voltage generation circuits 51 a , 51 b , and 51 c .
- the reference voltage generation circuit block 51 includes the plurality of reference voltage generation circuits 51 a , 51 b , and 51 c .
- bipolar transistors each having a base and a collector connected to each other are used as the conversion elements 144 a , 144 b , and 144 c .
- the conversion circuits 140 a , 140 b , and 140 c have the same circuit configuration and the same circuit characteristic as those of the conversion circuit 40 depicted in FIG. 7 .
- a basic configuration of a fourth modification depicted in FIG. 12 is similar to that of the first modification described above, and the reference voltage generation circuit block 51 includes the plurality of reference voltage generation circuits 51 a , 51 b , and 51 c .
- the reference voltage generation circuit block 51 includes the plurality of reference voltage generation circuits 51 a , 51 b , and 51 c .
- two-terminal switching elements each having a nonlinear voltage-current characteristic are used as the reference selection elements 112 a , 112 b , and 112 c .
- Selection elements similar to the selection element 12 depicted in FIG. 8 may be used as the reference selection elements 112 a , 112 b , and 112 c .
- the conversion circuits 140 a , 140 b , and 140 c have the same circuit configuration and the same circuit characteristic as those of the conversion circuit 40 depicted in FIG. 8 .
- the multivalued storage may be achieved by performing writing while a pulse waveform is changed in response to a write signal.
- PCM element or the iPCM element is used as the resistance change storage element in the embodiment and the various modifications described above, an ReRAM (resistive random access memory) element or a CBRAM (conductive bridge random access memory) element may be used as the resistance change storage element.
- ReRAM resistive random access memory
- CBRAM conductive bridge random access memory
Abstract
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-053481, filed Mar. 20, 2019, the entire contents of which are incorporated herein by reference.
- Embodiments described herein relate generally to a storage device.
- A storage device (semiconductor integrated circuit device) configured such that resistance change storage elements such as PCM (phase change memory) elements or iPCM (interfacial phase change memory) elements are integrated on a semiconductor substrate has been proposed.
- To achieve multivalued storage in the storage device using the resistance change storage elements described above, existing storage devices are not entirely satisfactory.
- Examples of related art include JP-A-H07-159426 and 2018 International Conference on Solid State Devices and Materials, Tokyo, 2018, pp 93-94 Superior Multilevel Resistive Switching Behaviors of N2-Plasma-Treated Stacked SiNx/GdOx RRAMs Ya-Ting Chan1, Yi Fu1, Tzu-Ming Chu1, and Jer-Chyi Wang1,2,3,* 1Department of Electronic Engineering, Chang Gung University, Guishan Dist. 33302, Taoyuan, Taiwan. 2Department of Neurosurgery, Chang Gung Memorial Hospital, Guishan Dist. 33305, Taoyuan, Taiwan. 3Department of Electronic Engineering, Ming Chi University of Technology, Taishan Dist. 24301, New Taipei City, Taiwan. Phone: +886-3-2118800 ext.5784 E-mail: jcwang@mail.cgu.edu.tw
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FIG. 1 is a circuit diagram depicting a configuration of a storage device according to an embodiment. -
FIG. 2 schematically depicts frequency distributions of resistance values of a resistance change storage element when a PCM element or an iPCM element is used as the resistance change storage element. -
FIG. 3 schematically depicts a resistance distribution characteristic in a case of an attempt to achieve multivalued storage using the resistance change storage element having a characteristic depicted inFIG. 2 . -
FIG. 4 is a chart representing resistance values on a logarithmic scale, as opposed to the frequency distributions of the resistance values ofFIG. 2 . -
FIG. 5 schematically depicts a resistance distribution characteristic in a case of an attempt to achieve the multivalued storage using the resistance change storage element having a characteristic depicted inFIG. 4 . -
FIG. 6 is a circuit diagram depicting a configuration of a first modification of the storage device according to the embodiment. -
FIG. 7 is a circuit diagram depicting a configuration of a second modification of the storage device according to the embodiment. -
FIG. 8 is a circuit diagram depicting a configuration of a third modification of the storage device according to the embodiment. -
FIG. 9 is a circuit diagram depicting a configuration of a first modification of a reference voltage generation circuit block in the storage device according to the embodiment. -
FIG. 10 is a circuit diagram depicting a configuration of a second modification of the reference voltage generation circuit block in the storage device according to the embodiment. -
FIG. 11 is a circuit diagram depicting a configuration of a third modification of the reference voltage generation circuit block in the storage device according to the embodiment. -
FIG. 12 is a circuit diagram depicting a configuration of a fourth modification of the reference voltage generation circuit block in the storage device according to the embodiment. - An embodiment provides appropriate multivalued storage in a storage device using a resistance change storage element.
- In general, according to one embodiment, a storage device includes: a memory cell including a storage component configured to set a plurality of data values in response to a plurality of resistance values and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage with at least one of a plurality of reference voltages.
- An embodiment will be described hereinafter with reference to the drawings.
-
FIG. 1 is a circuit diagram depicting a configuration of a storage device according to the embodiment. - The storage device according to the present embodiment includes a
memory cell 10, aword line 20, abit line 30, a conversion circuit (logarithmic amplifier circuit) 40, and acomparison circuit 50. - The
memory cell 10 includes a resistance change storage element (or a storage component) 11 to which a plurality of data values can be set in response to resistance values, and a selection element (or a selector) connected in series to the resistancechange storage element 11. - For example, a resistance change storage element, to which a plurality of resistance states in response to falling speeds of an applied voltage can be set, may be used as the resistance
change storage element 11. Specifically, the resistancechange storage element 11 can include at least one of: a PCM (phase change memory) element, an iPCM (interfacial phase change memory) element, an ReRAM (resistive random access memory) element, or a CBRAM (conductive bridge random access memory). - The
selection element 12 selects the resistancechange storage element 11, and a two-terminal element or a three-terminal element is used as theselection element 12. In the example depicted inFIG. 1 , a MOS transistor that is the three-terminal element is used as theselection element 12. - The
word line 20 is connected to thememory cell 10. Specifically, theword line 20 is connected to a gate of the MOS transistor (selection element 12), and a signal for selecting thememory cell 10 is supplied to theword line 20. That is, when a selection signal VWL is applied to theword line 20, the MOS transistor (selection element 12) is turned on and the resistancechange storage element 11 is selected. As a result, data can be written to or read from the resistancechange storage element 11. - The
bit line 30 to which a data signal from thememory cell 10 is input is connected to thememory cell 10. In other words, when thememory cell 10 is selected as described above, data is written to or read from theselected memory cell 10 via thebit line 30 connected to theselected memory cell 10. - The
conversion circuit 40 that nonlinearly converts a current in response to the data signal input to the bit line is connected to thebit line 30. For example, theconversion circuit 40 logarithmically converts the current input to thebit line 30 into a voltage. - The
conversion circuit 40 includes anoperational amplifier 41,PMOS transistors conversion element 44. Theconversion element 44 has a nonlinear voltage-current characteristic, nonlinearly converts the input current into the voltage, and outputs the voltage. Thecomparison circuit 50, to be described later, is connected to an input terminal of theconversion element 44, and thebit line 30 is connected to an output terminal of theconversion element 44. Turning on thePMOS transistor 43 by a signal VPG enables theconversion circuit 40 to operate as described above. - In an example depicted in
FIG. 1 , a two-terminal element (or two-terminal component) having a nonlinear voltage-current characteristic is used as theconversion element 44. - As the two-terminal element, a diode or a selector that contains a chalcogen element may be used.
- The selector that contains the chalcogen element turns into a high resistance state when a voltage applied across two terminals is lower than a threshold voltage, and turns into a low resistance state when the voltage applied across the two terminals is higher than the threshold voltage. The selector may contain at least one chalcogen element selected from among Te, Se, and S, or a chalcogenide that is a compound containing these chalcogen elements. Furthermore, the selector may contain at least one element selected from among B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.
- The
comparison circuit 50 is connected to theconversion circuit 40. Thecomparison circuit 50 compares the voltage into which the current is converted by theconversion circuit 40 with a plurality of reference voltages. Thecomparison circuit 50 includes a reference voltagegeneration circuit block 51 and anoperational amplifier 52. - The reference voltage
generation circuit block 51 generates a plurality of reference voltages, and includes a voltage-dividing circuit configured with a plurality of resistors (R1, R2, R3, and R4) connected in series and a switch circuit configured with a plurality of switch elements (SW1, SW2, SW3). Turning on any of the switch elements SW1, SW2, and SW3 enables any of voltages V1, V2, and V3 obtained by the voltage-dividing circuit to be supplied to an inverting input terminal of theoperational amplifier 52 as a reference voltage VREF. - A voltage Vsense into which the current is converted by the
conversion circuit 40 is input to a non-inverting input terminal of theoperational amplifier 52. Theoperational amplifier 52 compares the voltage Vsense input to the non-inverting input terminal with the reference voltage VREF (voltage V1, V2, or V3) input to the inverting input terminal, and outputs an output signal (output voltage VDOUT) based on a comparison result from an output terminal. - In the present embodiment, the
conversion circuit 40 nonlinearly converts the current from thebit line 30 into the voltage and supplies the resultant voltage to thecomparison circuit 50 as described above. Such a configuration makes it possible to achieve appropriate multivalued storage. The description will be additionally given below. -
FIG. 2 schematically depicts frequency distributions of resistance values of the resistance change storage element when the PCM element or the iPCM element is used as the resistance change storage element. A horizontal axis indicates a resistance value and a vertical axis indicates a frequency (appearance frequency). The horizontal axis (resistance value) is represented on a linear scale. In general, the PCM element and the iPCM element each has two states, for example, a low resistance state (Set state) and a high resistance state (Reset state).FIG. 2 schematically depicts the frequency distribution of the resistance value in a case of performing Set write and the frequency distribution of the resistance value in a case of performing Reset write. - As depicted in
FIG. 2 , the resistance value of the resistance change storage element relatively has a wider distribution on a low resistance value side in the case of performing each of the Set write and the Reset write. Therefore, in a case of an attempt to achieve multivalued storage using the resistancechange storage element 11 having such a resistance distribution characteristic, a resistance distribution characteristic as depicted inFIG. 3 is conceivable. Specifically, in a case of the attempt to achieve the multivalued storage by repeating writing and verification until the resistance value of the resistancechange storage element 11 is set in a resistance value range corresponding to a desired data value ((0,0), (0,1), (1,0), or (1,1) in an example ofFIG. 3 ), it is conceivable that resistance distribution characteristic as depicted in FIG. 3 is obtained. With such a resistance distribution characteristic, the resistance value range is extremely narrow on the low resistance value side; thus, it is difficult to perform an accurate read operation. -
FIG. 4 represents the horizontal axis (resistance value) on a logarithmic scale, as opposed to the resistance distribution characteristic ofFIG. 2 . As depicted inFIG. 4 , when the horizontal axis (resistance value) is represented on a logarithmic scale, it appears that the resistance distribution characteristic (frequency distribution) is averaged, compared with the case ofFIG. 2 where the horizontal axis (resistance value) is represented on a linear scale. - Taking this into consideration, when the horizontal axis is represented on a logarithmic scale, it is conceivable that the resistance distribution characteristic of the multivalued storage depicted in
FIG. 3 is changed to that depicted inFIG. 5 . That is, it appears that the resistance value ranges (resistance value ranges corresponding to the data values (0,0), (0,1), (1,0), and (1,1), respectively of the resistance distribution characteristic) are equalized. - In the present embodiment, the
conversion circuit 40 that nonlinearly converting the current from thebit line 30 into the voltage is provided on the basis of a content described above. As depicted inFIG. 5 , it is thereby possible to equalize the resistance value distributions of the resistance distribution characteristic in a logarithmic graph. This also enables thecomparison circuit 50 to use the equalized reference voltages (V1, V2, or V3), so that thecomparison circuit 50 can perform a precise comparison operation. In the present embodiment, therefore, it is possible to perform a precise read operation and achieve a nonvolatile storage device capable of appropriate multivalued storage. - Various modifications of the present embodiment will next be described.
-
FIG. 6 is a circuit configuration depicting a configuration of a first modification of the storage device according to the present embodiment. In the present configuration example, a diode-connected three-terminal element (or diode-connected three-terminal component) is used as theconversion element 44. Specifically, a PMOS transistor having a gate and a drain connected to each other is used as theconversion element 44. Even with such a configuration, similar operations to those in the embodiment can be achieved and similar advantages to those of the embodiment can be obtained. -
FIG. 7 is a circuit configuration depicting a configuration of a second modification of the storage device according to the present embodiment. In the present configuration example similarly to the first modification, a diode-connected three-terminal element is used as theconversion element 44. Specifically, a bipolar transistor having a base and a collector connected to each other is used as theconversion element 44. Even with such a configuration, similar operations to those in the embodiment can be achieved and similar advantages to those of the embodiment can be obtained. -
FIG. 8 is a circuit configuration depicting a configuration of a third modification of the storage device according to the present embodiment. In an example of the present configuration, a two-terminal element is used as theselection element 12. Specifically, a selector that is the two-terminal element having a nonlinear voltage-current characteristic and that may be a diode or may contain a chalcogen element is used as the switching element. As the two-terminal element used as theselection element 12, the diode or a selector as illustrated with reference toFIG. 1 or the selector that contains the chalcogen element as illustrated in the present modification may be used. - In a case of using the two-terminal element as the
selection element 12 as described in the present modification, a terminal that is not connected to the resistancechange storage element 11 out of two terminals of theselection element 12 is connected to theword line 20. Applying the selection signal VWL to theword line 20 to turn on theselection element 12 makes it possible to select thememory cell 10 and to write or read data to or from the resistancechange storage element 11. - It is noted that a configuration of combining the first, second, and third modifications as appropriate may also be adopted.
- Furthermore, the reference voltage
generation circuit block 51 in thecomparison circuit 50 divides a power supply voltage by resistances and generates the reference voltages in the embodiment and the modifications described above. However, since the diode, the PMOS transistor, and the bipolar transistor have temperature dependence, the generated reference voltages may be subjected to temperature dependence. -
FIGS. 9, 10, 11, and 12 are circuit diagrams depicting configurations of first, second, third, and fourth modifications of the reference voltagegeneration circuit block 51, respectively. In any of the modifications, the reference voltagegeneration circuit block 51 is configured to generate the reference voltages having the temperature dependence. - In the first modification depicted in
FIG. 9 , the reference voltagegeneration circuit block 51 includes a plurality of referencevoltage generation circuits - The reference
voltage generation circuit 51 a includes a reference resistance element (or reference resistor) 111 a, a reference selection element (or reference selector) 112 a connected in series to thereference resistance element 111 a, areference word line 120 a to which a signal for selecting thereference selection element 112 a is supplied, areference bit line 130 a to which a reference current is input from thereference resistance element 111 a, and aconversion circuit 140 a that nonlinearly converts the reference current input to thereference bit line 130 a into a reference voltage. Theconversion circuit 140 a includes anoperational amplifier 141 a,PMOS transistors conversion element 144 a. - Basic configurations of the reference
voltage generation circuits voltage generation circuit 51 a. That is, the referencevoltage generation circuit 51 b includes areference resistance element 111 b, areference selection element 112 b, areference word line 120 b, areference bit line 130 b, and aconversion circuit 140 b (anoperational amplifier 141 b,PMOS transistors conversion element 144 b). The referencevoltage generation circuit 51 c includes areference resistance element 111 c, areference selection element 112 c, areference word line 120 c, areference bit line 130 c, and aconversion circuit 140 c (anoperational amplifier 141 c,PMOS transistors conversion element 144 c). - The
conversion circuits conversion circuit 40 depicted inFIG. 1 . Any of the reference voltages V1, V2, and V3 generated by theconversion circuit operational amplifier 52 depicted inFIG. 1 via any of the switch elements SW1, SW2, and SW3 depicted inFIG. 1 . - In the configuration described above, it is assumed that a resistance value of the
reference resistance element 111 a is Ra, a resistance value of thereference resistance element 111 b is Rb, and a resistance value of thereference resistance element 111 c is Rc. Furthermore, it is assumed that for the resistance distribution characteristic of the resistancechange storage element 11 depicted in 1, a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (0,0) is R(0,0), a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (0,1) is R(0,1), a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (1,0) is R(1,0), and a resistance value at a center of a resistance distribution characteristic part corresponding to the data value (1,1) is R(1,1). - In this case, the resistance values R(0,0), R(0,1), R(1,0), and R(1,1) are set to satisfy the following equations.
-
log Ra=(log R (1,1)+log R (1,0))/2 -
log Rb=(log R (1,0)+log R (0,1))/2 -
log Rc=(log R (0,1)+log R (0,0))/2 - Setting the resistance values in this way makes it possible to optimize the resistance values Ra, Rb, and Rc of the
reference resistance elements FIG. 5 (on a logarithmic scale) even if a temperature changes. That is, inFIG. 5 (on a logarithmic scale), it is possible to locate the resistance value Ra of thereference resistance element 111 a at a midpoint between the resistance value R(1,1) at the center of the resistance distribution characteristic part corresponding to the data value (1,1) and the resistance value R(1,0) at the center of the resistance distribution characteristic part corresponding to the data value (1,0), locate the resistance value Rb of thereference resistance element 111 b at a midpoint between the resistance value R(1,0) at the center of the resistance distribution characteristic part corresponding to the data value (1,0) and the resistance value R(0,1) at the center of the resistance distribution characteristic part corresponding to the data value (0,1), and locate the resistance value Rc of thereference resistance element 111 c at a midpoint between the resistance value R(0,1) at the center of the resistance distribution characteristic part corresponding to the data value (0,1) and the resistance value R(0,0) at the center of the resistance distribution characteristic part corresponding to the data value (0,0). - The above relationship will be generalized. When it is assumed that x is a positive integer value, a resistance value at a center of the x-th resistance distribution characteristic part having an x-th lowest resistance value is Rx, resistance value at a center of the (x+1)-th resistance distribution characteristic part is Rx+1, and a resistance value of the reference resistance element having the resistance value between the resistance values Rx and Rx+1 is Rrefx−x+1, the following equation is satisfied.
-
log R refx−x+1=(log R x+log R x+1)/2 - A basic configuration of a second modification depicted in
FIG. 10 is similar to that of the first modification described above, and the reference voltagegeneration circuit block 51 includes the plurality of referencevoltage generation circuits conversion elements conversion circuits conversion circuit 40 depicted inFIG. 6 . - A basic configuration of a third modification depicted in
FIG. 11 is similar to that of the first modification described above, and the reference voltagegeneration circuit block 51 includes the plurality of referencevoltage generation circuits conversion elements conversion circuits conversion circuit 40 depicted inFIG. 7 . - A basic configuration of a fourth modification depicted in
FIG. 12 is similar to that of the first modification described above, and the reference voltagegeneration circuit block 51 includes the plurality of referencevoltage generation circuits reference selection elements selection element 12 depicted inFIG. 8 may be used as thereference selection elements conversion circuits conversion circuit 40 depicted inFIG. 8 . - The second, third, and fourth modifications described above can obtain similar advantages to those of the first modification.
- Moreover, while the case of achieving the multivalued storage by repeating writing and verification using a type of a pulse waveform is described in the embodiment and the various modifications described above, the multivalued storage may be achieved by performing writing while a pulse waveform is changed in response to a write signal.
- Furthermore, while the PCM element or the iPCM element is used as the resistance change storage element in the embodiment and the various modifications described above, an ReRAM (resistive random access memory) element or a CBRAM (conductive bridge random access memory) element may be used as the resistance change storage element.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (15)
log R refx−x+1=(log R x+log R x+1)/2,
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US11150873B2 (en) * | 2019-05-30 | 2021-10-19 | Kabushiki Kaisha Toshiba | Arithmetic apparatus |
US20220020411A1 (en) * | 2020-07-20 | 2022-01-20 | Nxp Usa, Inc. | Resistive memory with adjustable write parameter |
US11615840B2 (en) | 2019-09-19 | 2023-03-28 | Kioxia Corporation | Memory device |
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US5969340A (en) | 1995-09-22 | 1999-10-19 | Vansco Electronics Ltd. | Seed counting apparatus for a planter monitor |
EP1858027A1 (en) * | 2006-05-19 | 2007-11-21 | STMicroelectronics S.r.l. | A sensing circuit for semiconductor memories |
JP2008054077A (en) | 2006-08-25 | 2008-03-06 | Toshiba Corp | Logarithmic compression type analog-digital conversion circuit and semiconductor photosensor |
US20100220514A1 (en) * | 2009-03-02 | 2010-09-02 | Lyric Semiconductor, Inc. | Storage devices with soft processing |
JP6387022B2 (en) * | 2013-02-28 | 2018-09-05 | ヘルトアイス,クリストフ | Method for determining active input element of input setter and input setter |
JP6598493B2 (en) * | 2015-04-17 | 2019-10-30 | キヤノン株式会社 | Current-voltage conversion circuit, receiver, and imaging system |
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US11150873B2 (en) * | 2019-05-30 | 2021-10-19 | Kabushiki Kaisha Toshiba | Arithmetic apparatus |
US11615840B2 (en) | 2019-09-19 | 2023-03-28 | Kioxia Corporation | Memory device |
US20220020411A1 (en) * | 2020-07-20 | 2022-01-20 | Nxp Usa, Inc. | Resistive memory with adjustable write parameter |
US11581030B2 (en) * | 2020-07-20 | 2023-02-14 | Nxp Usa, Inc. | Resistive memory with adjustable write parameter |
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