US20160314836A1 - Reference voltage generation apparatuses and methods - Google Patents
Reference voltage generation apparatuses and methods Download PDFInfo
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- US20160314836A1 US20160314836A1 US14/693,275 US201514693275A US2016314836A1 US 20160314836 A1 US20160314836 A1 US 20160314836A1 US 201514693275 A US201514693275 A US 201514693275A US 2016314836 A1 US2016314836 A1 US 2016314836A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G11C2213/70—Resistive array aspects
- G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
Definitions
- RAM random-access memory
- ROM read only memory
- DRAM dynamic random access memory
- SDRAM synchronous dynamic random access memory
- non-volatile e.g., phase change memory, flash
- Non-volatile memories are useful elements of integrated circuits due to their ability to maintain data after removal of a power supply.
- Phase change materials have been investigated for use in non-volatile memory cells.
- Phase change memory (PCM) elements include phase change materials, such as chalcogenic semiconductor materials (e.g., chalcogenide alloys), that are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state that distinguishes the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance and a crystalline state exhibits a relatively low resistance.
- One of different logic levels e.g., logic 1 or logic 0
- the resistivity may vary by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
- each memory cell typically includes both a phase change memory element (PM) connected in series with a select device (SD).
- the SD may be a switching element that includes a diode, a transistor, or an ovonic threshold switch (OTS).
- OTS ovonic threshold switch
- the OTS is constructed with a chalcogenic material (i.e., it is an alloy containing at least one chalcogenic element). The OTS begins to conduct when a voltage above a threshold voltage V th is applied across the switch.
- the threshold voltage V th of the OTS is subject to drift over time.
- the threshold voltage drift may be harmful for OTS-selected memory arrays since it may prevent the storage element of chalcogenic material from being correctly read.
- the threshold voltage V th of the selector is not known with satisfactory precision and the chalcogenic storage element is crystalline (e.g., stores a logic “1”), the memory cell may be read as a logic “0” since, at the reading voltage, the switch has not yet transitioned to the conductive state.
- FIG. 1 shows the architecture of a memory array according to an embodiment of the present invention.
- FIG. 2 shows the electrical equivalent of a memory cell having a threshold switch according to an embodiment of the present invention.
- FIG. 3 shows a plot of current versus voltage characteristics for a threshold switch according to an embodiment of the present invention.
- FIG. 4 shows a plot of current versus voltage for a variable resistance memory element according to an embodiment of the present invention.
- FIG. 5 shows an electrical schematic diagram of a reference voltage generation apparatus to track threshold voltage shift in a memory cell according to an embodiment of the present invention.
- FIG. 6 shows a plot of bit line voltage versus time of a reference node voltage according to an embodiment of the present invention.
- FIG. 7 shows a flowchart of a method for performing a memory operation according to an embodiment of the present invention.
- FIG. 8 shows a block diagram of a system according to an embodiment of the present invention.
- apparatus, systems, and methods are described herein that may track cross-point memory cell threshold voltage based on a chalcogenide select device. Examples of such embodiments are now described in detail.
- FIG. 1 shows the architecture of a memory array according to an embodiment of the present invention.
- a plurality of memory cells 100 are arranged in rows and columns to form the array.
- the memory array may be referred to as a cross-point memory array since the memory cells 100 are interposed at cross-points between rows 102 (i.e., word lines) and columns 104 (i.e., bit lines) of the array.
- the memory cells 100 may include variable resistance memory cells as well as other types of memory cell technology.
- Each memory cell 100 includes a memory element 110 coupled in series with, and adjacent to, a select device 111 represented as a switch.
- FIG. 2 shows the electrical equivalent of a memory cell 100 (PM) having an ovonic threshold switch 111 (OTS) according to an embodiment of the present invention.
- the connection order of the memory element 110 (PM) and the select device (SD) 111 is for purposes of illustration only and may be reversed in another embodiment.
- the memory element 110 may include any variable-resistance memory element such as a memory element constructed of chalcogenic semiconductor materials having at least two distinct metastable phases (e.g., crystalline and amorphous).
- the memory element 110 is the data storage device of the memory cell 100 . If the memory element 110 is a PCM, its amorphous, high resistivity state may be referred to as a “reset” state while the crystalline, low resistivity state may be referred to as a “set” state.
- variable resistance material at the heart of a memory element 110 does not usually function as a linear resistor (unless it is in its fully crystallized state). Instead, the current passed by a variable resistance material will depend exponentially on the applied voltage. Accuracy in the read voltage (i.e. the voltage precharged onto the bit line before the select device is turned on) is therefore important in obtaining an accurate read operation.
- the select device 111 may be any type of switch that turns on to conduct current when a voltage across the switch is equal to or greater than a threshold voltage V th .
- the select device 111 may comprise a chalcogenic semiconductor material fixed in a single phase (generally amorphous) with two distinct regions of operation associated with different resistivities (e.g., ovonic threshold switch).
- a terminal of the select device 111 of each memory cell 100 is coupled to a respective bit line 104 .
- a terminal of the memory element 110 of each memory cell is coupled to a respective word line 102 .
- a memory array may be broken down into sub-elements such as tiles where a tile may comprise a group of memory cells.
- FIG. 3 shows a plot of current versus voltage characteristics for a threshold switch in a memory cell according to an embodiment of the present invention.
- the y-axis represents the threshold switch current I SD while the x-axis represents the threshold switch voltage V SD .
- the threshold switch has a high resistance for voltages below the threshold voltage V th,SD .
- the switch begins to conduct at a substantially constant, low voltage and has a low impedance. In this condition, if the memory element is in the set state, as seen in FIG. 4 , the memory cell is turned on. If the memory element is in the reset state, the memory cell remains off.
- the threshold switch When the current I SD falls below a hold current I H , the threshold switch returns to the high-impedance state. This behavior is symmetrical and also occurs when negative voltages are applied, and negative currents flow (not shown).
- FIG. 4 shows a plot of current versus voltage for a variable resistance memory element according to an embodiment of the present invention.
- the y-axis represents the memory element current I PM while the x-axis represents the memory element voltage V PM .
- the plot 400 of the amorphous state (i.e., reset state) of a variable resistance memory element is similar to the plot of the threshold switch performance as seen in FIG. 3 .
- the plot 401 of the crystalline state (i.e., set state) shows that the memory element has a lower conductance in the lower portion of the plot and a higher conductance in the upper portion.
- the problem associated with the threshold voltage (V th ) drift of the select device may be solved in many instances by using a circuit having a reference memory cell (or cells) to detect and store the threshold voltage V th of a cross-point memory cell based on the behavior of a chalcogenide select device.
- the reference memory cell(s) may provide a reference voltage for reading a plurality of memory cells.
- FIG. 5 shows an electrical schematic diagram of a reference voltage generation apparatus to track threshold voltage shift in a memory cell according to an embodiment of the present invention.
- the circuit uses a reference memory cell 500 that stores the threshold voltage.
- the reference memory cell 500 is fabricated so as to be located relatively close to the memory cell or group of memory cells for which it operates as the associated reference memory cell.
- the circuit of FIG. 5 generates a reference voltage V REF at the reference node that tracks the threshold voltage of a memory cell (or cells) (e.g., select device) as the threshold voltage shifts over time.
- the reference voltage V REF tracks the natural drift of V th for chalcogenide select devices and may be generated in a relatively short time (e.g., ⁇ 10 nanoseconds (ns)) that is compatible with a desired latency of storage class memories (approximately 100 ns). This is accomplished in the illustrated embodiment by using a PCM memory element in a set (i.e., crystallized) state as the reference cell.
- the reference voltage circuit includes a current source 501 that generates current I MIRROR .
- the illustrated embodiment uses a current mirror circuit comprising a pair of transistors 510 , 511 (e.g., p-type metal oxide semiconductor field effect transistors (MOSFETs)) coupled together at their control gates and their sources coupled to a first power supply that supplies positive supply voltage V PP .
- the current mirror circuit 501 further comprises a resistance R S 512 coupled between one of the transistors 510 and ground. In some embodiments, other current mirror source circuit configurations are used.
- the current source 501 is coupled to a pair of series-connected transistors 530 , 531 (e.g., p-type MOSFETs) in the I MIRROR path.
- These transistors 530 , 531 represent the bit line (sometimes referred to as a data line) decoding circuitry (i.e., column decoder) 560 for the memory cells to which the reference voltage circuit is coupled.
- the transistors 530 , 531 representing the bit line decoding circuitry 560 are for purposes of illustration only as there may be other quantities of memory cells to which the reference voltage circuit is coupled and, thus, the number of decoding path transistors 530 , 531 may be different.
- one reference cell may be used for each set of bits (e.g., the number of bits that form a word) that are written or read substantially simultaneously. For example, if 128 bits are read across 128 tiles in order to build one word (i.e., one bit per tile is read), one tile of reference cells may be used for every 128 tiles in order to track the threshold voltage V th for the bits included in each single word.
- the reference node REF between the current source 501 and the pair of series-connected transistors 530 , 531 provides the V REF voltage.
- the capacitance C REF 520 may represent a capacitance of an input node of an operational amplifier, of a bit line decoding path, configured as a buffer with unity gain.
- the capacitance C REF 520 may also represent an extra capacitance specifically added to the circuit for the purpose of maintaining the V REF voltage for a particular time during a read operation.
- the C REF 520 has a capacitance of approximately 400 femtofarads (fF).
- the reference memory cell 500 is coupled to one of the series-connected transistors 531 at a local bit line node LBL.
- the capacitance of the local bit lines that are coupled to the reference voltage circuit of FIG. 4 may be represented by the capacitance C LBL 535 .
- C LBL 535 has a capacitance of approximately 40 fF.
- the reference memory cell 500 is coupled to a clamp circuit 540 at a local word line (sometimes known to those of ordinary skill in the art as a word line) node LWL.
- the capacitance of the local word lines that are coupled to the reference voltage circuit of FIG. 4 may be represented by the capacitance C LWL 436 .
- C LWL 536 has a capacitance of approximately 40 fF.
- C LwL 436 is the capacitance that is equalized when the reference cell 500 reaches its threshold voltage.
- the clamp circuit 540 is represented by an n-channel MOSFET 540 with a control gate biased at V CLAMP .
- the clamp circuit 540 is coupled between the reference memory cell 500 and a second power supply that supplies a supply voltage V NN that is less than the V PP voltage.
- one or more access line (row) decoder circuits 570 may be coupled between the clamp circuit 540 and the second power supply represented by V NN .
- the access line decoder circuit 570 is represented by transistors 550 , 551 .
- the first power supply may supply a positive voltage while the second power supply may supply a negative voltage.
- the first power supply may supply a positive voltage while the second power supply may supply a relatively low voltage (e.g., 0V).
- the clamp circuit 540 in saturation, is configured to keep the LWL node at a relatively low voltage V NN while controlling a current I CLAMP .
- the clamp circuit 540 controls (i.e., maintains) the current I CLAMP at a fixed current while the source current I MIRROR increases.
- the source current I MIRROR is substantially equal to the current I CLAMP after the transitory response of the reference voltage generation circuit is complete.
- the MOSFET clamp circuit 540 is for purposes of illustration only as other circuitry may be used to form a clamp circuit.
- the clamp circuit may be integrated into the architecture of the current mirror circuit 501 in order to minimize the difference between the two currents.
- the clamp circuit 540 may be physically located as close as possible to the reference cell 500 in order to reduce C LWL .
- the clamp circuit 540 is coupled between the local word line node LWL and a pair of series-connected transistors 550 , 551 .
- the transistors 550 , 551 represent the access line decoding circuitry (i.e., row decoder) of memory cells coupled to the reference voltage circuit.
- the transistors 550 , 551 representing the access line decoding circuitry are for purposes of illustration only as there may be other quantities of memory cells to which the circuit is coupled thus using a different quantity of transistors.
- the row decoding path transistors 550 , 551 are coupled to the relatively low voltage V NN .
- FIG. 6 shows a plot of bit line voltage V BL versus time t of a reference node voltage according to an embodiment of the present invention.
- the operation of the reference voltage circuit of FIG. 5 is subsequently described as part of a memory operation such as a read operation. This description is for purposes of illustration only as other memory operations using a reference voltage may be executed using the circuit of FIG. 5 .
- the word line node LWL Prior to coupling the current source 501 to the reference memory cell 500 , through the bit line decoder circuit 530 , 531 , the word line node LWL is stabilized at V NN and the bit line node LBL (with the reference node REF) is pre-charged to a pre-bias voltage V prebias .
- the pre-bias voltage V prebias may be a voltage that is close to the minimum switching voltage of the reference memory cell 500 (i.e., SD threshold voltage V th ) but without risking reaching that threshold voltage V th during normal operations.
- the pre-bias voltage V prebias may be approximately 3-5V greater than V NN and approximately 1-2V less than V th of the reference memory cell 500 .
- the pre-bias voltage V prebias may be regulated as a function of the integrated circuit temperature. By starting the bit line at a voltage level approximately equal to V prebias , the circuit is able to reduce the time to ramp the bit line node LBL and reference node REF to the reference voltage V REF .
- the current source 501 current I MIRROR is coupled to the bit line node LBL and reference node REF. This initiates the ramped voltage plot of FIG. 6 . It can be seen that in this case the ramped voltage begins at the V prebias voltage and not 0V.
- the word line node LWL ramps up and tends to equalize toward the voltage reached by the bit line reference node REF. Due to charge sharing, the LBL and REF node voltage may be reduced (e.g., 10% down from stable V REF ). However, partial compensation of the charge sharing loss occurs (e.g., by an amount of approximately 0.2V) resulting in an addition to the ramp up value of the REF node voltage. Additional compensation for the charge sharing voltage loss may be performed (e.g., by the amplifier circuit) during delivery of the actual reference voltage to the sensing circuitry (not shown) during a sense (e.g., read) operation.
- V REF When the word line node LWL and bit line node LBL stabilize 601 as seen in FIG. 6 , the movement of the reference voltage V REF will slow down since I MIRROR and I CLAMP are substantially identical. The closer these currents are to being identical, the more stable the reference voltage matching.
- the reference memory cell 500 remains in the “on” state during the memory operation in order to maintain equilibrium (I MIRROR is above the typical holding current for the select device SD) and track the reference voltage drift during a memory operation. V REF is now ready to be delivered to the sensing circuit for use during the memory operation.
- FIG. 7 illustrates a flowchart of a method for performing a memory operation according to an embodiment of the present invention.
- the bit line is pre-charged to a pre-bias voltage V prebias that is greater than V NN but less than V th of the reference memory cell.
- the word line node LWL is allowed to stabilize at this voltage.
- a stabilized word line node LWL may be defined as the voltage not changing by more than approximately 0.2-0.4V.
- a source current I MIRROR is provided to the circuit to start the ramped bit line voltage (starting at V prebias ).
- the clamp current is maintained by the clamp circuit as the bit line voltage ramps up.
- the reference memory cell turns on when the ramped bit line voltage V BL reaches the memory cell's threshold voltage V th .
- the bit line voltage V BL continues to ramp up until the current from the current source I MIRROR is substantially the same as the clamp current I CLAMP that was maintained by the clamp circuit.
- the memory cell in the “on” state, maintains equilibrium of the source current and the clamp current to cause the reference voltage to track the threshold voltage of the select device.
- the reference voltage V REF may now be delivered to the sensing circuit in block 707 .
- a sensing operation may be performed using the generated reference voltage V REF .
- the reference voltage V REF may be adjusted by compensating for charge sharing loss during delivery of the voltage. This may be accomplished with an amplifier circuit or some other mechanism.
- FIG. 8 shows a block diagram of a system according to an embodiment of the present invention.
- the block diagram is for purposes of illustration for one possible implementation of the reference voltage circuit of FIG. 5 .
- Other embodiments may use different systems.
- the system includes a controller 802 .
- the controller 802 may include any control circuitry, such as a processor or state machine, that is configured to control memory operations of a memory device.
- the controller 802 may be configured to control generation of voltages and control signals used in the reference voltage circuit of FIG. 5 .
- a memory array 801 including one or more of the reference voltage circuits 800 of FIG. 5 , comprises a plurality of memory cells.
- the memory cells may include one or more different memory technologies such as PCM or flash.
- the memory array 801 further includes one or more sense circuits (e.g., sense amplifiers) coupled to the reference voltage circuit(s) 800 to receive the reference voltage as discussed previously.
- the memory array 801 may be coupled to the controller 802 over a bus 810 .
- the bus 810 may include addresses lines, data lines, and/or control lines to enable communication between the memory array 801 and the controller 802 .
- the controller 802 and memory array 801 may be part of a memory device such that both the controller 802 and the memory array 801 are part of the same integrated circuit.
- the memory array 801 may be on a separate integrated circuit from the controller 802 .
- an apparatus may be defined as circuitry, an integrated circuit die, a device, or a system.
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Abstract
Description
- Memory devices are typically provided as internal, semiconductor, integrated circuits in apparatuses such as computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile (e.g., phase change memory, flash) memory.
- Non-volatile memories are useful elements of integrated circuits due to their ability to maintain data after removal of a power supply. Phase change materials have been investigated for use in non-volatile memory cells. Phase change memory (PCM) elements include phase change materials, such as chalcogenic semiconductor materials (e.g., chalcogenide alloys), that are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state that distinguishes the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance and a crystalline state exhibits a relatively low resistance. One of different logic levels (e.g., logic 1 or logic 0) can be assigned to each of these states. In the chalcogenides, the resistivity may vary by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
- In one embodiment, each memory cell typically includes both a phase change memory element (PM) connected in series with a select device (SD). The SD may be a switching element that includes a diode, a transistor, or an ovonic threshold switch (OTS). Also, the OTS is constructed with a chalcogenic material (i.e., it is an alloy containing at least one chalcogenic element). The OTS begins to conduct when a voltage above a threshold voltage Vth is applied across the switch.
- The threshold voltage Vth of the OTS is subject to drift over time. The threshold voltage drift may be harmful for OTS-selected memory arrays since it may prevent the storage element of chalcogenic material from being correctly read. For example, if the threshold voltage Vth of the selector is not known with satisfactory precision and the chalcogenic storage element is crystalline (e.g., stores a logic “1”), the memory cell may be read as a logic “0” since, at the reading voltage, the switch has not yet transitioned to the conductive state.
-
FIG. 1 shows the architecture of a memory array according to an embodiment of the present invention. -
FIG. 2 shows the electrical equivalent of a memory cell having a threshold switch according to an embodiment of the present invention. -
FIG. 3 shows a plot of current versus voltage characteristics for a threshold switch according to an embodiment of the present invention. -
FIG. 4 shows a plot of current versus voltage for a variable resistance memory element according to an embodiment of the present invention. -
FIG. 5 shows an electrical schematic diagram of a reference voltage generation apparatus to track threshold voltage shift in a memory cell according to an embodiment of the present invention. -
FIG. 6 shows a plot of bit line voltage versus time of a reference node voltage according to an embodiment of the present invention. -
FIG. 7 shows a flowchart of a method for performing a memory operation according to an embodiment of the present invention. -
FIG. 8 shows a block diagram of a system according to an embodiment of the present invention. - To address some of the challenges of threshold voltage drift, as well as others, apparatus, systems, and methods are described herein that may track cross-point memory cell threshold voltage based on a chalcogenide select device. Examples of such embodiments are now described in detail.
-
FIG. 1 shows the architecture of a memory array according to an embodiment of the present invention. A plurality ofmemory cells 100 are arranged in rows and columns to form the array. The memory array may be referred to as a cross-point memory array since thememory cells 100 are interposed at cross-points between rows 102 (i.e., word lines) and columns 104 (i.e., bit lines) of the array. Thememory cells 100 may include variable resistance memory cells as well as other types of memory cell technology. - Each
memory cell 100 includes amemory element 110 coupled in series with, and adjacent to, aselect device 111 represented as a switch.FIG. 2 shows the electrical equivalent of a memory cell 100 (PM) having an ovonic threshold switch 111 (OTS) according to an embodiment of the present invention. The connection order of the memory element 110 (PM) and the select device (SD) 111 is for purposes of illustration only and may be reversed in another embodiment. - The memory element 110 (PM) may include any variable-resistance memory element such as a memory element constructed of chalcogenic semiconductor materials having at least two distinct metastable phases (e.g., crystalline and amorphous). The
memory element 110 is the data storage device of thememory cell 100. If thememory element 110 is a PCM, its amorphous, high resistivity state may be referred to as a “reset” state while the crystalline, low resistivity state may be referred to as a “set” state. - The variable resistance material at the heart of a
memory element 110 does not usually function as a linear resistor (unless it is in its fully crystallized state). Instead, the current passed by a variable resistance material will depend exponentially on the applied voltage. Accuracy in the read voltage (i.e. the voltage precharged onto the bit line before the select device is turned on) is therefore important in obtaining an accurate read operation. - The
select device 111 may be any type of switch that turns on to conduct current when a voltage across the switch is equal to or greater than a threshold voltage Vth. For example, theselect device 111 may comprise a chalcogenic semiconductor material fixed in a single phase (generally amorphous) with two distinct regions of operation associated with different resistivities (e.g., ovonic threshold switch). - Referring again to
FIG. 1 , a terminal of theselect device 111 of eachmemory cell 100 is coupled to arespective bit line 104. A terminal of thememory element 110 of each memory cell is coupled to arespective word line 102. A memory array may be broken down into sub-elements such as tiles where a tile may comprise a group of memory cells. -
FIG. 3 shows a plot of current versus voltage characteristics for a threshold switch in a memory cell according to an embodiment of the present invention. The y-axis represents the threshold switch current ISD while the x-axis represents the threshold switch voltage VSD. - It can be seen in
FIG. 3 that the threshold switch has a high resistance for voltages below the threshold voltage Vth,SD. When the applied voltage is equal to or exceeds the threshold voltage Vth,SD, the switch begins to conduct at a substantially constant, low voltage and has a low impedance. In this condition, if the memory element is in the set state, as seen inFIG. 4 , the memory cell is turned on. If the memory element is in the reset state, the memory cell remains off. - When the current ISD falls below a hold current IH, the threshold switch returns to the high-impedance state. This behavior is symmetrical and also occurs when negative voltages are applied, and negative currents flow (not shown).
-
FIG. 4 shows a plot of current versus voltage for a variable resistance memory element according to an embodiment of the present invention. The y-axis represents the memory element current IPM while the x-axis represents the memory element voltage VPM. - The
plot 400 of the amorphous state (i.e., reset state) of a variable resistance memory element is similar to the plot of the threshold switch performance as seen in FIG. 3. Theplot 401 of the crystalline state (i.e., set state) shows that the memory element has a lower conductance in the lower portion of the plot and a higher conductance in the upper portion. - The problem associated with the threshold voltage (Vth) drift of the select device may be solved in many instances by using a circuit having a reference memory cell (or cells) to detect and store the threshold voltage Vth of a cross-point memory cell based on the behavior of a chalcogenide select device. The reference memory cell(s) may provide a reference voltage for reading a plurality of memory cells.
-
FIG. 5 shows an electrical schematic diagram of a reference voltage generation apparatus to track threshold voltage shift in a memory cell according to an embodiment of the present invention. The circuit uses areference memory cell 500 that stores the threshold voltage. In an embodiment, thereference memory cell 500 is fabricated so as to be located relatively close to the memory cell or group of memory cells for which it operates as the associated reference memory cell. - The circuit of
FIG. 5 generates a reference voltage VREF at the reference node that tracks the threshold voltage of a memory cell (or cells) (e.g., select device) as the threshold voltage shifts over time. The reference voltage VREF tracks the natural drift of Vth for chalcogenide select devices and may be generated in a relatively short time (e.g., <10 nanoseconds (ns)) that is compatible with a desired latency of storage class memories (approximately 100 ns). This is accomplished in the illustrated embodiment by using a PCM memory element in a set (i.e., crystallized) state as the reference cell. - The reference voltage circuit includes a
current source 501 that generates current IMIRROR. The illustrated embodiment uses a current mirror circuit comprising a pair oftransistors 510, 511 (e.g., p-type metal oxide semiconductor field effect transistors (MOSFETs)) coupled together at their control gates and their sources coupled to a first power supply that supplies positive supply voltage VPP. Thecurrent mirror circuit 501 further comprises aresistance R S 512 coupled between one of thetransistors 510 and ground. In some embodiments, other current mirror source circuit configurations are used. - The
current source 501 is coupled to a pair of series-connectedtransistors 530, 531 (e.g., p-type MOSFETs) in the IMIRROR path. Thesetransistors transistors line decoding circuitry 560 are for purposes of illustration only as there may be other quantities of memory cells to which the reference voltage circuit is coupled and, thus, the number ofdecoding path transistors - In an embodiment, one reference cell may be used for each set of bits (e.g., the number of bits that form a word) that are written or read substantially simultaneously. For example, if 128 bits are read across 128 tiles in order to build one word (i.e., one bit per tile is read), one tile of reference cells may be used for every 128 tiles in order to track the threshold voltage Vth for the bits included in each single word.
- The reference node REF between the
current source 501 and the pair of series-connectedtransistors capacitance C REF 520 may represent a capacitance of an input node of an operational amplifier, of a bit line decoding path, configured as a buffer with unity gain. Thecapacitance C REF 520 may also represent an extra capacitance specifically added to the circuit for the purpose of maintaining the VREF voltage for a particular time during a read operation. In an embodiment, theC REF 520 has a capacitance of approximately 400 femtofarads (fF). - The
reference memory cell 500 is coupled to one of the series-connectedtransistors 531 at a local bit line node LBL. The capacitance of the local bit lines that are coupled to the reference voltage circuit ofFIG. 4 may be represented by thecapacitance C LBL 535. In an embodiment,C LBL 535 has a capacitance of approximately 40 fF. - The
reference memory cell 500 is coupled to aclamp circuit 540 at a local word line (sometimes known to those of ordinary skill in the art as a word line) node LWL. The capacitance of the local word lines that are coupled to the reference voltage circuit ofFIG. 4 may be represented by the capacitance CLWL 436. In an embodiment,C LWL 536 has a capacitance of approximately 40 fF. CLwL 436 is the capacitance that is equalized when thereference cell 500 reaches its threshold voltage. - The
clamp circuit 540 is represented by an n-channel MOSFET 540 with a control gate biased at VCLAMP. Theclamp circuit 540 is coupled between thereference memory cell 500 and a second power supply that supplies a supply voltage VNN that is less than the VPP voltage. As discussed subsequently, one or more access line (row)decoder circuits 570 may be coupled between theclamp circuit 540 and the second power supply represented by VNN. The accessline decoder circuit 570 is represented bytransistors - The
clamp circuit 540, in saturation, is configured to keep the LWL node at a relatively low voltage VNN while controlling a current ICLAMP. Theclamp circuit 540 controls (i.e., maintains) the current ICLAMP at a fixed current while the source current IMIRROR increases. The source current IMIRROR is substantially equal to the current ICLAMP after the transitory response of the reference voltage generation circuit is complete. TheMOSFET clamp circuit 540 is for purposes of illustration only as other circuitry may be used to form a clamp circuit. For example, the clamp circuit may be integrated into the architecture of thecurrent mirror circuit 501 in order to minimize the difference between the two currents. Theclamp circuit 540 may be physically located as close as possible to thereference cell 500 in order to reduce CLWL. - The
clamp circuit 540 is coupled between the local word line node LWL and a pair of series-connectedtransistors transistors transistors decoding path transistors - In describing the operation of the reference voltage circuit of
FIG. 5 , reference is made to the plot ofFIG. 6 .FIG. 6 shows a plot of bit line voltage VBL versus time t of a reference node voltage according to an embodiment of the present invention. The operation of the reference voltage circuit ofFIG. 5 is subsequently described as part of a memory operation such as a read operation. This description is for purposes of illustration only as other memory operations using a reference voltage may be executed using the circuit ofFIG. 5 . - Prior to coupling the
current source 501 to thereference memory cell 500, through the bitline decoder circuit reference memory cell 500. The pre-bias voltage Vprebias may be regulated as a function of the integrated circuit temperature. By starting the bit line at a voltage level approximately equal to Vprebias, the circuit is able to reduce the time to ramp the bit line node LBL and reference node REF to the reference voltage VREF. - After pre-charging the bit line and stabilizing the LWL voltage, the
current source 501 current IMIRROR is coupled to the bit line node LBL and reference node REF. This initiates the ramped voltage plot ofFIG. 6 . It can be seen that in this case the ramped voltage begins at the Vprebias voltage and not 0V. - The
current source 501 may provide an IMIRROR current that results in a ratio of ΔV/Δt that is substantially equal to IMIRROR/(CREF+CLBL). For example, this may result in a 0.2V/ns ramped voltage if IMIRROR=100 μA and CREF+CLBL=500 fF. - When the ramped voltage reaches the reference cell
threshold voltage V th 600, the word line node LWL ramps up and tends to equalize toward the voltage reached by the bit line reference node REF. Due to charge sharing, the LBL and REF node voltage may be reduced (e.g., 10% down from stable VREF). However, partial compensation of the charge sharing loss occurs (e.g., by an amount of approximately 0.2V) resulting in an addition to the ramp up value of the REF node voltage. Additional compensation for the charge sharing voltage loss may be performed (e.g., by the amplifier circuit) during delivery of the actual reference voltage to the sensing circuitry (not shown) during a sense (e.g., read) operation. - When the word line node LWL and bit line node LBL stabilize 601 as seen in
FIG. 6 , the movement of the reference voltage VREF will slow down since IMIRROR and ICLAMP are substantially identical. The closer these currents are to being identical, the more stable the reference voltage matching. Thereference memory cell 500 remains in the “on” state during the memory operation in order to maintain equilibrium (IMIRROR is above the typical holding current for the select device SD) and track the reference voltage drift during a memory operation. VREF is now ready to be delivered to the sensing circuit for use during the memory operation. -
FIG. 7 illustrates a flowchart of a method for performing a memory operation according to an embodiment of the present invention. Inblock 701, the bit line is pre-charged to a pre-bias voltage Vprebias that is greater than VNN but less than Vth of the reference memory cell. The word line node LWL is allowed to stabilize at this voltage. A stabilized word line node LWL may be defined as the voltage not changing by more than approximately 0.2-0.4V. - In
block 703, a source current IMIRROR is provided to the circuit to start the ramped bit line voltage (starting at Vprebias). Inblock 704, the clamp current is maintained by the clamp circuit as the bit line voltage ramps up. Inblock 705, the reference memory cell turns on when the ramped bit line voltage VBL reaches the memory cell's threshold voltage Vth. The bit line voltage VBL continues to ramp up until the current from the current source IMIRROR is substantially the same as the clamp current ICLAMP that was maintained by the clamp circuit. The memory cell, in the “on” state, maintains equilibrium of the source current and the clamp current to cause the reference voltage to track the threshold voltage of the select device. This provides a stable VREF after the transitory response of the circuit. The reference voltage VREF may now be delivered to the sensing circuit inblock 707. Inblock 709, a sensing operation may be performed using the generated reference voltage VREF. As described previously, the reference voltage VREF may be adjusted by compensating for charge sharing loss during delivery of the voltage. This may be accomplished with an amplifier circuit or some other mechanism. -
FIG. 8 shows a block diagram of a system according to an embodiment of the present invention. The block diagram is for purposes of illustration for one possible implementation of the reference voltage circuit ofFIG. 5 . Other embodiments may use different systems. - The system includes a
controller 802. Thecontroller 802 may include any control circuitry, such as a processor or state machine, that is configured to control memory operations of a memory device. For example, thecontroller 802 may be configured to control generation of voltages and control signals used in the reference voltage circuit ofFIG. 5 . - A
memory array 801, including one or more of thereference voltage circuits 800 ofFIG. 5 , comprises a plurality of memory cells. The memory cells may include one or more different memory technologies such as PCM or flash. Thememory array 801 further includes one or more sense circuits (e.g., sense amplifiers) coupled to the reference voltage circuit(s) 800 to receive the reference voltage as discussed previously. - The
memory array 801 may be coupled to thecontroller 802 over abus 810. Thebus 810 may include addresses lines, data lines, and/or control lines to enable communication between thememory array 801 and thecontroller 802. - The
controller 802 andmemory array 801 may be part of a memory device such that both thecontroller 802 and thememory array 801 are part of the same integrated circuit. In another embodiment, thememory array 801 may be on a separate integrated circuit from thecontroller 802. - For the purposes of this document, an apparatus may be defined as circuitry, an integrated circuit die, a device, or a system.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations.
Claims (21)
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US10566052B2 (en) | 2017-12-22 | 2020-02-18 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10607664B2 (en) | 2018-03-22 | 2020-03-31 | Micron Technology, Inc. | Sub-threshold voltage leakage current tracking |
US11183267B2 (en) * | 2019-07-12 | 2021-11-23 | Micron Technology, Inc. | Recovery management of retired super management units |
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JP2004335031A (en) * | 2003-05-09 | 2004-11-25 | Toshiba Corp | Semiconductor storage device |
US8050084B2 (en) * | 2006-09-05 | 2011-11-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, storage system having the same, and method of driving the nonvolatile memory device |
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US11385708B2 (en) * | 2018-08-14 | 2022-07-12 | Winbond Electronics Corp. | Memory devices and control methods thereof |
US20190043567A1 (en) * | 2018-08-28 | 2019-02-07 | Intel Corporation | Temperature-dependent read operation time adjustment in non-volatile memory devices |
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