US20200253044A1 - Wiring board - Google Patents
Wiring board Download PDFInfo
- Publication number
- US20200253044A1 US20200253044A1 US16/781,123 US202016781123A US2020253044A1 US 20200253044 A1 US20200253044 A1 US 20200253044A1 US 202016781123 A US202016781123 A US 202016781123A US 2020253044 A1 US2020253044 A1 US 2020253044A1
- Authority
- US
- United States
- Prior art keywords
- layer
- insulating layer
- opening portion
- metal layer
- side face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 471
- 239000002184 metal Substances 0.000 claims abstract description 471
- 239000010410 layer Substances 0.000 description 1241
- 239000004020 conductor Substances 0.000 description 110
- 238000000034 method Methods 0.000 description 69
- 239000004065 semiconductor Substances 0.000 description 58
- 229920005989 resin Polymers 0.000 description 54
- 239000011347 resin Substances 0.000 description 54
- 229910000679 solder Inorganic materials 0.000 description 44
- 230000003746 surface roughness Effects 0.000 description 42
- 239000000463 material Substances 0.000 description 38
- 238000004519 manufacturing process Methods 0.000 description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 36
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 36
- 239000012790 adhesive layer Substances 0.000 description 35
- 239000000758 substrate Substances 0.000 description 34
- 239000010931 gold Substances 0.000 description 30
- 239000011889 copper foil Substances 0.000 description 28
- 230000000149 penetrating effect Effects 0.000 description 25
- 238000005530 etching Methods 0.000 description 21
- 238000012986 modification Methods 0.000 description 21
- 230000004048 modification Effects 0.000 description 21
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 20
- 238000007788 roughening Methods 0.000 description 18
- 239000002335 surface treatment layer Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 239000000654 additive Substances 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 10
- 229920000647 polyepoxide Polymers 0.000 description 10
- 238000007747 plating Methods 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000007772 electroless plating Methods 0.000 description 8
- 238000003754 machining Methods 0.000 description 8
- 229910000881 Cu alloy Inorganic materials 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 6
- 239000007864 aqueous solution Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 230000000644 propagated effect Effects 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 239000000470 constituent Substances 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 4
- 229910001020 Au alloy Inorganic materials 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 4
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- -1 azole compound Chemical class 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000008094 contradictory effect Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- KAESVJOAVNADME-UHFFFAOYSA-N 1H-pyrrole Natural products C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 2
- 229910020888 Sn-Cu Inorganic materials 0.000 description 2
- 229910020988 Sn—Ag Inorganic materials 0.000 description 2
- 229910019204 Sn—Cu Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 239000004760 aramid Substances 0.000 description 2
- 229920003235 aromatic polyamide Polymers 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000003755 preservative agent Substances 0.000 description 2
- 230000002335 preservative effect Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000002759 woven fabric Substances 0.000 description 2
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Definitions
- the present disclosure relates to a wiring board.
- FIG. 38 shows an electronic component embedded type wiring board 400 according to the background art.
- the wiring board 400 has an insulating layer 410 , a metal layer 420 , an interlayer insulating layer 430 , and an opening portion 440 .
- the metal layer 420 is formed on an upper face of the insulating layer 410 .
- the interlayer insulating layer 430 is formed on the upper face of the insulating layer 410 so as to cover the metal layer 420 .
- the opening portion 440 penetrates the interlayer insulating layer 430 in a thickness direction.
- the wiring board 400 has an electronic component 450 , an insulating layer 460 and a wiring layer 470 .
- the electronic component 450 is disposed inside the opening portion 440 . With the insulating layer 460 , the opening portion 440 is filled and the electronic component 450 is entirely covered.
- the wiring layer 470 is electrically connected to electrodes 451 of the electronic component 450 and formed on an upper face of the insulating layer
- the peeling When the peeling occurs at the interface between the metal layer 420 and the insulating layer 460 , the peeling may be propagated to an interface between the interlayer insulating layer 430 and the insulating layer 460 , and the wiring layer 470 may be broken due to the propagated peeling. When the wiring layer 470 is broken, electric reliability of the wiring board 400 may be lowered.
- Certain embodiment provides a wiring board.
- the wiring board comprises:
- a second insulating layer that is formed on an upper face of the first insulating layer
- a third insulating layer that is formed on the upper face of the second insulating layer so as to cover the first metal layer
- a filling insulating layer that fills the opening portion and covers the electronic component
- a wiring layer that is formed on an upper face of the filling insulating layer.
- a first step portion is formed by a side face of the second insulating layer constituting an inner side face of the opening portion and a side face of the first metal layer constituting the inner side face of the opening portion.
- FIG. 1A is a schematic sectional view (a sectional view taken along a line 1 - 1 in FIG. 2 ) showing a wiring board according to a first embodiment
- FIG. 1B is an enlarged sectional view showing the wiring board according to the first embodiment
- FIG. 2 is a schematic plan view showing the wiring board according to the first embodiment
- FIG. 3 is a schematic perspective view showing the wiring board according to the first embodiment
- FIG. 4 is a schematic sectional view showing a semiconductor device according to the first embodiment
- FIGS. 5A to 5C are schematic sectional views showing a method for manufacturing the wiring board according to the first embodiment
- FIGS. 6A and 6B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 7A and 7B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 8A and 8B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 9A and 9B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 10A and 10B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 11A and 11B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIGS. 12A and 12B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment
- FIG. 13 is a schematic sectional view showing the method for manufacturing the wiring board according to the first embodiment
- FIG. 14 is a schematic sectional view showing a method for manufacturing the semiconductor device according to the first embodiment
- FIG. 15 is a schematic sectional view showing a wiring board according to a modification
- FIGS. 16A and 16B are schematic plan views showing the wiring board according to the modification.
- FIG. 17 is a schematic perspective view showing the wiring board according to the modification.
- FIG. 18 is a schematic sectional view showing a wiring board according to another modification.
- FIGS. 19A and 19B are schematic sectional views showing a method for manufacturing the wiring board according to the other modification
- FIGS. 20A and 20B are schematic sectional views showing the method for manufacturing the wiring board according to the other modification
- FIG. 21A is a schematic sectional view (a sectional view taken along a line 21 a - 21 a in FIG. 22 ) showing a wiring board according to a second embodiment
- FIG. 21B is an enlarged sectional view showing the wiring board according to the second embodiment
- FIG. 22 is a schematic plan view showing the wiring board according to the second embodiment.
- FIG. 23 is a schematic perspective view showing the wiring board according to the second embodiment.
- FIG. 24 is a schematic sectional view showing a semiconductor device according to the second embodiment.
- FIGS. 25A to 25C are schematic sectional views showing a method for manufacturing the wiring board according to the second embodiment
- FIGS. 26A and 26B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 27A and 27B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 28A and 28B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 29A and 29B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 30A and 30B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 31A and 31B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIGS. 32A and 32B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment
- FIG. 33 is a schematic sectional view showing a method for manufacturing the semiconductor device according to the second embodiment.
- FIG. 34 is a schematic sectional view showing a wiring board according to a modification
- FIGS. 35A and 35B are schematic plan views showing the wiring board according to the modification.
- FIG. 36 is a schematic perspective view showing the wiring board according to the modification.
- FIG. 37 is a schematic sectional view showing a wiring board according to another modification.
- FIG. 38 is a schematic sectional view showing a wiring board according to the background art.
- a first embodiment will be described below in accordance with FIG. 1A to FIG. 14 .
- a wiring board 10 has a structure in which a wiring layer 20 , an insulating layer 30 , a conductor layer 40 , an insulating layer 50 , a conductor layer 60 , an insulating layer 70 , an insulating layer 80 , and a wiring layer 90 are formed sequentially.
- the wiring board 10 in the present example has a form of a so-called “coreless board” which is free from any support substrate unlike a wiring board which is manufactured by a general build-up method, i.e. a wiring board in which a required number of build-up layers are formed sequentially on each or one of opposite faces of a core substrate serving as a support substrate.
- the wiring board 10 has one or more electronic components 110 (one electronic component 110 in FIG. 1A ) disposed in an opening portion 100 formed in the plurality of insulating layers 50 and 70 , a solder resist layer 120 formed on a lower face of the insulating layer 30 , and a solder resist layer 130 formed on an upper face of the insulating layer 80 .
- the wiring board 10 is a wiring board in which the electronic component 110 is embedded.
- cupper (Cu) or a copper alloy can be used as the material of the wiring layers 20 and 90 and the conductor layers 40 and 60 .
- any of insulating resins such as an epoxy resin and a polyimide resin or any of resin materials in which fillers made of silica, alumina, etc., are mixed with these resins can be used as the material of the insulating layers 30 , 50 , 70 and 80 .
- a reinforcing material-including insulating resin in which a reinforcing material such as a woven fabric or an unwoven fabric of glass, aramid or LCP (Liquid Crystal Polymer) fiber is impregnated with a thermosetting resin containing an epoxy resin, a polyimide resin, or the like, as a main component may be used as the material of the insulating layers 30 , 50 , 70 and 80 .
- a non-photosensitive insulating resin containing a thermosetting resin as a main component or an insulating resin containing a photosensitive resin as a main component can be used as the material of the insulating layers 30 , 50 , 70 and 80 .
- the wiring layer 20 is an outermost (lowermost in this case) wiring layer of the wiring board 10 .
- a lower face of the wiring layer 20 is exposed from the insulating layer 30 .
- the lower face of the wiring layer 20 in the present example is formed to be substantially flush with the lower face of the insulating layer 30 .
- the lower face of the wiring layer 20 may be formed to be recessed on the conductor layer 40 side relatively to the lower face of the insulating layer 30 .
- the thickness of the wiring layer 20 can be, for example, set in a range of about 10 to 30 ⁇ m.
- the insulating layer 30 is formed so as to cover an upper face and a side face of the wiring layer 20 and expose the lower face of the wiring layer 20 .
- a through hole 30 X penetrating the insulating layer 30 in a thickness direction so as to expose a portion of the upper face of the wiring layer 20 is formed at a predetermined place in the insulating layer 30 .
- the through hole 30 X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from an upper side (the conductor layer 40 side) toward a lower side (the wiring layer 20 side) in FIG. 1A .
- the through hole 30 X is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- a thickness between the upper face of the wiring layer 20 and an upper face of the insulating layer 30 can be, for example, set in a range of about 10 to 35 ⁇ m.
- the conductor layer 40 is formed on the upper face of the insulating layer 30 .
- the thickness of the conductor layer 40 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 40 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 40 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 40 .
- the surface roughness of the conductor layer 40 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the surface roughness Ra value is one kind of numerical value, which expresses the surface roughness and which is called arithmetical average roughness.
- the surface roughness Ra value is an arithmetic average of absolute values measured as a height varying within a measurement region from the surface which is an average line.
- the conductor layer 40 has, for example, a wiring layer 41 and a metal layer 42 .
- the wiring layer 41 and the metal layer 42 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 41 and the metal layer 42 are formed on one and the same plane.
- the wiring layer 41 is, for example, electrically connected to the wiring layer 20 through a via wiring filled in the through hole 30 X.
- the wiring layer 41 is, for example, formed integrally with the via wiring filled in the through hole 30 X.
- the metal layer 42 is, for example, formed in a mount region where the electronic component 110 is mounted.
- the metal layer 42 is, for example, formed at a position overlapping with the electronic component 110 in plan view.
- the metal layer 42 is, for example, formed at a position overlapping with the opening portion 100 in plan view.
- the planar shape of the metal layer 42 is, for example, formed to be larger than the planar shape of the opening portion 100 .
- An outer circumferential edge of the metal layer 42 is, for example, formed so as to surround an opening edge of the opening portion 100 from the outside in plan view.
- the metal layer 42 is, for example, formed into a rectangular shape in plan view.
- the metal layer 42 in the present example is, for example, a metal layer which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 42 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring.
- the metal layer 42 is, for example, electrically connected to another wiring layer or another conductor layer through a via wiring etc.
- the insulating layer 50 is formed on the upper face of the insulating layer 30 so as to cover the conductor layer 40 .
- a thickness between the upper face of the conductor layer 40 and an upper face of the insulating layer 50 can be, for example, set in a range of about 40 to 100 ⁇ m.
- a through hole 50 X penetrating the insulating layer 50 in the thickness direction so as to expose a portion of the upper face of the conductor layer 40 (the wiring layer 41 in this case) is formed at a predetermined place in the insulating layer 50 .
- the through hole 50 X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (the conductor layer 60 side) toward the lower side (the conductor layer 40 side) in FIG. 1A .
- the through hole 50 X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- the conductor layer 60 is formed on the upper face of the insulating layer 50 .
- the thickness of the conductor layer 60 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 60 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 60 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 60 .
- the surface roughness of the conductor layer 60 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the conductor layer 60 has, for example, a wiring layer 61 and a metal layer 62 .
- the wiring layer 61 and the metal layer 62 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 61 and the metal layer 62 are formed on one and the same plane.
- the wiring layer 61 is, for example, electrically connected to the wiring layer 41 through a via wiring filled in the through hole 50 X.
- the wiring layer 61 is, for example, formed integrally with the via wiring filled in the through hole 50 X.
- the metal layer 62 is, for example, formed so as to surround the mount region where the electronic component 110 is mounted.
- the metal layer 62 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 62 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When the metal layer 62 is the wiring pattern, the power source wiring or the ground wiring, for example, the metal layer 62 is electrically connected to another wiring layer or another conductor layer through a via wiring etc.
- the insulating layer 70 is formed on the upper face of the insulating layer 50 so as to cover the conductor layer 60 .
- a thickness between the upper face of the conductor layer 60 and an upper face of the insulating layer 70 can be, for example, set in a range of about 40 to 100 ⁇ m.
- the opening portion 100 is, for example, formed so as to penetrate the insulating layer 50 , the metal layer 62 and the insulating layer 70 in the thickness direction.
- the opening portion 100 is, for example, formed so as to expose a portion of an upper face of the metal layer 42 .
- the opening portion 100 is formed correspondingly to the electronic component 110 embedded in the opening portion 100 .
- the opening portion 100 in the present example is constituted by a through hole 50 Y, a through hole 62 Y and a through hole 70 Y.
- the through hole 50 Y penetrates the insulating layer 50 in the thickness direction.
- the through hole 62 Y penetrates the metal layer 62 in the thickness direction.
- the through hole 70 Y penetrates the insulating layer 70 in the thickness direction.
- each of the through holes 50 Y, 62 Y and 70 Y in the present example is formed into a rectangular shape in plan view.
- the through holes 50 Y, 62 Y and 70 Y are, for example, formed coaxially with each other. That is, positions of a central axis of the through hole 50 Y, a central axis of the through hole 62 Y and a central axis of the through hole 70 Y align with one another in plan view.
- Each of the planar shapes of the through holes 50 Y, 62 Y and 70 Y is formed to be larger than the planar shape of the electronic component 110 .
- the planar shape of the through hole 50 Y, 62 Y, 70 Y is, for example, formed to be smaller than the planar shape of the metal layer 42 .
- the through hole 62 Y is, for example, formed to be larger in planar shape than each of the through holes 50 Y and 70 Y.
- the metal layer 62 is, for example, formed so as to surround opening edges of the through holes 50 Y and 70 Y from the outside.
- the metal layer 62 is, for example, formed into a ring shape (frame shape) in plan view.
- the metal layer 62 in the present example is formed into a rectangular closed ring shape to continuously surround the opening edge of each of the through holes 50 Y and 70 Y over the whole circumference.
- FIG. 2 is a plan view in which the wiring board 10 shown in FIG. 1A is seen from top.
- the insulating layer 80 , the wiring layer 90 , the solder resist layer 130 , etc. are drawn in perspective.
- a side face 62 A of the metal layer 62 constituting an inner side face of the opening portion 100 (the through hole 62 Y) is provided at a position where the side face 62 A is set back (separated) inward of the insulating layer 50 from a side face 50 A of the insulating layer 50 constituting the inner side face of the opening portion 100 (the through hole 50 Y).
- the side face 62 A of the metal layer 62 is provided at a position where the side face 62 A is set back inward of the insulating layer 70 from a side face 70 A of the insulating layer 70 constituting the inner side face of the opening portion 100 (the through hole 70 Y).
- the side face 62 A of the metal layer 62 is provided at the position where the side face 62 A is set back in a direction to be separated more distantly from a planar center of the opening portion 100 than the side faces 50 A and 70 A of the insulating layers 50 and 70 .
- the side face 62 A of the metal layer 62 is, for example, formed so as to be set back from the side faces 50 A and 70 A of the insulating layers 50 and 70 over the whole circumference of the opening portion 100 .
- the upper face of the insulating layer 50 positioned in the vicinity of the side face 50 A of the insulating layer 50 is exposed from the metal layer 62 .
- a lower face of the insulating layer 70 positioned in the vicinity of the side face 70 A of the insulating layer 70 is exposed from the metal layer 62 .
- a recess 101 constituted by the side face 50 A of the insulating layer 50 , the upper face of the insulating layer 50 exposed from the metal layer 62 , the side face 62 A of the metal layer 62 , the lower face of the insulating layer 70 exposed from the metal layer 62 , and the side face 70 A of the insulating layer 70 is formed in the inner side face of the opening portion 100 .
- a step portion constituted by the recess 101 is formed in the inner side face of the opening portion 100 .
- the recess 101 is, for example, formed continuously over the whole circumference of the opening portion 100 .
- the through hole 50 Y of the insulating layer 50 is, for example, formed to be smaller in planar shape than the through hole 70 Y of the insulating layer 70 . That is, the through hole 50 Y has the smallest planar shape among the through holes 50 Y, 62 Y and 70 Y.
- the size of the through hole 50 Y can be, for example, set in a range of about 0.7 mm ⁇ 0.4 mm to 15 mm ⁇ 15 mm in plan view.
- the side face 70 A of the insulating layer 70 is provided at a position where the side face 70 A is set back in the direction to be separated more distantly from the planar center of the opening portion 100 than the side face 50 A of the insulating layer 50 .
- the side face 70 A of the insulating layer 70 is formed so as to be set back from the side face 50 A of the insulating layer 50 over the whole circumference of the opening portion 100 .
- a recess 42 X recessed on the insulating layer 30 side is formed in the upper face of the metal layer 42 exposed in the bottom of the opening portion 100 (specifically, the bottom of the through hole 50 Y).
- a bottom face and an inner side face of the recess 42 X are, for example, roughened faces.
- Surface roughness of the bottom face of the recess 42 X is, for example, formed to be larger than surface roughness of the upper face of the metal layer 42 covered with the insulating layer 50 .
- the surface roughness of the upper face of the metal layer 42 exposed in the bottom of the opening portion 100 is formed to be larger than the surface roughness of the upper face of the metal layer 42 covered with the insulating layer 50 .
- the electronic component 110 is mounted on (adhesively bonded to) the upper face of the metal layer 42 (specifically, the bottom face of the recess 42 X) exposed from the opening portion 100 through an adhesive layer 112 . That is, the electronic component 110 is disposed inside the opening portion 100 .
- the adhesive layer 112 is formed on the upper face of the metal layer 42 .
- an epoxy-based, polyimide-based or silicone-based thermosetting adhesive agent can be used as the material of the adhesive layer 112 .
- an active component such as a semiconductor chip, a transistor or a diode or a passive component such as a chip capacitor, a chip inductor or a chip resistor can be used as the electronic component 110 .
- a component made of silicon or a component made of ceramic can be used as the electronic component 110 .
- the electronic component 110 according to the present embodiment is a semiconductor chip.
- a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip.
- a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip or a flash memory chip can be used as the semiconductor chip.
- the electronic component 110 can be, for example, made of a semiconductor substrate.
- silicon etc. can be used as the material of the semiconductor substrate.
- Electrode terminals 111 are provided on, of the electronic component 110 , a circuit formation face 110 A where a semiconductor integrated circuit (not shown) is formed.
- the electrode terminals 111 are, for example, metal posts each formed in the shape of a column extending upward from the circuit formation face 110 A.
- copper or a copper alloy can be used as the material of the electrode terminals 111 .
- the electronic component 110 is bonded to the upper face of the metal layer 42 by the adhesive layer 112 in a state in which a back face (a lower face in this case) of the electronic component 110 opposite to the circuit formation face 110 A is opposed to the upper face of the metal layer 42 , i.e. faces up.
- Upper faces of the electrode terminals 111 are, for example, formed on the same plane as the upper face of the insulating layer 70 or formed to be lower than the upper face of the insulating layer 70 .
- the insulating layer 80 is formed so as to fill the opening portion 100 and entirely cover the electronic component 110 .
- the insulating layer 80 is, for example, formed so as to cover an entire side face of the adhesive layer 112 , an entire side face of the electronic component 110 , the entire circuit formation face 110 A exposed from the electrode terminals 111 , and the upper faces and side faces of the electrode terminals 111 .
- the insulating layer 80 is, for example, formed so as to cover the surface of the metal layer 42 exposed from the adhesive layer 112 inside the opening portion 100 .
- the insulating layer 80 is, for example, formed so as to fill the opening portion 100 and the recess 101 formed in the inner side face of the opening portion 100 .
- the insulating layer 80 is formed so as to cover the entire side face 50 A of the insulating layer 50 , the entire upper face of the insulating layer 50 exposed from the metal layer 62 , the entire side face 62 A of the metal layer 62 , the entire lower face of the insulating layer 70 exposed from the metal layer 62 , and the entire side face 70 A of the insulating layer 70 .
- the insulating layer 80 is, for example, formed to bite into the lower face of the insulating layer 70 exposed by the recess 101 .
- the insulating layer 80 is, for example, formed so as to cover the entire upper face of the insulating layer 70 .
- a through hole 80 X penetrating the insulating layers 70 and 80 in the thickness direction so as to expose a portion of the upper face of the conductor layer 60 (the wiring layer 61 in this case) is formed at a required place in the insulating layers 70 and 80 .
- a through hole 80 Y penetrating the insulating layer 80 in the thickness direction so as to expose a portion of the upper face of each of the electrode terminals 111 is formed at a required place in the insulating layer 80 .
- Each of the through holes 80 X and 80 Y is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (the wiring layer 90 side) toward the lower side (the wiring layer 61 side or the electrode terminal 111 side) in FIG. 1A .
- the through hole 80 X, 80 Y is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- the wiring layer 90 is formed on the upper face of the insulating layer 80 .
- the wiring layer 90 is, for example, an outermost (uppermost in this case) wiring layer of the wiring board 10 .
- the wiring layer 90 has a wiring layer electrically connected to the wiring layer 61 through a via wiring filled in the through hole 80 X.
- the wiring layer 90 has a wiring layer electrically connected to the electrode terminal 111 through a via wiring filled in the through hole 80 Y.
- the wiring layer 90 is formed integrally with the via wiring filled in the through hole 80 X or the through hole 80 Y.
- the thickness of the wiring layer 90 can be, for example, set in a range of about 10 to 30 ⁇ m.
- the solder resist layer 120 is formed on the lower face of the outermost (lowermost in this case) insulating layer 30 so as to cover the lowermost wiring layer 20 .
- an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist layer 120 .
- the thickness of the solder resist layer 120 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An opening portion 120 X for exposing at least a portion of the lower face of the lowermost wiring layer 20 as a pad P 1 is formed in the solder resist layer 120 .
- an external connection terminal such as a solder ball or a lead pin, which is used when the wiring board 10 is mounted on a mount board such as a motherboard is connected to the pad P 1 . That is, the pad P 1 in the present example functions as an external connection pad.
- a surface treatment layer may be formed on a lower face of the pad P 1 if occasions demand.
- a gold (Au) layer, a nickel (Ni) layer/Au layer (a metal layer in which the Ni layer and the Au layer are formed in the named order), an Ni layer/palladium (Pd) layer/Au layer (a metal layer in which the Ni layer, the Pd layer and the Au layer are formed in the named order), etc. can be listed as examples of the surface treatment layer.
- the Au layer is a metal layer made of Au or an Au alloy.
- the Ni layer is a metal layer made of Ni or an Ni alloy.
- the Pd layer is a metal layer made of Pd or a Pd alloy.
- a metal layer (an electroless plating metal layer) formed by an electroless plating method can be used as each of the Ni layer, the Au layer and the Pd layer.
- an OSP (Organic Solderability Preservative) film formed by applying antioxidation treatment such as OSP treatment to the surface of the pad P 1 can be used as another example of the surface treatment layer.
- An organic coating of an azole compound, an imidazole compound, or the like, can be used as the OSP film.
- the wiring layer 20 per se exposed from the opening portion 120 X (or the surface treatment layer in the case where the surface treatment layer is formed on the wiring layer 20 ) may be set as the external connection terminal.
- the solder resist layer 130 is formed on the upper face of the outermost (uppermost in this case) insulating layer 80 so as to cover the uppermost wiring layer 90 .
- an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist layer 130 .
- the thickness of the solder resist layer 130 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An opening portion 130 X is formed in the solder resist layer 130 in order to expose at least a portion of the uppermost wiring layer 90 as a pad P 2 .
- the pad P 2 functions, for example, as an electronic component mounting pad in order to be electrically connected to an electronic component such as a semiconductor chip.
- a surface treatment layer may be formed on the surface (an upper face and a side face or only an upper face) of the pad P 2 if occasions demand.
- Metal layers such as an Au layer, an Ni layer/Au layer and an Ni layer/Pd layer/Au layer and an OSP film can be used as examples of the surface treatment layer.
- the semiconductor device 11 has the wiring board 10 , one or more semiconductor chips 140 (one semiconductor chip 140 in FIG. 4 ), and an underfill resin 150 .
- the semiconductor chip 140 is flip-chip mounted on the wiring board 10 . That is, a bump 141 disposed and provided on a circuit formation face (a lower face in this case) of the semiconductor chip 140 is bonded to the pad P 2 of the wiring board 10 . Thus, the semiconductor chip 140 is electrically connected to the pad P 2 (the wiring layer 90 ) through the bump 141 .
- a logic chip such as a CPU chip or a GPU chip, or a memory chip such as a DRAM chip, an SRAM chip or a flash memory chip can be used as the semiconductor chip 140 .
- the logic chip and the memory chip may be configured in combination and mounted on the wiring board 10 .
- a gold bump or a solder bump can be used as the bump 141 .
- an alloy containing lead (Pb), a tin (Sn)—Au alloy, an Sn—Cu alloy, an Sn—Ag alloy, an Sn—silver (Ag)—Cu alloy, or the like can be used as the material of the solder bump.
- the underfill resin 150 is provided to fill a gap between the wiring board 10 and the semiconductor chip 140 .
- an insulating resin such as an epoxy resin can be used as the material of the underfill resin 150 .
- portions to be final constituent elements of the wiring board 10 will be designated by signs of the final constituent elements for convenience of explanation in the description.
- a support substrate 160 is prepared, as shown in FIG. 5A .
- a plate-like material high in rigidity such as silicon, glass or metal (such as copper) can be used as the material of the support substrate 160 .
- a metal plate or a metal foil sheet can be used as the support substrate 160 .
- a copper foil sheet in which an ultrathin copper foil sheet about 2 to 5 ⁇ m thick is pasted to a support body copper foil sheet, which is about 35 to 70 ⁇ m thick, through a peeling layer is used as the support substrate 160 in the present example.
- a metal film 161 covering an entire upper face of the support substrate 160 is formed on the upper face of the support substrate 160 .
- the metal film 161 is formed on an upper face of the ultrathin copper foil sheet of the support substrate 160 .
- the metal film 161 can be, for example, formed by a sputtering method, a vapor deposition method or an electrolytic plating method.
- an electrically conductive material serving as a stopper layer when the support substrate 160 is etched and removed can be used as the material of the metal film 161 .
- an electrically conductive material which can be selectively etched and removed from a wiring layer 20 e.g.
- a Cu layer which will be formed by a subsequent step can be used as the material of the metal film 161 .
- a metal such as nickel (Ni), titanium (Ti), chromium (Cr), tin, cobalt (Co), iron (Fe) or palladium or an alloy containing at least one metal selected from the aforementioned metals can be used as the material of such a metal film 161 .
- Ni is used as the material of the metal film 161 in the present example.
- the thickness of the metal film 161 can be, for example, set in a range of about 0.1 to 1.0 ⁇ m.
- the wiring layer 20 is formed on an upper face of the metal film 161 .
- the wiring layer 20 can be, for example, formed by a semi-additive method. Specifically, first, a resist pattern (not shown) having an opening portion corresponding to the shape of the wiring layer 20 is formed on the upper face of the metal film 161 . Successively, by an electrolytic copper plating method using the support substrate 160 and the metal film 161 as power feed layers, a copper plating coating is deposited on the upper face of the metal film 161 exposed from the opening portion of the resist pattern. Then, the resist pattern is removed. In this manner, the wiring layer 20 can be formed on the metal film 161 . Incidentally, any of various wiring formation methods such as a subtractive method other than the semi-additive method can be also used as the method for forming the wiring layer 20 .
- an insulating layer 30 having a through hole 30 X exposing a portion of an upper face of the wiring layer 20 is formed on the upper face of the metal film 161 in a step shown in FIG. 5B .
- a resin film is used as the insulating layer 30
- the resin film is laminated on the upper face of the metal film 161 by thermocompression bonding, and the resin film is patterned by a photolithographic method in order to form the insulating layer 30 .
- a liquid or paste-like insulating resin may be applied to the upper face of the metal film 161 by a spin coating method etc., and the insulating resin may be patterned by a photolithographic method in order to form the insulating layer 30 .
- a via wiring filled in the through hole 30 X is formed, and a conductor layer 40 is formed on an upper face of the insulating layer 30 , for example, by a semi-additive method, in a step shown in FIG. 5C .
- the conductor layer 40 has a wiring layer 41 and a metal layer 42 .
- the wiring layer 41 is electrically connected to the wiring layer 20 through the via wiring filled in the through hole 30 X.
- the metal layer 42 is formed in a mount region of an electronic component 110 (see FIG. 1A ).
- roughening treatment is applied to the conductor layer 40 in a step shown in FIG. 6A .
- An entire upper face and an entire side face of the conductor layer 40 are formed into roughened faces by the roughening treatment.
- blackening treatment, etching treatment, plating, blast treatment, or the like can be performed as the roughening treatment.
- an insulating layer 50 having a through hole 50 X exposing a portion of an upper face of the wiring layer 41 is formed on the upper face of the insulating layer 30 in a similar manner to or the same manner as the step shown in FIG. 5B , in a step shown in FIG. 6B .
- the insulating layer 50 is formed so as to cover an entire upper face and an entire side face of the metal layer 42 .
- a via wiring filled in the through hole 50 X is formed, and a conductor layer 60 is formed on an upper face of the insulating layer 50 , for example, by a semi-additive method, in a step shown in FIG. 7A .
- the conductor layer 60 has a wiring layer 61 and a metal layer 62 .
- the wiring layer 61 is electrically connected to the wiring layer 41 through the via wiring filled in the through hole 50 X.
- the metal layer 62 has a through hole 62 Y. On this occasion, the planar shape of the through hole 62 Y is formed to be smaller than the planar shape of the metal layer 42 .
- roughening treatment is applied to the conductor layer 60 .
- an entire upper face and an entire side face of the conductor layer 60 are formed into roughened faces.
- blackening treatment, etching treatment, plating, blast treatment, or the like can be performed as the roughening treatment.
- an insulating layer 70 covering the wiring layer 61 and the metal layer 62 is formed on the upper face of the insulating layer 50 in a similar manner to or the same manner as the step shown in FIG. 5B , in a step shown in FIG. 7B .
- the insulating layer 70 is formed so as to cover an entire upper face and an entire side face of the metal layer 62 .
- the insulating layer 70 is formed so as to fill the through hole 62 Y.
- a through hole 70 Y penetrating the insulating layer 70 in a thickness direction is formed and a through hole 50 Y penetrating the insulating layer 50 in the thickness direction is formed, so that a portion of the metal layer 42 corresponding to the mount region of the electronic component 110 (see FIG. 1A ) is exposed from the through holes 70 Y and 50 Y.
- the through holes 50 Y and 70 Y can be, for example, formed by a laser machining method using a CO 2 laser, a YAG laser, or the like.
- the planar shape of the through hole 70 Y is formed to be one size larger than the planar shape of the through hole 62 Y of the metal layer 62 . Therefore, a portion of the upper face of the metal layer 62 in the vicinity of the opening edge of the through hole 70 Y is exposed from the insulating layer 70 .
- the metal layer 62 exposed from the insulating layer 70 functions as a mask and a stopper layer during the laser machining. Therefore, the through hole 50 Y penetrating the insulating layer 50 in the thickness direction is formed in the insulating layer 50 exposed from the through hole 62 Y of the metal layer 62 .
- the planar shape of the through hole 50 Y is formed into a size substantially equal to the planar shape of the through hole 62 Y.
- the metal layer 42 functions as a stopper layer during the laser machining.
- the through hole 50 Y, the through hole 62 Y and the through hole 70 Y are formed to communicate with one another so that an opening portion 100 penetrating the insulating layer 50 , the metal layer 62 and the insulating layer 70 in the thickness direction is formed.
- the portion of the upper face of the metal layer 42 is exposed from the opening portion 100 .
- a portion of the metal layer 62 is removed so as to make the planar shape of the through hole 62 Y of the metal layer 62 larger than each of the planar shapes of the through holes 50 Y and 70 Y.
- the metal layer 62 can be, for example, removed by isotropic etching using the insulating layer 70 as an etching mask.
- the isotropic etching first, the metal layer 62 exposed from the insulating layer 70 is etched and removed.
- the metal layer 62 covered with the insulating layer 70 is also removed due to a side etch phenomenon in which the etching proceeds in an in-plane direction of the metal layer 62 .
- a side face 62 A of the metal layer 62 constituting the inner side face of the opening portion 100 is set back in a direction to be separated more distantly from the planar center of the opening portion 100 than each of side faces 50 A and 70 A of the insulating layers 50 and 70 .
- a recess 101 constituted by the side face 62 A of the metal layer 62 and the side faces 50 A and 70 A of the insulating layers 50 and 70 is formed in the inner side face of the opening portion 100 .
- a step portion made up of the recess 101 is formed in the inner side face of the opening portion 100 in the present step.
- the metal layer 42 is also etched and removed at the same time when the metal layer 62 is etched and removed.
- a recess 42 X recessed on the insulating layer 30 side is formed in the upper face of the metal layer 42 exposed from the insulating layer 50 .
- surface roughness of a bottom face of the recess 42 X is larger than that prior to the etching treatment. Therefore, the surface roughness of the bottom face of the recess 42 X is larger than surface roughness of the upper face of the metal layer 42 covered with the insulating layer 50 .
- an adhesive layer 112 is formed on the upper face of the metal layer 42 exposed from the opening portion 100 .
- the adhesive layer 112 can be, for example, formed by applying a liquid resin or a paste-like resin which will be the adhesive layer 112 , to the upper face of the metal layer 42 .
- an adhesive agent made of an epoxy-based resin is used as the adhesive layer 112 .
- the resin agent in A-stage is used as the adhesive layer 112 in the present step.
- the resin agent in B-stage may be used as the adhesive layer 112 in the present step.
- the electronic component 110 is mounted on the adhesive layer 112 inside the opening portion 100 by use of a mounter. On this occasion, the electronic component 110 is fixed on the adhesive layer 112 in a face-up state.
- an insulating layer 80 with which the opening portion 100 and the recess 101 are filled is formed.
- the insulating layer 80 is formed so as to cover the entire surface of the electronic component 110 not in contact with the adhesive layer 112 .
- the insulating layer 80 is formed so as to cover an entire upper face of the insulating layer 70 .
- upper faces of electrode terminals 111 of the electronic component 110 are formed either on the same plane as the upper face of the insulating layer 70 or to be lower than the upper face of the insulating layer 70 . Accordingly, an upper face of the insulating layer 80 can be formed flatly.
- a through hole 80 X penetrating the insulating layers 70 and 80 continuously in the thickness direction is formed at a required place in the insulating layers 70 and 80
- through holes 80 Y are formed at required places in the insulating layer 80 .
- the through holes 80 X and 80 Y can be, for example, formed by a laser machining method using a CO 2 laser, a YAG laser, or the like.
- via wirings with which the through holes 80 X and 80 Y are filled are formed, and a wiring layer 90 electrically connected to the wiring layer 61 or the electrode terminals 111 through the via wirings is formed on the upper face of the insulating layer 80 , for example, by a semi-additive method.
- a solder resist layer 130 having an opening portion 130 X is formed on the upper face of the insulating layer 80 .
- the solder resist layer 130 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.
- the wiring layer 90 exposed from the opening portion 130 X is a pad P 2 .
- a metal layer i.e. a surface treatment layer
- the metal layer can be, for example, formed by an electroless plating method.
- the support substrate 160 is removed.
- the support body copper foil sheet of the support substrate 160 is mechanically peeled from the ultrathin copper foil sheet.
- the peeling layer is interposed between the support body copper foil sheet and the ultrathin copper foil sheet. Since an adhesive force between the support body copper foil sheet and the ultrathin copper foil sheet is weak, the support body copper foil sheet can be easily peeled from the ultrathin copper foil sheet.
- the ultrathin copper foil sheet remaining on the metal film 161 is, for example, removed by wet etching using an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. On this occasion, the metal film 161 functions as a stopper layer when the ultrathin copper foil sheet of the support substrate 160 is etched.
- the metal film 161 is removed by etching.
- the metal film 161 is selectively etched and removed from the wiring layer 20 (the Cu layer) by wet etching using a hydrogen peroxide/nitric acid-based solution.
- the wiring layer 20 and the insulating layer 30 function as stopper layers when the metal film 161 is etched.
- a lower face of the wiring layer 20 and a lower face of the insulating layer 30 are exposed to the outside, as shown in FIG. 12B .
- the lower face of the wiring layer 20 and the lower face of the insulating layer 30 which are in contact with an upper face of the metal film 161 are formed into a shape extending along the upper face (a flat face in this case) of the metal film 161 . Therefore, the lower face of the wiring layer 20 and the lower face of the insulating layer 30 are formed to be substantially flush with each other.
- a solder resist layer 120 having an opening portion 120 X is formed on the lower face of the insulating layer 30 in a similar manner to or the same manner as the step shown in FIG. 12A .
- the wiring layer 20 exposed from the opening portion 120 X serves as a pad P 1 .
- a metal layer i.e. a surface treatment layer
- the metal layer can be, for example, formed by an electroless plating method.
- the wiring board 10 shown in FIGS. 1A and 1B can be manufactured.
- the wiring board 10 can be used in a reversed state or can be disposed at any angle.
- a semiconductor chip 140 having a bump 141 formed on a circuit formation face of the semiconductor chip 140 is prepared in a step shown in FIG. 14 .
- the bump 141 of the semiconductor chip 140 is flip-chip bonded onto the pad P 2 of the wiring board 10 .
- the bump 141 is a solder bump
- reflow treatment is performed after the bump 141 and the pad P 2 are aligned with each other.
- the bump 141 (the solder bump) is melted so that the bump 141 is electrically connected to the pad P 2 .
- an underfill resin 150 (see FIG. 4 ) is formed between an upper face of the wiring board 10 and a lower face of the semiconductor chip 140 .
- the semiconductor device 11 shown in FIG. 4 can be manufactured by the aforementioned manufacturing process.
- the step portion constituted by the side face 50 A of the insulating layer 50 and the side face 62 A of the metal layer 62 is formed in the inner side face of the opening portion 100 where the electronic component 110 is received.
- the step portion is also formed in an interface between the inner side face of the opening portion 100 and the insulating layer 80 with which the opening portion 100 is filled. Peeling of the insulating layer 80 propagated to the interface between the insulating layer 50 and the insulating layer 80 can be stopped by the step portion.
- stress is apt to be concentrated on the vicinity of an opening edge of the bottom of the opening portion 100 when a warp or thermal stress occurs in the wiring board 10 .
- the peeling of the insulating layer 80 may occur at the interface between the metal layer 42 and the insulating layer 80 in the vicinity of the opening edge of the bottom of the opening portion 100 .
- the peeling may be propagated to the interface between the inner side face of the opening portion 100 and the insulating layer 80 .
- the peeling of the insulating layer 80 can be stopped at the step portion.
- the peeling of the insulating layer 80 can be stopped halfway in the depth direction of the opening portion 100 .
- the wiring layer 90 formed on the upper face of the insulating layer 80 can be suitably suppressed from being broken due to the peeling of the insulating layer 80 .
- lowering of electrical reliability of the wiring board 10 can be suitably suppressed.
- the recess 101 constituted by the side face 50 A of the insulating layer 50 , the upper face of the insulating layer 50 exposed from the metal layer 62 , the side face 62 A of the metal layer 62 , the lower face of the insulating layer 70 exposed from the metal layer 62 , and the side face 70 A of the insulating layer 70 is formed in the inner side face of the opening portion 100 . That is, the side face 62 A of the metal layer 62 is set back from the side faces 50 A and 70 A of the insulating layers 50 and 70 so that the recess 101 is formed.
- the step portion is constituted by the recess 101 . Further, the insulating layer 80 is formed so as to fill the recess 101 .
- a portion of the insulating layer 80 (specifically, the insulating layer 80 with which the recess 101 is filled) is formed to bite into the lower face of the insulating layer 70 . Therefore, tight adhesiveness between the insulating layer 70 and the insulating layer 80 can be improved due to an anchor effect.
- the recess 101 is formed into a closed ring shape so as to surround the opening portion 100 over the whole circumference in plan view. In other words, the recess 101 is formed to entirely surround the electronic component 110 in plan view. According to the configuration, peeling of the insulating layer 80 can be stopped by the recess 101 even when the peeling occurred at any position of the opening edge of the bottom of the opening portion 100 .
- the aforementioned first embodiment may be changed suitably and carried out in the following modes.
- the aforementioned first embodiment and the following modifications can be combined with each other and carried out within a range in which the first embodiment and the modifications are not technically contradictory to each other.
- the opening portion 100 is constituted by two insulating layers 50 and 70 and one metal layer 62 .
- the numbers of the insulating layers and the metal layers constituting the opening portion 100 are not limited particularly.
- An opening portion 102 where an electronic component 110 is received may be constituted by three insulating layers 50 , 70 and 180 and two metal layers 63 and 173 , for example, as in a wiring board 10 A shown in FIG. 15 .
- the structure of the wiring board 10 A will be described below.
- the same members as the aforementioned members shown in FIG. 1A to FIG. 14 are referred to by the same signs respectively and correspondingly, and detailed description about respective elements of the members will be omitted.
- a conductor layer 60 has a wiring layer 61 and the metal layer 63 .
- the wiring layer 61 and the metal layer 63 are formed separately from each other to be electrically insulated from each other.
- the metal layer 63 is, for example, formed so as to surround a mount region where the electronic component 110 is mounted.
- the insulating layer 70 is formed on an upper face of the insulating layer 50 so as to cover the conductor layer 60 .
- a through hole 70 X penetrating the insulating layer 70 in a thickness direction to expose a portion of an upper face of the conductor layer 60 (the wiring layer 61 in this case) is formed at a required place in the insulating layer 70 .
- the through hole 70 X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- a conductor layer 170 is formed on an upper face of the insulating layer 70 .
- the thickness of the conductor layer 170 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 170 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 170 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 170 .
- the surface roughness of the conductor layer 170 can, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the conductor layer 170 has a wiring layer 171 and the metal layer 173 .
- the wiring layer 171 and the metal layer 173 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 171 is, for example, electrically connected to the wiring layer 61 through a via wiring filled in the through hole 70 X.
- the wiring layer 171 is, for example, formed integrally with the via wiring filled in the through hole 70 X.
- the metal layer 173 is, for example, formed so as to surround the mount region where the electronic component 110 is mounted.
- Each of the metal layers 63 and 173 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 63 , 173 may be a wiring pattern for drawing a wiring, or may be a power source wiring or a ground wiring.
- the insulating layer 180 is formed on the upper face of the insulating layer 70 so as to cover the conductor layer 170 .
- a thickness between the upper face of the conductor layer 170 and an upper face of the insulating layer 180 can be, for example, set in a range of about 40 to 100 ⁇ m.
- the opening portion 102 is, for example, formed so as to penetrate the insulating layer 50 , the metal layer 63 , the insulating layer 70 , the metal layer 173 and the insulating layer 180 in the thickness direction.
- the opening portion 102 is, for example, formed so as to expose a portion of an upper face of a metal layer 42 .
- the opening portion 102 is formed correspondingly to the electronic component 110 embedded in the opening portion 102 .
- the opening portion 102 in the present example is constituted by a through hole 50 Y of the insulating layer 50 , a through hole 63 Y, a through hole 70 Y of the insulating layer 70 , a through hole 173 Y and a through hole 180 Y which communicate with one another.
- the through hole 63 Y penetrates the metal layer 63 in the thickness direction.
- the through hole 173 Y penetrates the metal layer 173 in the thickness direction.
- the through hole 180 Y penetrates the insulating layer 180 in the thickness direction.
- the planar shape of each of the through holes 50 Y, 63 Y, 70 Y, 173 Y and 180 Y is, for example, formed into a rectangular shape.
- the through holes 50 Y, 63 Y, 70 Y, 173 Y and 180 Y are, for example, formed coaxially with one another.
- the planar shape of each of the through holes 50 Y, 63 Y, 70 Y, 173 Y and 180 Y is, for example, formed to be larger than the planar shape of the electronic component 110 , and formed to be smaller than the planar shape of the metal layer 42 .
- the through hole 63 Y, 173 Y is, for example, formed to be larger in planar shape than the through hole 50 Y, 70 Y, 180 Y.
- the metal layer 63 , 173 is, for example, formed so as to surround an opening edge of the through hole 50 Y, 70 Y, 180 Y from the outside.
- the planar shape of the metal layer 63 , 173 is, for example, formed into a closed ring shape which continuously surrounds the opening edge of the through hole 50 Y, 70 Y, 180 Y over the whole circumference.
- a side face 63 A of the metal layer 63 constituting an inner side face of the opening portion 102 (the through hole 63 Y) is provided at a position where the side face 63 A is set back in a direction to be separately more distantly from the planar center of the opening portion 102 than a side face 50 A, 70 A of the insulating layer 50 , 70 .
- a recess 103 constituted by the side face 50 A of the insulating layer 50 , the upper face of the insulating layer 50 exposed from the metal layer 63 , the side face 63 A of the metal layer 63 , the lower face of the insulating layer 70 exposed from the metal layer 63 , and the side face 70 A of the insulating layer 70 is formed in the inner side face of the opening portion 102 .
- a side face 173 A of the metal layer 173 constituting the inner side face of the opening portion 102 (the through hole 173 Y) is provided at a position where the side face 173 A is set back inward of the insulating layer 70 from the side face 70 A of the insulating layer 70 .
- the side face 173 A of the metal layer 173 is provided at a position where the side face 173 A is set back inward of the insulating layer 180 from a side face 180 A of the insulating layer 180 constituting the inner side face of the opening portion 102 (the through hole 180 Y).
- the side face 173 A of the metal layer 173 is provided at the position where the side face 173 A is set back in the direction to be separated more distantly from the planar center of the opening portion 102 than the side face 70 A, 180 A of the insulating layer 70 , 180 .
- a recess 104 constituted by the side face 70 A of the insulating layer 70 , the upper face of the insulating layer 70 exposed from the metal layer 173 , the side face 173 A of the metal layer 173 , a lower face of the insulating layer 180 exposed from the metal layer 173 , and the side face 180 A of the insulating layer 180 is formed in the inner side face of the opening portion 102 .
- a first step portion constituted by the recess 103 and a second step portion constituted by the recess 104 are formed in the inner side face of the opening portion 102 .
- the electronic component 101 is mounted on the upper face of the metal layer 42 exposed from the opening portion 102 , through an adhesive layer 112 .
- the insulating layer 80 is formed so as to fill the opening portion 102 , the recess 103 and the recess 104 .
- the opening portion 102 is formed so as to penetrate the metal layers 63 and 173 and the insulating layers 50 , 70 and 180 in the thickness direction.
- the opening portion 102 can be formed to be deeper accordingly. Therefore, even when a high electronic component 110 is embedded, the opening portion 102 deep enough to receive the electronic component 110 therein can be formed easily.
- FIGS. 16A and 16B and FIG. 17 can be also used as the respective metal layers 63 and 173 .
- the structures will be described below in detail.
- FIG. 16A is a plan view of the metal layer 42 , the insulating layer 50 , the metal layer 63 , the insulating layer 70 and the electronic component 110 , as seen from the upper face side of the insulating layer 70 .
- FIG. 16B is a plan view of the metal layer 42 , the insulating layers 50 and 70 , the metal layer 173 , the insulating layer 180 and the electronic component 110 , as seen from the upper face side of the insulating layer 180 .
- the metal layer 63 has metal layers 64 each of which is shaped like a rectangle in plan view.
- the metal layers 64 are, for example, formed so as to surround the opening edges of the through holes 50 Y and 70 Y.
- the metal layer 173 has metal layers 174 each of which is shaped like a rectangle in plan view.
- the metal layers 174 are, for example, formed so as to surround the opening edge of the through hole 180 Y.
- a planar shape of the metal layers 64 and the metal layers 174 which are superimposed on each other in plan view is formed into a closed ring shape (a rectangular closed ring shape in this case) surrounding the opening edge of the opening portion 102 (the through holes 50 Y, 70 Y and 180 Y) over the whole circumference.
- the metal layers 63 and 173 in the present example are formed so that the planar shape of the two metal layers 63 and 173 which are superimposed on each other in plan view is formed into a closed ring shape surrounding the opening edge of the opening portion 102 over the whole circumference.
- the metal layers 64 and the metal layers 174 are formed to alternate each other in the circumferential direction of the opening portion 102 .
- each of the metal layers 64 is formed at a position not overlapping with any metal layer 174 in plan view.
- each of the metal layers 174 is formed at a position not overlapping with any metal layer 64 in plan view.
- the metal layers 64 and the metal layers 174 may have some portions overlapping with each other in plan view.
- the side face 63 A of each of the metal layers 64 constituting the inner side face of the opening portion 102 is provided at a position where the side face 63 A is set back in a direction to be separated more distantly from the planar center of the opening portion 102 than each of the side faces 50 A and 70 A of the insulating layers 50 and 70 .
- recesses 103 each of which is constituted by the side face 50 A of the insulating layer 50 , the side face 63 A of the metal layer 64 and the side face 70 A of the insulating layer 70 are formed in the inner side face of the opening portion 102 .
- the recesses 103 are formed at predetermined intervals in the circumferential direction of the opening portion 102 .
- the side face 173 A of each of the metal layers 174 constituting the inner side face of the opening portion 102 is provided at a position where the side face 173 A is set back in the direction to be separated more distantly from the planar center of the opening portion 102 than each of the side faces 70 A and 180 A of the insulating layers 70 and 180 .
- recesses 104 each of which is constituted by the side face 70 A of the insulating layer 70 , the side face 173 A of the metal layer 174 and the side face 180 A of the insulating layer 180 are formed in the inner side face of the opening portion 102 .
- the recesses 104 are formed at predetermined intervals in the circumferential direction of the opening portion 102 .
- the recesses 103 and 104 are formed so that, for example, the planar shape of the recesses 103 and 104 which are superimposed on each other in plan view is formed into a closed ring shape surrounding the opening portion 102 over the whole circumference.
- the recesses 103 and the recesses 104 are formed to alternate each other in the circumferential direction of the opening portion 102 .
- each of the recesses 103 is formed at a position not overlapping with any recess 104 in plan view.
- each of the recesses 104 is formed at a position not overlapping with any recess 103 in plan view.
- the recesses 103 and 104 are formed so that the planar shape of the recesses 103 and the recesses 104 which are superimposed on each other in plan view is formed into a closed ring shape surrounding the opening portion 102 over the whole circumference.
- the combination of the recesses 103 and the recesses 104 is formed so as to entirely surround the electronic component 110 in plan view.
- step portions are formed in the inner side face of the opening portion 102 by the metal layers 63 and 173 .
- the degree of freedom for designing the planar shape of each of the metal layers 63 and 173 can be improved in comparison with when a step portion is formed in the inner side face of the opening portion 102 by one metal layer.
- the electronic component 110 is mounted on the upper face of the metal layer 42 exposed from the opening portion 100 .
- the electronic component 110 may be mounted on the upper face of the insulating layer 30 exposed from the opening portion 100 , for example, as in a wiring board 10 B shown in FIG. 18 .
- the electronic component 110 is bonded to the upper face of the insulating layer 30 exposed from the opening portion 100 in a face-up state by the adhesive layer 112 .
- a through hole 42 Y penetrating the metal layer 42 in the thickness direction is formed in the metal layer 42 in this case.
- the opening portion 100 in the present example is constituted by the through hole 42 Y of the metal layer 42 , the through hole 50 Y of the insulating layer 50 , the through hole 62 Y of the metal layer 62 and the through hole 70 Y of the insulating layer 70 which communicate with one another. That is, the opening portion 100 in the present example is formed so as to penetrate the metal layer 42 , the insulating layer 50 , the metal layer 62 and the insulating layer 70 in the thickness direction.
- the through hole 42 Y is, for example, formed to be larger in planar shape than each of the through holes 50 Y and 70 Y.
- the metal layer 42 is, for example, formed so as to surround the opening edge of the through hole 50 Y, 70 Y from the outside.
- the planar shape of the metal layer 42 is, for example, formed into a ring shape.
- the planar shape of the metal layer 42 in the present example is formed into a closed ring shape continuously surrounding the opening edge of the through hole 50 Y, 70 Y over the whole circumference.
- the side face 42 A of the metal layer 42 constituting the inner side face of the opening portion 100 (the though hole 42 Y) is provided at a position where the side face 42 A is set back in a direction to be separated more distantly from the planar center of the opening portion 100 than the side face 50 A of the insulating layer 50 .
- the side face 42 A of the metal layer 42 is formed so as to be set back from the side face 50 A of the insulating layer 50 over the whole circumference of the opening portion 100 .
- a recess 105 (a step portion) constituted by the side face 42 A of the metal layer 42 , the lower face of the insulating layer 50 exposed from the metal layer 42 , and the side face 50 A of the insulating layer 50 is formed in the inner side face of the opening portion 100 .
- the through hole 62 Y in the present example is, for example, formed to be larger in planar shape than the through hole 42 Y. That is, the side face 62 A of the metal layer 62 is provided at a position where the side face 62 A is set back in the direction to be separated more distantly from the planar center of the opening portion 100 than the side face 42 A of the metal layer 42 .
- a distance between the side face 42 A of the metal layer 42 constituting the inner side face of the opening portion 100 and the side face 50 A of the insulating layer 50 constituting the inner side face of the opening portion 100 is shorter than a distance between the side face 62 A of the metal layer 62 constituting the inner side face of the opening portion 100 and the side face 50 A of the insulating layer 50 constituting the inner side face of the opening portion 100 .
- the opening portion 100 is formed so as to penetrate the metal layer 42 in the thickness direction. Accordingly, the opening portion 100 can be formed to be deeper by the thickness of the metal layer 42 . Therefore, even when a high electronic component 110 is embedded, the opening portion 100 deep enough to receive the electronic component 110 can be formed easily.
- steps similar to or the same as the steps shown in FIG. 5A to FIG. 8A are carried out so as to form a structure body shown in FIG. 19A . That is, in the structure body shown in FIG. 19A , a through hole 50 Y of an insulating layer 50 , a through hole 62 Y of a metal layer 62 and a through hole 70 Y of an insulating layer 70 are made to communicate with one another so that an opening portion 100 penetrating the insulating layer 50 , the metal layer 62 and the insulating layer 70 in a thickness direction is formed.
- a portion of the metal layer 62 is removed so as to make the planar shape of the through hole 62 Y larger than the planar shape of each of the through holes 50 Y and 70 Y, and a through hole 42 Y penetrating a metal layer 42 in the thickness direction is formed.
- the removal of the metal layer 62 and the formation of the through hole 42 Y can be, for example, performed by isotropic etching using the insulating layer 70 as an etching mask. By the isotropic etching, first, the metal layer 62 exposed from the insulating layer 70 is etched and removed, and the metal layer 42 exposed from the insulating layers 50 and 70 is etched and removed.
- the metal layers 42 and 62 covered with the insulating layers 50 and 70 is also removed due to a side etch phenomenon in which the etching proceeds in an in-plane direction of the metal layers 42 and 62 .
- side faces 42 A and 62 A of the metal layers 42 and 62 are set back in a direction to be separated more distantly from the planar center of the opening portion 100 than side faces 50 A and 70 A of the insulating layers 50 and the 70 .
- a recess 101 or a recess 105 is formed in an inner side face of the opening portion 100 by the side face 42 A of the metal layer 42 and the side face 50 A of the insulating layer 50 or by the side face 62 A of the metal layer 62 and the side face 70 A of the insulating layer 70 .
- a two-step portion constituted by the recesses 101 and 105 is formed in the inner side face of the opening portion 100 .
- an adhesive layer 112 is formed on an upper face of an insulating layer 30 exposed from the opening portion 100 in a similar manner to or the same manner as the step shown in FIG. 9B .
- an electronic component 110 is mounted on the adhesive layer 112 inside the opening portion 100 by use of a mounter in a similar manner to or the same manner as the step shown in FIG. 10A .
- an insulating layer 80 with which the opening portion 100 and the recesses 101 and 105 are filled is formed in a similar manner to or the same manner as the step shown in FIG. 10B .
- steps similar to or the same as the steps shown in FIG. 11A to FIG. 12A are carried out.
- a structure body shown in FIG. 20B can be obtained.
- steps similar to or the same as the steps shown in FIG. 12B and FIG. 13 are carried out.
- the wiring board 10 B in the present modification can be manufactured.
- the recess 101 is formed over the whole circumference of the opening portion 100 .
- the present invention is not limited thereto.
- the recess 101 may be formed in only a circumferential portion of the opening portion 100 .
- a wiring board 210 has a structure in which a wiring layer 220 , an insulating layer 230 , a conductor layer 240 , an insulating layer 250 , a conductor layer 260 , an insulating layer 270 , an insulating layer 280 , and a wiring layer 290 are formed sequentially.
- the wiring board 210 in the present example has a form of a so-called “coreless board” which is support substrate-free and different from a wiring board which is manufactured by a general build-up method, i.e. a wiring board in which a required number of build-up layers are formed sequentially on each or one of opposite faces of a core substrate serving as a support substrate.
- the wiring board 210 has one or more electronic components 310 (one electronic component 310 in FIG. 21A ) disposed inside an opening portion 300 formed in the plurality of insulating layers 250 and 270 , a solder resist layer 320 formed on a lower face of the insulating layer 230 , and a solder resist layer 330 formed on an upper face of the insulating layer 280 .
- the wiring board 210 is a wiring board in which the electronic component 310 is embedded.
- cupper (Cu) or a copper alloy can be used as the material of the wiring layers 220 and 290 and the conductor layers 240 and 260 .
- any of insulating resins such as an epoxy resin and a polyimide resin or any of resin materials in which fillers made of silica, alumina, etc., are mixed with these resins can be used as the material of the insulating layers 230 , 250 , 270 and 280 .
- a reinforcing material-including insulating resin in which a reinforcing material such as a woven fabric or an unwoven fabric of glass, aramid or LCP (Liquid Crystal Polymer) fiber is impregnated with a thermosetting resin containing an epoxy resin, a polyimide resin, or the like, as a main component may be used as the material of the insulating layers 230 , 250 , 270 and 280 .
- a non-photosensitive insulating resin containing a thermosetting resin as a main component or an insulating resin containing a photosensitive resin as a main component can be used as the material of the insulating layers 230 , 250 , 270 and 280 .
- the wiring layer 220 is an outermost (lowermost in this case) wiring layer of the wiring board 210 .
- a lower face of the wiring layer 220 is exposed from the insulating layer 230 .
- the lower face of the wiring layer 220 in the present example is formed to be substantially flush with the lower face of the insulating layer 230 .
- the lower face of the wiring layer 220 may be formed to be recessed on the conductor layer 240 side relatively to the lower face of the insulating layer 230 .
- the thickness of the wiring layer 220 can be, for example, set in a range of about 10 to 30 Gm.
- the insulating layer 230 is formed so as to cover an upper face and a side face of the wiring layer 220 and expose the lower face of the wiring layer 220 .
- a through hole 230 X penetrating the insulating layer 230 in a thickness direction so as to expose a portion of the upper face of the wiring layer 220 is formed at a predetermined place in the insulating layer 230 .
- the through hole 230 X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from an upper side (the conductor layer 240 side) toward a lower side (the wiring layer 220 side) in FIG. 21A .
- the through hole 230 X is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- a thickness between the upper face of the wiring layer 220 and an upper face of the insulating layer 230 can be, for example, set in a range of about 10 to 35 ⁇ m.
- the conductor layer 240 is formed on the upper face of the insulating layer 230 .
- the thickness of the conductor layer 240 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 240 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 240 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 240 .
- the surface roughness of the conductor layer 240 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the surface roughness Ra value is one kind of numerical value, which expresses the surface roughness and which is called arithmetical average roughness.
- the surface roughness Ra value is an arithmetic average of absolute values measured as a height varying within a measurement region from the surface which is an average line.
- the conductor layer 240 has, for example, a wiring layer 241 and a metal layer 242 .
- the wiring layer 241 and the metal layer 242 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 241 and the metal layer 242 are formed on one and the same plane.
- the wiring layer 241 is, for example, electrically connected to the wiring layer 220 through a via wiring filled in the through hole 230 X.
- the wiring layer 241 is, for example, formed integrally with the via wiring filled in the through hole 230 X.
- the metal layer 242 is, for example, formed in a mount region where the electronic component 310 is mounted.
- the metal layer 242 is, for example, formed at a position overlapping with the electronic component 310 in plan view.
- the metal layer 242 is, for example, formed at a position overlapping with the opening portion 300 in plan view.
- the planar shape of the metal layer 242 is, for example, formed to be larger than the planar shape of the opening portion 300 .
- An outer circumferential edge of the metal layer 242 is, for example, formed so as to surround an opening edge of the opening portion 300 from the outside in plan view.
- the metal layer 242 is, for example, formed into a rectangular shape in plan view.
- the metal layer 242 in the present example is, for example, a metal layer which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 242 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring.
- the metal layer 242 is, for example, electrically connected to another wiring layer or another conductor layer through a via wiring etc.
- the insulating layer 250 is formed on the upper face of the insulating layer 230 so as to cover the conductor layer 240 .
- a thickness between the upper face of the conductor layer 240 and an upper face of the insulating layer 250 can be, for example, set in a range of about 40 to 100 ⁇ m.
- a through hole 250 X penetrating the insulating layer 250 in the thickness direction so as to expose a portion of the upper face of the conductor layer 240 (the wiring layer 241 in this case) is formed at a predetermined place in the insulating layer 250 .
- the through hole 250 X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (the conductor layer 260 side) toward the lower side (the conductor layer 240 side) in FIG. 21A .
- the through hole 250 X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- the conductor layer 260 is formed on the upper face of the insulating layer 250 .
- the thickness of the conductor layer 260 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 260 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 260 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 260 .
- the surface roughness of the conductor layer 260 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the conductor layer 260 has, for example, a wiring layer 261 and a metal layer 262 .
- the wiring layer 261 and the metal layer 262 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 261 and the metal layer 262 are formed on one and the same plane.
- the wiring layer 261 is, for example, electrically connected to the wiring layer 241 through a via wiring filled in the through hole 250 X.
- the wiring layer 261 is, for example, formed integrally with the via wiring filled in the through hole 250 X.
- the metal layer 262 is, for example, formed so as to surround the mount region where the electronic component 310 is mounted.
- the metal layer 262 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 262 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When the metal layer 262 is the wiring pattern, the power source wiring or the ground wiring, for example, the metal layer 262 is electrically connected to another wiring layer or another conductor layer through a via wiring etc.
- the insulating layer 270 is formed on the upper face of the insulating layer 250 so as to cover the conductor layer 260 .
- a thickness between the upper face of the conductor layer 260 and an upper face of the insulating layer 270 can be, for example, set in a range of about 40 to 100 ⁇ m.
- the opening portion 300 is, for example, formed so as to penetrate the insulating layer 250 , the metal layer 262 and the insulating layer 270 in the thickness direction.
- the opening portion 300 is, for example, formed so as to expose a portion of an upper face of the metal layer 242 .
- the opening portion 300 is formed correspondingly to the electronic component 310 embedded in the opening portion 300 .
- the opening portion 300 in the present example is constituted by a through hole 250 Y, a through hole 262 Y and a through hole 270 Y.
- the through hole 250 Y penetrates the insulating layer 250 in the thickness direction.
- the through hole 262 Y penetrates the metal layer 262 in the thickness direction.
- the through hole 270 Y penetrates the insulating layer 270 in the thickness direction.
- each of the through holes 250 Y, 262 Y and 270 Y in the present example is formed into a rectangular shape in plan view.
- the through holes 250 Y, 262 Y and 270 Y are, for example, formed coaxially with each other. That is, positions of a central axis of the through hole 250 Y, a central axis of the through hole 262 Y and a central axis of the through hole 270 Y align with one another in plan view.
- Each of the planar shapes of the through holes 250 Y, 262 Y and 270 Y is formed to be larger than the planar shape of the electronic component 310 .
- the planar shape of the through hole 250 Y, 262 Y, 270 Y is, for example, formed to be smaller than the planar shape of the metal layer 242 .
- the through hole 262 Y is, for example, formed to be smaller in planar shape than each of the through holes 250 Y and 270 Y. That is, the through hole 262 Y has a smallest planar shape among the through holes 250 Y, 262 Y and 270 Y.
- the size of the through hole 262 Y can be, for example, set in a range of about 0.7 mm ⁇ 0.7 mm to 15 mm ⁇ 15 mm in plan view.
- the metal layer 262 is, for example, formed so as to surround opening edges of the through holes 250 Y and 270 Y from the inside.
- the metal layer 262 is, for example, formed into a ring shape (frame shape) in plan view.
- the metal layer 262 in the present example is formed into a rectangular closed ring shape in plan view to continuously surround the opening edge of each of the through holes 250 Y and 270 Y over the whole circumference.
- FIG. 22 is a plan view in which the wiring board 210 shown in FIG. 21A is seen from top.
- the insulating layer 280 , the wiring layer 290 and the solder resist layer 330 , etc. are drawn in perspective.
- the metal layer 262 has a protrusion portion 263 protruding into the inside of the opening portion 300 from a side face 250 A of the insulating layer 250 constituting an inner side face of the opening portion 300 (the through hole 250 Y).
- a side face 263 A of the protrusion portion 263 is provided at a position where the side face 263 A protrudes in a direction to be closer to the planar center of the opening portion 300 than the side face 250 A of the insulating layer 250 .
- the side face 263 A of the protrusion portion 263 is provided at a position where the side face 263 A protrudes in the direction to be closer to the planar center of the opening portion 300 than a side face 270 A of the insulating layer 270 constituting the inner side face of the opening portion 300 (the through hole 270 Y).
- the protrusion portion 263 is formed continuously over the whole circumference of the opening portion 300 .
- An upper face and a lower face of the protrusion portion 263 are exposed from the insulating layers 270 and 250 .
- a convex step portion 301 constituted by the side face 250 A of the insulating layer 250 , the lower face of the protrusion portion 263 , the side face 263 A of the protrusion portion 263 , the upper face of the protrusion portion 263 and the side face 270 A of the insulating layer 270 is formed in the inner side face of the opening portion 300 .
- the step portion 301 is, for example, formed continuously over the whole circumference of the opening portion 300 .
- the surface of the metal layer 262 exposed from the insulating layers 250 and 270 is, for example, a roughened face.
- the upper face and the side face of the protrusion portion 263 are, for example, formed to be larger in surface roughness than an upper face of the metal layer 262 covered with the insulating layer 270 .
- the through hole 250 Y of the insulating layer 250 is, for example, formed to be smaller in planar shape than the through hole 270 Y of the insulating layer 270 .
- the side face 270 A of the insulating layer 270 is, for example, provided at a position where the side face 270 A is set back in a direction to be separated more distantly from the planar center of the opening portion 300 than the side face 250 A of the insulating layer 250 .
- the side face 270 A of the insulating layer 270 is formed so as to be set back from the side face 250 A of the insulating layer 250 over the whole circumference of the opening portion 300 .
- a recess 242 X recessed on the insulating layer 230 side is formed in the upper face of the metal layer 242 exposed in the bottom of the opening portion 300 (specifically, the bottom of the through hole 250 Y).
- a bottom face and an inner side face of the recess 242 X are, for example, roughened faces.
- Surface roughness of the bottom face of the recess 242 X is, for example, formed to be larger than surface roughness of the upper face of the metal layer 242 covered with the insulating layer 250 .
- the surface roughness of the upper face of the metal layer 242 exposed in the bottom of the opening portion 300 is formed to be larger than the surface roughness of the upper face of the metal layer 242 covered with the insulating layer 250 .
- the electronic component 310 is mounted on (adhesively bonded to) the upper face of the metal layer 242 (specifically, the bottom face of the recess 242 X) exposed from the opening portion 300 through an adhesive layer 312 . That is, the electronic component 310 is disposed inside the opening portion 300 .
- the adhesive layer 312 is formed on the upper face of the metal layer 242 .
- an epoxy-based, polyimide-based or silicone-based thermosetting adhesive agent can be used as the material of the adhesive layer 312 .
- an active component such as a semiconductor chip, a transistor or a diode or a passive component such as a chip capacitor, a chip inductor or a chip resistor can be used as the electronic component 310 .
- a component made of silicon or a component made of ceramic can be used as the electronic component 310 .
- the electronic component 310 according to the present embodiment is a semiconductor chip.
- a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip.
- a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip or a flash memory chip can be used as the semiconductor chip.
- the electronic component 310 can be, for example, made of a semiconductor substrate.
- silicon etc. can be used as the material of the semiconductor substrate.
- Electrode terminals 311 are provided on, of the electronic component 310 , a circuit formation face 310 A where a semiconductor integrated circuit (not shown) is formed.
- the electrode terminals 311 are, for example, metal posts each formed in the shape of a column extending upward from the circuit formation face 310 A.
- copper or a copper alloy can be used as the material of the electrode terminals 311 .
- the electronic component 310 is bonded to the upper face of the metal layer 242 by the adhesive layer 312 in a state in which a back face (a lower face in this case) of the electronic component 310 opposite to the circuit formation face 310 A is opposed to the upper face of the metal layer 242 (i.e. faces-up state).
- Upper faces of the electrode terminals 311 are, for example, formed on the same plane as the upper face of the insulating layer 270 or formed to be lower than the upper face of the insulating layer 270 .
- the insulating layer 280 is formed so as to fill the opening portion 300 and entirely cover the electronic component 310 .
- the insulating layer 280 is, for example, formed so as to cover an entire side face of the adhesive layer 312 , an entire side face of the electronic component 310 , the entire circuit formation face 310 A exposed from the electrode terminals 311 , and the upper faces and side faces of the electrode terminals 311 .
- the insulating layer 280 is, for example, formed so as to cover the surface of the metal layer 242 exposed from the adhesive layer 312 inside the opening portion 300 .
- the insulating layer 280 is formed so as to cover the entire side face 250 A of the insulating layer 250 , the entire lower face of the protrusion portion 263 of the metal layer 262 , the entire side face 263 A of the protrusion portion 263 , the entire upper face of the protrusion portion 263 , and the entire side face 270 A of the insulating layer 270 .
- the insulating layer 280 is, for example, formed so as to cover the entire surface (the lower face, the upper face and the side face) of the protrusion portion 263 .
- the protrusion portion 263 is formed so as to bite into the insulating layer 280 .
- the insulating layer 280 is, for example, formed so as to cover the entire upper face of the insulating layer 270 .
- a through hole 280 X penetrating the insulating layers 270 and 280 in the thickness direction so as to expose a portion of the upper face of the conductor layer 260 (the wiring layer 261 in this case) is formed at a required place in the insulating layers 270 and 280 .
- a through hole 280 Y penetrating the insulating layer 280 in the thickness direction so as to expose a portion of the upper face of each of the electrode terminals 311 is formed at a required place in the insulating layer 280 .
- Each of the through holes 280 X and 280 Y is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (the wiring layer 290 side) toward the lower side (the wiring layer 261 side or the electrode terminal 311 side) in FIG. 21A .
- the through hole 280 X, 280 Y is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- the wiring layer 290 is formed on the upper face of the insulating layer 280 .
- the wiring layer 290 is, for example, an outermost (uppermost in this case) wiring layer of the wiring board 210 .
- the wiring layer 290 has a wiring layer electrically connected to the wiring layer 261 through a via wiring filled in the through hole 280 X.
- the wiring layer 290 has a wiring layer electrically connected to the electrode terminal 311 through a via wiring filled in the through hole 280 Y.
- the wiring layer 290 is formed integrally with the via wiring filled in the through hole 280 X or the through hole 280 Y.
- the thickness of the wiring layer 290 can be, for example, set in a range of about 10 to 30 ⁇ m.
- the solder resist layer 320 is formed on the lower face of the outermost (lowermost in this case) insulating layer 230 so as to cover the lowermost wiring layer 220 .
- an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist layer 320 .
- the thickness of the solder resist layer 320 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An opening portion 320 X serving for exposing at least a portion of the lower face of the lowermost wiring layer 220 as a pad P 11 is formed in the solder resist layer 320 .
- an external connection terminal such as a solder ball or a lead pin, which is used when the wiring board 210 is mounted on a mount board such as a motherboard is connected to the pad P 11 . That is, the pad P 11 in the present example functions as an external connection pad.
- a surface treatment layer may be formed on a lower face of the pad P 11 if occasions demand.
- a gold (Au) layer, a nickel (Ni) layer/Au layer (a metal layer in which the Ni layer and the Au layer are formed in the named order), an Ni layer/palladium (Pd) layer/Au layer (a metal layer in which the Ni layer, the Pd layer and the Au layer are formed in the named order), etc. can be listed as examples of the surface treatment layer.
- the Au layer is a metal layer made of Au or an Au alloy.
- the Ni layer is a metal layer made of Ni or an Ni alloy.
- the Pd layer is a metal layer made of Pd or a Pd alloy.
- a metal layer (an electroless plating metal layer) formed by an electroless plating method can be used as each of the Ni layer, the Au layer and the Pd layer.
- an OSP (Organic Solderability Preservative) film formed by applying antioxidation treatment such as OSP treatment to the surface of the pad P 11 can be used as another example of the surface treatment layer.
- An organic coating of an azole compound, an imidazole compound, or the like, can be used as the OSP film.
- the wiring layer 220 per se exposed from the opening portion 320 X (or the surface treatment layer in the case where the surface treatment layer is formed on the wiring layer 220 ) may be set as the external connection terminal.
- the solder resist layer 330 is formed on the upper face of the outermost (uppermost in this case) insulating layer 280 so as to cover the uppermost wiring layer 290 .
- an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist layer 330 .
- the thickness of the solder resist layer 330 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An opening portion 330 X serving for exposing at least a portion of the uppermost wiring layer 290 as a pad P 12 is formed in the solder resist layer 330 .
- the pad P 12 functions, for example, as an electronic component mounting pad in order to be electrically connected to an electronic component such as a semiconductor chip.
- a surface treatment layer may be formed on the surface (an upper face and a side face or only an upper face) of the pad P 12 if occasions demand.
- Metal layers such as an Au layer, an Ni layer/Au layer and an Ni layer/Pd layer/Au layer and an OSP film can be used as examples of the surface treatment layer.
- the semiconductor device 211 has the wiring board 210 , one or more semiconductor chips 340 (one semiconductor chip 340 in FIG. 24 ), and an underfill resin 350 .
- the semiconductor chip 340 is flip-chip mounted on the wiring board 210 . That is, a bump 341 provided and disposed on a circuit formation face (a lower face in this case) of the semiconductor chip 340 is bonded to the pad P 12 of the wiring board 210 . Thus, the semiconductor chip 340 is electrically connected to the pad P 12 (the wiring layer 290 ) through the bump 341 .
- a logic chip such as a CPU chip or a GPU chip, or a memory chip such as a DRAM chip, an SRAM chip or a flash memory chip can be used as the semiconductor chip 340 .
- the logic chip and the memory chip may be configured in combination and mounted on the wiring board 210 .
- a gold bump or a solder bump can be used as the bump 341 .
- an alloy containing lead (Pb), a tin (Sn)—Au alloy, an Sn—Cu alloy, an Sn—Ag alloy, an Sn-silver (Ag)—Cu alloy, or the like can be used as the material of the solder bump.
- the underfill resin 350 is provided to fill a gap between the wiring board 210 and the semiconductor chip 340 .
- an insulating resin such as an epoxy resin can be used as the material of the underfill resin 350 .
- portions to be final constituent elements of the wiring board 10 will be designated by signs of the final constituent elements for convenience of explanation in the description.
- a support substrate 360 is prepared, as shown in FIG. 25A .
- a plate-like material high in rigidity such as silicon, glass or metal (such as copper) can be used as the material of the support substrate 360 .
- a metal plate or a metal foil sheet can be used as the support substrate 360 .
- a copper foil sheet in which an ultrathin copper foil sheet about 2 to 5 ⁇ m thick is pasted to a support body copper foil sheet, which is about 35 to 70 ⁇ m thick, through a peeling layer is used as the support substrate 360 in the present example.
- a metal film 361 covering an entire upper face of the support substrate 360 is formed on the upper face of the support substrate 360 .
- the metal film 361 is formed on an upper face of the ultrathin copper foil sheet of the support substrate 360 .
- the metal film 361 can be, for example, formed by a sputtering method, a vapor deposition method or an electrolytic plating method.
- an electrically conductive material serving as a stopper layer when the support substrate 360 is etched and removed can be used as the material of the metal film 361 .
- an electrically conductive material which can be selectively etched and removed from a wiring layer 220 e.g.
- a Cu layer which will be formed by a subsequent step can be used as the material of the metal film 361 .
- a metal such as nickel (Ni), titanium (Ti), chromium (Cr), tin, cobalt (Co), iron (Fe) or palladium or an alloy containing at least one metal selected from the aforementioned metals can be used as the material of such a metal film 361 .
- Ni is used as the material of the metal film 361 in the present example.
- the thickness of the metal film 361 can be, for example, set in a range of about 0.1 to 1.0 ⁇ m.
- the wiring layer 220 is formed on an upper face of the metal film 361 .
- the wiring layer 220 can be, for example, formed by a semi-additive method. Specifically, first, a resist pattern (not shown) having an opening portion corresponding to the shape of the wiring layer 220 is formed on the upper face of the metal film 361 . Successively, by an electrolytic copper plating method using the support substrate 360 and the metal film 361 as power feed layers, a copper plating coating is deposited on the upper face of the metal film 361 exposed from the opening portion of the resist pattern. Then, the resist pattern is removed. In this manner, the wiring layer 220 can be formed on the metal film 361 . Incidentally, any of various wiring formation methods such as a subtractive method other than the semi-additive method can be also used as the method for forming the wiring layer 220 .
- an insulating layer 230 having a through hole 230 X exposing a portion of an upper face of the wiring layer 220 is formed on the upper face of the metal film 361 in a step shown in FIG. 25B .
- a resin film is used as the insulating layer 230
- the resin film is laminated on the upper face of the metal film 361 by thermocompression bonding, and the resin film is patterned by a photolithographic method in order to form the insulating layer 230 .
- a liquid or paste-like insulating resin may be applied to the upper face of the metal film 361 by a spin coating method etc., and the insulating resin may be patterned by a photolithographic method in order to form the insulating layer 230 .
- a via wiring filled in the through hole 230 X is formed, and a conductor layer 240 is formed on an upper face of the insulating layer 230 , for example, by a semi-additive method, in a step shown in FIG. 25C .
- the conductor layer 240 has a wiring layer 241 and a metal layer 242 .
- the wiring layer 241 is electrically connected to the wiring layer 220 through the via wiring filled in the through hole 230 X.
- the metal layer 242 is formed in a mount region of an electronic component 310 (see FIG. 21A ).
- roughening treatment is applied to the conductor layer 240 in a step shown in FIG. 26A .
- An entire upper face and an entire side face of the conductor layer 240 are formed into roughened faces by the roughening treatment.
- blackening treatment, etching treatment, plating, blast treatment, or the like can be performed as the roughening treatment.
- an insulating layer 250 having a through hole 250 X exposing a portion of an upper face of the wiring layer 241 is formed on the upper face of the insulating layer 230 in a similar manner to or the same manner as the step shown in FIG. 25B , in a step shown in FIG. 26B .
- the insulating layer 250 is formed so as to cover an entire upper face and an entire side face of the metal layer 242 .
- a via wiring filled in the through hole 250 X is formed, and a conductor layer 260 is formed on an upper face of the insulating layer 250 , for example, by a semi-additive method, in a step shown in FIG. 27A .
- the conductor layer 260 has a wiring layer 261 and a metal layer 262 .
- the wiring layer 261 is electrically connected to the wiring layer 241 through the via wiring filled in the through hole 250 X.
- the metal layer 262 has a through hole 262 Y. On this occasion, the planar shape of the through hole 262 Y is formed to be smaller than the planar shape of the metal layer 242 .
- roughening treatment is applied to the conductor layer 260 .
- an entire upper face and an entire side face of the conductor layer 260 are formed into roughened faces.
- blackening treatment, etching treatment, plating, blast treatment, or the like can be performed as the roughening treatment.
- an insulating layer 270 covering the wiring layer 261 and the metal layer 262 is formed on the upper face of the insulating layer 250 in a similar manner to or the same manner as the step shown in FIG. 25B , in a step shown in FIG. 27B .
- the insulating layer 270 is formed so as to cover an entire upper face and an entire side face of the metal layer 262 .
- the insulating layer 270 is formed so as to fill the through hole 262 Y.
- a through hole 270 Y penetrating the insulating layer 270 in a thickness direction is formed and a through hole 250 Y penetrating the insulating layer 250 in the thickness direction is formed, so that a portion of the metal layer 242 corresponding to the mount region of the electronic component 310 (see FIG. 21A ) is exposed from the through holes 270 Y and 250 Y.
- the through holes 250 Y and 270 Y can be, for example, formed by a laser machining method using a CO 2 laser, a YAG laser, or the like.
- the planar shape of the through hole 270 Y is formed to be one size larger than the planar shape of the through hole 262 Y of the metal layer 262 . Therefore, a portion of the upper face of the metal layer 262 in the vicinity of the opening edge of the through hole 270 Y is exposed from the insulating layer 270 .
- the metal layer 262 exposed from the insulating layer 270 functions as a mask and a stopper layer during the laser machining. Therefore, the through hole 250 Y penetrating the insulating layer 250 in the thickness direction is formed in the insulating layer 250 exposed from the through hole 262 Y of the metal layer 262 .
- the planar shape of the through hole 250 Y is formed into a size substantially equal to the planar shape of the through hole 262 Y.
- the metal layer 242 functions as a stopper layer during the laser machining.
- the through hole 250 Y, the through hole 262 Y and the through hole 270 Y are formed to communicate with one another so that an opening portion 300 penetrating the insulating layer 250 , the metal layer 262 and the insulating layer 270 in the thickness direction is formed.
- the portion of the upper face of the metal layer 242 is exposed from the opening portion 300 .
- roughening treatment is applied to the upper face of the metal layer 242 exposed from the insulating layer 250 .
- the entire upper face of the metal layer 242 exposed from the insulating layer 250 is formed into a roughened face.
- a recess 242 X recessed on the insulating layer 230 side is formed in the upper face of the metal layer 242 exposed from the insulating layer 250 . Further, surface roughness of a bottom face of the recess 242 X is larger than that prior to etching treatment.
- the surface roughness of the bottom face of the recess 242 X is larger than surface roughness of the upper face of the metal layer 242 covered with the insulating layer 250 .
- blackening treatment, etching treatment, plating, blast treatment, or the like can be performed as the roughening treatment.
- the surface (a lower face, an upper face and a side face) of the protrusion portion 263 of the metal layer 262 exposed from the insulating layers 250 and 270 is roughened at the same time when the metal layer 242 is roughened.
- surface roughness of the surface of the protrusion portion 263 is larger than that prior to etching treatment. Therefore, the surface roughness of the surface of the protrusion portion 263 is larger than the surface roughness of the upper face of the metal layer 242 covered with the insulating layer 250 .
- an adhesive layer 312 is formed on the upper face of the metal layer 242 exposed from the opening portion 300 .
- the adhesive layer 312 can be, for example, formed by applying a liquid resin or a paste-like resin which will be the adhesive layer 312 , to the upper face of the metal layer 242 .
- an adhesive agent made of an epoxy-based resin is used as the adhesive layer 312 .
- the resin agent in A-stage is used as the adhesive layer 312 in the present step.
- the resin agent in B-stage may be used as the adhesive layer 312 in the present step.
- the electronic component 310 is mounted on the adhesive layer 312 inside the opening portion 300 by use of a mounter. On this occasion, the electronic component 310 is fixed on the adhesive layer 312 in a face-up state.
- an insulating layer 280 with which the opening portion 300 is filled is formed.
- the insulating layer 280 is formed so as to cover the entire surface of the electronic component 310 not in contact with the adhesive layer 312 .
- the insulating layer 280 is formed so as to cover the entire surface of the protrusion portion 263 which has been subjected to roughening treatment.
- the insulating layer 280 is formed so as to cover an entire upper face of the insulating layer 270 .
- upper faces of electrode terminals 311 of the electronic component 310 are formed either on the same plane as the upper face of the insulating layer 270 or to be lower than the upper face of the insulating layer 270 . Accordingly, an upper face of the insulating layer 280 can be formed flatly.
- a through hole 280 X penetrating the insulating layers 270 and 280 continuously in the thickness direction is formed at a required place in the insulating layers 270 and 280
- through holes 280 Y are formed at required places in the insulating layer 280 .
- the through holes 280 X and 280 Y can be, for example, formed by a laser machining method using a CO 2 laser, a YAG laser, or the like.
- via wirings with which the through holes 280 X and 280 Y are filled are formed, and a wiring layer 290 electrically connected to the wiring layer 261 or the electrode terminals 311 through the via wirings is formed on the upper face of the insulating layer 280 , for example, by a semi-additive method.
- a solder resist layer 330 having an opening portion 330 X is formed on the upper face of the insulating layer 280 .
- the solder resist layer 330 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.
- the wiring layer 290 exposed from the opening portion 330 X is a pad P 12 .
- a metal layer i.e. a surface treatment layer
- the metal layer can be, for example, formed by an electroless plating method.
- the support substrate 360 is removed.
- the support body copper foil sheet of the support substrate 360 is mechanically peeled from the ultrathin copper foil sheet.
- the peeling layer is interposed between the support body copper foil sheet and the ultrathin copper foil sheet. Since an adhesive force between the support body copper foil sheet and the ultrathin copper foil sheet is weak, the support body copper foil sheet can be easily peeled from the ultrathin copper foil sheet.
- the ultrathin copper foil sheet remaining on the metal film 361 is, for example, removed by wet etching using an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. On this occasion, the metal film 361 functions as a stopper layer when the ultrathin copper foil sheet of the support substrate 360 is etched.
- the metal film 361 is removed by etching.
- the metal film 361 is selectively etched and removed from the wiring layer 220 (the Cu layer) by wet etching using a hydrogen peroxide/nitric acid-based solution.
- the wiring layer 220 and the insulating layer 230 function as stopper layers when the metal film 361 is etched.
- a lower face of the wiring layer 220 and a lower face of the insulating layer 230 are exposed to the outside, as shown in FIG. 32A .
- the lower face of the wiring layer 220 and the lower face of the insulating layer 230 which are in contact with an upper face of the metal film 361 are formed into a shape extending along the upper face (a flat face in this case) of the metal film 361 . Therefore, the lower face of the wiring layer 220 and the lower face of the insulating layer 230 are formed to be substantially flush with each other.
- a solder resist layer 320 having an opening portion 320 X is formed on the lower face of the insulating layer 230 in a similar manner to or the same manner as the step shown in FIG. 31B .
- the wiring layer 220 exposed from the opening portion 320 X serves as a pad P 11 .
- a metal layer i.e. a surface treatment layer
- the metal layer can be, for example, formed by an electroless plating method.
- the wiring board 210 shown in FIGS. 21A and 21B can be manufactured.
- the wiring board 210 can be used in a reversed state or can be disposed at any angle.
- a semiconductor chip 340 having a bump 341 formed on a circuit formation face of the semiconductor chip 340 is prepared in a step shown in FIG. 33 .
- the bump 341 of the semiconductor chip 340 is flip-chip bonded onto the pad P 12 of the wiring board 210 .
- the bump 341 is a solder bump
- reflow treatment is performed after the bump 341 and the pad P 12 are aligned with each other.
- the bump 341 (the solder bump) is melted so that the bump 341 is electrically connected to the pad P 12 .
- an underfill resin 350 (see FIG. 24 ) is formed between an upper face of the wiring board 210 and a lower face of the semiconductor chip 340 .
- the semiconductor device 211 shown in FIG. 24 can be manufactured by the aforementioned manufacturing process.
- the step portion 301 constituted by the side face 250 A of the insulating layer 250 and the side face 263 A of the protrusion 263 of the metal layer 262 is formed in the inner side face of the opening portion 300 where the electronic component 310 is received.
- a step portion is also formed in an interface between the inner side face of the opening portion 300 and the insulating layer 280 with which the opening portion 300 is filled.
- the peeling of the insulating layer 280 may occur at the interface between the metal layer 242 and the insulating layer 280 in the vicinity of the opening edge of the bottom of the opening portion 300 .
- the peeling may be propagated to the interface between the inner side face of the opening portion 300 and the insulating layer 280 .
- the peeling of the insulating layer 280 can be stopped at the step portion 301 .
- the peeling of the insulating layer 280 can be stopped halfway in the depth direction of the opening portion 300 . Accordingly, the wiring layer 290 formed on the upper face of the insulating layer 280 can be suitably suppressed from being broken due to the peeling of the insulating layer 280 . As a result, lowering of electrical reliability of the wiring board 210 can be suitably suppressed.
- the convex step portion 301 constituted by the side face 250 A of the insulating layer 250 , the lower face of the protrusion portion 263 exposed from the insulating layer 250 , the side face 263 A of the protrusion portion 263 , the upper face of the protrusion portion 263 exposed from the insulating layer 270 , and the side face 270 A of the insulating layer 270 is formed in the inner side face of the opening portion 300 . That is, a portion of the metal layer 262 is formed to protrude more inward of the opening portion 300 than the side faces 250 A and 270 A of the insulating layers 250 and 270 so that the step portion 301 is formed in the inner side face of the opening portion 300 .
- the insulating layer 280 is formed so as to cover the entire surface of the metal layer 262 (i.e. the protrusion portion 263 ) protruding more inward of the opening portion 300 than the side faces 250 A and 270 A of the insulating layers 250 and 270 .
- the protrusion portion 263 of the metal layer 262 is formed so as to bite into the insulating layer 280 . Therefore, tight adhesiveness between the metal layer 262 and the insulating layer 280 can be improved due to an anchor effect.
- the step portion 301 is formed into a closed ring shape so as to surround the opening portion 300 over the whole circumference in plan view. According to the configuration, peeling of the insulating layer 280 can be stopped by the step portion 301 even when the peeling occurs at any position of the opening edge of the bottom of the opening portion 300 .
- the aforementioned second embodiment may be changed suitably and carried out in the following modes.
- the aforementioned second embodiment and the following modifications can be combined with each other and carried out within a range in which the second embodiment and the modifications are not technically contradictory to each other.
- the opening portion 300 is constituted by two insulating layers 250 and 270 and one metal layer 262 .
- the numbers of the insulating layers and the metal layers constituting the opening portion 300 are not limited particularly.
- an opening portion 302 where an electronic component 310 is received may be constituted by three insulating layers 250 , 270 and 380 and two metal layers 264 and 374 .
- the structure of the wiring board 210 A will be described below.
- the same members as the aforementioned members shown in FIG. 21A to FIG. 33 are referred to by the same signs respectively and correspondingly, and detailed description about respective elements of the members will be omitted.
- a conductor layer 260 has a wiring layer 261 and the metal layer 264 .
- the wiring layer 261 and the metal layer 264 are formed separately from each other to be electrically insulated from each other.
- the metal layer 264 is, for example, formed so as to surround a mount region where the electronic component 310 is mounted.
- the insulating layer 270 is formed on an upper face of the insulating layer 250 so as to cover the conductor layer 260 .
- a through hole 270 X penetrating the insulating layer 270 in a thickness direction to expose a portion of an upper face of the conductor layer 260 (the wiring layer 261 in this case) is formed at a required place in the insulating layer 270 .
- the through hole 270 X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end.
- a conductor layer 370 is formed on an upper face of the insulating layer 270 .
- the thickness of the conductor layer 370 can be, for example, set in a range of about 10 to 30 ⁇ m.
- An upper face and a side face of the conductor layer 370 are, for example, roughened faces.
- the upper face and the side face of the conductor layer 370 are, for example, formed into roughened faces larger in surface roughness than a lower face of the conductor layer 370 .
- the surface roughness of the conductor layer 370 can, for example, set to be not lower than 200 nm in terms of surface roughness Ra value.
- the conductor layer 370 has a wiring layer 371 and the metal layer 374 .
- the wiring layer 371 and the metal layer 374 are formed separately from each other to be electrically insulated from each other.
- the wiring layer 371 is, for example, electrically connected to the wiring layer 261 through a via wiring filled in the through hole 270 X.
- the wiring layer 371 is, for example, formed integrally with the via wiring filled in the through hole 270 X.
- the metal layer 374 is, for example, formed so as to surround the mount region where the electronic component 310 is mounted.
- Each of the metal layers 264 and 374 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer.
- the metal layer 264 , 374 may be a wiring pattern for drawing a wiring, or may be a power source wiring or a ground wiring.
- the insulating layer 380 is formed on the upper face of the insulating layer 270 so as to cover the conductor layer 370 .
- a thickness between the upper face of the conductor layer 370 and an upper face of the insulating layer 380 can be, for example, set in a range of about 40 to 100 ⁇ m.
- the opening portion 302 is, for example, formed so as to penetrate the insulating layer 250 , the metal layer 264 , the insulating layer 270 , the metal layer 374 and the insulating layer 380 in the thickness direction.
- the opening portion 302 is, for example, formed so as to expose a portion of an upper face of a metal layer 242 .
- the opening portion 302 is formed correspondingly to the electronic component 310 embedded in the opening portion 302 .
- the opening portion 302 in the present example is constituted by a through hole 250 Y of the insulating layer 250 , a through hole 264 Y, a through hole 270 Y of the insulating layer 270 , a through hole 374 Y and a through hole 380 Y which communicate with one another.
- the through hole 264 Y penetrates the metal layer 264 in the thickness direction.
- the through hole 374 Y penetrates the metal layer 374 in the thickness direction.
- the through hole 380 Y penetrates the insulating layer 380 in the thickness direction.
- each of the through holes 250 Y, 264 Y, 270 Y, 374 Y and 380 Y is, for example, formed into a rectangular shape.
- the through holes 250 Y, 264 Y, 270 Y, 374 Y and 380 Y are, for example, formed coaxially with one another.
- the planar shape of each of the through holes 250 Y, 264 Y, 270 Y 374 Y and 380 Y is, for example, formed to be larger than the planar shape of the electronic component 310 , and formed to be smaller than the planar shape of the metal layer 242 .
- the through hole 264 Y, 374 Y is, for example, formed to be smaller in planar shape than the through hole 250 Y, 270 Y, 380 Y.
- the metal layer 264 , 374 is, for example, formed so as to surround an opening edge of the through hole 250 Y, 270 Y, 380 Y from the inside.
- the planar shape of the metal layer 264 , 374 is, for example, formed into a closed ring shape which continuously surrounds the opening edge of the through hole 250 Y, 270 Y, 380 Y over the whole circumference.
- the metal layer 264 has a protrusion portion 265 protruding inward of the opening portion 300 from each of side faces 250 A and 270 A of the insulating layers 250 and 270 .
- a side face 265 A of the protrusion portion 265 is provided at a position where the side face 265 A protrudes in a direction to be closer to the planar center of the opening portion 302 than the side faces 250 A and 270 A of the insulating layers 250 and 270 .
- a convex step portion 303 constituted by the side face 250 A of the insulating layer 250 , a lower face of the protrusion portion 265 , the side face 265 A of the protrusion portion 265 , an upper face of the protrusion portion 265 and the side face 270 A of the insulating layer 270 is formed in an inner side face of the opening portion 302 .
- the metal layer 374 has a protrusion portion 375 protruding inward of the opening portion 302 from the side face 270 A of the insulating layer 270 .
- a side face 375 A of the protrusion portion 375 is provided at a position where the side face 375 A protrudes in the direction to be closer to the planar center of the opening portion 302 than a side face 380 A of the insulating layer 380 and the side face 270 A of the insulating layer 270 which constitute the inner side face of the opening portion 302 (the through hole 308 Y).
- a convex step portion 304 constituted by the side face 270 A of the insulating layer 270 , a lower face of the protrusion portion 375 , the side face 375 A of the protrusion portion 375 , an upper face of the protrusion portion 375 and the side face 380 A of the insulating layer 380 is formed in the inner side face of the opening portion 302 .
- the side face 380 A of the insulating layer 380 is, for example, provided at a position where the side face 380 A is set back in a direction to be separated more distantly from the planar center of the opening portion 302 than the side faces 250 A and 270 A of the insulating layers 250 and 270 .
- the electronic component 310 is mounted on the upper face of the metal layer 242 exposed from the opening portion 302 , through an adhesive layer 312 .
- the insulating layer 280 is formed so as to fill the opening portion 302 and cover the entire surfaces of the step portions 303 and 304 .
- the insulating layer 280 is formed so as to cover the entire surface of the protrusion portion 265 of the metal layer 264 and the entire surface of the protrusion portion 375 of the metal layer 374 .
- the opening portion 302 is formed so as to penetrate the metal layers 264 and 374 and the insulating layers 250 , 270 and 380 in the thickness direction.
- the opening portion 302 can be formed to be deeper accordingly. Therefore, even when a high electronic component 310 is embedded, the opening portion 302 deep enough to receive the electronic component 310 therein can be formed easily.
- FIG. 35A is a plan view of the metal layer 242 , the insulating layer 250 , the metal layer 264 , the insulating layer 270 and the electronic component 310 , as seen from the upper face side of the insulating layer 270 .
- FIG. 35A is a plan view of the metal layer 242 , the insulating layer 250 , the metal layer 264 , the insulating layer 270 and the electronic component 310 , as seen from the upper face side of the insulating layer 270 .
- FIG. 35A is a plan view of the metal layer 242 , the insulating layer 250 , the metal layer 264 , the insulating layer 270 and the electronic component 310 , as seen from the upper face side of the insulating layer 270 .
- FIG. 35A is a plan view of the metal layer 242 , the insulating layer 250 , the metal layer 264 , the insulating layer 270 and the electronic component 310 , as seen from the upper face side of the
- 35B is a plan view of the metal layer 242 , the insulating layers 250 and 270 , the metal layer 374 , the insulating layer 380 and the electronic component 310 , as seen from the upper face side of the insulating layer 380 .
- the metal layer 264 has metal layers 266 each of which is shaped like a rectangle in plan view.
- the metal layers 266 are, for example, formed so as to surround the opening edge of the through hole 250 Y.
- the metal layer 374 has metal layers 376 each of which is shaped like a rectangle in plan view.
- the metal layers 376 are, for example, formed so as to surround the opening edge of the through hole 380 Y.
- a planar shape of the metal layers 266 and the metal layers 376 which are superimposed on each other in plan view is formed into a closed ring shape (a rectangular closed ring shape in this case) surrounding an opening edge of the opening portion 302 over the whole circumference. That is, the metal layers 264 and 374 in the present example are formed so that the planar shape of the two metal layers 264 and 374 which are superimposed on each other in plan view is formed into the closed ring shape surrounding the opening edge of the opening portion 302 over the whole circumference.
- the metal layers 266 and the metal layers 376 are formed to alternate each other in the circumferential direction of the opening portion 302 .
- each of the metal layers 266 is formed at a position not overlapping with any metal layer 374 in plan view.
- each of the metal layers 376 is formed at a position not overlapping with any metal layer 266 in plan view.
- the metal layers 266 and the metal layers 376 may have some portions overlapping with each other in plan view.
- the side face 265 A of each of the metal layers 266 constituting the inner side face of the opening portion 302 is provided at a position where the side face 265 A protrudes in a direction to be closer to the planar center of the opening portion 302 than each of the side faces 250 A and 270 A of the insulating layers 250 and 270 .
- step portions 303 each of which is constituted by the side face 250 A of the insulating layer 250 , the side face 265 A of the metal layer 266 , and the side face 270 A of the insulating layer 270 are formed in the inner side face of the opening portion 302 .
- the step portions 303 are formed at predetermined intervals in the circumferential direction of the opening portion 302 .
- the side face 375 A of each of the metal layers 376 constituting the inner side face of the opening portion 302 is provided at a position where the side face 375 A protrudes in a direction to be closer to the planar center of the opening portion 302 than each of the side faces 270 A and 380 A of the insulating layers 270 and 380 .
- step portions 304 each of which is constituted by the side face 270 A of the insulating layer 270 , the side face 375 A of the metal layer 376 , and the side face 380 A of the insulating layer 380 are formed in the inner side face of the opening portion 302 .
- the step portions 304 are formed at predetermined intervals in the circumferential direction of the opening portion 302 .
- the step portions 303 and 304 are formed so that, for example, the planar shape of the recesses 303 and 304 which are superimposed on each other in plan view is formed into a closed ring shape surrounding the opening portion 302 over the whole circumference.
- the step portions 303 and the step portions 304 are formed to alternate each other in the circumferential direction of the opening portion 302 .
- each of the step portions 303 is formed at a position not overlapping with any step portion 304 in plan view.
- each of the step portions 304 are formed at a position not overlapping with any step portion 303 in plan view.
- portions overlapping with the metal layers 376 in plan view are, for example, provided at positions where the portions of the side face 270 A protrude in a direction to be closer to the planar center of the opening portion 302 than the side face 380 A of the insulating layer 380 .
- the portions overlapping with the metal layers 376 in plan view are, for example, formed on the same plane as the side face 250 A of the insulating layer 250 .
- portions not overlapping with the metal layers 376 in plan view are, for example, formed on the same plane as the side face 380 A of the insulating layer 380 .
- the step portions 303 and the step portions 304 are formed so that the planar shape of the step portions 303 and 304 which are superimposed on each other in plan view is formed into a closed ring shape surrounding the opening portion 302 over the whole circumference.
- peeling of the insulating layer 280 can be stopped by one of the step portions 303 and 304 even when the peeling occurs at any position of the opening edge of the bottom of the opening portion 302 .
- step portions are formed in the inner side face of the opening portion 302 by the metal layers 264 and 374 .
- the degree of freedom for designing the planar shape of each of the metal layers 264 and 374 can be improved in comparison with when a step portion is formed in the inner side face of the opening portion 302 by one metal layer.
- the step portion 301 is formed over the whole circumference of the opening portion 300 .
- the present invention is not limited thereto.
- the step portion 301 may be formed at only a circumferential portion of the opening portion 300 .
- a stepwise step portion 306 may be formed in an inner side face of an opening portion 305 where an electronic component 310 is received.
- a through hole 250 Y of an insulating layer 250 a through hole 262 Y of a metal layer 260 and a through hole 270 Y of an insulating layer 270 communicate with one another to thereby constitute the opening portion 305 .
- the planar shape of the through hole 262 Y of the metal layer 262 is formed to be larger than the planar shape of the through hole 250 Y of the insulating layer 250 .
- the planar shape of the through hole 270 Y of the insulating layer 270 is formed to be larger than the planar shape of the through hole 262 Y of the metal layer 262 .
- a side face 262 A of the metal layer 262 is provided at a position where the side face 262 A is set back in a direction to be separated more distantly from the planar center of the opening portion 305 than a side face 250 A of the insulating layer 250 . Therefore, an upper face of the insulating layer 250 positioned in the vicinity of the side face 250 A of the insulating layer 250 is exposed from the metal layer 262 .
- a side face 270 A of the insulating layer 270 is provided at a position where the side face 270 A is set back in the direction to be separated more distantly from the planar center of the opening portion 305 than the side face 262 A of the metal layer 262 .
- the stepwise step portion 306 constituted by the side face 250 A of the insulating layer 250 , the upper face of the insulating layer 250 exposed from the metal layer 262 , the side face 262 A of the metal layer 262 , the upper face of the metal layer 262 exposed from the insulating layer 270 , and the side face 270 A of the insulating layer 270 is formed in the inner side face of the opening portion 305 .
- An insulating layer 280 in this case is formed to cover the entire surface of the stepwise step portion 306 .
- each of the through holes 50 Y, 62 Y and 70 Y or the through holes 250 Y, 262 Y and 270 Y constituting the opening portion 100 or 300 is substantially formed into a rectangular shape in sectional view. That is, the through hole 50 Y, 62 Y, 70 Y, 250 Y, 262 Y, 270 Y is formed so that an opening width of an upper side opening end and an opening width of a lower side opening end are substantially equal to each other.
- the present invention is not limited thereto.
- the through hole 50 Y, 62 Y, 70 Y, 250 Y, 262 Y, 270 Y may be formed into a taper shape whose opening width is reduced as it goes from an upper side toward a lower side.
- the structure of the wiring board 10 or 210 in each of the aforementioned embodiments is not limited particularly.
- the numbers, arrangement, etc. of wiring layers and insulating layers in a wiring structure formed on an upper face of the insulating layer 80 or 280 can be modified/changed variously.
- the numbers, arrangement, etc. of wiring layers and insulating layers in a wiring structure formed on a lower face of the insulating layer 30 or 230 can be modified/changed variously.
- a wiring layer may be formed on an upper face of the insulating layer 70 or 270 .
- the upper face and the side face of the wiring layer 20 , 90 , 220 , 290 in each of the aforementioned embodiments may be formed into roughened faces in a similar manner to or the same manner as the conductor layer 40 etc.
- the wiring layer 41 , 61 , 241 , 261 in the conductor layer 40 , 60 , 240 , 260 may be omitted.
- the solder resist layer 120 , 130 , 320 , 330 may be omitted.
- the wiring board 10 or 210 is embodied as a coreless board.
- the present invention is not limited thereto.
- the wiring board 10 or 210 may be embodied as a core-including build-up board having a core substrate.
- the number of the electronic components 110 embedded in the wiring board 10 or 210 in each of the aforementioned embodiments is not limited particularly.
- the electronic components embedded in the wiring board 10 or 210 are not limited to one kind. Any kinds of electronic components may be embedded in the wiring board 10 or 210 .
- the pad P 1 or P 11 is used as an external connection pad
- the pad P 2 or P 12 is used as an electronic component mounting pad.
- the present invention is not limited thereto.
- the pad P 1 or P 11 may be used as an electronic component mounting pad
- the pad P 2 or P 12 may be used as an external connection pad.
- one semiconductor chip 140 or 340 is mounted on the wiring board 10 or 210 .
- a plurality of semiconductor chips 140 or 340 may be mounted on the wiring board 10 or 210 .
- a logic chip and a memory chip may be mounted in combination on the wiring board 10 or 210 .
- a chip component such as a chip capacitor, a chip inductor or a chip resistor, or another electronic component such as a crystal resonator may be mounted on the wiring board 10 or 210 in place of the semiconductor chip 140 or 340 .
- a mounting form of the electronic component such as the semiconductor chip 140 or 340 , the chip component or the crystal resonator may be modified/changed variously.
- Examples of the mounting form of the electronic component include a flip-chip mounting form, a wire bonding mounting form, a solder mounting form or a mounting form using a combination of those mounting forms.
- the manufacturing method is embodied as a manufacturing method for obtaining a single piece (obtaining one piece).
- the manufacturing method may be embodied as a manufacturing method for obtaining a plurality of pieces.
- a method for manufacturing a wiring board comprising:
- the second through hole penetrating the second insulating layer in a thickness direction to communicate with the first through hole, the second through hole being different in size of planar shape from the first through hole, the third through hole penetrating the third insulating layer in the thickness direction to communicate with the first through hole, the third through hole being different in size of planar shape from the first through hole;
- the forming second through hole and the third through hole comprises:
- the forming second through hole and the third through hole comprises:
- filling insulating layer is formed so as to cover the entire surface of the roughened portion of the first metal layer.
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Abstract
Description
- This application claims priority from Japanese Patent Applications No. 2019-019431, filed on Feb. 6, 2019, the entire contents of which are herein incorporated by reference.
- The present disclosure relates to a wiring board.
- In the background art, there has been known a wiring board in which an electronic component such as a semiconductor chip or a chip capacitor is embedded (e.g. see JP-A-2016-039214). The electronic component is disposed in an opening portion formed in an interlayer insulating layer of the wiring board.
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FIG. 38 shows an electronic component embeddedtype wiring board 400 according to the background art. Thewiring board 400 has aninsulating layer 410, ametal layer 420, aninterlayer insulating layer 430, and anopening portion 440. Themetal layer 420 is formed on an upper face of theinsulating layer 410. Theinterlayer insulating layer 430 is formed on the upper face of theinsulating layer 410 so as to cover themetal layer 420. Theopening portion 440 penetrates theinterlayer insulating layer 430 in a thickness direction. Thewiring board 400 has anelectronic component 450, aninsulating layer 460 and awiring layer 470. Theelectronic component 450 is disposed inside theopening portion 440. With theinsulating layer 460, theopening portion 440 is filled and theelectronic component 450 is entirely covered. Thewiring layer 470 is electrically connected toelectrodes 451 of theelectronic component 450 and formed on an upper face of theinsulating layer 460. - However, tight adhesiveness between the
metal layer 420 which is exposed in the bottom of theopening portion 440 and theinsulating layer 460 with which theopening portion 440 is filled is not excellent in thewiring board 400. In addition, tight adhesiveness between theinterlayer insulating layer 430 which has theopening portion 440 and theinsulating layer 460 with which theopening portion 440 is filled is not excellent in thewiring board 400. Therefore, when, for example, a warp or thermal stress occurs in thewiring board 400, stress is concentrated on the vicinity of anopening edge 480 of the bottom of theopening portion 440 so that peeling is apt to occur at an interface between themetal layer 420 and theinsulating layer 460. When the peeling occurs at the interface between themetal layer 420 and theinsulating layer 460, the peeling may be propagated to an interface between theinterlayer insulating layer 430 and theinsulating layer 460, and thewiring layer 470 may be broken due to the propagated peeling. When thewiring layer 470 is broken, electric reliability of thewiring board 400 may be lowered. - Certain embodiment provides a wiring board.
- The wiring board comprises:
- a first insulating layer;
- a second insulating layer that is formed on an upper face of the first insulating layer;
- a first metal layer that is formed on an upper face of the second insulating layer;
- a third insulating layer that is formed on the upper face of the second insulating layer so as to cover the first metal layer;
- an opening portion that penetrates at least the second insulating layer, the first metal layer and the third insulating layer in a thickness direction of the wiring board;
- an electronic component that is provided in the opening portion;
- a filling insulating layer that fills the opening portion and covers the electronic component and
- a wiring layer that is formed on an upper face of the filling insulating layer.
- A first step portion is formed by a side face of the second insulating layer constituting an inner side face of the opening portion and a side face of the first metal layer constituting the inner side face of the opening portion.
-
FIG. 1A is a schematic sectional view (a sectional view taken along a line 1-1 inFIG. 2 ) showing a wiring board according to a first embodiment; -
FIG. 1B is an enlarged sectional view showing the wiring board according to the first embodiment; -
FIG. 2 is a schematic plan view showing the wiring board according to the first embodiment; -
FIG. 3 is a schematic perspective view showing the wiring board according to the first embodiment; -
FIG. 4 is a schematic sectional view showing a semiconductor device according to the first embodiment; -
FIGS. 5A to 5C are schematic sectional views showing a method for manufacturing the wiring board according to the first embodiment; -
FIGS. 6A and 6B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 7A and 7B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 8A and 8B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 9A and 9B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 10A and 10B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 11A and 11B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIGS. 12A and 12B are schematic sectional views showing the method for manufacturing the wiring board according to the first embodiment; -
FIG. 13 is a schematic sectional view showing the method for manufacturing the wiring board according to the first embodiment; -
FIG. 14 is a schematic sectional view showing a method for manufacturing the semiconductor device according to the first embodiment; -
FIG. 15 is a schematic sectional view showing a wiring board according to a modification; -
FIGS. 16A and 16B are schematic plan views showing the wiring board according to the modification; -
FIG. 17 is a schematic perspective view showing the wiring board according to the modification; -
FIG. 18 is a schematic sectional view showing a wiring board according to another modification; -
FIGS. 19A and 19B are schematic sectional views showing a method for manufacturing the wiring board according to the other modification; -
FIGS. 20A and 20B are schematic sectional views showing the method for manufacturing the wiring board according to the other modification; -
FIG. 21A is a schematic sectional view (a sectional view taken along a line 21 a-21 a inFIG. 22 ) showing a wiring board according to a second embodiment; -
FIG. 21B is an enlarged sectional view showing the wiring board according to the second embodiment; -
FIG. 22 is a schematic plan view showing the wiring board according to the second embodiment; -
FIG. 23 is a schematic perspective view showing the wiring board according to the second embodiment; -
FIG. 24 is a schematic sectional view showing a semiconductor device according to the second embodiment; -
FIGS. 25A to 25C are schematic sectional views showing a method for manufacturing the wiring board according to the second embodiment; -
FIGS. 26A and 26B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 27A and 27B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 28A and 28B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 29A and 29B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 30A and 30B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 31A and 31B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIGS. 32A and 32B are schematic sectional views showing the method for manufacturing the wiring board according to the second embodiment; -
FIG. 33 is a schematic sectional view showing a method for manufacturing the semiconductor device according to the second embodiment; -
FIG. 34 is a schematic sectional view showing a wiring board according to a modification; -
FIGS. 35A and 35B are schematic plan views showing the wiring board according to the modification; -
FIG. 36 is a schematic perspective view showing the wiring board according to the modification, -
FIG. 37 is a schematic sectional view showing a wiring board according to another modification; and -
FIG. 38 is a schematic sectional view showing a wiring board according to the background art. - Embodiments will be described below with reference to the accompanying drawings. Incidentally, some of the accompanying drawings show characteristic portions in an enlarged manner for convenience in order to make the characteristics easy to understand. Therefore, constituent elements do not always have the same dimensional ratios etc. as real ones. In addition, in sectional views, in order to make sectional structures of members easy to understand, some of the members are illustrated by a satin pattern rather than by hatching while others are illustrated without hatching. Incidentally, in the description of the present invention, the term “plan view” means a view of a subject seen from a vertical direction (an up/down direction in the drawings) of
FIG. 1 etc., and the term “planar shape” means a shape of the subject viewed from the vertical direction ofFIG. 1 etc. - A first embodiment will be described below in accordance with
FIG. 1A toFIG. 14 . - As shown in
FIG. 1A , awiring board 10 has a structure in which awiring layer 20, an insulatinglayer 30, aconductor layer 40, an insulatinglayer 50, aconductor layer 60, an insulatinglayer 70, an insulatinglayer 80, and awiring layer 90 are formed sequentially. Thewiring board 10 in the present example has a form of a so-called “coreless board” which is free from any support substrate unlike a wiring board which is manufactured by a general build-up method, i.e. a wiring board in which a required number of build-up layers are formed sequentially on each or one of opposite faces of a core substrate serving as a support substrate. - The
wiring board 10 has one or more electronic components 110 (oneelectronic component 110 inFIG. 1A ) disposed in anopening portion 100 formed in the plurality of insulatinglayers layer 120 formed on a lower face of the insulatinglayer 30, and a solder resistlayer 130 formed on an upper face of the insulatinglayer 80. Thewiring board 10 is a wiring board in which theelectronic component 110 is embedded. - Here, for example, cupper (Cu) or a copper alloy can be used as the material of the wiring layers 20 and 90 and the conductor layers 40 and 60. For example, any of insulating resins such as an epoxy resin and a polyimide resin or any of resin materials in which fillers made of silica, alumina, etc., are mixed with these resins can be used as the material of the insulating
layers layers layers - The
wiring layer 20 is an outermost (lowermost in this case) wiring layer of thewiring board 10. A lower face of thewiring layer 20 is exposed from the insulatinglayer 30. The lower face of thewiring layer 20 in the present example is formed to be substantially flush with the lower face of the insulatinglayer 30. Incidentally, the lower face of thewiring layer 20 may be formed to be recessed on theconductor layer 40 side relatively to the lower face of the insulatinglayer 30. The thickness of thewiring layer 20 can be, for example, set in a range of about 10 to 30 μm. - The insulating
layer 30 is formed so as to cover an upper face and a side face of thewiring layer 20 and expose the lower face of thewiring layer 20. A throughhole 30X penetrating the insulatinglayer 30 in a thickness direction so as to expose a portion of the upper face of thewiring layer 20 is formed at a predetermined place in the insulatinglayer 30. The throughhole 30X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from an upper side (theconductor layer 40 side) toward a lower side (thewiring layer 20 side) inFIG. 1A . For example, the throughhole 30X is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. Incidentally, a thickness between the upper face of thewiring layer 20 and an upper face of the insulatinglayer 30 can be, for example, set in a range of about 10 to 35 μm. - The
conductor layer 40 is formed on the upper face of the insulatinglayer 30. The thickness of theconductor layer 40 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 40 are, for example, roughened faces. The upper face and the side face of theconductor layer 40 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 40. The surface roughness of theconductor layer 40 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. Here, the surface roughness Ra value is one kind of numerical value, which expresses the surface roughness and which is called arithmetical average roughness. Specifically, the surface roughness Ra value is an arithmetic average of absolute values measured as a height varying within a measurement region from the surface which is an average line. - The
conductor layer 40 has, for example, awiring layer 41 and ametal layer 42. Thewiring layer 41 and themetal layer 42 are formed separately from each other to be electrically insulated from each other. Thewiring layer 41 and themetal layer 42 are formed on one and the same plane. - The
wiring layer 41 is, for example, electrically connected to thewiring layer 20 through a via wiring filled in the throughhole 30X. Thewiring layer 41 is, for example, formed integrally with the via wiring filled in the throughhole 30X. - The
metal layer 42 is, for example, formed in a mount region where theelectronic component 110 is mounted. Themetal layer 42 is, for example, formed at a position overlapping with theelectronic component 110 in plan view. Themetal layer 42 is, for example, formed at a position overlapping with theopening portion 100 in plan view. The planar shape of themetal layer 42 is, for example, formed to be larger than the planar shape of theopening portion 100. An outer circumferential edge of themetal layer 42 is, for example, formed so as to surround an opening edge of theopening portion 100 from the outside in plan view. Themetal layer 42 is, for example, formed into a rectangular shape in plan view. Themetal layer 42 in the present example is, for example, a metal layer which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. Themetal layer 42 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When themetal layer 42 is the wiring pattern, the power source wiring or the ground wiring, themetal layer 42 is, for example, electrically connected to another wiring layer or another conductor layer through a via wiring etc. - The insulating
layer 50 is formed on the upper face of the insulatinglayer 30 so as to cover theconductor layer 40. Incidentally, a thickness between the upper face of theconductor layer 40 and an upper face of the insulatinglayer 50 can be, for example, set in a range of about 40 to 100 μm. - A through
hole 50X penetrating the insulatinglayer 50 in the thickness direction so as to expose a portion of the upper face of the conductor layer 40 (thewiring layer 41 in this case) is formed at a predetermined place in the insulatinglayer 50. The throughhole 50X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (theconductor layer 60 side) toward the lower side (theconductor layer 40 side) inFIG. 1A . The throughhole 50X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. - The
conductor layer 60 is formed on the upper face of the insulatinglayer 50. The thickness of theconductor layer 60 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 60 are, for example, roughened faces. The upper face and the side face of theconductor layer 60 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 60. The surface roughness of theconductor layer 60 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. - The
conductor layer 60 has, for example, awiring layer 61 and ametal layer 62. Thewiring layer 61 and themetal layer 62 are formed separately from each other to be electrically insulated from each other. Thewiring layer 61 and themetal layer 62 are formed on one and the same plane. - The
wiring layer 61 is, for example, electrically connected to thewiring layer 41 through a via wiring filled in the throughhole 50X. Thewiring layer 61 is, for example, formed integrally with the via wiring filled in the throughhole 50X. - The
metal layer 62 is, for example, formed so as to surround the mount region where theelectronic component 110 is mounted. Themetal layer 62 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. Themetal layer 62 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When themetal layer 62 is the wiring pattern, the power source wiring or the ground wiring, for example, themetal layer 62 is electrically connected to another wiring layer or another conductor layer through a via wiring etc. - The insulating
layer 70 is formed on the upper face of the insulatinglayer 50 so as to cover theconductor layer 60. Incidentally, a thickness between the upper face of theconductor layer 60 and an upper face of the insulatinglayer 70 can be, for example, set in a range of about 40 to 100 μm. - The
opening portion 100 is, for example, formed so as to penetrate the insulatinglayer 50, themetal layer 62 and the insulatinglayer 70 in the thickness direction. Theopening portion 100 is, for example, formed so as to expose a portion of an upper face of themetal layer 42. Theopening portion 100 is formed correspondingly to theelectronic component 110 embedded in theopening portion 100. - The
opening portion 100 in the present example is constituted by a throughhole 50Y, a throughhole 62Y and a throughhole 70Y. The throughhole 50Y penetrates the insulatinglayer 50 in the thickness direction. The throughhole 62Y penetrates themetal layer 62 in the thickness direction. The throughhole 70Y penetrates the insulatinglayer 70 in the thickness direction. - As shown in
FIG. 2 , each of the throughholes holes hole 50Y, a central axis of the throughhole 62Y and a central axis of the throughhole 70Y align with one another in plan view. Each of the planar shapes of the throughholes electronic component 110. The planar shape of the throughhole metal layer 42. - The through
hole 62Y is, for example, formed to be larger in planar shape than each of the throughholes metal layer 62 is, for example, formed so as to surround opening edges of the throughholes metal layer 62 is, for example, formed into a ring shape (frame shape) in plan view. Themetal layer 62 in the present example is formed into a rectangular closed ring shape to continuously surround the opening edge of each of the throughholes - Incidentally,
FIG. 2 is a plan view in which thewiring board 10 shown inFIG. 1A is seen from top. InFIG. 2 , the insulatinglayer 80, thewiring layer 90, the solder resistlayer 130, etc. are drawn in perspective. - As shown in
FIG. 1B andFIG. 3 , aside face 62A of themetal layer 62 constituting an inner side face of the opening portion 100 (the throughhole 62Y) is provided at a position where the side face 62A is set back (separated) inward of the insulatinglayer 50 from aside face 50A of the insulatinglayer 50 constituting the inner side face of the opening portion 100 (the throughhole 50Y). Theside face 62A of themetal layer 62 is provided at a position where the side face 62A is set back inward of the insulatinglayer 70 from aside face 70A of the insulatinglayer 70 constituting the inner side face of the opening portion 100 (the throughhole 70Y). That is, theside face 62A of themetal layer 62 is provided at the position where the side face 62A is set back in a direction to be separated more distantly from a planar center of theopening portion 100 than the side faces 50A and 70A of the insulatinglayers side face 62A of themetal layer 62 is, for example, formed so as to be set back from the side faces 50A and 70A of the insulatinglayers opening portion 100. The upper face of the insulatinglayer 50 positioned in the vicinity of theside face 50A of the insulatinglayer 50 is exposed from themetal layer 62. In addition, a lower face of the insulatinglayer 70 positioned in the vicinity of theside face 70A of the insulatinglayer 70 is exposed from themetal layer 62. Thus, arecess 101 constituted by theside face 50A of the insulatinglayer 50, the upper face of the insulatinglayer 50 exposed from themetal layer 62, theside face 62A of themetal layer 62, the lower face of the insulatinglayer 70 exposed from themetal layer 62, and theside face 70A of the insulatinglayer 70 is formed in the inner side face of theopening portion 100. In other words, a step portion constituted by therecess 101 is formed in the inner side face of theopening portion 100. Therecess 101 is, for example, formed continuously over the whole circumference of theopening portion 100. - As shown in
FIG. 2 , the throughhole 50Y of the insulatinglayer 50 is, for example, formed to be smaller in planar shape than the throughhole 70Y of the insulatinglayer 70. That is, the throughhole 50Y has the smallest planar shape among the throughholes hole 50Y can be, for example, set in a range of about 0.7 mm×0.4 mm to 15 mm×15 mm in plan view. - As shown in
FIG. 1B , theside face 70A of the insulatinglayer 70 is provided at a position where the side face 70A is set back in the direction to be separated more distantly from the planar center of theopening portion 100 than theside face 50A of the insulatinglayer 50. For example, theside face 70A of the insulatinglayer 70 is formed so as to be set back from theside face 50A of the insulatinglayer 50 over the whole circumference of theopening portion 100. - A
recess 42X recessed on the insulatinglayer 30 side is formed in the upper face of themetal layer 42 exposed in the bottom of the opening portion 100 (specifically, the bottom of the throughhole 50Y). A bottom face and an inner side face of therecess 42X are, for example, roughened faces. Surface roughness of the bottom face of therecess 42X is, for example, formed to be larger than surface roughness of the upper face of themetal layer 42 covered with the insulatinglayer 50. In other words, the surface roughness of the upper face of themetal layer 42 exposed in the bottom of theopening portion 100 is formed to be larger than the surface roughness of the upper face of themetal layer 42 covered with the insulatinglayer 50. - As shown in
FIG. 1A , theelectronic component 110 is mounted on (adhesively bonded to) the upper face of the metal layer 42 (specifically, the bottom face of therecess 42X) exposed from theopening portion 100 through anadhesive layer 112. That is, theelectronic component 110 is disposed inside theopening portion 100. Theadhesive layer 112 is formed on the upper face of themetal layer 42. For example, an epoxy-based, polyimide-based or silicone-based thermosetting adhesive agent can be used as the material of theadhesive layer 112. - For example, an active component such as a semiconductor chip, a transistor or a diode or a passive component such as a chip capacitor, a chip inductor or a chip resistor can be used as the
electronic component 110. For example, a component made of silicon or a component made of ceramic can be used as theelectronic component 110. Theelectronic component 110 according to the present embodiment is a semiconductor chip. For example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip. In addition, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip or a flash memory chip can be used as the semiconductor chip. - The
electronic component 110 can be, for example, made of a semiconductor substrate. For example, silicon etc. can be used as the material of the semiconductor substrate.Electrode terminals 111 are provided on, of theelectronic component 110, a circuit formation face 110A where a semiconductor integrated circuit (not shown) is formed. Theelectrode terminals 111 are, for example, metal posts each formed in the shape of a column extending upward from thecircuit formation face 110A. For example, copper or a copper alloy can be used as the material of theelectrode terminals 111. - The
electronic component 110 is bonded to the upper face of themetal layer 42 by theadhesive layer 112 in a state in which a back face (a lower face in this case) of theelectronic component 110 opposite to the circuit formation face 110A is opposed to the upper face of themetal layer 42, i.e. faces up. Upper faces of theelectrode terminals 111 are, for example, formed on the same plane as the upper face of the insulatinglayer 70 or formed to be lower than the upper face of the insulatinglayer 70. - The insulating
layer 80 is formed so as to fill theopening portion 100 and entirely cover theelectronic component 110. The insulatinglayer 80 is, for example, formed so as to cover an entire side face of theadhesive layer 112, an entire side face of theelectronic component 110, the entirecircuit formation face 110A exposed from theelectrode terminals 111, and the upper faces and side faces of theelectrode terminals 111. The insulatinglayer 80 is, for example, formed so as to cover the surface of themetal layer 42 exposed from theadhesive layer 112 inside theopening portion 100. The insulatinglayer 80 is, for example, formed so as to fill theopening portion 100 and therecess 101 formed in the inner side face of theopening portion 100. - As shown in
FIG. 1B , the insulatinglayer 80 is formed so as to cover theentire side face 50A of the insulatinglayer 50, the entire upper face of the insulatinglayer 50 exposed from themetal layer 62, theentire side face 62A of themetal layer 62, the entire lower face of the insulatinglayer 70 exposed from themetal layer 62, and theentire side face 70A of the insulatinglayer 70. The insulatinglayer 80 is, for example, formed to bite into the lower face of the insulatinglayer 70 exposed by therecess 101. - As shown in
FIG. 1A , the insulatinglayer 80 is, for example, formed so as to cover the entire upper face of the insulatinglayer 70. A throughhole 80X penetrating the insulatinglayers wiring layer 61 in this case) is formed at a required place in the insulatinglayers hole 80Y penetrating the insulatinglayer 80 in the thickness direction so as to expose a portion of the upper face of each of theelectrode terminals 111 is formed at a required place in the insulatinglayer 80. Each of the throughholes wiring layer 90 side) toward the lower side (thewiring layer 61 side or theelectrode terminal 111 side) inFIG. 1A . For example, the throughhole - The
wiring layer 90 is formed on the upper face of the insulatinglayer 80. Thewiring layer 90 is, for example, an outermost (uppermost in this case) wiring layer of thewiring board 10. Thewiring layer 90 has a wiring layer electrically connected to thewiring layer 61 through a via wiring filled in the throughhole 80X. Thewiring layer 90 has a wiring layer electrically connected to theelectrode terminal 111 through a via wiring filled in the throughhole 80Y. Thewiring layer 90 is formed integrally with the via wiring filled in the throughhole 80X or the throughhole 80Y. The thickness of thewiring layer 90 can be, for example, set in a range of about 10 to 30 μm. - The solder resist
layer 120 is formed on the lower face of the outermost (lowermost in this case) insulatinglayer 30 so as to cover thelowermost wiring layer 20. For example, an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resistlayer 120. The thickness of the solder resistlayer 120 can be, for example, set in a range of about 10 to 30 μm. - An
opening portion 120X for exposing at least a portion of the lower face of thelowermost wiring layer 20 as a pad P1 is formed in the solder resistlayer 120. For example, an external connection terminal such as a solder ball or a lead pin, which is used when thewiring board 10 is mounted on a mount board such as a motherboard is connected to the pad P1. That is, the pad P1 in the present example functions as an external connection pad. - Incidentally, a surface treatment layer may be formed on a lower face of the pad P1 if occasions demand. A gold (Au) layer, a nickel (Ni) layer/Au layer (a metal layer in which the Ni layer and the Au layer are formed in the named order), an Ni layer/palladium (Pd) layer/Au layer (a metal layer in which the Ni layer, the Pd layer and the Au layer are formed in the named order), etc. can be listed as examples of the surface treatment layer. Here, the Au layer is a metal layer made of Au or an Au alloy. The Ni layer is a metal layer made of Ni or an Ni alloy. The Pd layer is a metal layer made of Pd or a Pd alloy. For example, a metal layer (an electroless plating metal layer) formed by an electroless plating method can be used as each of the Ni layer, the Au layer and the Pd layer. In addition, an OSP (Organic Solderability Preservative) film formed by applying antioxidation treatment such as OSP treatment to the surface of the pad P1 can be used as another example of the surface treatment layer. An organic coating of an azole compound, an imidazole compound, or the like, can be used as the OSP film. Incidentally, the
wiring layer 20 per se exposed from theopening portion 120X (or the surface treatment layer in the case where the surface treatment layer is formed on the wiring layer 20) may be set as the external connection terminal. - The solder resist
layer 130 is formed on the upper face of the outermost (uppermost in this case) insulatinglayer 80 so as to cover theuppermost wiring layer 90. For example, an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resistlayer 130. The thickness of the solder resistlayer 130 can be, for example, set in a range of about 10 to 30 μm. - An
opening portion 130X is formed in the solder resistlayer 130 in order to expose at least a portion of theuppermost wiring layer 90 as a pad P2. The pad P2 functions, for example, as an electronic component mounting pad in order to be electrically connected to an electronic component such as a semiconductor chip. - Incidentally, a surface treatment layer may be formed on the surface (an upper face and a side face or only an upper face) of the pad P2 if occasions demand. Metal layers such as an Au layer, an Ni layer/Au layer and an Ni layer/Pd layer/Au layer and an OSP film can be used as examples of the surface treatment layer.
- Next, the structure of a
semiconductor device 11 will be described in accordance withFIG. 4 . Thesemiconductor device 11 has thewiring board 10, one or more semiconductor chips 140 (onesemiconductor chip 140 inFIG. 4 ), and anunderfill resin 150. Thesemiconductor chip 140 is flip-chip mounted on thewiring board 10. That is, abump 141 disposed and provided on a circuit formation face (a lower face in this case) of thesemiconductor chip 140 is bonded to the pad P2 of thewiring board 10. Thus, thesemiconductor chip 140 is electrically connected to the pad P2 (the wiring layer 90) through thebump 141. - For example, a logic chip such as a CPU chip or a GPU chip, or a memory chip such as a DRAM chip, an SRAM chip or a flash memory chip can be used as the
semiconductor chip 140. Incidentally, when a plurality ofsemiconductor chips 140 are mounted on thewiring board 10, the logic chip and the memory chip may be configured in combination and mounted on thewiring board 10. - For example, a gold bump or a solder bump can be used as the
bump 141. For example, an alloy containing lead (Pb), a tin (Sn)—Au alloy, an Sn—Cu alloy, an Sn—Ag alloy, an Sn—silver (Ag)—Cu alloy, or the like, can be used as the material of the solder bump. - The
underfill resin 150 is provided to fill a gap between thewiring board 10 and thesemiconductor chip 140. For example, an insulating resin such as an epoxy resin can be used as the material of theunderfill resin 150. - Next, a method for manufacturing the
wiring board 10 will be described. Incidentally, portions to be final constituent elements of thewiring board 10 will be designated by signs of the final constituent elements for convenience of explanation in the description. - First, a
support substrate 160 is prepared, as shown inFIG. 5A . For example, a plate-like material high in rigidity, such as silicon, glass or metal (such as copper) can be used as the material of thesupport substrate 160. For example, a metal plate or a metal foil sheet can be used as thesupport substrate 160. A copper foil sheet in which an ultrathin copper foil sheet about 2 to 5 μm thick is pasted to a support body copper foil sheet, which is about 35 to 70 μm thick, through a peeling layer is used as thesupport substrate 160 in the present example. - Next, a
metal film 161 covering an entire upper face of thesupport substrate 160 is formed on the upper face of thesupport substrate 160. For example, themetal film 161 is formed on an upper face of the ultrathin copper foil sheet of thesupport substrate 160. Themetal film 161 can be, for example, formed by a sputtering method, a vapor deposition method or an electrolytic plating method. For example, an electrically conductive material serving as a stopper layer when thesupport substrate 160 is etched and removed can be used as the material of themetal film 161. In addition, for example, an electrically conductive material which can be selectively etched and removed from a wiring layer 20 (e.g. a Cu layer) which will be formed by a subsequent step can be used as the material of themetal film 161. For example, a metal such as nickel (Ni), titanium (Ti), chromium (Cr), tin, cobalt (Co), iron (Fe) or palladium or an alloy containing at least one metal selected from the aforementioned metals can be used as the material of such ametal film 161. Ni is used as the material of themetal film 161 in the present example. The thickness of themetal film 161 can be, for example, set in a range of about 0.1 to 1.0 μm. - Successively, the
wiring layer 20 is formed on an upper face of themetal film 161. Thewiring layer 20 can be, for example, formed by a semi-additive method. Specifically, first, a resist pattern (not shown) having an opening portion corresponding to the shape of thewiring layer 20 is formed on the upper face of themetal film 161. Successively, by an electrolytic copper plating method using thesupport substrate 160 and themetal film 161 as power feed layers, a copper plating coating is deposited on the upper face of themetal film 161 exposed from the opening portion of the resist pattern. Then, the resist pattern is removed. In this manner, thewiring layer 20 can be formed on themetal film 161. Incidentally, any of various wiring formation methods such as a subtractive method other than the semi-additive method can be also used as the method for forming thewiring layer 20. - Next, an insulating
layer 30 having a throughhole 30X exposing a portion of an upper face of thewiring layer 20 is formed on the upper face of themetal film 161 in a step shown inFIG. 5B . When, for example, a resin film is used as the insulatinglayer 30, the resin film is laminated on the upper face of themetal film 161 by thermocompression bonding, and the resin film is patterned by a photolithographic method in order to form the insulatinglayer 30. Alternatively, a liquid or paste-like insulating resin may be applied to the upper face of themetal film 161 by a spin coating method etc., and the insulating resin may be patterned by a photolithographic method in order to form the insulatinglayer 30. - Next, a via wiring filled in the through
hole 30X is formed, and aconductor layer 40 is formed on an upper face of the insulatinglayer 30, for example, by a semi-additive method, in a step shown inFIG. 5C . Theconductor layer 40 has awiring layer 41 and ametal layer 42. Thewiring layer 41 is electrically connected to thewiring layer 20 through the via wiring filled in the throughhole 30X. Themetal layer 42 is formed in a mount region of an electronic component 110 (seeFIG. 1A ). - Successively, roughening treatment is applied to the
conductor layer 40 in a step shown inFIG. 6A . An entire upper face and an entire side face of theconductor layer 40 are formed into roughened faces by the roughening treatment. For example, blackening treatment, etching treatment, plating, blast treatment, or the like, can be performed as the roughening treatment. - Next, an insulating
layer 50 having a throughhole 50X exposing a portion of an upper face of thewiring layer 41 is formed on the upper face of the insulatinglayer 30 in a similar manner to or the same manner as the step shown inFIG. 5B , in a step shown inFIG. 6B . On this occasion, the insulatinglayer 50 is formed so as to cover an entire upper face and an entire side face of themetal layer 42. - Next, a via wiring filled in the through
hole 50X is formed, and aconductor layer 60 is formed on an upper face of the insulatinglayer 50, for example, by a semi-additive method, in a step shown inFIG. 7A . Theconductor layer 60 has awiring layer 61 and ametal layer 62. Thewiring layer 61 is electrically connected to thewiring layer 41 through the via wiring filled in the throughhole 50X. Themetal layer 62 has a throughhole 62Y. On this occasion, the planar shape of the throughhole 62Y is formed to be smaller than the planar shape of themetal layer 42. - Successively, roughening treatment is applied to the
conductor layer 60. By the roughening treatment, an entire upper face and an entire side face of theconductor layer 60 are formed into roughened faces. For example, blackening treatment, etching treatment, plating, blast treatment, or the like, can be performed as the roughening treatment. - Next, an insulating
layer 70 covering thewiring layer 61 and themetal layer 62 is formed on the upper face of the insulatinglayer 50 in a similar manner to or the same manner as the step shown inFIG. 5B , in a step shown inFIG. 7B . On this occasion, the insulatinglayer 70 is formed so as to cover an entire upper face and an entire side face of themetal layer 62. The insulatinglayer 70 is formed so as to fill the throughhole 62Y. - Next, in a step shown in
FIG. 8A , a throughhole 70Y penetrating the insulatinglayer 70 in a thickness direction is formed and a throughhole 50Y penetrating the insulatinglayer 50 in the thickness direction is formed, so that a portion of themetal layer 42 corresponding to the mount region of the electronic component 110 (seeFIG. 1A ) is exposed from the throughholes holes - In the present step, the planar shape of the through
hole 70Y is formed to be one size larger than the planar shape of the throughhole 62Y of themetal layer 62. Therefore, a portion of the upper face of themetal layer 62 in the vicinity of the opening edge of the throughhole 70Y is exposed from the insulatinglayer 70. On this occasion, themetal layer 62 exposed from the insulatinglayer 70 functions as a mask and a stopper layer during the laser machining. Therefore, the throughhole 50Y penetrating the insulatinglayer 50 in the thickness direction is formed in the insulatinglayer 50 exposed from the throughhole 62Y of themetal layer 62. Thus, the planar shape of the throughhole 50Y is formed into a size substantially equal to the planar shape of the throughhole 62Y. In the present step, themetal layer 42 functions as a stopper layer during the laser machining. - By the present step, the through
hole 50Y, the throughhole 62Y and the throughhole 70Y are formed to communicate with one another so that anopening portion 100 penetrating the insulatinglayer 50, themetal layer 62 and the insulatinglayer 70 in the thickness direction is formed. The portion of the upper face of themetal layer 42 is exposed from theopening portion 100. - Successively, resin smear adhering to the exposed face of the
metal layer 42 exposed in the bottom of the opening portion 100 (specifically, the bottom of the throughhole 50Y) is removed by desmear treatment in a step shown inFIG. 8B . By the desmear treatment, portions of the insulatinglayers opening portion 100 are removed. Therefore, side faces 50A and 70A of the insulatinglayers opening portion 100 are set back in a direction to be separated more distantly from the planar center of theopening portion 100. Thus, a portion of a lower face of themetal layer 62 is exposed from the insulatinglayer 50. - Next, in a step shown in
FIG. 9A , a portion of themetal layer 62 is removed so as to make the planar shape of the throughhole 62Y of themetal layer 62 larger than each of the planar shapes of the throughholes metal layer 62 can be, for example, removed by isotropic etching using the insulatinglayer 70 as an etching mask. By the isotropic etching, first, themetal layer 62 exposed from the insulatinglayer 70 is etched and removed. Successively, by the isotropic etching, themetal layer 62 covered with the insulatinglayer 70 is also removed due to a side etch phenomenon in which the etching proceeds in an in-plane direction of themetal layer 62. Thus, aside face 62A of themetal layer 62 constituting the inner side face of theopening portion 100 is set back in a direction to be separated more distantly from the planar center of theopening portion 100 than each of side faces 50A and 70A of the insulatinglayers recess 101 constituted by theside face 62A of themetal layer 62 and the side faces 50A and 70A of the insulatinglayers opening portion 100. In other words, a step portion made up of therecess 101 is formed in the inner side face of theopening portion 100 in the present step. - In the present step, the
metal layer 42 is also etched and removed at the same time when themetal layer 62 is etched and removed. By the etching removal, arecess 42X recessed on the insulatinglayer 30 side is formed in the upper face of themetal layer 42 exposed from the insulatinglayer 50. Further, surface roughness of a bottom face of therecess 42X is larger than that prior to the etching treatment. Therefore, the surface roughness of the bottom face of therecess 42X is larger than surface roughness of the upper face of themetal layer 42 covered with the insulatinglayer 50. - Next, in a step shown in
FIG. 9B , anadhesive layer 112 is formed on the upper face of themetal layer 42 exposed from theopening portion 100. Theadhesive layer 112 can be, for example, formed by applying a liquid resin or a paste-like resin which will be theadhesive layer 112, to the upper face of themetal layer 42. Incidentally, for example, an adhesive agent made of an epoxy-based resin is used as theadhesive layer 112. In addition, the resin agent in A-stage is used as theadhesive layer 112 in the present step. Incidentally, the resin agent in B-stage may be used as theadhesive layer 112 in the present step. - Successively, in a step shown in
FIG. 10A , theelectronic component 110 is mounted on theadhesive layer 112 inside theopening portion 100 by use of a mounter. On this occasion, theelectronic component 110 is fixed on theadhesive layer 112 in a face-up state. - Next, in a step shown in
FIG. 10B , an insulatinglayer 80 with which theopening portion 100 and therecess 101 are filled is formed. The insulatinglayer 80 is formed so as to cover the entire surface of theelectronic component 110 not in contact with theadhesive layer 112. The insulatinglayer 80 is formed so as to cover an entire upper face of the insulatinglayer 70. On this occasion, upper faces ofelectrode terminals 111 of theelectronic component 110 are formed either on the same plane as the upper face of the insulatinglayer 70 or to be lower than the upper face of the insulatinglayer 70. Accordingly, an upper face of the insulatinglayer 80 can be formed flatly. - Next, in a step shown in
FIG. 11A , a throughhole 80X penetrating the insulatinglayers layers holes 80Y are formed at required places in the insulatinglayer 80. The throughholes - Successively, in a step shown in
FIG. 11B , via wirings with which the throughholes wiring layer 90 electrically connected to thewiring layer 61 or theelectrode terminals 111 through the via wirings is formed on the upper face of the insulatinglayer 80, for example, by a semi-additive method. - Next, in a step shown in
FIG. 12A , a solder resistlayer 130 having anopening portion 130X is formed on the upper face of the insulatinglayer 80. The solder resistlayer 130 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape. By the present step, thewiring layer 90 exposed from theopening portion 130X is a pad P2. Incidentally, for example, a metal layer (i.e. a surface treatment layer) in which an Ni layer and an Au layer are formed in the named order may be formed on the pad P2 if occasions demand. The metal layer can be, for example, formed by an electroless plating method. - Successively, the
support substrate 160 is removed. For example, the support body copper foil sheet of thesupport substrate 160 is mechanically peeled from the ultrathin copper foil sheet. On this occasion, the peeling layer is interposed between the support body copper foil sheet and the ultrathin copper foil sheet. Since an adhesive force between the support body copper foil sheet and the ultrathin copper foil sheet is weak, the support body copper foil sheet can be easily peeled from the ultrathin copper foil sheet. Then, the ultrathin copper foil sheet remaining on themetal film 161 is, for example, removed by wet etching using an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. On this occasion, themetal film 161 functions as a stopper layer when the ultrathin copper foil sheet of thesupport substrate 160 is etched. - Successively, the
metal film 161 is removed by etching. When, for example, Ni is used as the material of themetal film 161, themetal film 161 is selectively etched and removed from the wiring layer 20 (the Cu layer) by wet etching using a hydrogen peroxide/nitric acid-based solution. On this occasion, thewiring layer 20 and the insulatinglayer 30 function as stopper layers when themetal film 161 is etched. By the present step, a lower face of thewiring layer 20 and a lower face of the insulatinglayer 30 are exposed to the outside, as shown inFIG. 12B . On this occasion, the lower face of thewiring layer 20 and the lower face of the insulatinglayer 30 which are in contact with an upper face of the metal film 161 (seeFIG. 12A ) are formed into a shape extending along the upper face (a flat face in this case) of themetal film 161. Therefore, the lower face of thewiring layer 20 and the lower face of the insulatinglayer 30 are formed to be substantially flush with each other. - Next, in a step shown in
FIG. 13 , a solder resistlayer 120 having anopening portion 120X is formed on the lower face of the insulatinglayer 30 in a similar manner to or the same manner as the step shown inFIG. 12A . Thus, thewiring layer 20 exposed from theopening portion 120X serves as a pad P1. Incidentally, for example, a metal layer (i.e. a surface treatment layer) in which an Ni layer and an Au layer are formed in the named order may be formed on the pad P1 if occasions demand. The metal layer can be, for example, formed by an electroless plating method. - By the aforementioned manufacturing process, the
wiring board 10 shown inFIGS. 1A and 1B can be manufactured. Incidentally, thewiring board 10 can be used in a reversed state or can be disposed at any angle. - Next, a method for manufacturing a
semiconductor device 11 will be described. - First, a
semiconductor chip 140 having abump 141 formed on a circuit formation face of thesemiconductor chip 140 is prepared in a step shown inFIG. 14 . Successively, thebump 141 of thesemiconductor chip 140 is flip-chip bonded onto the pad P2 of thewiring board 10. For example, when thebump 141 is a solder bump, reflow treatment is performed after thebump 141 and the pad P2 are aligned with each other. As a result, the bump 141 (the solder bump) is melted so that thebump 141 is electrically connected to the pad P2. - Successively, an underfill resin 150 (see
FIG. 4 ) is formed between an upper face of thewiring board 10 and a lower face of thesemiconductor chip 140. - The
semiconductor device 11 shown inFIG. 4 can be manufactured by the aforementioned manufacturing process. - Next, operations and effects of the present embodiment will be described.
- (1) The step portion constituted by the
side face 50A of the insulatinglayer 50 and theside face 62A of themetal layer 62 is formed in the inner side face of theopening portion 100 where theelectronic component 110 is received. In the configuration, the step portion is also formed in an interface between the inner side face of theopening portion 100 and the insulatinglayer 80 with which theopening portion 100 is filled. Peeling of the insulatinglayer 80 propagated to the interface between the insulatinglayer 50 and the insulatinglayer 80 can be stopped by the step portion. To give detailed description, stress is apt to be concentrated on the vicinity of an opening edge of the bottom of theopening portion 100 when a warp or thermal stress occurs in thewiring board 10. Therefore, the peeling of the insulatinglayer 80 may occur at the interface between themetal layer 42 and the insulatinglayer 80 in the vicinity of the opening edge of the bottom of theopening portion 100. When the peeling occurs at the interface between themetal layer 42 and the insulatinglayer 80, the peeling may be propagated to the interface between the inner side face of theopening portion 100 and the insulatinglayer 80. On this occasion, due to the step portion formed in the inner side face of theopening portion 100 in thewiring board 10 according to the present embodiment, the peeling of the insulatinglayer 80 can be stopped at the step portion. Thus, the peeling of the insulatinglayer 80 can be stopped halfway in the depth direction of theopening portion 100. Accordingly, thewiring layer 90 formed on the upper face of the insulatinglayer 80 can be suitably suppressed from being broken due to the peeling of the insulatinglayer 80. As a result, lowering of electrical reliability of thewiring board 10 can be suitably suppressed. - (2) The
recess 101 constituted by theside face 50A of the insulatinglayer 50, the upper face of the insulatinglayer 50 exposed from themetal layer 62, theside face 62A of themetal layer 62, the lower face of the insulatinglayer 70 exposed from themetal layer 62, and theside face 70A of the insulatinglayer 70 is formed in the inner side face of theopening portion 100. That is, theside face 62A of themetal layer 62 is set back from the side faces 50A and 70A of the insulatinglayers recess 101 is formed. The step portion is constituted by therecess 101. Further, the insulatinglayer 80 is formed so as to fill therecess 101. Thus, a portion of the insulating layer 80 (specifically, the insulatinglayer 80 with which therecess 101 is filled) is formed to bite into the lower face of the insulatinglayer 70. Therefore, tight adhesiveness between the insulatinglayer 70 and the insulatinglayer 80 can be improved due to an anchor effect. - (3) The
recess 101 is formed into a closed ring shape so as to surround theopening portion 100 over the whole circumference in plan view. In other words, therecess 101 is formed to entirely surround theelectronic component 110 in plan view. According to the configuration, peeling of the insulatinglayer 80 can be stopped by therecess 101 even when the peeling occurred at any position of the opening edge of the bottom of theopening portion 100. - Incidentally, the aforementioned first embodiment may be changed suitably and carried out in the following modes. The aforementioned first embodiment and the following modifications can be combined with each other and carried out within a range in which the first embodiment and the modifications are not technically contradictory to each other.
- In the aforementioned first embodiment, the
opening portion 100 is constituted by two insulatinglayers metal layer 62. However, the numbers of the insulating layers and the metal layers constituting theopening portion 100 are not limited particularly. - An
opening portion 102 where anelectronic component 110 is received may be constituted by three insulatinglayers metal layers wiring board 10A shown inFIG. 15 . The structure of thewiring board 10A will be described below. Incidentally, the same members as the aforementioned members shown inFIG. 1A toFIG. 14 are referred to by the same signs respectively and correspondingly, and detailed description about respective elements of the members will be omitted. - For example, a
conductor layer 60 has awiring layer 61 and themetal layer 63. Thewiring layer 61 and themetal layer 63 are formed separately from each other to be electrically insulated from each other. Themetal layer 63 is, for example, formed so as to surround a mount region where theelectronic component 110 is mounted. - The insulating
layer 70 is formed on an upper face of the insulatinglayer 50 so as to cover theconductor layer 60. A throughhole 70X penetrating the insulatinglayer 70 in a thickness direction to expose a portion of an upper face of the conductor layer 60 (thewiring layer 61 in this case) is formed at a required place in the insulatinglayer 70. The throughhole 70X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. - A
conductor layer 170 is formed on an upper face of the insulatinglayer 70. The thickness of theconductor layer 170 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 170 are, for example, roughened faces. The upper face and the side face of theconductor layer 170 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 170. The surface roughness of theconductor layer 170 can, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. - For example, the
conductor layer 170 has awiring layer 171 and themetal layer 173. Thewiring layer 171 and themetal layer 173 are formed separately from each other to be electrically insulated from each other. - The
wiring layer 171 is, for example, electrically connected to thewiring layer 61 through a via wiring filled in the throughhole 70X. Thewiring layer 171 is, for example, formed integrally with the via wiring filled in the throughhole 70X. Themetal layer 173 is, for example, formed so as to surround the mount region where theelectronic component 110 is mounted. - Each of the metal layers 63 and 173 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. For example, the
metal layer - The insulating
layer 180 is formed on the upper face of the insulatinglayer 70 so as to cover theconductor layer 170. Incidentally, a thickness between the upper face of theconductor layer 170 and an upper face of the insulatinglayer 180 can be, for example, set in a range of about 40 to 100 μm. - The
opening portion 102 is, for example, formed so as to penetrate the insulatinglayer 50, themetal layer 63, the insulatinglayer 70, themetal layer 173 and the insulatinglayer 180 in the thickness direction. Theopening portion 102 is, for example, formed so as to expose a portion of an upper face of ametal layer 42. Theopening portion 102 is formed correspondingly to theelectronic component 110 embedded in theopening portion 102. - The
opening portion 102 in the present example is constituted by a throughhole 50Y of the insulatinglayer 50, a throughhole 63Y, a throughhole 70Y of the insulatinglayer 70, a throughhole 173Y and a throughhole 180Y which communicate with one another. The throughhole 63Y penetrates themetal layer 63 in the thickness direction. The throughhole 173Y penetrates themetal layer 173 in the thickness direction. The throughhole 180Y penetrates the insulatinglayer 180 in the thickness direction. - The planar shape of each of the through
holes holes holes electronic component 110, and formed to be smaller than the planar shape of themetal layer 42. - The through
hole hole metal layer hole metal layer hole - A
side face 63A of themetal layer 63 constituting an inner side face of the opening portion 102 (the throughhole 63Y) is provided at a position where the side face 63A is set back in a direction to be separately more distantly from the planar center of theopening portion 102 than aside face layer recess 103 constituted by theside face 50A of the insulatinglayer 50, the upper face of the insulatinglayer 50 exposed from themetal layer 63, theside face 63A of themetal layer 63, the lower face of the insulatinglayer 70 exposed from themetal layer 63, and theside face 70A of the insulatinglayer 70 is formed in the inner side face of theopening portion 102. - A
side face 173A of themetal layer 173 constituting the inner side face of the opening portion 102 (the throughhole 173Y) is provided at a position where the side face 173A is set back inward of the insulatinglayer 70 from theside face 70A of the insulatinglayer 70. Theside face 173A of themetal layer 173 is provided at a position where the side face 173A is set back inward of the insulatinglayer 180 from aside face 180A of the insulatinglayer 180 constituting the inner side face of the opening portion 102 (the throughhole 180Y). That is, theside face 173A of themetal layer 173 is provided at the position where the side face 173A is set back in the direction to be separated more distantly from the planar center of theopening portion 102 than the side face 70A, 180A of the insulatinglayer recess 104 constituted by theside face 70A of the insulatinglayer 70, the upper face of the insulatinglayer 70 exposed from themetal layer 173, theside face 173A of themetal layer 173, a lower face of the insulatinglayer 180 exposed from themetal layer 173, and theside face 180A of the insulatinglayer 180 is formed in the inner side face of theopening portion 102. Thus, a first step portion constituted by therecess 103 and a second step portion constituted by therecess 104 are formed in the inner side face of theopening portion 102. - The
electronic component 101 is mounted on the upper face of themetal layer 42 exposed from theopening portion 102, through anadhesive layer 112. The insulatinglayer 80 is formed so as to fill theopening portion 102, therecess 103 and therecess 104. - According to the aforementioned configuration, the
opening portion 102 is formed so as to penetrate the metal layers 63 and 173 and the insulatinglayers layers opening portion 102 can be formed to be deeper accordingly. Therefore, even when a highelectronic component 110 is embedded, theopening portion 102 deep enough to receive theelectronic component 110 therein can be formed easily. - When the
opening portion 102 is formed to penetrate two ormore metal layers FIG. 15 , structures shown inFIGS. 16A and 16B andFIG. 17 can be also used as therespective metal layers FIG. 16A is a plan view of themetal layer 42, the insulatinglayer 50, themetal layer 63, the insulatinglayer 70 and theelectronic component 110, as seen from the upper face side of the insulatinglayer 70. In addition,FIG. 16B is a plan view of themetal layer 42, the insulatinglayers metal layer 173, the insulatinglayer 180 and theelectronic component 110, as seen from the upper face side of the insulatinglayer 180. - As shown in
FIG. 16A , themetal layer 63 hasmetal layers 64 each of which is shaped like a rectangle in plan view. The metal layers 64 are, for example, formed so as to surround the opening edges of the throughholes - As shown in
FIG. 16B , themetal layer 173 hasmetal layers 174 each of which is shaped like a rectangle in plan view. The metal layers 174 are, for example, formed so as to surround the opening edge of the throughhole 180Y. A planar shape of the metal layers 64 and the metal layers 174 which are superimposed on each other in plan view is formed into a closed ring shape (a rectangular closed ring shape in this case) surrounding the opening edge of the opening portion 102 (the throughholes metal layers opening portion 102 over the whole circumference. - As shown in
FIGS. 16A and 16B andFIG. 17 , the metal layers 64 and the metal layers 174 are formed to alternate each other in the circumferential direction of theopening portion 102. For example, each of the metal layers 64 is formed at a position not overlapping with anymetal layer 174 in plan view. In a similar manner or the same manner, each of the metal layers 174 is formed at a position not overlapping with anymetal layer 64 in plan view. Incidentally, the metal layers 64 and the metal layers 174 may have some portions overlapping with each other in plan view. - As shown in
FIG. 17 , theside face 63A of each of the metal layers 64 constituting the inner side face of theopening portion 102 is provided at a position where the side face 63A is set back in a direction to be separated more distantly from the planar center of theopening portion 102 than each of the side faces 50A and 70A of the insulatinglayers side face 50A of the insulatinglayer 50, theside face 63A of themetal layer 64 and theside face 70A of the insulatinglayer 70 are formed in the inner side face of theopening portion 102. Therecesses 103 are formed at predetermined intervals in the circumferential direction of theopening portion 102. - The
side face 173A of each of the metal layers 174 constituting the inner side face of theopening portion 102 is provided at a position where the side face 173A is set back in the direction to be separated more distantly from the planar center of theopening portion 102 than each of the side faces 70A and 180A of the insulatinglayers side face 70A of the insulatinglayer 70, theside face 173A of themetal layer 174 and theside face 180A of the insulatinglayer 180 are formed in the inner side face of theopening portion 102. Therecesses 104 are formed at predetermined intervals in the circumferential direction of theopening portion 102. - The
recesses recesses opening portion 102 over the whole circumference. Therecesses 103 and therecesses 104 are formed to alternate each other in the circumferential direction of theopening portion 102. For example, each of therecesses 103 is formed at a position not overlapping with anyrecess 104 in plan view. In a similar manner or the same manner, each of therecesses 104 is formed at a position not overlapping with anyrecess 103 in plan view. - In the aforementioned configuration, the
recesses recesses 103 and therecesses 104 which are superimposed on each other in plan view is formed into a closed ring shape surrounding theopening portion 102 over the whole circumference. In other words, the combination of therecesses 103 and therecesses 104 is formed so as to entirely surround theelectronic component 110 in plan view. Thus, peeling of the insulatinglayer 80 can be stopped by one of therecesses opening portion 102. - In addition, kinds of step portions are formed in the inner side face of the
opening portion 102 by the metal layers 63 and 173. In this manner, the degree of freedom for designing the planar shape of each of the metal layers 63 and 173 can be improved in comparison with when a step portion is formed in the inner side face of theopening portion 102 by one metal layer. - In the aforementioned embodiment, the
electronic component 110 is mounted on the upper face of themetal layer 42 exposed from theopening portion 100. However, the present invention is not limited thereto. Theelectronic component 110 may be mounted on the upper face of the insulatinglayer 30 exposed from theopening portion 100, for example, as in a wiring board 10B shown inFIG. 18 . For example, theelectronic component 110 is bonded to the upper face of the insulatinglayer 30 exposed from theopening portion 100 in a face-up state by theadhesive layer 112. A throughhole 42Y penetrating themetal layer 42 in the thickness direction is formed in themetal layer 42 in this case. Theopening portion 100 in the present example is constituted by the throughhole 42Y of themetal layer 42, the throughhole 50Y of the insulatinglayer 50, the throughhole 62Y of themetal layer 62 and the throughhole 70Y of the insulatinglayer 70 which communicate with one another. That is, theopening portion 100 in the present example is formed so as to penetrate themetal layer 42, the insulatinglayer 50, themetal layer 62 and the insulatinglayer 70 in the thickness direction. - The through
hole 42Y is, for example, formed to be larger in planar shape than each of the throughholes metal layer 42 is, for example, formed so as to surround the opening edge of the throughhole metal layer 42 is, for example, formed into a ring shape. The planar shape of themetal layer 42 in the present example is formed into a closed ring shape continuously surrounding the opening edge of the throughhole - The
side face 42A of themetal layer 42 constituting the inner side face of the opening portion 100 (the thoughhole 42Y) is provided at a position where the side face 42A is set back in a direction to be separated more distantly from the planar center of theopening portion 100 than theside face 50A of the insulatinglayer 50. For example, theside face 42A of themetal layer 42 is formed so as to be set back from theside face 50A of the insulatinglayer 50 over the whole circumference of theopening portion 100. A recess 105 (a step portion) constituted by theside face 42A of themetal layer 42, the lower face of the insulatinglayer 50 exposed from themetal layer 42, and theside face 50A of the insulatinglayer 50 is formed in the inner side face of theopening portion 100. - The through
hole 62Y in the present example is, for example, formed to be larger in planar shape than the throughhole 42Y. That is, theside face 62A of themetal layer 62 is provided at a position where the side face 62A is set back in the direction to be separated more distantly from the planar center of theopening portion 100 than theside face 42A of themetal layer 42. In other words, a distance between theside face 42A of themetal layer 42 constituting the inner side face of theopening portion 100 and theside face 50A of the insulatinglayer 50 constituting the inner side face of theopening portion 100 is shorter than a distance between theside face 62A of themetal layer 62 constituting the inner side face of theopening portion 100 and theside face 50A of the insulatinglayer 50 constituting the inner side face of theopening portion 100. - In the aforementioned configuration, the
opening portion 100 is formed so as to penetrate themetal layer 42 in the thickness direction. Accordingly, theopening portion 100 can be formed to be deeper by the thickness of themetal layer 42. Therefore, even when a highelectronic component 110 is embedded, theopening portion 100 deep enough to receive theelectronic component 110 can be formed easily. - Next, a method for manufacturing the wiring board 10B will be described. First, steps similar to or the same as the steps shown in
FIG. 5A toFIG. 8A are carried out so as to form a structure body shown inFIG. 19A . That is, in the structure body shown inFIG. 19A , a throughhole 50Y of an insulatinglayer 50, a throughhole 62Y of ametal layer 62 and a throughhole 70Y of an insulatinglayer 70 are made to communicate with one another so that anopening portion 100 penetrating the insulatinglayer 50, themetal layer 62 and the insulatinglayer 70 in a thickness direction is formed. - Successively, in a step shown in
FIG. 19B , a portion of themetal layer 62 is removed so as to make the planar shape of the throughhole 62Y larger than the planar shape of each of the throughholes hole 42Y penetrating ametal layer 42 in the thickness direction is formed. The removal of themetal layer 62 and the formation of the throughhole 42Y can be, for example, performed by isotropic etching using the insulatinglayer 70 as an etching mask. By the isotropic etching, first, themetal layer 62 exposed from the insulatinglayer 70 is etched and removed, and themetal layer 42 exposed from the insulatinglayers layers opening portion 100 than side faces 50A and 70A of the insulatinglayers 50 and the 70. As a result, arecess 101 or arecess 105 is formed in an inner side face of theopening portion 100 by theside face 42A of themetal layer 42 and theside face 50A of the insulatinglayer 50 or by theside face 62A of themetal layer 62 and theside face 70A of the insulatinglayer 70. In other words, in the present step, a two-step portion constituted by therecesses opening portion 100. - Next, in a step shown in
FIG. 20A , anadhesive layer 112 is formed on an upper face of an insulatinglayer 30 exposed from theopening portion 100 in a similar manner to or the same manner as the step shown inFIG. 9B . Successively, anelectronic component 110 is mounted on theadhesive layer 112 inside theopening portion 100 by use of a mounter in a similar manner to or the same manner as the step shown inFIG. 10A . Next, an insulatinglayer 80 with which theopening portion 100 and therecesses FIG. 10B . - Next, steps similar to or the same as the steps shown in
FIG. 11A toFIG. 12A are carried out. Thus, a structure body shown inFIG. 20B can be obtained. Then, steps similar to or the same as the steps shown inFIG. 12B andFIG. 13 are carried out. Thus, the wiring board 10B in the present modification can be manufactured. - In the aforementioned first embodiment, the
recess 101 is formed over the whole circumference of theopening portion 100. However, the present invention is not limited thereto. For example, therecess 101 may be formed in only a circumferential portion of theopening portion 100. - A second embodiment will be described below in accordance with
FIG. 21A toFIG. 33 . As shown inFIG. 21A , awiring board 210 has a structure in which awiring layer 220, an insulatinglayer 230, aconductor layer 240, an insulatinglayer 250, aconductor layer 260, an insulatinglayer 270, an insulatinglayer 280, and awiring layer 290 are formed sequentially. Thewiring board 210 in the present example has a form of a so-called “coreless board” which is support substrate-free and different from a wiring board which is manufactured by a general build-up method, i.e. a wiring board in which a required number of build-up layers are formed sequentially on each or one of opposite faces of a core substrate serving as a support substrate. - The
wiring board 210 has one or more electronic components 310 (oneelectronic component 310 inFIG. 21A ) disposed inside anopening portion 300 formed in the plurality of insulatinglayers layer 320 formed on a lower face of the insulatinglayer 230, and a solder resistlayer 330 formed on an upper face of the insulatinglayer 280. Thewiring board 210 is a wiring board in which theelectronic component 310 is embedded. - Here, for example, cupper (Cu) or a copper alloy can be used as the material of the wiring layers 220 and 290 and the conductor layers 240 and 260. For example, any of insulating resins such as an epoxy resin and a polyimide resin or any of resin materials in which fillers made of silica, alumina, etc., are mixed with these resins can be used as the material of the insulating
layers layers layers - The
wiring layer 220 is an outermost (lowermost in this case) wiring layer of thewiring board 210. A lower face of thewiring layer 220 is exposed from the insulatinglayer 230. The lower face of thewiring layer 220 in the present example is formed to be substantially flush with the lower face of the insulatinglayer 230. Incidentally, the lower face of thewiring layer 220 may be formed to be recessed on theconductor layer 240 side relatively to the lower face of the insulatinglayer 230. The thickness of thewiring layer 220 can be, for example, set in a range of about 10 to 30 Gm. - The insulating
layer 230 is formed so as to cover an upper face and a side face of thewiring layer 220 and expose the lower face of thewiring layer 220. A throughhole 230X penetrating the insulatinglayer 230 in a thickness direction so as to expose a portion of the upper face of thewiring layer 220 is formed at a predetermined place in the insulatinglayer 230. The throughhole 230X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from an upper side (theconductor layer 240 side) toward a lower side (thewiring layer 220 side) inFIG. 21A . For example, the throughhole 230X is formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. Incidentally, a thickness between the upper face of thewiring layer 220 and an upper face of the insulatinglayer 230 can be, for example, set in a range of about 10 to 35 μm. - The
conductor layer 240 is formed on the upper face of the insulatinglayer 230. The thickness of theconductor layer 240 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 240 are, for example, roughened faces. The upper face and the side face of theconductor layer 240 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 240. The surface roughness of theconductor layer 240 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. Here, the surface roughness Ra value is one kind of numerical value, which expresses the surface roughness and which is called arithmetical average roughness. Specifically, the surface roughness Ra value is an arithmetic average of absolute values measured as a height varying within a measurement region from the surface which is an average line. - The
conductor layer 240 has, for example, awiring layer 241 and ametal layer 242. Thewiring layer 241 and themetal layer 242 are formed separately from each other to be electrically insulated from each other. Thewiring layer 241 and themetal layer 242 are formed on one and the same plane. - The
wiring layer 241 is, for example, electrically connected to thewiring layer 220 through a via wiring filled in the throughhole 230X. Thewiring layer 241 is, for example, formed integrally with the via wiring filled in the throughhole 230X. - The
metal layer 242 is, for example, formed in a mount region where theelectronic component 310 is mounted. Themetal layer 242 is, for example, formed at a position overlapping with theelectronic component 310 in plan view. Themetal layer 242 is, for example, formed at a position overlapping with theopening portion 300 in plan view. The planar shape of themetal layer 242 is, for example, formed to be larger than the planar shape of theopening portion 300. An outer circumferential edge of themetal layer 242 is, for example, formed so as to surround an opening edge of theopening portion 300 from the outside in plan view. Themetal layer 242 is, for example, formed into a rectangular shape in plan view. Themetal layer 242 in the present example is, for example, a metal layer which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. Themetal layer 242 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When themetal layer 242 is the wiring pattern, the power source wiring or the ground wiring, themetal layer 242 is, for example, electrically connected to another wiring layer or another conductor layer through a via wiring etc. - The insulating
layer 250 is formed on the upper face of the insulatinglayer 230 so as to cover theconductor layer 240. Incidentally, a thickness between the upper face of theconductor layer 240 and an upper face of the insulatinglayer 250 can be, for example, set in a range of about 40 to 100 μm. - A through
hole 250X penetrating the insulatinglayer 250 in the thickness direction so as to expose a portion of the upper face of the conductor layer 240 (thewiring layer 241 in this case) is formed at a predetermined place in the insulatinglayer 250. The throughhole 250X is, for example, formed into a taper shape in which an opening width (an opening diameter) is reduced as it goes from the upper side (theconductor layer 260 side) toward the lower side (theconductor layer 240 side) inFIG. 21A . The throughhole 250X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. - The
conductor layer 260 is formed on the upper face of the insulatinglayer 250. The thickness of theconductor layer 260 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 260 are, for example, roughened faces. The upper face and the side face of theconductor layer 260 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 260. The surface roughness of theconductor layer 260 can be, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. - The
conductor layer 260 has, for example, awiring layer 261 and ametal layer 262. Thewiring layer 261 and themetal layer 262 are formed separately from each other to be electrically insulated from each other. Thewiring layer 261 and themetal layer 262 are formed on one and the same plane. - The
wiring layer 261 is, for example, electrically connected to thewiring layer 241 through a via wiring filled in the throughhole 250X. Thewiring layer 261 is, for example, formed integrally with the via wiring filled in the throughhole 250X. - The
metal layer 262 is, for example, formed so as to surround the mount region where theelectronic component 310 is mounted. Themetal layer 262 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. Themetal layer 262 may be, for example, a wiring pattern for drawing a wiring or may be a power source wiring or a ground wiring. When themetal layer 262 is the wiring pattern, the power source wiring or the ground wiring, for example, themetal layer 262 is electrically connected to another wiring layer or another conductor layer through a via wiring etc. - The insulating
layer 270 is formed on the upper face of the insulatinglayer 250 so as to cover theconductor layer 260. Incidentally, a thickness between the upper face of theconductor layer 260 and an upper face of the insulatinglayer 270 can be, for example, set in a range of about 40 to 100 μm. - The
opening portion 300 is, for example, formed so as to penetrate the insulatinglayer 250, themetal layer 262 and the insulatinglayer 270 in the thickness direction. Theopening portion 300 is, for example, formed so as to expose a portion of an upper face of themetal layer 242. Theopening portion 300 is formed correspondingly to theelectronic component 310 embedded in theopening portion 300. - The
opening portion 300 in the present example is constituted by a throughhole 250Y, a throughhole 262Y and a throughhole 270Y. The throughhole 250Y penetrates the insulatinglayer 250 in the thickness direction. The throughhole 262Y penetrates themetal layer 262 in the thickness direction. The throughhole 270Y penetrates the insulatinglayer 270 in the thickness direction. - As shown in
FIG. 22 , each of the throughholes holes hole 250Y, a central axis of the throughhole 262Y and a central axis of the throughhole 270Y align with one another in plan view. Each of the planar shapes of the throughholes electronic component 310. The planar shape of the throughhole metal layer 242. - The through
hole 262Y is, for example, formed to be smaller in planar shape than each of the throughholes hole 262Y has a smallest planar shape among the throughholes hole 262Y can be, for example, set in a range of about 0.7 mm×0.7 mm to 15 mm×15 mm in plan view. - The
metal layer 262 is, for example, formed so as to surround opening edges of the throughholes metal layer 262 is, for example, formed into a ring shape (frame shape) in plan view. Themetal layer 262 in the present example is formed into a rectangular closed ring shape in plan view to continuously surround the opening edge of each of the throughholes - Incidentally,
FIG. 22 is a plan view in which thewiring board 210 shown inFIG. 21A is seen from top. InFIG. 22 , the insulatinglayer 280, thewiring layer 290 and the solder resistlayer 330, etc. are drawn in perspective. - As shown in
FIG. 21B andFIG. 23 , themetal layer 262 has aprotrusion portion 263 protruding into the inside of theopening portion 300 from aside face 250A of the insulatinglayer 250 constituting an inner side face of the opening portion 300 (the throughhole 250Y). Aside face 263A of theprotrusion portion 263 is provided at a position where the side face 263A protrudes in a direction to be closer to the planar center of theopening portion 300 than theside face 250A of the insulatinglayer 250. Theside face 263A of theprotrusion portion 263 is provided at a position where the side face 263A protrudes in the direction to be closer to the planar center of theopening portion 300 than aside face 270A of the insulatinglayer 270 constituting the inner side face of the opening portion 300 (the throughhole 270Y). For example, theprotrusion portion 263 is formed continuously over the whole circumference of theopening portion 300. An upper face and a lower face of theprotrusion portion 263 are exposed from the insulatinglayers convex step portion 301 constituted by theside face 250A of the insulatinglayer 250, the lower face of theprotrusion portion 263, theside face 263A of theprotrusion portion 263, the upper face of theprotrusion portion 263 and theside face 270A of the insulatinglayer 270 is formed in the inner side face of theopening portion 300. Thestep portion 301 is, for example, formed continuously over the whole circumference of theopening portion 300. - The surface of the
metal layer 262 exposed from the insulatinglayers 250 and 270 (i.e. the upper face, the lower face and the side face of the protrusion portion 263) is, for example, a roughened face. The upper face and the side face of theprotrusion portion 263 are, for example, formed to be larger in surface roughness than an upper face of themetal layer 262 covered with the insulatinglayer 270. - As shown in
FIG. 22 , the throughhole 250Y of the insulatinglayer 250 is, for example, formed to be smaller in planar shape than the throughhole 270Y of the insulatinglayer 270. - As shown in
FIG. 21B , theside face 270A of the insulatinglayer 270 is, for example, provided at a position where the side face 270A is set back in a direction to be separated more distantly from the planar center of theopening portion 300 than theside face 250A of the insulatinglayer 250. For example, theside face 270A of the insulatinglayer 270 is formed so as to be set back from theside face 250A of the insulatinglayer 250 over the whole circumference of theopening portion 300. - A
recess 242X recessed on the insulatinglayer 230 side is formed in the upper face of themetal layer 242 exposed in the bottom of the opening portion 300 (specifically, the bottom of the throughhole 250Y). A bottom face and an inner side face of therecess 242X are, for example, roughened faces. Surface roughness of the bottom face of therecess 242X is, for example, formed to be larger than surface roughness of the upper face of themetal layer 242 covered with the insulatinglayer 250. In other words, the surface roughness of the upper face of themetal layer 242 exposed in the bottom of theopening portion 300 is formed to be larger than the surface roughness of the upper face of themetal layer 242 covered with the insulatinglayer 250. - As shown in
FIG. 21A , theelectronic component 310 is mounted on (adhesively bonded to) the upper face of the metal layer 242 (specifically, the bottom face of therecess 242X) exposed from theopening portion 300 through anadhesive layer 312. That is, theelectronic component 310 is disposed inside theopening portion 300. Theadhesive layer 312 is formed on the upper face of themetal layer 242. For example, an epoxy-based, polyimide-based or silicone-based thermosetting adhesive agent can be used as the material of theadhesive layer 312. - For example, an active component such as a semiconductor chip, a transistor or a diode or a passive component such as a chip capacitor, a chip inductor or a chip resistor can be used as the
electronic component 310. For example, a component made of silicon or a component made of ceramic can be used as theelectronic component 310. Theelectronic component 310 according to the present embodiment is a semiconductor chip. For example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip. In addition, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip or a flash memory chip can be used as the semiconductor chip. - The
electronic component 310 can be, for example, made of a semiconductor substrate. For example, silicon etc. can be used as the material of the semiconductor substrate.Electrode terminals 311 are provided on, of theelectronic component 310, a circuit formation face 310A where a semiconductor integrated circuit (not shown) is formed. Theelectrode terminals 311 are, for example, metal posts each formed in the shape of a column extending upward from thecircuit formation face 310A. For example, copper or a copper alloy can be used as the material of theelectrode terminals 311. - The
electronic component 310 is bonded to the upper face of themetal layer 242 by theadhesive layer 312 in a state in which a back face (a lower face in this case) of theelectronic component 310 opposite to the circuit formation face 310A is opposed to the upper face of the metal layer 242 (i.e. faces-up state). Upper faces of theelectrode terminals 311 are, for example, formed on the same plane as the upper face of the insulatinglayer 270 or formed to be lower than the upper face of the insulatinglayer 270. - The insulating
layer 280 is formed so as to fill theopening portion 300 and entirely cover theelectronic component 310. The insulatinglayer 280 is, for example, formed so as to cover an entire side face of theadhesive layer 312, an entire side face of theelectronic component 310, the entirecircuit formation face 310A exposed from theelectrode terminals 311, and the upper faces and side faces of theelectrode terminals 311. The insulatinglayer 280 is, for example, formed so as to cover the surface of themetal layer 242 exposed from theadhesive layer 312 inside theopening portion 300. - As shown in
FIG. 21B , the insulatinglayer 280 is formed so as to cover theentire side face 250A of the insulatinglayer 250, the entire lower face of theprotrusion portion 263 of themetal layer 262, theentire side face 263A of theprotrusion portion 263, the entire upper face of theprotrusion portion 263, and theentire side face 270A of the insulatinglayer 270. Thus, the insulatinglayer 280 is, for example, formed so as to cover the entire surface (the lower face, the upper face and the side face) of theprotrusion portion 263. In other words, theprotrusion portion 263 is formed so as to bite into the insulatinglayer 280. - As shown in
FIG. 21A , the insulatinglayer 280 is, for example, formed so as to cover the entire upper face of the insulatinglayer 270. A throughhole 280X penetrating the insulatinglayers wiring layer 261 in this case) is formed at a required place in the insulatinglayers hole 280Y penetrating the insulatinglayer 280 in the thickness direction so as to expose a portion of the upper face of each of theelectrode terminals 311 is formed at a required place in the insulatinglayer 280. Each of the throughholes wiring layer 290 side) toward the lower side (thewiring layer 261 side or theelectrode terminal 311 side) inFIG. 21A . For example, the throughhole - The
wiring layer 290 is formed on the upper face of the insulatinglayer 280. Thewiring layer 290 is, for example, an outermost (uppermost in this case) wiring layer of thewiring board 210. Thewiring layer 290 has a wiring layer electrically connected to thewiring layer 261 through a via wiring filled in the throughhole 280X. Thewiring layer 290 has a wiring layer electrically connected to theelectrode terminal 311 through a via wiring filled in the throughhole 280Y. Thewiring layer 290 is formed integrally with the via wiring filled in the throughhole 280X or the throughhole 280Y. The thickness of thewiring layer 290 can be, for example, set in a range of about 10 to 30 μm. - The solder resist
layer 320 is formed on the lower face of the outermost (lowermost in this case) insulatinglayer 230 so as to cover thelowermost wiring layer 220. For example, an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resistlayer 320. The thickness of the solder resistlayer 320 can be, for example, set in a range of about 10 to 30 μm. - An
opening portion 320X serving for exposing at least a portion of the lower face of thelowermost wiring layer 220 as a pad P11 is formed in the solder resistlayer 320. For example, an external connection terminal such as a solder ball or a lead pin, which is used when thewiring board 210 is mounted on a mount board such as a motherboard is connected to the pad P11. That is, the pad P11 in the present example functions as an external connection pad. - Incidentally, a surface treatment layer may be formed on a lower face of the pad P11 if occasions demand. A gold (Au) layer, a nickel (Ni) layer/Au layer (a metal layer in which the Ni layer and the Au layer are formed in the named order), an Ni layer/palladium (Pd) layer/Au layer (a metal layer in which the Ni layer, the Pd layer and the Au layer are formed in the named order), etc. can be listed as examples of the surface treatment layer. Here, the Au layer is a metal layer made of Au or an Au alloy. The Ni layer is a metal layer made of Ni or an Ni alloy. The Pd layer is a metal layer made of Pd or a Pd alloy. For example, a metal layer (an electroless plating metal layer) formed by an electroless plating method can be used as each of the Ni layer, the Au layer and the Pd layer. In addition, an OSP (Organic Solderability Preservative) film formed by applying antioxidation treatment such as OSP treatment to the surface of the pad P11 can be used as another example of the surface treatment layer. An organic coating of an azole compound, an imidazole compound, or the like, can be used as the OSP film. Incidentally, the
wiring layer 220 per se exposed from theopening portion 320X (or the surface treatment layer in the case where the surface treatment layer is formed on the wiring layer 220) may be set as the external connection terminal. - The solder resist
layer 330 is formed on the upper face of the outermost (uppermost in this case) insulatinglayer 280 so as to cover theuppermost wiring layer 290. For example, an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resistlayer 330. The thickness of the solder resistlayer 330 can be, for example, set in a range of about 10 to 30 μm. - An
opening portion 330X serving for exposing at least a portion of theuppermost wiring layer 290 as a pad P12 is formed in the solder resistlayer 330. The pad P12 functions, for example, as an electronic component mounting pad in order to be electrically connected to an electronic component such as a semiconductor chip. - Incidentally, a surface treatment layer may be formed on the surface (an upper face and a side face or only an upper face) of the pad P12 if occasions demand. Metal layers such as an Au layer, an Ni layer/Au layer and an Ni layer/Pd layer/Au layer and an OSP film can be used as examples of the surface treatment layer.
- Next, the structure of a
semiconductor device 211 will be described in accordance withFIG. 24 . Thesemiconductor device 211 has thewiring board 210, one or more semiconductor chips 340 (onesemiconductor chip 340 inFIG. 24 ), and anunderfill resin 350. Thesemiconductor chip 340 is flip-chip mounted on thewiring board 210. That is, abump 341 provided and disposed on a circuit formation face (a lower face in this case) of thesemiconductor chip 340 is bonded to the pad P12 of thewiring board 210. Thus, thesemiconductor chip 340 is electrically connected to the pad P12 (the wiring layer 290) through thebump 341. - For example, a logic chip such as a CPU chip or a GPU chip, or a memory chip such as a DRAM chip, an SRAM chip or a flash memory chip can be used as the
semiconductor chip 340. Incidentally, when a plurality ofsemiconductor chips 340 are mounted on thewiring board 210, the logic chip and the memory chip may be configured in combination and mounted on thewiring board 210. - For example, a gold bump or a solder bump can be used as the
bump 341. For example, an alloy containing lead (Pb), a tin (Sn)—Au alloy, an Sn—Cu alloy, an Sn—Ag alloy, an Sn-silver (Ag)—Cu alloy, or the like, can be used as the material of the solder bump. - The
underfill resin 350 is provided to fill a gap between thewiring board 210 and thesemiconductor chip 340. For example, an insulating resin such as an epoxy resin can be used as the material of theunderfill resin 350. - Next, a method for manufacturing the
wiring board 210 will be described. Incidentally, portions to be final constituent elements of thewiring board 10 will be designated by signs of the final constituent elements for convenience of explanation in the description. - First, a
support substrate 360 is prepared, as shown inFIG. 25A . For example, a plate-like material high in rigidity, such as silicon, glass or metal (such as copper) can be used as the material of thesupport substrate 360. For example, a metal plate or a metal foil sheet can be used as thesupport substrate 360. A copper foil sheet in which an ultrathin copper foil sheet about 2 to 5 μm thick is pasted to a support body copper foil sheet, which is about 35 to 70 μm thick, through a peeling layer is used as thesupport substrate 360 in the present example. - Next, a
metal film 361 covering an entire upper face of thesupport substrate 360 is formed on the upper face of thesupport substrate 360. For example, themetal film 361 is formed on an upper face of the ultrathin copper foil sheet of thesupport substrate 360. Themetal film 361 can be, for example, formed by a sputtering method, a vapor deposition method or an electrolytic plating method. For example, an electrically conductive material serving as a stopper layer when thesupport substrate 360 is etched and removed can be used as the material of themetal film 361. In addition, for example, an electrically conductive material which can be selectively etched and removed from a wiring layer 220 (e.g. a Cu layer) which will be formed by a subsequent step can be used as the material of themetal film 361. For example, a metal such as nickel (Ni), titanium (Ti), chromium (Cr), tin, cobalt (Co), iron (Fe) or palladium or an alloy containing at least one metal selected from the aforementioned metals can be used as the material of such ametal film 361. Ni is used as the material of themetal film 361 in the present example. The thickness of themetal film 361 can be, for example, set in a range of about 0.1 to 1.0 μm. - Successively, the
wiring layer 220 is formed on an upper face of themetal film 361. Thewiring layer 220 can be, for example, formed by a semi-additive method. Specifically, first, a resist pattern (not shown) having an opening portion corresponding to the shape of thewiring layer 220 is formed on the upper face of themetal film 361. Successively, by an electrolytic copper plating method using thesupport substrate 360 and themetal film 361 as power feed layers, a copper plating coating is deposited on the upper face of themetal film 361 exposed from the opening portion of the resist pattern. Then, the resist pattern is removed. In this manner, thewiring layer 220 can be formed on themetal film 361. Incidentally, any of various wiring formation methods such as a subtractive method other than the semi-additive method can be also used as the method for forming thewiring layer 220. - Next, an insulating
layer 230 having a throughhole 230X exposing a portion of an upper face of thewiring layer 220 is formed on the upper face of themetal film 361 in a step shown inFIG. 25B . When, for example, a resin film is used as the insulatinglayer 230, the resin film is laminated on the upper face of themetal film 361 by thermocompression bonding, and the resin film is patterned by a photolithographic method in order to form the insulatinglayer 230. Alternatively, a liquid or paste-like insulating resin may be applied to the upper face of themetal film 361 by a spin coating method etc., and the insulating resin may be patterned by a photolithographic method in order to form the insulatinglayer 230. - Next, a via wiring filled in the through
hole 230X is formed, and aconductor layer 240 is formed on an upper face of the insulatinglayer 230, for example, by a semi-additive method, in a step shown inFIG. 25C . Theconductor layer 240 has awiring layer 241 and ametal layer 242. Thewiring layer 241 is electrically connected to thewiring layer 220 through the via wiring filled in the throughhole 230X. Themetal layer 242 is formed in a mount region of an electronic component 310 (seeFIG. 21A ). - Successively, roughening treatment is applied to the
conductor layer 240 in a step shown inFIG. 26A . An entire upper face and an entire side face of theconductor layer 240 are formed into roughened faces by the roughening treatment. For example, blackening treatment, etching treatment, plating, blast treatment, or the like, can be performed as the roughening treatment. - Next, an insulating
layer 250 having a throughhole 250X exposing a portion of an upper face of thewiring layer 241 is formed on the upper face of the insulatinglayer 230 in a similar manner to or the same manner as the step shown inFIG. 25B , in a step shown inFIG. 26B . On this occasion, the insulatinglayer 250 is formed so as to cover an entire upper face and an entire side face of themetal layer 242. - Next, a via wiring filled in the through
hole 250X is formed, and aconductor layer 260 is formed on an upper face of the insulatinglayer 250, for example, by a semi-additive method, in a step shown inFIG. 27A . Theconductor layer 260 has awiring layer 261 and ametal layer 262. Thewiring layer 261 is electrically connected to thewiring layer 241 through the via wiring filled in the throughhole 250X. Themetal layer 262 has a throughhole 262Y. On this occasion, the planar shape of the throughhole 262Y is formed to be smaller than the planar shape of themetal layer 242. - Successively, roughening treatment is applied to the
conductor layer 260. By the roughening treatment, an entire upper face and an entire side face of theconductor layer 260 are formed into roughened faces. For example, blackening treatment, etching treatment, plating, blast treatment, or the like, can be performed as the roughening treatment. - Next, an insulating
layer 270 covering thewiring layer 261 and themetal layer 262 is formed on the upper face of the insulatinglayer 250 in a similar manner to or the same manner as the step shown inFIG. 25B , in a step shown inFIG. 27B . On this occasion, the insulatinglayer 270 is formed so as to cover an entire upper face and an entire side face of themetal layer 262. The insulatinglayer 270 is formed so as to fill the throughhole 262Y. - Next, in a step shown in
FIG. 28A , a throughhole 270Y penetrating the insulatinglayer 270 in a thickness direction is formed and a throughhole 250Y penetrating the insulatinglayer 250 in the thickness direction is formed, so that a portion of themetal layer 242 corresponding to the mount region of the electronic component 310 (seeFIG. 21A ) is exposed from the throughholes holes - In the present step, the planar shape of the through
hole 270Y is formed to be one size larger than the planar shape of the throughhole 262Y of themetal layer 262. Therefore, a portion of the upper face of themetal layer 262 in the vicinity of the opening edge of the throughhole 270Y is exposed from the insulatinglayer 270. On this occasion, themetal layer 262 exposed from the insulatinglayer 270 functions as a mask and a stopper layer during the laser machining. Therefore, the throughhole 250Y penetrating the insulatinglayer 250 in the thickness direction is formed in the insulatinglayer 250 exposed from the throughhole 262Y of themetal layer 262. Thus, the planar shape of the throughhole 250Y is formed into a size substantially equal to the planar shape of the throughhole 262Y. In the present step, themetal layer 242 functions as a stopper layer during the laser machining. - In the present step, the through
hole 250Y, the throughhole 262Y and the throughhole 270Y are formed to communicate with one another so that anopening portion 300 penetrating the insulatinglayer 250, themetal layer 262 and the insulatinglayer 270 in the thickness direction is formed. The portion of the upper face of themetal layer 242 is exposed from theopening portion 300. - Successively, resin smear adhering to the exposed face of the
metal layer 242 exposed in the bottom of the opening portion 300 (specifically, the bottom of the throughhole 250Y) is removed by desmear treatment in a step shown inFIG. 28B . By the desmear treatment, portions of the insulatinglayers opening portion 300 are removed. Therefore, side faces 250A and 270A of the insulatinglayers opening portion 300 are set back in a direction to be separated more distantly from the planar center of theopening portion 300. Thus, a portion of themetal layer 262 is exposed from the insulatinglayers protrusion portion 263 protruding so as to be closer to the planar center of theopening portion 300 than theside face 250A of the insulatinglayer 250 is formed in themetal layer 262. - Next, in a step shown in
FIG. 29A , roughening treatment is applied to the upper face of themetal layer 242 exposed from the insulatinglayer 250. By the roughening treatment, the entire upper face of themetal layer 242 exposed from the insulatinglayer 250 is formed into a roughened face. In addition, by the roughening treatment, arecess 242X recessed on the insulatinglayer 230 side is formed in the upper face of themetal layer 242 exposed from the insulatinglayer 250. Further, surface roughness of a bottom face of therecess 242X is larger than that prior to etching treatment. Therefore, the surface roughness of the bottom face of therecess 242X is larger than surface roughness of the upper face of themetal layer 242 covered with the insulatinglayer 250. For example, blackening treatment, etching treatment, plating, blast treatment, or the like, can be performed as the roughening treatment. - In the present step, the surface (a lower face, an upper face and a side face) of the
protrusion portion 263 of themetal layer 262 exposed from the insulatinglayers metal layer 242 is roughened. Thus, surface roughness of the surface of theprotrusion portion 263 is larger than that prior to etching treatment. Therefore, the surface roughness of the surface of theprotrusion portion 263 is larger than the surface roughness of the upper face of themetal layer 242 covered with the insulatinglayer 250. - Next, in a step shown in
FIG. 29B , anadhesive layer 312 is formed on the upper face of themetal layer 242 exposed from theopening portion 300. Theadhesive layer 312 can be, for example, formed by applying a liquid resin or a paste-like resin which will be theadhesive layer 312, to the upper face of themetal layer 242. Incidentally, for example, an adhesive agent made of an epoxy-based resin is used as theadhesive layer 312. In addition, the resin agent in A-stage is used as theadhesive layer 312 in the present step. Incidentally, the resin agent in B-stage may be used as theadhesive layer 312 in the present step. - Successively, the
electronic component 310 is mounted on theadhesive layer 312 inside theopening portion 300 by use of a mounter. On this occasion, theelectronic component 310 is fixed on theadhesive layer 312 in a face-up state. - Next, in a step shown in
FIG. 30A , an insulatinglayer 280 with which theopening portion 300 is filled is formed. The insulatinglayer 280 is formed so as to cover the entire surface of theelectronic component 310 not in contact with theadhesive layer 312. The insulatinglayer 280 is formed so as to cover the entire surface of theprotrusion portion 263 which has been subjected to roughening treatment. The insulatinglayer 280 is formed so as to cover an entire upper face of the insulatinglayer 270. On this occasion, upper faces ofelectrode terminals 311 of theelectronic component 310 are formed either on the same plane as the upper face of the insulatinglayer 270 or to be lower than the upper face of the insulatinglayer 270. Accordingly, an upper face of the insulatinglayer 280 can be formed flatly. - Next, in a step shown in
FIG. 30B , a throughhole 280X penetrating the insulatinglayers layers holes 280Y are formed at required places in the insulatinglayer 280. The throughholes - Successively, in a step shown in
FIG. 31A , via wirings with which the throughholes wiring layer 290 electrically connected to thewiring layer 261 or theelectrode terminals 311 through the via wirings is formed on the upper face of the insulatinglayer 280, for example, by a semi-additive method. - Next, in a step shown in
FIG. 31B , a solder resistlayer 330 having anopening portion 330X is formed on the upper face of the insulatinglayer 280. The solder resistlayer 330 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape. By the present step, thewiring layer 290 exposed from theopening portion 330X is a pad P12. Incidentally, for example, a metal layer (i.e. a surface treatment layer) in which an Ni layer and an Au layer are formed in the named order may be formed on the pad P12 if occasions demand. The metal layer can be, for example, formed by an electroless plating method. - Successively, the
support substrate 360 is removed. For example, the support body copper foil sheet of thesupport substrate 360 is mechanically peeled from the ultrathin copper foil sheet. On this occasion, the peeling layer is interposed between the support body copper foil sheet and the ultrathin copper foil sheet. Since an adhesive force between the support body copper foil sheet and the ultrathin copper foil sheet is weak, the support body copper foil sheet can be easily peeled from the ultrathin copper foil sheet. Then, the ultrathin copper foil sheet remaining on themetal film 361 is, for example, removed by wet etching using an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. On this occasion, themetal film 361 functions as a stopper layer when the ultrathin copper foil sheet of thesupport substrate 360 is etched. - Successively, the
metal film 361 is removed by etching. When, for example, Ni is used as the material of themetal film 361, themetal film 361 is selectively etched and removed from the wiring layer 220 (the Cu layer) by wet etching using a hydrogen peroxide/nitric acid-based solution. On this occasion, thewiring layer 220 and the insulatinglayer 230 function as stopper layers when themetal film 361 is etched. By the present step, a lower face of thewiring layer 220 and a lower face of the insulatinglayer 230 are exposed to the outside, as shown inFIG. 32A . On this occasion, the lower face of thewiring layer 220 and the lower face of the insulatinglayer 230 which are in contact with an upper face of the metal film 361 (seeFIG. 31B ) are formed into a shape extending along the upper face (a flat face in this case) of themetal film 361. Therefore, the lower face of thewiring layer 220 and the lower face of the insulatinglayer 230 are formed to be substantially flush with each other. - Next, in a step shown in
FIG. 32B , a solder resistlayer 320 having anopening portion 320X is formed on the lower face of the insulatinglayer 230 in a similar manner to or the same manner as the step shown inFIG. 31B . Thus, thewiring layer 220 exposed from theopening portion 320X serves as a pad P11. Incidentally, for example, a metal layer (i.e. a surface treatment layer) in which an Ni layer and an Au layer are formed in the named order may be formed on the pad P11 if occasions demand. The metal layer can be, for example, formed by an electroless plating method. - By the aforementioned manufacturing process, the
wiring board 210 shown inFIGS. 21A and 21B can be manufactured. Incidentally, thewiring board 210 can be used in a reversed state or can be disposed at any angle. - Next, a method for manufacturing the
semiconductor device 211 will be described. First, asemiconductor chip 340 having abump 341 formed on a circuit formation face of thesemiconductor chip 340 is prepared in a step shown inFIG. 33 . Successively, thebump 341 of thesemiconductor chip 340 is flip-chip bonded onto the pad P12 of thewiring board 210. When, for example, thebump 341 is a solder bump, reflow treatment is performed after thebump 341 and the pad P12 are aligned with each other. As a result, the bump 341 (the solder bump) is melted so that thebump 341 is electrically connected to the pad P12. - Successively, an underfill resin 350 (see
FIG. 24 ) is formed between an upper face of thewiring board 210 and a lower face of thesemiconductor chip 340. Thesemiconductor device 211 shown inFIG. 24 can be manufactured by the aforementioned manufacturing process. - Next, operations and effects of the present embodiment will be described.
- (2-1) The
step portion 301 constituted by theside face 250A of the insulatinglayer 250 and theside face 263A of theprotrusion 263 of themetal layer 262 is formed in the inner side face of theopening portion 300 where theelectronic component 310 is received. In the configuration, a step portion is also formed in an interface between the inner side face of theopening portion 300 and the insulatinglayer 280 with which theopening portion 300 is filled. Thus, peeling of the insulatinglayer 280 can be stopped by thestep portion 301 even when the peeling is propagated to the interface between the insulatinglayer 250 and the insulatinglayer 280. To give detailed description, stress is apt to be concentrated on the vicinity of the opening edge of the bottom of theopening portion 300 when a warp or thermal stress occurs in thewiring board 210. Therefore, the peeling of the insulatinglayer 280 may occur at the interface between themetal layer 242 and the insulatinglayer 280 in the vicinity of the opening edge of the bottom of theopening portion 300. When the peeling occurs at the interface between themetal layer 242 and the insulatinglayer 280, the peeling may be propagated to the interface between the inner side face of theopening portion 300 and the insulatinglayer 280. On this occasion, due to thestep portion 301 formed in the inner side face of theopening portion 300, the peeling of the insulatinglayer 280 can be stopped at thestep portion 301. Thus, the peeling of the insulatinglayer 280 can be stopped halfway in the depth direction of theopening portion 300. Accordingly, thewiring layer 290 formed on the upper face of the insulatinglayer 280 can be suitably suppressed from being broken due to the peeling of the insulatinglayer 280. As a result, lowering of electrical reliability of thewiring board 210 can be suitably suppressed. - (2-2) The
convex step portion 301 constituted by theside face 250A of the insulatinglayer 250, the lower face of theprotrusion portion 263 exposed from the insulatinglayer 250, theside face 263A of theprotrusion portion 263, the upper face of theprotrusion portion 263 exposed from the insulatinglayer 270, and theside face 270A of the insulatinglayer 270 is formed in the inner side face of theopening portion 300. That is, a portion of themetal layer 262 is formed to protrude more inward of theopening portion 300 than the side faces 250A and 270A of the insulatinglayers step portion 301 is formed in the inner side face of theopening portion 300. Further, the insulatinglayer 280 is formed so as to cover the entire surface of the metal layer 262 (i.e. the protrusion portion 263) protruding more inward of theopening portion 300 than the side faces 250A and 270A of the insulatinglayers protrusion portion 263 of themetal layer 262 is formed so as to bite into the insulatinglayer 280. Therefore, tight adhesiveness between themetal layer 262 and the insulatinglayer 280 can be improved due to an anchor effect. - (2-3) The
step portion 301 is formed into a closed ring shape so as to surround theopening portion 300 over the whole circumference in plan view. According to the configuration, peeling of the insulatinglayer 280 can be stopped by thestep portion 301 even when the peeling occurs at any position of the opening edge of the bottom of theopening portion 300. - Incidentally, the aforementioned second embodiment may be changed suitably and carried out in the following modes. The aforementioned second embodiment and the following modifications can be combined with each other and carried out within a range in which the second embodiment and the modifications are not technically contradictory to each other.
- In the aforementioned second embodiment, the
opening portion 300 is constituted by two insulatinglayers metal layer 262. However, the numbers of the insulating layers and the metal layers constituting theopening portion 300 are not limited particularly. - For example, as in a
wiring board 210A shown inFIG. 34 , anopening portion 302 where anelectronic component 310 is received may be constituted by three insulatinglayers metal layers wiring board 210A will be described below. Incidentally, the same members as the aforementioned members shown inFIG. 21A toFIG. 33 are referred to by the same signs respectively and correspondingly, and detailed description about respective elements of the members will be omitted. - For example, a
conductor layer 260 has awiring layer 261 and themetal layer 264. Thewiring layer 261 and themetal layer 264 are formed separately from each other to be electrically insulated from each other. Themetal layer 264 is, for example, formed so as to surround a mount region where theelectronic component 310 is mounted. - The insulating
layer 270 is formed on an upper face of the insulatinglayer 250 so as to cover theconductor layer 260. A throughhole 270X penetrating the insulatinglayer 270 in a thickness direction to expose a portion of an upper face of the conductor layer 260 (thewiring layer 261 in this case) is formed at a required place in the insulatinglayer 270. The throughhole 270X is, for example, formed into an inverted truncated conical shape in which an opening diameter of a lower side opening end is smaller than an opening diameter of an upper side opening end. - A
conductor layer 370 is formed on an upper face of the insulatinglayer 270. The thickness of theconductor layer 370 can be, for example, set in a range of about 10 to 30 μm. An upper face and a side face of theconductor layer 370 are, for example, roughened faces. The upper face and the side face of theconductor layer 370 are, for example, formed into roughened faces larger in surface roughness than a lower face of theconductor layer 370. The surface roughness of theconductor layer 370 can, for example, set to be not lower than 200 nm in terms of surface roughness Ra value. - For example, the
conductor layer 370 has awiring layer 371 and themetal layer 374. Thewiring layer 371 and themetal layer 374 are formed separately from each other to be electrically insulated from each other. - The
wiring layer 371 is, for example, electrically connected to thewiring layer 261 through a via wiring filled in the throughhole 270X. Thewiring layer 371 is, for example, formed integrally with the via wiring filled in the throughhole 270X. Themetal layer 374 is, for example, formed so as to surround the mount region where theelectronic component 310 is mounted. - Each of the metal layers 264 and 374 in the present example is, for example, a dummy pattern which is electrically isolated (floating) without being electrically connected to any other wiring layer or any other conductor layer. For example, the
metal layer - The insulating
layer 380 is formed on the upper face of the insulatinglayer 270 so as to cover theconductor layer 370. Incidentally, a thickness between the upper face of theconductor layer 370 and an upper face of the insulatinglayer 380 can be, for example, set in a range of about 40 to 100 μm. - The
opening portion 302 is, for example, formed so as to penetrate the insulatinglayer 250, themetal layer 264, the insulatinglayer 270, themetal layer 374 and the insulatinglayer 380 in the thickness direction. Theopening portion 302 is, for example, formed so as to expose a portion of an upper face of ametal layer 242. Theopening portion 302 is formed correspondingly to theelectronic component 310 embedded in theopening portion 302. - The
opening portion 302 in the present example is constituted by a throughhole 250Y of the insulatinglayer 250, a throughhole 264Y, a throughhole 270Y of the insulatinglayer 270, a throughhole 374Y and a throughhole 380Y which communicate with one another. The throughhole 264Y penetrates themetal layer 264 in the thickness direction. The throughhole 374Y penetrates themetal layer 374 in the thickness direction. The throughhole 380Y penetrates the insulatinglayer 380 in the thickness direction. - The planar shape of each of the through
holes holes holes 270 Y electronic component 310, and formed to be smaller than the planar shape of themetal layer 242. - The through
hole hole metal layer hole metal layer hole - The
metal layer 264 has aprotrusion portion 265 protruding inward of theopening portion 300 from each of side faces 250A and 270A of the insulatinglayers side face 265A of theprotrusion portion 265 is provided at a position where the side face 265A protrudes in a direction to be closer to the planar center of theopening portion 302 than the side faces 250A and 270A of the insulatinglayers convex step portion 303 constituted by theside face 250A of the insulatinglayer 250, a lower face of theprotrusion portion 265, theside face 265A of theprotrusion portion 265, an upper face of theprotrusion portion 265 and theside face 270A of the insulatinglayer 270 is formed in an inner side face of theopening portion 302. - The
metal layer 374 has aprotrusion portion 375 protruding inward of theopening portion 302 from theside face 270A of the insulatinglayer 270. Aside face 375A of theprotrusion portion 375 is provided at a position where the side face 375A protrudes in the direction to be closer to the planar center of theopening portion 302 than aside face 380A of the insulatinglayer 380 and theside face 270A of the insulatinglayer 270 which constitute the inner side face of the opening portion 302 (the through hole 308Y). Thus, aconvex step portion 304 constituted by theside face 270A of the insulatinglayer 270, a lower face of theprotrusion portion 375, theside face 375A of theprotrusion portion 375, an upper face of theprotrusion portion 375 and theside face 380A of the insulatinglayer 380 is formed in the inner side face of theopening portion 302. - The
side face 380A of the insulatinglayer 380 is, for example, provided at a position where the side face 380A is set back in a direction to be separated more distantly from the planar center of theopening portion 302 than the side faces 250A and 270A of the insulatinglayers electronic component 310 is mounted on the upper face of themetal layer 242 exposed from theopening portion 302, through anadhesive layer 312. The insulatinglayer 280 is formed so as to fill theopening portion 302 and cover the entire surfaces of thestep portions layer 280 is formed so as to cover the entire surface of theprotrusion portion 265 of themetal layer 264 and the entire surface of theprotrusion portion 375 of themetal layer 374. - According to the aforementioned configuration, the
opening portion 302 is formed so as to penetrate the metal layers 264 and 374 and the insulatinglayers layers opening portion 302 can be formed to be deeper accordingly. Therefore, even when a highelectronic component 310 is embedded, theopening portion 302 deep enough to receive theelectronic component 310 therein can be formed easily. - When the
opening portion 302 is formed to penetrate two ormore metal layers FIG. 34 , structures shown inFIGS. 35A and 35B andFIG. 36 can be also used as therespective metal layers FIG. 35A is a plan view of themetal layer 242, the insulatinglayer 250, themetal layer 264, the insulatinglayer 270 and theelectronic component 310, as seen from the upper face side of the insulatinglayer 270. In addition,FIG. 35B is a plan view of themetal layer 242, the insulatinglayers metal layer 374, the insulatinglayer 380 and theelectronic component 310, as seen from the upper face side of the insulatinglayer 380. - As shown in
FIG. 35A , themetal layer 264 hasmetal layers 266 each of which is shaped like a rectangle in plan view. The metal layers 266 are, for example, formed so as to surround the opening edge of the throughhole 250Y. - As shown in
FIG. 35B , themetal layer 374 hasmetal layers 376 each of which is shaped like a rectangle in plan view. The metal layers 376 are, for example, formed so as to surround the opening edge of the throughhole 380Y. A planar shape of the metal layers 266 and the metal layers 376 which are superimposed on each other in plan view is formed into a closed ring shape (a rectangular closed ring shape in this case) surrounding an opening edge of theopening portion 302 over the whole circumference. That is, the metal layers 264 and 374 in the present example are formed so that the planar shape of the twometal layers opening portion 302 over the whole circumference. - As shown in
FIGS. 35A and 35B andFIG. 36 , the metal layers 266 and the metal layers 376 are formed to alternate each other in the circumferential direction of theopening portion 302. For example, each of the metal layers 266 is formed at a position not overlapping with anymetal layer 374 in plan view. In a similar manner or the same manner, each of the metal layers 376 is formed at a position not overlapping with anymetal layer 266 in plan view. Incidentally, the metal layers 266 and the metal layers 376 may have some portions overlapping with each other in plan view. - As shown in
FIG. 36 , theside face 265A of each of the metal layers 266 constituting the inner side face of theopening portion 302 is provided at a position where the side face 265A protrudes in a direction to be closer to the planar center of theopening portion 302 than each of the side faces 250A and 270A of the insulatinglayers step portions 303 each of which is constituted by theside face 250A of the insulatinglayer 250, theside face 265A of themetal layer 266, and theside face 270A of the insulatinglayer 270 are formed in the inner side face of theopening portion 302. Thestep portions 303 are formed at predetermined intervals in the circumferential direction of theopening portion 302. - The
side face 375A of each of the metal layers 376 constituting the inner side face of theopening portion 302 is provided at a position where the side face 375A protrudes in a direction to be closer to the planar center of theopening portion 302 than each of the side faces 270A and 380A of the insulatinglayers step portions 304 each of which is constituted by theside face 270A of the insulatinglayer 270, theside face 375A of themetal layer 376, and theside face 380A of the insulatinglayer 380 are formed in the inner side face of theopening portion 302. Thestep portions 304 are formed at predetermined intervals in the circumferential direction of theopening portion 302. - The
step portions recesses opening portion 302 over the whole circumference. Thestep portions 303 and thestep portions 304 are formed to alternate each other in the circumferential direction of theopening portion 302. For example, each of thestep portions 303 is formed at a position not overlapping with anystep portion 304 in plan view. In a similar manner or the same manner, each of thestep portions 304 are formed at a position not overlapping with anystep portion 303 in plan view. - Here, of the
side face 270A of the insulatinglayer 270, portions overlapping with the metal layers 376 in plan view are, for example, provided at positions where the portions of the side face 270A protrude in a direction to be closer to the planar center of theopening portion 302 than theside face 380A of the insulatinglayer 380. Of theside face 270A of the insulatinglayer 270, the portions overlapping with the metal layers 376 in plan view are, for example, formed on the same plane as theside face 250A of the insulatinglayer 250. On the other hand, of theside face 270A of the insulatinglayer 270, portions not overlapping with the metal layers 376 in plan view are, for example, formed on the same plane as theside face 380A of the insulatinglayer 380. - In the aforementioned configuration, the
step portions 303 and thestep portions 304 are formed so that the planar shape of thestep portions opening portion 302 over the whole circumference. Thus, peeling of the insulatinglayer 280 can be stopped by one of thestep portions opening portion 302. - In addition, kinds of step portions are formed in the inner side face of the
opening portion 302 by the metal layers 264 and 374. In this manner, the degree of freedom for designing the planar shape of each of the metal layers 264 and 374 can be improved in comparison with when a step portion is formed in the inner side face of theopening portion 302 by one metal layer. - In the aforementioned second embodiment, the
step portion 301 is formed over the whole circumference of theopening portion 300. The present invention is not limited thereto. For example, thestep portion 301 may be formed at only a circumferential portion of theopening portion 300. - Each of the aforementioned embodiments can be changed and carried out as follows. The aforementioned embodiments and the following modifications can be combined with each other and carried out in a range that the embodiments and the modifications are not technically contradictory to each other.
- For example, as shown in
FIG. 37 , a stepwise step portion 306 may be formed in an inner side face of anopening portion 305 where anelectronic component 310 is received. In a wiring board 210B shown inFIG. 37 , a throughhole 250Y of an insulatinglayer 250, a throughhole 262Y of ametal layer 260 and a throughhole 270Y of an insulatinglayer 270 communicate with one another to thereby constitute theopening portion 305. - The planar shape of the through
hole 262Y of themetal layer 262 is formed to be larger than the planar shape of the throughhole 250Y of the insulatinglayer 250. The planar shape of the throughhole 270Y of the insulatinglayer 270 is formed to be larger than the planar shape of the throughhole 262Y of themetal layer 262. - A
side face 262A of themetal layer 262 is provided at a position where the side face 262A is set back in a direction to be separated more distantly from the planar center of theopening portion 305 than aside face 250A of the insulatinglayer 250. Therefore, an upper face of the insulatinglayer 250 positioned in the vicinity of theside face 250A of the insulatinglayer 250 is exposed from themetal layer 262. In addition, aside face 270A of the insulatinglayer 270 is provided at a position where the side face 270A is set back in the direction to be separated more distantly from the planar center of theopening portion 305 than theside face 262A of themetal layer 262. Therefore, an upper face of themetal layer 262 positioned in the vicinity of theside face 262A of themetal layer 262 is exposed from the insulatinglayer 270. Thus, the stepwise step portion 306 constituted by theside face 250A of the insulatinglayer 250, the upper face of the insulatinglayer 250 exposed from themetal layer 262, theside face 262A of themetal layer 262, the upper face of themetal layer 262 exposed from the insulatinglayer 270, and theside face 270A of the insulatinglayer 270 is formed in the inner side face of theopening portion 305. An insulatinglayer 280 in this case is formed to cover the entire surface of the stepwise step portion 306. - In the
wiring board holes holes opening portion hole hole - The structure of the
wiring board layer layer layer - The upper face and the side face of the
wiring layer conductor layer 40 etc. In each of the aforementioned embodiments, thewiring layer conductor layer layer - In each of the aforementioned embodiments, the
wiring board wiring board - The number of the
electronic components 110 embedded in thewiring board wiring board wiring board - In each of the aforementioned embodiments, the pad P1 or P11 is used as an external connection pad, and the pad P2 or P12 is used as an electronic component mounting pad. The present invention is not limited thereto. For example, the pad P1 or P11 may be used as an electronic component mounting pad, and the pad P2 or P12 may be used as an external connection pad.
- In the
semiconductor device semiconductor chip wiring board semiconductor chips wiring board wiring board - In addition, a chip component such as a chip capacitor, a chip inductor or a chip resistor, or another electronic component such as a crystal resonator may be mounted on the
wiring board semiconductor chip - In addition, a mounting form of the electronic component such as the
semiconductor chip - In the aforementioned embodiments, the manufacturing method is embodied as a manufacturing method for obtaining a single piece (obtaining one piece). However, the manufacturing method may be embodied as a manufacturing method for obtaining a plurality of pieces. The aforementioned various embodiments are summarized as follows.
- (1) A method for manufacturing a wiring board, comprising:
- forming a second insulating layer on an upper face of a first insulating layer;
- forming a first metal layer having a first through hole on an upper face of the second insulating layer;
- forming a third insulating layer on the upper face of the second insulating layer so as to cover the first metal layer;
- forming a second through hole and a third through hole, the second through hole penetrating the second insulating layer in a thickness direction to communicate with the first through hole, the second through hole being different in size of planar shape from the first through hole, the third through hole penetrating the third insulating layer in the thickness direction to communicate with the first through hole, the third through hole being different in size of planar shape from the first through hole;
- mounting an electronic component in an opening portion that includes the first through hole, the second through hole and the third through hole communicating with one another;
- forming a filling insulating layer so as to fill the opening portion and cover the electronic component; and
- forming a wiring layer on an upper face of the filling insulating layer.
- (2) The method for manufacturing a wiring board according to clause (1), wherein:
- the forming second through hole and the third through hole comprises:
- forming the second through hole in the second insulating layer and forming the third through hole in the third insulating layer, the second through hole being larger in planar shape than the first through hole, the third through hole being larger in planar shape than the first through hole; and
- removing a portion of the first metal layer so as to make the planar shape of the first through hole larger than the planar shape of the second through hole.
- (3) The method for manufacturing a wiring board according to clause (1), wherein:
- the forming second through hole and the third through hole comprises:
- forming the second through hole in the second insulating layer and forming the third through hole in the third insulating layer, the second through hole being larger in planar shape than the first through hole, the third through hole being larger in planar shape than the first through hole; and
- applying roughening treatment to a portion of the first metal layer exposed from the second through hole and the third through hole,
- wherein the filling insulating layer is formed so as to cover the entire surface of the roughened portion of the first metal layer.
Claims (11)
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JP2019019431A JP7265877B2 (en) | 2019-02-06 | 2019-02-06 | wiring board |
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