US20200194589A1 - Fin field effect transistor structure with particular gate appearance - Google Patents
Fin field effect transistor structure with particular gate appearance Download PDFInfo
- Publication number
- US20200194589A1 US20200194589A1 US16/243,014 US201916243014A US2020194589A1 US 20200194589 A1 US20200194589 A1 US 20200194589A1 US 201916243014 A US201916243014 A US 201916243014A US 2020194589 A1 US2020194589 A1 US 2020194589A1
- Authority
- US
- United States
- Prior art keywords
- gate
- fin
- lower portion
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention generally relates to a semiconductor structure, and more specifically, relates to a fin field effect transistor (FinFET) structure with particular gate appearance.
- FinFET fin field effect transistor
- MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- the poly-Si based dummy gate or sacrificial gate would be formed in advance on the fin for shaping the gate.
- the dummy gate will be replaced with laminated structure such as high-k gate dielectric layer, work function layer, and one or more metal layers to form metal gate in later processes.
- the present invention is to provide a fin field effect transistor (FinFET) structure with particular features at positions where gates abut fins.
- FinFET fin field effect transistor
- One purpose of the present invention is to provide a semiconductor structure with particular gate appearance, featuring a substrate, a fin on the substrate, wherein a longitudinal direction of the fin is a first direction, and a gate on the substrate and traversing over the fin, wherein a longitudinal direction of the gate is a second direction, and the gate is divided into an upper portion on a top surface of the fin and a lower portion at two sides of the fin, and the lower portion of the gate has protrusions laterally extending in the first direction at positions abutting the fin.
- Another purpose of the present invention is to provide a 3D semiconductor structure, featuring a substrate, a fin on the substrate, wherein a longitudinal direction of the fin is a first direction, and a gate on the substrate and traversing over the fin, wherein a longitudinal direction of the gate is a second direction, and the gate is divided into an upper portion on a top surface of the fin and a lower portion at two sides of the fin, and the lower portion of the gate has protrusions laterally extending in the first direction at positions abutting the fin.
- FIG. 1 is a layout of active patterns and gate patterns of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in accordance with the preferred embodiment of the present invention
- FIG. 2 is a perspective drawing of the fin field effect transistor (FinFET) structure with particular gate appearance in accordance with the preferred embodiment of the present invention
- FIG. 3 is a partially enlarged drawing of the active patterns and the gate patterns in accordance with the preferred embodiment of the present invention.
- FIG. 4 is a perspective drawing of the FinFET structure with particular gate appearance in accordance with another embodiment of the present invention.
- FIG. 1 is a layout of active patterns and gate patterns of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in accordance with the preferred embodiment of the present invention.
- MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- the substrate 100 on the layout area will be defined with p-well (not shown) doped with p-type dopants corresponding to an NMOS transistor and n-well (not shown) doped with n-type dopants corresponding to a PMOS transistor. Since the well region mentioned above is not essential feature of the present invention, they are not shown in the figure in case of obscuring the key point of the present invention.
- linear active patterns 102 such as fin patterns, are defined on a corresponding p-well region or n-well region with identical pitch P 1 and extending in a first direction D 1 .
- the pitch P 1 is the shortest distance between a first side of a fin 102 and a first side of an adjacent fin 102 .
- a plurality of gate patterns 104 are defined on the substrate 100 and traverses over the linear active patterns 102 .
- the gate patterns 104 generally have identical pitch P 2 and extend in a second direction D 2 , wherein the second direction D 2 is usually perpendicular to the first direction D 1 , and the pitch P 1 might be the same as the pitch D 2 .
- the pitch P 1 might be different from the pitch P 2 .
- adjacent linear active patterns 102 in a row may be provided with slot cut regions 103 separating therebetween.
- the linear active patterns 102 and the gate patterns 104 may be defined by photolithographic processes.
- FIG. 2 is a perspective drawing of the fin field effect transistor (FinFET) structure with particular gate appearance in accordance with the preferred embodiment of the present invention.
- the structural portion shown in FIG. 2 is exactly the portion shown by dashed circles in FIG. 1 , wherein a gate 104 a is shown traversing over a fin 102 a .
- the gate 104 a and the fin 102 a are defined respectively by the gate pattern 104 and the linear active pattern 102 shown in FIG. 1 .
- performing an etch process to a material layer (ex. silicon or poly-silicon layer, respectively) using a photoresist or hard mask with the gate patterns 104 or linear active patterns 102 as an etch mask to form the patterns.
- the gate 104 a may be a dummy gate or sacrificial gate that is formed in advance on the fin for shaping the gate.
- the dummy gate will be replaced with laminated structure such as high-k gate dielectric layer, work function layer, and one or more metal layer to form metal gate in later processes.
- laminated structure such as high-k gate dielectric layer, work function layer, and one or more metal layer to form metal gate in later processes.
- the aforementioned components will not be shown in the figures except for the gate pattern 104 and the fin 102 a in case of obscuring the key points of the present invention.
- the fin 102 a protrudes from the substrate 100 and extends in a longitudinal first direction D 1 .
- the gate 104 a is disposed on the substrate 100 and extends in a longitudinal second direction D 2 .
- the second direction D 2 is preferably perpendicular to the first direction D 1 , but not limited thereto.
- the gate 104 a is divided into an upper portion 104 b on a top surface of the fin 102 a and a lower portion 104 c at two sides of the fin 102 a , wherein, due to the effect of etch process, the width of gate 104 a in the second direction D 2 tapers from the lower portion 104 c to the upper portion 104 b .
- the width of gate 104 a in the first direction D 1 tapers from the lower portion 104 c to the upper portion 104 b .
- the fin 102 a is also provided with this kind of tapering feature.
- the lower portion 104 c of the gate 104 a has protrusions 106 feature laterally extending in the first direction D 1 at positions abutting the fin 102 a .
- the upper portion 104 b of the gate 104 a that does not abut with the fin 102 a will not be provided with this kind of protrusion feature.
- This feature may also be observed in FIG. 1 . It can be seen that the positions where the gate patterns 104 and the linear active patterns 102 abutting are all provided with this kind of protrusions 106 feature.
- some gate patterns 104 in the figure have only one side abutting with the linear active pattern 102 (i.e. the fin). As the portion “c” shown in the figure, the sides of these gate patterns 104 that do not abut with the linear active patterns 102 are not provided with this protrusions 106 feature. Only the side abutting with the linear active pattern 102 has protrusions 106 feature.
- many slot cut regions 103 are formed on the layout plan to separate adjacent linear active patterns 102 . These regions break single linear active pattern 102 into several linear active patterns 102 in a row. It can be seen in the figure that some gate patterns 104 have a side adjacent to the slot cut region 103 and a side not adjacent to the slot cut region 103 . Wherein, the protruding degree of the protrusion 106 protruding toward the adjacent slot cut region 103 would be larger than the protruding degree of the protrusion 106 on the side not adjacent to the slot cut portion. For example, as shown in FIG. 1 , the protruding degree of protrusion 106 in the portion “a” would be larger than the protruding degree of protrusion 106 in the portion “b”.
- FIG. 3 is a partially enlarged drawing of an area shown in the dashed frame of FIG. 1 .
- the protrusion 106 features in the aforementioned portion “a” and portion “b” and the feature having no protrusion in the portion “c” are shown more clearly in the partially enlarged drawing of FIG. 3 .
- FIG. 4 is a perspective drawing of the FinFET structure with particular gate appearance in accordance with another embodiment of the present invention.
- the structure shown in the embodiment of FIG. 4 is similar to the structure shown in the embodiment of FIG. 2 , with the only difference that the top surface of the protrusion 106 is not flush with the top surface of the lower portion 104 c of the gate 104 a like the one shown in FIG. 2 . Rather, it is lower than the top surface of the lower portion 104 c by a certain degree.
- the present invention also discloses a 3D semiconductor structure, including a substrate 100 , a fin 102 a on the substrate 100 , wherein a longitudinal direction of the fin 102 a is a first direction D 1 , and a gate 104 a on the substrate 100 and traversing over the fin 102 a , wherein a longitudinal direction of the gate 104 a is a second direction D 2 , and the gate 104 a is divided into an upper portion 104 b on a top surface of the fin 102 a and a lower portion 104 c at two sides of the fin 102 a , and the lower portion 104 c of the gate 104 a has protrusions 106 laterally extending in the first direction D 1 at positions abutting the fin 102 a.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The present invention generally relates to a semiconductor structure, and more specifically, relates to a fin field effect transistor (FinFET) structure with particular gate appearance.
- A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect transistor widely used in analogue electronics and digital electronics with advantages of available area, operating speed, power consumption, and manufacturing cost better than conventional Bipolar Junction Transistor (BJT), therefore, are widely adopted by the industry.
- As the advances of MOSFET technology, the length of gate is shrunk to below 20 nm. The problem of current leakage is increasingly serious since the source and drain are getting too close together. The shrinking of gate length also reduces the contact area of gate and channel, thereby weakening the influence of the gate to the channel. In order to solve this problem, the industry develops 3D Fin Field-Effect Transistors (FinFET) featuring the fin design to increase the contact area of gate and channel. The aforementioned problem is, therefore, solved.
- In replacement metal gate (RMG) or gate last technology, the poly-Si based dummy gate or sacrificial gate would be formed in advance on the fin for shaping the gate. The dummy gate will be replaced with laminated structure such as high-k gate dielectric layer, work function layer, and one or more metal layers to form metal gate in later processes.
- The present invention is to provide a fin field effect transistor (FinFET) structure with particular features at positions where gates abut fins.
- One purpose of the present invention is to provide a semiconductor structure with particular gate appearance, featuring a substrate, a fin on the substrate, wherein a longitudinal direction of the fin is a first direction, and a gate on the substrate and traversing over the fin, wherein a longitudinal direction of the gate is a second direction, and the gate is divided into an upper portion on a top surface of the fin and a lower portion at two sides of the fin, and the lower portion of the gate has protrusions laterally extending in the first direction at positions abutting the fin.
- Another purpose of the present invention is to provide a 3D semiconductor structure, featuring a substrate, a fin on the substrate, wherein a longitudinal direction of the fin is a first direction, and a gate on the substrate and traversing over the fin, wherein a longitudinal direction of the gate is a second direction, and the gate is divided into an upper portion on a top surface of the fin and a lower portion at two sides of the fin, and the lower portion of the gate has protrusions laterally extending in the first direction at positions abutting the fin.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
-
FIG. 1 is a layout of active patterns and gate patterns of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in accordance with the preferred embodiment of the present invention; -
FIG. 2 is a perspective drawing of the fin field effect transistor (FinFET) structure with particular gate appearance in accordance with the preferred embodiment of the present invention; -
FIG. 3 is a partially enlarged drawing of the active patterns and the gate patterns in accordance with the preferred embodiment of the present invention; and -
FIG. 4 is a perspective drawing of the FinFET structure with particular gate appearance in accordance with another embodiment of the present invention. - It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
- In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
- Please refer to
FIG. 1 first, which is a layout of active patterns and gate patterns of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in accordance with the preferred embodiment of the present invention. In the exemplary design architecture of CMOS integrated circuit, thesubstrate 100 on the layout area will be defined with p-well (not shown) doped with p-type dopants corresponding to an NMOS transistor and n-well (not shown) doped with n-type dopants corresponding to a PMOS transistor. Since the well region mentioned above is not essential feature of the present invention, they are not shown in the figure in case of obscuring the key point of the present invention. - As shown in
FIG. 1 , linearactive patterns 102, such as fin patterns, are defined on a corresponding p-well region or n-well region with identical pitch P1 and extending in a first direction D1. The pitch P1 is the shortest distance between a first side of afin 102 and a first side of anadjacent fin 102. Furthermore, a plurality ofgate patterns 104 are defined on thesubstrate 100 and traverses over the linearactive patterns 102. Thegate patterns 104 generally have identical pitch P2 and extend in a second direction D2, wherein the second direction D2 is usually perpendicular to the first direction D1, and the pitch P1 might be the same as the pitch D2. Alternatively, the pitch P1 might be different from the pitch P2. Please note that adjacent linearactive patterns 102 in a row may be provided withslot cut regions 103 separating therebetween. The linearactive patterns 102 and thegate patterns 104 may be defined by photolithographic processes. - In actual structure, the
gate pattern 104 may include a gate oxide layer (not shown) and a conductive layer (not shown) formed on the gate oxide layer. Thegate pattern 104 functions as a gate electrode for a PMOS transistor or a NMOS transistor. The linearactive patterns 102 at two sides of thegate pattern 104 are usually formed with a source and drain, such as doped epitaxial SiGe structures. Insulating interlayers (not shown) are further formed on the linearactive patterns 102 and thegate patterns 104. Contacts (not shown) are formed in these insulating interlayers and are electrically connected withunderlying gate patterns 104 or source/drain to interconnect to other circuit. Except for thegate patterns 104, the aforementioned components will not be shown in the figures in case of obscuring the key points of the present invention. - Please refer to
FIG. 2 , which is a perspective drawing of the fin field effect transistor (FinFET) structure with particular gate appearance in accordance with the preferred embodiment of the present invention. The structural portion shown inFIG. 2 is exactly the portion shown by dashed circles inFIG. 1 , wherein agate 104 a is shown traversing over afin 102 a. Thegate 104 a and thefin 102 a are defined respectively by thegate pattern 104 and the linearactive pattern 102 shown inFIG. 1 . For example, performing an etch process to a material layer (ex. silicon or poly-silicon layer, respectively) using a photoresist or hard mask with thegate patterns 104 or linearactive patterns 102 as an etch mask to form the patterns. In replacement metal gate (RMG) or gate last technology, thegate 104 a may be a dummy gate or sacrificial gate that is formed in advance on the fin for shaping the gate. The dummy gate will be replaced with laminated structure such as high-k gate dielectric layer, work function layer, and one or more metal layer to form metal gate in later processes. LikeFIG. 1 , the aforementioned components will not be shown in the figures except for thegate pattern 104 and thefin 102 a in case of obscuring the key points of the present invention. - As shown in
FIG. 2 , thefin 102 a protrudes from thesubstrate 100 and extends in a longitudinal first direction D1. Thegate 104 a is disposed on thesubstrate 100 and extends in a longitudinal second direction D2. The second direction D2 is preferably perpendicular to the first direction D1, but not limited thereto. In the embodiment of the present invention, thegate 104 a is divided into anupper portion 104 b on a top surface of thefin 102 a and alower portion 104 c at two sides of thefin 102 a, wherein, due to the effect of etch process, the width ofgate 104 a in the second direction D2 tapers from thelower portion 104 c to theupper portion 104 b. Similarly, the width ofgate 104 a in the first direction D1 tapers from thelower portion 104 c to theupper portion 104 b. Thefin 102 a is also provided with this kind of tapering feature. - Please note that, as shown in
FIG. 2 in the embodiment of the present invention, thelower portion 104 c of thegate 104 a hasprotrusions 106 feature laterally extending in the first direction D1 at positions abutting thefin 102 a. Theupper portion 104 b of thegate 104 a that does not abut with thefin 102 a will not be provided with this kind of protrusion feature. This feature may also be observed inFIG. 1 . It can be seen that the positions where thegate patterns 104 and the linearactive patterns 102 abutting are all provided with this kind ofprotrusions 106 feature. - Furthermore, as shown in
FIG. 1 , it can be seen that somegate patterns 104 in the figure have only one side abutting with the linear active pattern 102 (i.e. the fin). As the portion “c” shown in the figure, the sides of thesegate patterns 104 that do not abut with the linearactive patterns 102 are not provided with thisprotrusions 106 feature. Only the side abutting with the linearactive pattern 102 hasprotrusions 106 feature. - On the other hand, as shown in
FIG. 1 , many slot cutregions 103 are formed on the layout plan to separate adjacent linearactive patterns 102. These regions break single linearactive pattern 102 into several linearactive patterns 102 in a row. It can be seen in the figure that somegate patterns 104 have a side adjacent to the slot cutregion 103 and a side not adjacent to the slot cutregion 103. Wherein, the protruding degree of theprotrusion 106 protruding toward the adjacent slot cutregion 103 would be larger than the protruding degree of theprotrusion 106 on the side not adjacent to the slot cut portion. For example, as shown inFIG. 1 , the protruding degree ofprotrusion 106 in the portion “a” would be larger than the protruding degree ofprotrusion 106 in the portion “b”. -
FIG. 3 is a partially enlarged drawing of an area shown in the dashed frame ofFIG. 1 . Theprotrusion 106 features in the aforementioned portion “a” and portion “b” and the feature having no protrusion in the portion “c” are shown more clearly in the partially enlarged drawing ofFIG. 3 . - Please refer to
FIG. 4 , which is a perspective drawing of the FinFET structure with particular gate appearance in accordance with another embodiment of the present invention. The structure shown in the embodiment ofFIG. 4 is similar to the structure shown in the embodiment ofFIG. 2 , with the only difference that the top surface of theprotrusion 106 is not flush with the top surface of thelower portion 104 c of thegate 104 a like the one shown inFIG. 2 . Rather, it is lower than the top surface of thelower portion 104 c by a certain degree. - According to the inventive features described in previous paragraphs, the present invention also discloses a 3D semiconductor structure, including a
substrate 100, afin 102 a on thesubstrate 100, wherein a longitudinal direction of thefin 102 a is a first direction D1, and agate 104 a on thesubstrate 100 and traversing over thefin 102 a, wherein a longitudinal direction of thegate 104 a is a second direction D2, and thegate 104 a is divided into anupper portion 104 b on a top surface of thefin 102 a and alower portion 104 c at two sides of thefin 102 a, and thelower portion 104 c of thegate 104 a hasprotrusions 106 laterally extending in the first direction D1 at positions abutting thefin 102 a. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (16)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811516618.8A CN111312817B (en) | 2018-12-12 | 2018-12-12 | Fin field effect transistor structure with special grid shape |
CN201811516618.8 | 2018-12-12 | ||
CN201811516618 | 2018-12-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
US10686079B1 US10686079B1 (en) | 2020-06-16 |
US20200194589A1 true US20200194589A1 (en) | 2020-06-18 |
Family
ID=71073001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/243,014 Active US10686079B1 (en) | 2018-12-12 | 2019-01-08 | Fin field effect transistor structure with particular gate appearance |
Country Status (2)
Country | Link |
---|---|
US (1) | US10686079B1 (en) |
CN (1) | CN111312817B (en) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100577610B1 (en) | 2003-07-15 | 2006-05-10 | 삼성전자주식회사 | semiconductor device, method for manufacturing semiconductor decice, SRAM device and method for manufacturing SRAM |
KR101198127B1 (en) * | 2005-09-30 | 2012-11-12 | 엘지디스플레이 주식회사 | LCD and Method of fabricating of the same |
US8629512B2 (en) * | 2012-03-28 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate stack of fin field effect transistor with slanted sidewalls |
KR102017616B1 (en) * | 2013-01-02 | 2019-09-03 | 삼성전자주식회사 | Field effect transistor |
KR102287398B1 (en) * | 2015-01-14 | 2021-08-06 | 삼성전자주식회사 | Semiconductor device |
US10262870B2 (en) * | 2015-07-02 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
CN106920748B (en) * | 2015-12-25 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and forming method thereof |
-
2018
- 2018-12-12 CN CN201811516618.8A patent/CN111312817B/en active Active
-
2019
- 2019-01-08 US US16/243,014 patent/US10686079B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10686079B1 (en) | 2020-06-16 |
CN111312817A (en) | 2020-06-19 |
CN111312817B (en) | 2023-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9299785B2 (en) | Reducing resistance in source and drain regions of FinFETs | |
US8174073B2 (en) | Integrated circuit structures with multiple FinFETs | |
US10418480B2 (en) | Semiconductor device capable of high-voltage operation | |
CN103426915B (en) | There is the semiconductor device of autoregistration cross tie part | |
US8610236B2 (en) | Edge devices layout for improved performance | |
US11670678B2 (en) | Integrated circuit structure | |
US20170263717A1 (en) | Semiconductor device capable of high-voltage operation | |
US10141400B2 (en) | Semiconductor devices including field effect transistors with dummy gates on isolation | |
KR101634498B1 (en) | Diode structure compatible with finfet process | |
JP2002270850A (en) | Dual-gate field effect transistor | |
JP2010087436A (en) | Semiconductor device | |
JPWO2005020325A1 (en) | Semiconductor device and manufacturing method thereof | |
US10090325B1 (en) | Circuit cells having separated gate electrodes | |
US20070278613A1 (en) | Semiconductor device | |
US10665690B2 (en) | Gate-controlled bipolar junction transistor and operation method thereof | |
US10163904B1 (en) | Semiconductor device structure | |
US10686079B1 (en) | Fin field effect transistor structure with particular gate appearance | |
US11569235B2 (en) | Semiconductor device and method of manufacturing the same | |
US20050224884A1 (en) | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same | |
US20230137101A1 (en) | Integrated Circuit Structure of N-Type and P-Type FinFET Transistors | |
US20220254778A1 (en) | Semiconductor Device and Method for Manufacturing the Same | |
US9640629B1 (en) | Semiconductor device and method of manufacturing the same | |
KR102475451B1 (en) | Method of manufacturing semiconductor devices | |
JP2005129635A (en) | Soi semiconductor integrated circuit device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, CHIH-YI;CHIU, CHENG-PU;WEI, HUANG-REN;AND OTHERS;REEL/FRAME:047936/0312 Effective date: 20190104 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |