US20200127158A1 - Method of manufacturing light emitting element - Google Patents
Method of manufacturing light emitting element Download PDFInfo
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- US20200127158A1 US20200127158A1 US16/658,527 US201916658527A US2020127158A1 US 20200127158 A1 US20200127158 A1 US 20200127158A1 US 201916658527 A US201916658527 A US 201916658527A US 2020127158 A1 US2020127158 A1 US 2020127158A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 28
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 230000014509 gene expression Effects 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000002086 nanomaterial Substances 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- USZGMDQWECZTIQ-UHFFFAOYSA-N [Mg](C1C=CC=C1)C1C=CC=C1 Chemical compound [Mg](C1C=CC=C1)C1C=CC=C1 USZGMDQWECZTIQ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- -1 or InGaZnO4 Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000009210 therapy by ultrasound Methods 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Definitions
- the present disclosure relates to a method of manufacturing a light emitting element.
- JP 2016-25357A a base layer 120 is formed on a substrate 101, and a mask layer 130 and a mold layer 135 having a plurality of openings are formed on the base layer 120. A plurality of first conductivity-type semiconductor cores 142 are formed in the plurality of openings. Subsequently, the mold layer 135 is removed, and an active layer 144 and a second conductivity-type semiconductor layer 146 are formed on the first conductivity-type semiconductor cores 142.
- a plurality of rod-shaped light emitting nanostructures 140 are obtained. Subsequently, a portion of the light emitting nanostructures 140 is removed to form regions, and a second electrode 180 and a first electrode 170 are formed on the regions.
- a plurality of rod-shaped light-emitting (nano) structures formed on a single substrate may be divided in several light-emitting regions. In such cases, the rod-shaped light-emitting structures at borders of the regions may be removed.
- such an electrode forming region can be determined according to the quality of the rod-shaped structures. For example, defectively formed rod-shaped structures may be removed to provide a region that is used as the electrode forming region. Also, a mask formed with a plurality of openings respectively corresponding to a plurality of rod-shaped structures may be used in such a procedure, in which defective rod-shaped structures may result at openings located at outer peripheral portion of the mask. In order to avoid formation of such defective rod-shaped structures, openings in a mask may be omitted at locations corresponding to an electrode forming region.
- defective rod-shaped structures may still occur near the electrode forming region.
- a procedure in which a plurality of rod-shaped structures are formed and then a part of plurality of rod-shaped structures is removed to provide an electrode forming region and an electrode is disposed on the electrode forming region such defective rod-shaped structures can be avoided.
- a part of the rod-shaped structures is removed while retaining the mask layer provided to form the rod-shaped structures.
- a portion of the rod-shaped structures may remain in the openings of the mask layer.
- upper surfaces and lateral surfaces of the remaining rod-shaped structure and other portions of the surface may differ in quality, which may result in an electrode of film quality different in portions, which may further result in an inferior contact between the semiconductor and the electrode. Removing the remaining portions of the rod-shaped structures requires additional operations, which increases manufacturing time.
- An object of certain embodiments described in the present disclosure is to provide a method of manufacturing a light-emitting element, in which rod-shaped structures in an electrode forming surface can be reliably removed.
- a method of manufacturing a light-emitting element includes, sequentially: forming a first conductive-type semiconductor layer on a substrate; forming an insulating film defining a plurality of openings and a plurality of rods of a first conductive-type semiconductor on the first conductive-type semiconductor layer, a respective one of the rods being disposed through a respective one of the plurality of openings of the insulating film; forming a light-emitting layer covering outer surfaces of the plurality of rods; forming a second conductive-type semiconductor layer covering outer surfaces of the light-emitting layer, to obtain a plurality of rod-shaped layered structures, a respective one of the plurality of rod-shaped layered structures including the rod, the light-emitting layer, and the second conductive type semiconductor layer; forming a photoresist pattern covering a portion of the plurality of the rod-shaped layered structures; removing a portion of the insulating film in a region that are not covered by the photoresist pattern; and
- rod-shaped layered structures on an electrode forming surface can be reliably removed.
- FIG. 1 is a flow chart showing a flow of a method of manufacturing according to one embodiment.
- FIG. 2 is a cross-sectional view schematically showing a product at completion of a step of forming a first conductive-type semiconductor layer according to one embodiment.
- FIG. 3 is a cross-sectional view schematically showing a product at completion of a step of forming an insulating film according to one embodiment.
- FIG. 4 is a cross-sectional view schematically showing a product at completion of a step of forming rods according to one embodiment.
- FIG. 5 is a partially enlarged view of FIG. 4 .
- FIG. 6 is a cross-sectional view schematically showing a product at completion of a step of forming a light emitting layer according to one embodiment.
- FIG. 7 is a cross-sectional view schematically showing a product at completion of a step of forming a second conductive-type semiconductor layer according to one embodiment.
- FIG. 8 is a cross-sectional view schematically showing a product at completion of a step of forming an electrically conductive film according to one embodiment.
- FIG. 9 is a cross-sectional view schematically showing a product at completion of a step of forming a photoresist pattern according to one embodiment.
- FIG. 10 is a cross-sectional view schematically showing a product at completion of a step of removing an insulating film according to one embodiment.
- FIG. 11 is a cross-sectional view schematically showing a product at completion of a step of removing rod-shaped layered structures according to one embodiment.
- FIG. 12 is a cross-sectional view schematically showing a product at completion of a step of forming a protective film according to one embodiment.
- FIG. 13 is a cross-sectional view schematically showing a product at completion of a step of forming a first electrode and a second electrode according to one embodiment.
- FIG. 1 is a flow chart showing a flow of a method of manufacturing according to one embodiment.
- a method of manufacturing a light-emitting element according to the present embodiment includes forming a first conductive-type semiconductor layer (S 102 ), forming an insulating film and rods (S 103 ), forming a light-emitting layer (S 108 ), forming a second conductive-type semiconductor layer (S 110 ), forming an electrically conductive film (S 112 ), forming a photoresist pattern (S 114 ), removing the insulating film (S 116 ), removing rod-shaped layered structures (S 118 ), forming a protective film (S 120 ), and forming a first electrode and a second electrode (S 122 ).
- an “n-type” is referred to as a “first conductive-type” and a “p-type is referred to as a “second conductive-type”.
- FIG. 2 is a schematic cross-sectional view illustrating a step of forming a first conductive-type semiconductor layer (S 102 ) according to one embodiment.
- a buffer layer 104 is formed on the main surface 102 a
- an n-type semiconductor layer 106 is formed on the buffer layer 104 .
- the substrate 102 for example, a sapphire (Al 2 O 3 ) substrate, a SiC substrate, a nitride semiconductor substrate, or the like can be used.
- a nitride semiconductor such as GaN or AlN can be used for the buffer layer 104 .
- a nitride semiconductor such as GaN or AlN can be used.
- an n-type nitride semiconductor such as an n-type GaN-based semiconductor can be used for the buffer layer 104 .
- an n-type nitride semiconductor such as an n-type GaN-based semiconductor can be used for example.
- an example employing a sapphire substrate as the substrate 102 , a GaN layer as the buffer layer 104 , and an n-type GaN layer as the n-type semiconductor layer 106 will be illustrated.
- a reaction device such as an MOCVD device can be used to form each semiconductor layer.
- the crystal plane of a sapphire substrate with a Miller index (0001) is preferably used as a main surface 102 a that is a growth surface.
- the term “(0001) plane” includes a plane that is slightly inclined to the (0001) plane. More specifically, a surface with an off angle in a range of 0.5° to 2.0° with respect to the (0001) plane is preferably used as the growth surface.
- the substrate 102 is preferably pre-treated before forming the buffer layer 104 on the substrate 102 .
- the substrate 102 is heated in the reaction device to heat-treat (thermal cleaning) the main surface 102 a .
- the temperature for the heat treatment can be set in a range of 900 to 1,200° C. and the heating duration can be set in a range of about 2 to 15 minutes.
- the main surface 102 a of the substrate 102 can be purified with this heat treatment.
- NH 3 gas is supplied in the reaction device and the main surface 102 a of the substrate 102 is nitrided.
- the temperature for the nitriding treatment can be set in a range of 900 to 1,100° C. and the heating duration can be set in a range of 1 to 30 minutes. With such a nitriding treatment, the nitride semiconductor of a (000-1) plane can be grown on the main surface 102 a.
- a buffer layer 104 is grown on the nitrided main surface 102 a of the substrate 102 .
- the buffer layer 104 of GaN can be grown with the temperature of the substrate 102 at 550° C. and the source gases are supplied.
- the source gas for gallium can be trimethyl gallium (TMG) gas or trimethyl gallium (TEG) gas, and the source gas for nitride can be NH 3 gas.
- the buffer layer 104 can have a thickness of about 20 nm, for example.
- the buffer layer 104 of amorphous GaN may be grown and subsequently a heat treatment may be applied. It is preferable that the temperature for the heat treatment is set at 1,000° C. or greater and the heating duration is set in a range of about several minutes to about 1 hour, in an atmosphere of nitrogen gas or a mixed gas of nitrogen gas and NH 3 gas.
- an n-type GaN layer is grown as an n-type semiconductor layer 106 on the buffer layer 104 .
- a GaN layer to which Si is added can be employed, for example.
- the GaN layer to which Si is added can be grown with the source gas described above to which a silane gas is added.
- the cross-sectional view shown in FIG. 2 schematically illustrates a buffer layer 104 and the n-type semiconductor layer 106 layered in order on the substrate 102 .
- the n-type semiconductor layer 106 may be directly grown on the substrate 102 without providing the buffer layer 104 .
- One or more other layers such as an undoped semiconductor layer may be grown before growing the n-type semiconductor layer 106 .
- the n-type semiconductor layer 106 of a (000-1) plane can be grown on the surface (main surface 102 a ) of the substrate 102 .
- the step of forming the insulating film and the rods (S 103 ) can further include forming an insulating film (S 104 ) and forming rods (S 106 ).
- FIG. 3 is a cross-sectional view schematically showing a product at completion of a step of forming an insulating film (S 104 ).
- an insulating film 108 defining a plurality of openings 108 a is formed on the upper surface that is one of the main surfaces of the n-type semiconductor layer 106 .
- the insulating film 108 serves as a mask in a subsequent operation.
- a material such as SiO 2 or SiN can be used.
- the insulating film 108 defines a plurality of openings 108 a that are through-openings in the thickness direction (up-an up-down direction in FIG.
- each of the openings 108 a a part of an upper surface of the n-type semiconductor layer 106 is exposed.
- the plurality of openings 108 a can be formed by using, for example, photolithography.
- the openings 108 a can be formed in an appropriate shape such as a circular shape, an elliptic shape, or a polygonal shape in a top view.
- an appropriate shape such as a circular shape, an elliptic shape, or a polygonal shape in a top view.
- the openings 108 a are preferably formed with a shape that can facilitate growth of the hexagonal prisms of the semiconductor rods, which is, more specifically, a circular shape or a regular hexagonal shape in a top view.
- a shape that can facilitate growth of the hexagonal prisms of the semiconductor rods which is, more specifically, a circular shape or a regular hexagonal shape in a top view.
- FIG. 4 is a cross-sectional view schematically showing a product at completion of a step of forming rods (S 106 ).
- FIG. 5 is a partially enlarged view of FIG. 4 .
- a plurality of rods 112 of the n-type semiconductor layer (rods of the first conductive-type semiconductor) are formed on respective parts of the upper surface of the n-type semiconductor layer 106 exposed in the plurality of openings 108 a of the insulating film 108 .
- the description below illustrates forming of an n-type GaN crystal, the same as the n-type semiconductor layer 106 , as each of the rods 112 .
- the rods 112 can be grown by for example, raising the temperature of the substrate 102 in a range of 900 to 1,100° C. and supplying source gases.
- TMG or TEG can be used as the source gas for gallium
- NH 3 gas can be used as the source gas for nitrogen
- silane gas can be used as the source gas for an n-type dopant.
- the insulating film 108 prevents growth of the GaN-based semiconductor thereon, such that the GaN crystals grow on the parts of the upper surface of the n-type semiconductor layer 106 exposed in the openings 108 a form semiconductor rods respectively extending in upward direction.
- the height of the rods 112 can be adjusted by a supplying time of the source gases.
- GaN-based crystals When the grown surface is a nitrided surface of the sapphire substrate 102 , GaN-based crystals mainly grows in [000-1] direction. Accordingly, the rods 112 are also mainly grown in [000-1] direction of GaN crystals. That is, the rods 112 grow from the n-type semiconductor layer 106 in an upward direction, which is [000-1] direction of the GaN crystals.
- a GaN-based crystal has a hexagonal system wurtzite type crystal structure. The rods 112 grown in [000-1] direction tend to form hexagonal-columnar shapes.
- the rods 112 grown through the openings 108 a defined in a circular shape tend to form a hexagonal-columnar shape, but not a circular columnar shape.
- the lateral surfaces of the rods 112 grown into hexagonal-columnar shapes are an m-plane of the GaN-based crystals.
- the rods 112 grown out through the openings 108 a take hexagonal-columnar shapes, such that a transverse dimension D of a respective one of the rods 112 as shown in FIG. 5 becomes greater than the diameter d of its corresponding opening. Accordingly, the base portions 112 a of the rods 112 (i.e., portions in the openings 108 a ) are the narrowest portions in the rods 112 . Meanwhile, when the GaN-based semiconductors are grown in [000-1] direction, migration of the GaN-based semiconductors is reduced compared to that grown in [0001] direction, which reduces growth in traverse directions.
- the rods 112 grow in an upward direction without a significant increase in a traverse dimension.
- the rods 112 of relatively uniform traverse dimension (thickness) can be obtained.
- the greater the diameter of the openings 108 a the thicker the rods 112 . Accordingly, the thickness of the rods 112 can be controlled by the diameter of the openings 108 a.
- FIG. 6 is a cross-sectional view schematically showing a product at completion of the step of forming a light emitting layer (S 108 ).
- the light emitting layer 114 is formed to cover outer surfaces of a respective one of the rods 112 . That is, the light-emitting layer 114 is formed not only on the upper surfaces of the rods 112 but also on the lateral surfaces of the respective one of the rods 112 .
- the light-emitting layer 114 may have a multi-quantum well (MQW) structure.
- MQW multi-quantum well
- a nitride semiconductor can be used for the light-emitting layer 114 .
- the light-emitting layer 114 may have a structure in which a plurality of GaN barrier layers and a plurality of InGaN well layers alternately layered.
- the wavelength of the light emitted from the light-emitting layer 114 can be determined by adjusting forming conditions of the light-emitting layer 114 .
- a light-emitting layer to emit blue light can be formed at a temperature of the substrate 102 in a range of about 800 to 900° C., with supplying source gases.
- the source gases include trimethyl gallium (TMG) or triethyl gallium (TEG) as a source gas of gallium, NH3 as a source gas of nitrogen, and trimethyl indium (TMI) as a source gas of indium.
- FIG. 7 is a cross-sectional view schematically showing a product at completion of a step of forming a second conductive-type semiconductor layer (S 110 ) according to one embodiment.
- a p-type semiconductor layer 116 covering the outer surfaces of the light-emitting layer 114 of a respective one of the rods 112 is formed.
- the p-type semiconductor layer 116 may be a p-type nitride semiconductor such as a p-type GaN-based semiconductor.
- the p-type semiconductor layer 116 may be formed by layering a plurality of p-type GaN layers or a plurality of p-type AlGaN layers with different p-type dopant concentrations.
- the p-type semiconductor layer 116 can be formed, for example, at a temperature of the substrate 102 in a range of about 800 to 900° C., with supplying source gases.
- TMG or TEG can be used as a source gas of gallium and NH 3 can be used as a source gas of nitrogen.
- Mg is used as a p-type dopant, for example, bis(cyclopentadienyl)magnesium (Cp2Mg) can be used as a source gas.
- the p-type semiconductor layer 116 is formed as shown in FIG. 7 , thus, the rod-shaped layered structures 110 , each of which includes the rod 112 , the light-emitting layer 114 , and the p-type semiconductor layer 116 , are formed.
- the rod-shaped layered structures 110 serve as a light-emitting part of the light-emitting element according to the present embodiment.
- intervals of adjacent rods 112 may affect growth rate of the light-emitting layer 114 and the p-type semiconductor layer 116 .
- the expression “intervals of adjacent rods 112 ” used in the present specification refers to a distance between the centers of two adjacent openings 108 a defined in the insulating film 108 (illustrated in FIG. 3 ) in a plan view.
- An expression “intervals of adjacent rod-shaped layered structures 110 ” refers to similar configuration.
- the light-emitting layer 114 and the p-type semiconductor layer 116 can be grown respectively at a substantially uniform growth rate.
- the openings 108 a can be defined in a right triangular grid in a plan view, which allows formation of the rods 112 at substantially uniform intervals in the step of forming rods (S 106 ).
- a direction through the centers of the openings 108 a in a plan view is preferably in parallel to the m-axis direction of the GaN-based crystals that form the rods 112 , that is, preferably in parallel to the a-axis of the sapphire substrate 102 .
- the rods 112 having a hexagonal pyramid shape formed in a right triangular grid are adjacent one other with lateral surfaces facing substantially in parallel to each other.
- each of the light-emitting layer 114 and the p-type semiconductor layer 116 can be formed at a substantially uniform growth rate on the lateral surfaces of each of the rods 112 , which allows for forming each of the light-emitting layer 114 and the p-type semiconductor layer 116 with a substantially uniform thickness.
- the distance between each two adjacent rods 112 affects the indium incorporation into the InGaN well layer of the light emitting layer 114 .
- the InGaN well layer is formed with a supply of a source gas for In at a constant flow rate, the greater the distance between each two adjacent rods 112 , the greater amount of In incorporated into the InGaN well layer.
- the rod-shaped layered structures 110 configured to emit light of different wavelengths can be formed by adjusting the distance between each two adjacent rods 112 .
- a group of rods 112 formed with greater intervals, a group of rods 112 formed with smaller intervals, and a group of rods 112 formed with intermediate intervals on a single substrate 102 allows for three regions of the rod-shaped layered structures, each configured to emit red light, green light, and blue light, respectively, formed on a single substrate 102 .
- the rod-shaped layered structures 110 configured to emit light of a desired wavelength can be obtained.
- the expression “thickness of rod-shaped layered structure 110 ” refers to a maximum dimension of a width of cross section of the rod-shaped layered structure 110 .
- average thickness refers to an average value of the thickness of ten rod-shaped layered structures 110 that are adjacent to one other.
- Each of two adjacent rod-shaped layered structures 110 are spaced apart from each other such that an electrically conductive film 120 , which will be described later in the specification, can be formed on the outer surfaces of the rod-shaped layered structures 110 .
- the shortest distance between the outer surfaces of the adjacent rod-shaped layered structures 110 can be adjusted within a range of 25 nm to 190 ⁇ m.
- the rod-shaped layered structures 110 can have a height within a range of 1 to 100 ⁇ m.
- FIG. 8 is a cross-sectional view schematically showing a product at completion of a step S 112 of forming an electrically conductive film (S 112 ).
- an electrically conductive film 120 covering a plurality of rod-shaped layered structures 110 is formed.
- the electrically conductive film 120 include an electrically conductive oxide film made of such as indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, or InGaZnO 4 , and Ag film.
- the electrically conductive film 120 may be a single film or a multilayered film.
- the description below illustrates forming of an ITO film as the electrically conductive film 120 .
- a material transmissive to light emitted to the rod-shaped layered structures 110 such as an ITO
- the electrically conductive film 120 is formed by way of sputtering, without using a resist pattern. Accordingly, as shown in FIG. 8 , the electrically conductive film 120 covers not only the outer surfaces of the rod-shaped layered structures 110 but also continuously covers the upper surface of the insulating film 108 .
- the p-type semiconductor layer 116 is a p-type nitride semiconductor layer
- electric resistance is relatively higher than that of an n-type nitride semiconductor layer, such that the entire outer surfaces of the rod-shaped layered structures 110 are preferably covered by the electrically conductive film 120 .
- the electric current can be supplied to the entire portions of the p-type semiconductor layer 116 that forms the outer surfaces of the rod-shaped layered structures 110 , which allows emission of light from the entire outer surfaces of the rod-shaped layered structures 110 .
- the electrically conductive film 120 before the step of forming a photoresist pattern (S 114 ).
- the p-type semiconductor layer 116 can be protected against a developing solvent required to remove the photoresist pattern in a later step.
- the concentration of the p-type dopant is generally high, which leads to a reduction in the quality of crystallinity, which causes the p-type semiconductor layer 116 to be susceptible to be etched by the developing solvent.
- the p-type semiconductor layer 116 can be protected by the electrically conductive film 120 in the step S 114 .
- FIG. 9 is a cross-sectional view schematically showing a product at completion of a step of forming a photoresist pattern: S 114 according to one embodiment.
- a photoresist pattern 130 covering a portion of the plurality of rod-shaped layered structures 110 is formed.
- the photoresist pattern 130 includes first portions exposing a first portion of the plurality of rod-shaped layered structures 110 that are to be removed in the step of removing rod-shaped layered structures (S 118 ), and second portions covering a second portion of the plurality of rod-shaped layered structures 110 .
- the first portion of the plurality of rod-shaped layered structures 110 to be removed in the step of removing rod-shaped layered structures (S 118 ) is located in a region where an electrode to be formed, and the second portion of the plurality of rod-shaped layered structures 110 covered by the photoresist pattern 130 is configured to function as a light-emitting region of the light-emitting element.
- FIG. 10 is a cross-sectional view schematically showing a product at completion of a step of removing the insulating film (S 116 ).
- the electrically conductive film 120 and the insulating film 108 in the region that is not covered by the photoresist pattern 130 are removed by etching.
- the narrow base portions 112 a of the rod-shaped layered structures 110 are exposed by removing the insulating film 108 .
- FIG. 11 is a cross-sectional view schematically showing a product at completion of a step of removing rod-shaped layered structures: S 118 .
- the step of removing rod-shaped layered structures S 118
- the first portion of the plurality of rod-shaped layered structures 110 that is not covered by the photoresist pattern 130 is removed.
- the plurality of rod-shaped layered structures 110 can be mechanically removed by using ultrasonic waves in water.
- the insulating film 108 is removed prior to removing the rod-shaped layered structures 110 , which exposes the narrow base portions 112 a of the rod-shaped layered structures 110 , which facilitates removing of the rod-shaped layered structures 110 .
- the rod-shaped layered structures 110 can be more thoroughly removed at their base portions, compared to a conventional method in which the rod-shaped layered structures are removed before removing the insulating film. Further, according to the method as in the present embodiment, in which the rods 112 are grown through openings of the insulating film 108 , the base portion of a respective one of the rods 112 that is in the opening and surrounded by the insulating film 108 is narrower compared to the portion grown above the opening. Accordingly, removing the insulating film 108 to expose the narrow base portions, and then removing the rod-shaped layered structures 110 , can reduce time required to remove the rod-shaped layered structures 110 .
- wet etching may be performed and then the rod-shaped layered structures 110 may be removed by using ultrasonic waves.
- the rods 112 have a hexagonal prism shape with the lateral surfaces of the m-plane, the lateral surfaces are not easily wet-etched.
- forming the openings 108 a in a circular shape allows for forming of the base portions 112 a in a columnar shape, which can be easily wet-etched.
- Wet-etching further narrows the base portions 112 a in a columnar shape, and subsequent apply of ultrasonic waves can further reduce time required to remove the rod-shaped layered structures 110 .
- Wet etching can be performed, for example, by using tetramethylammonium hydroxide (TMAH).
- TMAH tetramethylammonium hydroxide
- the narrow base portions 112 a of the rod-shaped layered structures 110 are exposed, allowing a reduction in time required for removing the rod-shaped layered structures 110 even by using wet etching, compared to that by using a conventional method.
- the first conductive-type semiconductor layer is the first-conductive-type nitride semiconductor layer and the upper surface is a (000-1) plane
- it can be easily etched by using an etching solution such as TMAH for wet etching, compared to etching a (0001) plane.
- TMAH etching solution
- a long-time etching of a (000-1) plane may result in a rough surface, which may result in an inferior contact with the electrode.
- the rod-shaped layered structures 110 can be entirely removed respectively down to the bottom of the base portion. Nevertheless, removing the rod-shaped layered structures 110 may cause some irregularities on the surface of the n-type semiconductor layer 106 .
- the surface of the n-type semiconductor layer 106 may be subjected to etching to increase flatness. For this purpose, for example, a reactive ion etching (RIE) may be used.
- FIG. 11 is a cross-sectional view schematically showing a state in which flatness of the upper surface of the n-type semiconductor layer 106 has been improved by etching. Removing the rod-shaped layered structures 110 produces rod-free regions on the upper surface of the n-type semiconductor layer 106 , which includes a first region indicated by “A” and a second region indicated by “B”, as shown in FIG. 11 .
- FIG. 12 is a cross-sectional view schematically showing a product at completion of a step of forming a protective film (S 120 ).
- the resist pattern 130 is removed, and an insulating protective film 140 is formed on exposed portions of the upper surface of the n-type semiconductor layer 106 in the second region B, continuously onto a portion of the remaining plurality of rod-shaped layered structures 110 .
- the electrically conductive film 120 is formed on the outer surfaces of a respective one of the plurality of rod-shaped layered structures 110 , such that substantially the insulating protective film 140 is formed on the portions of the upper surface of the n-type semiconductor layer 106 exposed in the second region B, and continuously on portions of the electrically conductive film 120 covering the outer surfaces of a portion of the plurality of rod-shaped layered structures 110 .
- the protective film 140 can be formed with an insulating member that is transmissive to light emitted from the rod-shaped layered structures 110 , for example, SiO 2 , SiN, Al 2 O 3 , or the like, can be used. As described above, the insulating protective film 140 is preferably formed on the portion of the upper surface of the n-type semiconductor layer 106 exposed adjacent to the remaining plurality of rod-shaped layered structures 110 , and continuously on portions of the outer surfaces of the electrically conductive film 120 covering the rod-shaped layered structures 110 located adjacent to the region B. Accordingly, the possibility of occurrence of short circuit between the n-type semiconductor layer 106 and the electrically conductive film 120 , caused by adhesion of dust or the like, may be reduced.
- FIG. 13 is a cross-sectional view schematically showing a product at completion of a step of forming a first electrode and a second electrode (S 122 ) according to one embodiment.
- a first electrode 150 electrically connected to the n-type semiconductor layer 106 is formed on the upper surface of the n-type semiconductor layer 106 exposed in the first region A, and a second electrode 160 electrically connected to the p-type semiconductor layer 116 and also extended onto a portion of the outer surface of the protective film 140 in the second region B is formed.
- the expression “electrically connected to the p-type semiconductor layer 116 ” used above also refers to a case in which electrical connection to the p-type semiconductor layer 116 is through the electrically conductive film 120 , when the electrically conductive film 120 is provided.
- suitable materials of the first electrode 150 and the second electrode 160 include a single metal such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr and W, and an alloy whose main component is one or more of those metals.
- an electrode material layer can be formed by sequentially layering Ti and Au.
- the first electrode 150 and the second electrode 160 can be discretely formed, but it is preferable to form the first electrode 150 and the second electrode 160 simultaneously using the same material, which allows a reduction in manufacturing time.
- the first electrode 150 and the second electrode 160 can be formed, for example, as described below.
- a resist pattern defining openings at predetermined locations for the first electrode 150 and the second electrode 160 is formed, then, using a vapor deposition method, a sputtering method, or the like, an electrode material layer for the first electrode 150 and the second electrode 160 is formed.
- a resist pattern defining an opening at a predetermined location for the first electrode 150 and the second electrode 160 may be formed. Subsequently, through lift-off, the resist pattern and the electrode material layer formed on the resist pattern are removed.
- the first electrode 150 and the second electrode 160 are formed to complete the light emitting element.
- the insulating film 108 is removed before removing the rod-shaped layered structures 110 . Accordingly, the base portions 112 a of the rod-shaped layered structures 110 are exposed, which facilitates removing of the rod-shaped layered structures 110 . This allows for more thorough removal of the rod-shaped layered structures 110 respectively at the root of the base portion, and accordingly, the rod-shaped layered structures 110 can be removed more completely, compared to the use of a conventional method in which the insulating film is removed after removing the rod-shaped layered structures 110 .
- n-type is indicated as “first conductive-type” and “p-type” is indicated as “second conductive-type”, but vice-versa, “p-type” may be indicated as “first conductive-type” and “n-type” may be indicated as “second conductive-type”.
- the electrically conductive film 120 is not necessary.
- the rods are formed after forming the insulating film, but the rods may be formed before forming the insulating film.
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Abstract
Description
- The present application claims priority under 35 U. S. C. § 119 to Japanese Patent Application No. 2018-199299, filed Oct. 23, 2018, the contents of which are hereby incorporated by reference in their entirety.
- The present disclosure relates to a method of manufacturing a light emitting element.
- Semiconductor light emitting elements including three-dimensional light emitting nanostructures and methods of manufacturing such light emitting elements have been proposed. One example thereof is illustrated in Japanese Patent Publication No. 2016-25357. In the method described in JP 2016-25357A, a
base layer 120 is formed on a substrate 101, and amask layer 130 and a mold layer 135 having a plurality of openings are formed on thebase layer 120. A plurality of first conductivity-type semiconductor cores 142 are formed in the plurality of openings. Subsequently, the mold layer 135 is removed, and an active layer 144 and a second conductivity-type semiconductor layer 146 are formed on the first conductivity-type semiconductor cores 142. Accordingly, a plurality of rod-shapedlight emitting nanostructures 140 are obtained. Subsequently, a portion of thelight emitting nanostructures 140 is removed to form regions, and a second electrode 180 and a first electrode 170 are formed on the regions. - In some cases, a plurality of rod-shaped light-emitting (nano) structures formed on a single substrate may be divided in several light-emitting regions. In such cases, the rod-shaped light-emitting structures at borders of the regions may be removed.
- In a procedure in which a plurality of rod-shaped structures are formed and subsequently a part of the rod-shaped structures is removed to provide a region to dispose an electrode, such an electrode forming region can be determined according to the quality of the rod-shaped structures. For example, defectively formed rod-shaped structures may be removed to provide a region that is used as the electrode forming region. Also, a mask formed with a plurality of openings respectively corresponding to a plurality of rod-shaped structures may be used in such a procedure, in which defective rod-shaped structures may result at openings located at outer peripheral portion of the mask. In order to avoid formation of such defective rod-shaped structures, openings in a mask may be omitted at locations corresponding to an electrode forming region. However, defective rod-shaped structures may still occur near the electrode forming region. In contrast, in a procedure in which a plurality of rod-shaped structures are formed and then a part of plurality of rod-shaped structures is removed to provide an electrode forming region and an electrode is disposed on the electrode forming region, such defective rod-shaped structures can be avoided.
- In the procedure described in JP 2016-25357A, a part of the rod-shaped structures is removed while retaining the mask layer provided to form the rod-shaped structures. A portion of the rod-shaped structures may remain in the openings of the mask layer. When a portion of the rod-shaped structures remain in the electrode forming region, upper surfaces and lateral surfaces of the remaining rod-shaped structure and other portions of the surface may differ in quality, which may result in an electrode of film quality different in portions, which may further result in an inferior contact between the semiconductor and the electrode. Removing the remaining portions of the rod-shaped structures requires additional operations, which increases manufacturing time.
- An object of certain embodiments described in the present disclosure is to provide a method of manufacturing a light-emitting element, in which rod-shaped structures in an electrode forming surface can be reliably removed.
- A method of manufacturing a light-emitting element includes, sequentially: forming a first conductive-type semiconductor layer on a substrate; forming an insulating film defining a plurality of openings and a plurality of rods of a first conductive-type semiconductor on the first conductive-type semiconductor layer, a respective one of the rods being disposed through a respective one of the plurality of openings of the insulating film; forming a light-emitting layer covering outer surfaces of the plurality of rods; forming a second conductive-type semiconductor layer covering outer surfaces of the light-emitting layer, to obtain a plurality of rod-shaped layered structures, a respective one of the plurality of rod-shaped layered structures including the rod, the light-emitting layer, and the second conductive type semiconductor layer; forming a photoresist pattern covering a portion of the plurality of the rod-shaped layered structures; removing a portion of the insulating film in a region that are not covered by the photoresist pattern; and removing a portion of the plurality of rod-shaped layered structures in the region that are not covered by the photoresist pattern.
- Using the method of manufacturing according to certain embodiments of the disclosure, rod-shaped layered structures on an electrode forming surface can be reliably removed.
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FIG. 1 is a flow chart showing a flow of a method of manufacturing according to one embodiment. -
FIG. 2 is a cross-sectional view schematically showing a product at completion of a step of forming a first conductive-type semiconductor layer according to one embodiment. -
FIG. 3 is a cross-sectional view schematically showing a product at completion of a step of forming an insulating film according to one embodiment. -
FIG. 4 is a cross-sectional view schematically showing a product at completion of a step of forming rods according to one embodiment. -
FIG. 5 is a partially enlarged view ofFIG. 4 . -
FIG. 6 is a cross-sectional view schematically showing a product at completion of a step of forming a light emitting layer according to one embodiment. -
FIG. 7 is a cross-sectional view schematically showing a product at completion of a step of forming a second conductive-type semiconductor layer according to one embodiment. -
FIG. 8 is a cross-sectional view schematically showing a product at completion of a step of forming an electrically conductive film according to one embodiment. -
FIG. 9 is a cross-sectional view schematically showing a product at completion of a step of forming a photoresist pattern according to one embodiment. -
FIG. 10 is a cross-sectional view schematically showing a product at completion of a step of removing an insulating film according to one embodiment. -
FIG. 11 is a cross-sectional view schematically showing a product at completion of a step of removing rod-shaped layered structures according to one embodiment. -
FIG. 12 is a cross-sectional view schematically showing a product at completion of a step of forming a protective film according to one embodiment. -
FIG. 13 is a cross-sectional view schematically showing a product at completion of a step of forming a first electrode and a second electrode according to one embodiment. - Next, embodiments of the present invention will be described in detail with reference to the drawings.
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FIG. 1 is a flow chart showing a flow of a method of manufacturing according to one embodiment. A method of manufacturing a light-emitting element according to the present embodiment includes forming a first conductive-type semiconductor layer (S102), forming an insulating film and rods (S103), forming a light-emitting layer (S108), forming a second conductive-type semiconductor layer (S110), forming an electrically conductive film (S112), forming a photoresist pattern (S114), removing the insulating film (S116), removing rod-shaped layered structures (S118), forming a protective film (S120), and forming a first electrode and a second electrode (S122). In the present embodiment, an “n-type” is referred to as a “first conductive-type” and a “p-type is referred to as a “second conductive-type”. -
FIG. 2 is a schematic cross-sectional view illustrating a step of forming a first conductive-type semiconductor layer (S102) according to one embodiment. In the step of forming the first conductive-type semiconductor layer S102, using amain surface 102 a that is one of main surfaces of asubstrate 102 as a growth surface, abuffer layer 104 is formed on themain surface 102 a, and an n-type semiconductor layer 106 is formed on thebuffer layer 104. For thesubstrate 102, for example, a sapphire (Al2O3) substrate, a SiC substrate, a nitride semiconductor substrate, or the like can be used. For thebuffer layer 104, for example, a nitride semiconductor such as GaN or AlN can be used. For the n-type semiconductor layer 106, for example, an n-type nitride semiconductor such as an n-type GaN-based semiconductor can be used. In the present embodiment, an example employing a sapphire substrate as thesubstrate 102, a GaN layer as thebuffer layer 104, and an n-type GaN layer as the n-type semiconductor layer 106 will be illustrated. In the present embodiment, a reaction device such as an MOCVD device can be used to form each semiconductor layer. - The crystal plane of a sapphire substrate with a Miller index (0001) is preferably used as a
main surface 102 a that is a growth surface. In the present specification, the term “(0001) plane” includes a plane that is slightly inclined to the (0001) plane. More specifically, a surface with an off angle in a range of 0.5° to 2.0° with respect to the (0001) plane is preferably used as the growth surface. - The
substrate 102 is preferably pre-treated before forming thebuffer layer 104 on thesubstrate 102. For example, thesubstrate 102 is heated in the reaction device to heat-treat (thermal cleaning) themain surface 102 a. The temperature for the heat treatment can be set in a range of 900 to 1,200° C. and the heating duration can be set in a range of about 2 to 15 minutes. Themain surface 102 a of thesubstrate 102 can be purified with this heat treatment. - Subsequently, NH3 gas is supplied in the reaction device and the
main surface 102 a of thesubstrate 102 is nitrided. The temperature for the nitriding treatment can be set in a range of 900 to 1,100° C. and the heating duration can be set in a range of 1 to 30 minutes. With such a nitriding treatment, the nitride semiconductor of a (000-1) plane can be grown on themain surface 102 a. - Subsequently, a
buffer layer 104 is grown on the nitridedmain surface 102 a of thesubstrate 102. For example, thebuffer layer 104 of GaN can be grown with the temperature of thesubstrate 102 at 550° C. and the source gases are supplied. The source gas for gallium can be trimethyl gallium (TMG) gas or trimethyl gallium (TEG) gas, and the source gas for nitride can be NH3 gas. Thebuffer layer 104 can have a thickness of about 20 nm, for example. Thebuffer layer 104 of amorphous GaN may be grown and subsequently a heat treatment may be applied. It is preferable that the temperature for the heat treatment is set at 1,000° C. or greater and the heating duration is set in a range of about several minutes to about 1 hour, in an atmosphere of nitrogen gas or a mixed gas of nitrogen gas and NH3 gas. - Further, an n-type GaN layer is grown as an n-
type semiconductor layer 106 on thebuffer layer 104. For the n-type GaN layer, a GaN layer to which Si is added can be employed, for example. The GaN layer to which Si is added can be grown with the source gas described above to which a silane gas is added. The cross-sectional view shown inFIG. 2 schematically illustrates abuffer layer 104 and the n-type semiconductor layer 106 layered in order on thesubstrate 102. When a substrate such as a GaN substrate that allows growth of the n-type semiconductor layer 106 without the interveningbuffer layer 104 is used as thesubstrate 102, the n-type semiconductor layer 106 may be directly grown on thesubstrate 102 without providing thebuffer layer 104. One or more other layers such as an undoped semiconductor layer may be grown before growing the n-type semiconductor layer 106. As described above, with nitriding the surface of thesubstrate 102, the n-type semiconductor layer 106 of a (000-1) plane can be grown on the surface (main surface 102 a) of thesubstrate 102. - The step of forming the insulating film and the rods (S103) can further include forming an insulating film (S104) and forming rods (S106).
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FIG. 3 is a cross-sectional view schematically showing a product at completion of a step of forming an insulating film (S104). In the step of forming an insulating film (S104), an insulatingfilm 108 defining a plurality ofopenings 108 a is formed on the upper surface that is one of the main surfaces of the n-type semiconductor layer 106. The insulatingfilm 108 serves as a mask in a subsequent operation. For the insulatingfilm 108, a material such as SiO2 or SiN can be used. The insulatingfilm 108 defines a plurality ofopenings 108 a that are through-openings in the thickness direction (up-an up-down direction inFIG. 3 ) of the insulatingfilm 108. In each of theopenings 108 a, a part of an upper surface of the n-type semiconductor layer 106 is exposed. The plurality ofopenings 108 a can be formed by using, for example, photolithography. - The
openings 108 a can be formed in an appropriate shape such as a circular shape, an elliptic shape, or a polygonal shape in a top view. As described later in the specification, when a nitride semiconductor having a wurtzite structure with an upward growth in [000-1] direction (c.f., an upward direction) is grown on the upper surface of the n-type semiconductor layer 106 exposed in each of the openings of the insulatingfilm 108, a semiconductor rod of a hexagonal prism shape with the lateral surfaces of an m-plane is grown. For this reason, theopenings 108 a are preferably formed with a shape that can facilitate growth of the hexagonal prisms of the semiconductor rods, which is, more specifically, a circular shape or a regular hexagonal shape in a top view. When each of theopenings 108 a is formed in a regular hexagonal shape in a top view, highly precise positioning is required to obtain exact matching between the sides of the regular hexagon and the m-plane of the semiconductor rod. Meanwhile, such precise positioning is not needed when each of theopenings 108 a is formed in a circular shape. With other reasons to be described later in the specification, acircular opening 108 a is more preferable. - In the present specification, expressions such as “upper”, “lower”, and the like used to indicate the directions or locations of components, such as “an upper surface,” are used to express relative directional relationships, relative positional relationships, and the like between the components in a drawing that is referred to, and unless specifically indicated, are not intended to show absolute positional relationships. For example, the “upper surface” of the n-
type semiconductor layer 106 described above is directed to a main surface of the n-type semiconductor layer 106 that is not in contact with thebuffer layer 104, but because the surface faces upward inFIG. 3 , is indicated as the “upper surface” for convenience of explanation. -
FIG. 4 is a cross-sectional view schematically showing a product at completion of a step of forming rods (S106).FIG. 5 is a partially enlarged view ofFIG. 4 . In the step of forming the rods (S106), a plurality ofrods 112 of the n-type semiconductor layer (rods of the first conductive-type semiconductor) are formed on respective parts of the upper surface of the n-type semiconductor layer 106 exposed in the plurality ofopenings 108 a of the insulatingfilm 108. The description below illustrates forming of an n-type GaN crystal, the same as the n-type semiconductor layer 106, as each of therods 112. Therods 112 can be grown by for example, raising the temperature of thesubstrate 102 in a range of 900 to 1,100° C. and supplying source gases. In this case, similar to that for the n-type semiconductor layer 106, TMG or TEG can be used as the source gas for gallium, NH3 gas can be used as the source gas for nitrogen, and silane gas can be used as the source gas for an n-type dopant. The insulatingfilm 108 prevents growth of the GaN-based semiconductor thereon, such that the GaN crystals grow on the parts of the upper surface of the n-type semiconductor layer 106 exposed in theopenings 108 a form semiconductor rods respectively extending in upward direction. The height of therods 112 can be adjusted by a supplying time of the source gases. - When the grown surface is a nitrided surface of the
sapphire substrate 102, GaN-based crystals mainly grows in [000-1] direction. Accordingly, therods 112 are also mainly grown in [000-1] direction of GaN crystals. That is, therods 112 grow from the n-type semiconductor layer 106 in an upward direction, which is [000-1] direction of the GaN crystals. A GaN-based crystal has a hexagonal system wurtzite type crystal structure. Therods 112 grown in [000-1] direction tend to form hexagonal-columnar shapes. Accordingly, therods 112 grown through theopenings 108 a defined in a circular shape tend to form a hexagonal-columnar shape, but not a circular columnar shape. The lateral surfaces of therods 112 grown into hexagonal-columnar shapes are an m-plane of the GaN-based crystals. - When the
openings 108 a are defined in a circular shape, therods 112 grown out through theopenings 108 a take hexagonal-columnar shapes, such that a transverse dimension D of a respective one of therods 112 as shown inFIG. 5 becomes greater than the diameter d of its corresponding opening. Accordingly, thebase portions 112 a of the rods 112 (i.e., portions in theopenings 108 a) are the narrowest portions in therods 112. Meanwhile, when the GaN-based semiconductors are grown in [000-1] direction, migration of the GaN-based semiconductors is reduced compared to that grown in [0001] direction, which reduces growth in traverse directions. Accordingly, therods 112 grow in an upward direction without a significant increase in a traverse dimension. Thus, therods 112 of relatively uniform traverse dimension (thickness) can be obtained. The greater the diameter of theopenings 108 a, the thicker therods 112. Accordingly, the thickness of therods 112 can be controlled by the diameter of theopenings 108 a. -
FIG. 6 is a cross-sectional view schematically showing a product at completion of the step of forming a light emitting layer (S108). In the step of forming a light emitting layer (S108), thelight emitting layer 114 is formed to cover outer surfaces of a respective one of therods 112. That is, the light-emittinglayer 114 is formed not only on the upper surfaces of therods 112 but also on the lateral surfaces of the respective one of therods 112. The light-emittinglayer 114 may have a multi-quantum well (MQW) structure. For the light-emittinglayer 114, a nitride semiconductor can be used. The light-emittinglayer 114 may have a structure in which a plurality of GaN barrier layers and a plurality of InGaN well layers alternately layered. The wavelength of the light emitted from the light-emittinglayer 114 can be determined by adjusting forming conditions of the light-emittinglayer 114. For example, a light-emitting layer to emit blue light can be formed at a temperature of thesubstrate 102 in a range of about 800 to 900° C., with supplying source gases. Examples of the source gases include trimethyl gallium (TMG) or triethyl gallium (TEG) as a source gas of gallium, NH3 as a source gas of nitrogen, and trimethyl indium (TMI) as a source gas of indium. -
FIG. 7 is a cross-sectional view schematically showing a product at completion of a step of forming a second conductive-type semiconductor layer (S110) according to one embodiment. In the step of forming the second conductive-type semiconductor layer (S110), a p-type semiconductor layer 116 covering the outer surfaces of the light-emittinglayer 114 of a respective one of therods 112 is formed. The p-type semiconductor layer 116 may be a p-type nitride semiconductor such as a p-type GaN-based semiconductor. The p-type semiconductor layer 116 may be formed by layering a plurality of p-type GaN layers or a plurality of p-type AlGaN layers with different p-type dopant concentrations. - The p-
type semiconductor layer 116 can be formed, for example, at a temperature of thesubstrate 102 in a range of about 800 to 900° C., with supplying source gases. TMG or TEG can be used as a source gas of gallium and NH3 can be used as a source gas of nitrogen. When Mg is used as a p-type dopant, for example, bis(cyclopentadienyl)magnesium (Cp2Mg) can be used as a source gas. - The p-
type semiconductor layer 116 is formed as shown inFIG. 7 , thus, the rod-shapedlayered structures 110, each of which includes therod 112, the light-emittinglayer 114, and the p-type semiconductor layer 116, are formed. The rod-shapedlayered structures 110 serve as a light-emitting part of the light-emitting element according to the present embodiment. - When the light-emitting
layer 114 and the p-type semiconductor layer 116 are formed on the lateral surfaces of a respective one of therods 112, the intervals ofadjacent rods 112 may affect growth rate of the light-emittinglayer 114 and the p-type semiconductor layer 116. The expression “intervals ofadjacent rods 112” used in the present specification refers to a distance between the centers of twoadjacent openings 108 a defined in the insulating film 108 (illustrated inFIG. 3 ) in a plan view. An expression “intervals of adjacent rod-shapedlayered structures 110” refers to similar configuration. When the plurality ofrods 112 are formed at substantially uniform intervals, the light-emittinglayer 114 and the p-type semiconductor layer 116 can be grown respectively at a substantially uniform growth rate. For example, in the step of forming an insulating film (S104) (illustrated inFIG. 3 ), theopenings 108 a can be defined in a right triangular grid in a plan view, which allows formation of therods 112 at substantially uniform intervals in the step of forming rods (S106). Further, a direction through the centers of theopenings 108 a in a plan view is preferably in parallel to the m-axis direction of the GaN-based crystals that form therods 112, that is, preferably in parallel to the a-axis of thesapphire substrate 102. With this arrangement, therods 112 having a hexagonal pyramid shape formed in a right triangular grid are adjacent one other with lateral surfaces facing substantially in parallel to each other. In this case, each of the light-emittinglayer 114 and the p-type semiconductor layer 116 can be formed at a substantially uniform growth rate on the lateral surfaces of each of therods 112, which allows for forming each of the light-emittinglayer 114 and the p-type semiconductor layer 116 with a substantially uniform thickness. - The distance between each two adjacent rods 112 (i.e., intervals of rods 112) affects the indium incorporation into the InGaN well layer of the
light emitting layer 114. When the InGaN well layer is formed with a supply of a source gas for In at a constant flow rate, the greater the distance between each twoadjacent rods 112, the greater amount of In incorporated into the InGaN well layer. The higher the content of In in the InGaN well layer, the longer wavelength side the wavelength of light emitted from the InGaN well layer. Accordingly, the rod-shapedlayered structures 110 configured to emit light of different wavelengths can be formed by adjusting the distance between each twoadjacent rods 112. For example, providing a group ofrods 112 formed with greater intervals, a group ofrods 112 formed with smaller intervals, and a group ofrods 112 formed with intermediate intervals on asingle substrate 102 allows for three regions of the rod-shaped layered structures, each configured to emit red light, green light, and blue light, respectively, formed on asingle substrate 102. - For example, by adjusting a thickness of each of the rod-shaped
layered structures 110 in a direction parallel to the main surface of the n-type semiconductor layer 106 (on which the rod-shapedlayered structures 110 are formed) within a range of 50 nm to 10 μm, and adjusting a distance between each two adjacent rod-shapedlayered structures 110 within a range of 75 nm to 200 μm, the rod-shapedlayered structures 110 configured to emit light of a desired wavelength can be obtained. The expression “thickness of rod-shapedlayered structure 110” refers to a maximum dimension of a width of cross section of the rod-shapedlayered structure 110. The expression “average thickness” refers to an average value of the thickness of ten rod-shapedlayered structures 110 that are adjacent to one other. Each of two adjacent rod-shapedlayered structures 110 are spaced apart from each other such that an electricallyconductive film 120, which will be described later in the specification, can be formed on the outer surfaces of the rod-shapedlayered structures 110. More specifically, the shortest distance between the outer surfaces of the adjacent rod-shapedlayered structures 110 can be adjusted within a range of 25 nm to 190 μm. The rod-shapedlayered structures 110 can have a height within a range of 1 to 100 μm. -
FIG. 8 is a cross-sectional view schematically showing a product at completion of a step S112 of forming an electrically conductive film (S112). In the step S112, an electricallyconductive film 120 covering a plurality of rod-shapedlayered structures 110 is formed. Examples of the electricallyconductive film 120 include an electrically conductive oxide film made of such as indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, or InGaZnO4, and Ag film. The electricallyconductive film 120 may be a single film or a multilayered film. - The description below illustrates forming of an ITO film as the electrically
conductive film 120. In a configuration in which light is extracted upward, it is advantageous that a material transmissive to light emitted to the rod-shapedlayered structures 110, such as an ITO, is used for the electricallyconductive film 120. For example, the electricallyconductive film 120 is formed by way of sputtering, without using a resist pattern. Accordingly, as shown inFIG. 8 , the electricallyconductive film 120 covers not only the outer surfaces of the rod-shapedlayered structures 110 but also continuously covers the upper surface of the insulatingfilm 108. When the p-type semiconductor layer 116 is a p-type nitride semiconductor layer, electric resistance is relatively higher than that of an n-type nitride semiconductor layer, such that the entire outer surfaces of the rod-shapedlayered structures 110 are preferably covered by the electricallyconductive film 120. With this arrangement, the electric current can be supplied to the entire portions of the p-type semiconductor layer 116 that forms the outer surfaces of the rod-shapedlayered structures 110, which allows emission of light from the entire outer surfaces of the rod-shapedlayered structures 110. - Therefore, it is preferable to form the electrically
conductive film 120 before the step of forming a photoresist pattern (S114). With this arrangement, the p-type semiconductor layer 116 can be protected against a developing solvent required to remove the photoresist pattern in a later step. In particular, when the p-type semiconductor layer 116 is a p-type nitride semiconductor layer, the concentration of the p-type dopant is generally high, which leads to a reduction in the quality of crystallinity, which causes the p-type semiconductor layer 116 to be susceptible to be etched by the developing solvent. By forming the electricallyconductive film 120 that covers the p-type semiconductor layer 116, before performing the step S114 of forming photoresist pattern, the p-type semiconductor layer 116 can be protected by the electricallyconductive film 120 in the step S114. -
FIG. 9 is a cross-sectional view schematically showing a product at completion of a step of forming a photoresist pattern: S114 according to one embodiment. In the step of forming a photoresist pattern (S114), aphotoresist pattern 130 covering a portion of the plurality of rod-shapedlayered structures 110 is formed. Thephotoresist pattern 130 includes first portions exposing a first portion of the plurality of rod-shapedlayered structures 110 that are to be removed in the step of removing rod-shaped layered structures (S118), and second portions covering a second portion of the plurality of rod-shapedlayered structures 110. The first portion of the plurality of rod-shapedlayered structures 110 to be removed in the step of removing rod-shaped layered structures (S118) is located in a region where an electrode to be formed, and the second portion of the plurality of rod-shapedlayered structures 110 covered by thephotoresist pattern 130 is configured to function as a light-emitting region of the light-emitting element. -
FIG. 10 is a cross-sectional view schematically showing a product at completion of a step of removing the insulating film (S116). In the step of removing the insulating film (S116), the electricallyconductive film 120 and the insulatingfilm 108 in the region that is not covered by thephotoresist pattern 130 are removed by etching. As shown inFIG. 10 , thenarrow base portions 112 a of the rod-shapedlayered structures 110 are exposed by removing the insulatingfilm 108. -
FIG. 11 is a cross-sectional view schematically showing a product at completion of a step of removing rod-shaped layered structures: S118. In the step of removing rod-shaped layered structures (S118), the first portion of the plurality of rod-shapedlayered structures 110 that is not covered by thephotoresist pattern 130 is removed. For example, the plurality of rod-shapedlayered structures 110 can be mechanically removed by using ultrasonic waves in water. In the present embodiment, the insulatingfilm 108 is removed prior to removing the rod-shapedlayered structures 110, which exposes thenarrow base portions 112 a of the rod-shapedlayered structures 110, which facilitates removing of the rod-shapedlayered structures 110. Accordingly, the rod-shapedlayered structures 110 can be more thoroughly removed at their base portions, compared to a conventional method in which the rod-shaped layered structures are removed before removing the insulating film. Further, according to the method as in the present embodiment, in which therods 112 are grown through openings of the insulatingfilm 108, the base portion of a respective one of therods 112 that is in the opening and surrounded by the insulatingfilm 108 is narrower compared to the portion grown above the opening. Accordingly, removing the insulatingfilm 108 to expose the narrow base portions, and then removing the rod-shapedlayered structures 110, can reduce time required to remove the rod-shapedlayered structures 110. - In the method of removing the rod-shaped
layered structures 110, wet etching may be performed and then the rod-shapedlayered structures 110 may be removed by using ultrasonic waves. When therods 112 have a hexagonal prism shape with the lateral surfaces of the m-plane, the lateral surfaces are not easily wet-etched. However, forming theopenings 108 a in a circular shape allows for forming of thebase portions 112 a in a columnar shape, which can be easily wet-etched. Wet-etching further narrows thebase portions 112 a in a columnar shape, and subsequent apply of ultrasonic waves can further reduce time required to remove the rod-shapedlayered structures 110. Wet etching can be performed, for example, by using tetramethylammonium hydroxide (TMAH). In the present embodiment, thenarrow base portions 112 a of the rod-shapedlayered structures 110 are exposed, allowing a reduction in time required for removing the rod-shapedlayered structures 110 even by using wet etching, compared to that by using a conventional method. - Further, when the first conductive-type semiconductor layer is the first-conductive-type nitride semiconductor layer and the upper surface is a (000-1) plane, it can be easily etched by using an etching solution such as TMAH for wet etching, compared to etching a (0001) plane. A long-time etching of a (000-1) plane may result in a rough surface, which may result in an inferior contact with the electrode. For this reason, when the first conductive-type semiconductor layer is the first conductive-type nitride semiconductor layer and the upper surface is a (000-1) plane, it is preferable not to use wet etching for removing the rod-shaped
layered structures 110, or to use wet etching in combination with ultrasonic treatment. - As described above, according to the present embodiment, the rod-shaped
layered structures 110 can be entirely removed respectively down to the bottom of the base portion. Nevertheless, removing the rod-shapedlayered structures 110 may cause some irregularities on the surface of the n-type semiconductor layer 106. When higher degree of flatness is required on the surface of the n-type semiconductor layer 106 after removing the rod-shapedlayered structures 110, the surface of the n-type semiconductor layer 106 may be subjected to etching to increase flatness. For this purpose, for example, a reactive ion etching (RIE) may be used.FIG. 11 is a cross-sectional view schematically showing a state in which flatness of the upper surface of the n-type semiconductor layer 106 has been improved by etching. Removing the rod-shapedlayered structures 110 produces rod-free regions on the upper surface of the n-type semiconductor layer 106, which includes a first region indicated by “A” and a second region indicated by “B”, as shown inFIG. 11 . -
FIG. 12 is a cross-sectional view schematically showing a product at completion of a step of forming a protective film (S120). In the step of forming a protective film (S120), the resistpattern 130 is removed, and an insulatingprotective film 140 is formed on exposed portions of the upper surface of the n-type semiconductor layer 106 in the second region B, continuously onto a portion of the remaining plurality of rod-shapedlayered structures 110. In the present embodiment, the electricallyconductive film 120 is formed on the outer surfaces of a respective one of the plurality of rod-shapedlayered structures 110, such that substantially the insulatingprotective film 140 is formed on the portions of the upper surface of the n-type semiconductor layer 106 exposed in the second region B, and continuously on portions of the electricallyconductive film 120 covering the outer surfaces of a portion of the plurality of rod-shapedlayered structures 110. - The
protective film 140 can be formed with an insulating member that is transmissive to light emitted from the rod-shapedlayered structures 110, for example, SiO2, SiN, Al2O3, or the like, can be used. As described above, the insulatingprotective film 140 is preferably formed on the portion of the upper surface of the n-type semiconductor layer 106 exposed adjacent to the remaining plurality of rod-shapedlayered structures 110, and continuously on portions of the outer surfaces of the electricallyconductive film 120 covering the rod-shapedlayered structures 110 located adjacent to the region B. Accordingly, the possibility of occurrence of short circuit between the n-type semiconductor layer 106 and the electricallyconductive film 120, caused by adhesion of dust or the like, may be reduced. -
FIG. 13 is a cross-sectional view schematically showing a product at completion of a step of forming a first electrode and a second electrode (S122) according to one embodiment. In the step of forming a first electrode and a second electrode (S122), afirst electrode 150 electrically connected to the n-type semiconductor layer 106 is formed on the upper surface of the n-type semiconductor layer 106 exposed in the first region A, and asecond electrode 160 electrically connected to the p-type semiconductor layer 116 and also extended onto a portion of the outer surface of theprotective film 140 in the second region B is formed. The expression “electrically connected to the p-type semiconductor layer 116” used above also refers to a case in which electrical connection to the p-type semiconductor layer 116 is through the electricallyconductive film 120, when the electricallyconductive film 120 is provided. - Examples of suitable materials of the
first electrode 150 and thesecond electrode 160 include a single metal such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr and W, and an alloy whose main component is one or more of those metals. For example, an electrode material layer can be formed by sequentially layering Ti and Au. Thefirst electrode 150 and thesecond electrode 160 can be discretely formed, but it is preferable to form thefirst electrode 150 and thesecond electrode 160 simultaneously using the same material, which allows a reduction in manufacturing time. - The
first electrode 150 and thesecond electrode 160 can be formed, for example, as described below. A resist pattern defining openings at predetermined locations for thefirst electrode 150 and thesecond electrode 160 is formed, then, using a vapor deposition method, a sputtering method, or the like, an electrode material layer for thefirst electrode 150 and thesecond electrode 160 is formed. Alternatively, a resist pattern defining an opening at a predetermined location for thefirst electrode 150 and thesecond electrode 160 may be formed. Subsequently, through lift-off, the resist pattern and the electrode material layer formed on the resist pattern are removed. Thus, as shown inFIG. 13 , thefirst electrode 150 and thesecond electrode 160 are formed to complete the light emitting element. - As described above, in the present embodiment, the insulating
film 108 is removed before removing the rod-shapedlayered structures 110. Accordingly, thebase portions 112 a of the rod-shapedlayered structures 110 are exposed, which facilitates removing of the rod-shapedlayered structures 110. This allows for more thorough removal of the rod-shapedlayered structures 110 respectively at the root of the base portion, and accordingly, the rod-shapedlayered structures 110 can be removed more completely, compared to the use of a conventional method in which the insulating film is removed after removing the rod-shapedlayered structures 110. - While embodiments of the present invention have been described, the technical scope of the present invention is not limited thereto. It will be apparent to those of ordinary skill in the art that various modifications and improvements may be applied to the embodiments described above, without departing from the technical scope of the present invention. All such modifications and improvements apparent to those skilled in the art are deemed to be within the scope of the disclosure as defined by the appended claims. For example, in the embodiments described above, “n-type” is indicated as “first conductive-type” and “p-type” is indicated as “second conductive-type”, but vice-versa, “p-type” may be indicated as “first conductive-type” and “n-type” may be indicated as “second conductive-type”. When a semiconductor material having a relatively low resistivity is used for the p-
type semiconductor layer 116, or when emission from the entire of the rod-shapedlayered structures 110 is not required, the electricallyconductive film 120 is not necessary. In the embodiments described above, the rods are formed after forming the insulating film, but the rods may be formed before forming the insulating film. For example, it may be such that growing the n-type semiconductor layer and disposing a mask of a plurality of dots on the surface of the n-type semiconductor layer, then etching is performed to create a plurality of rods corresponding to the mask, which exposes the n-type semiconductor layer around the rods, then, an insulating film is formed on the n-type semiconductor layer exposed around the rods. - Although the embodiments have been described in detail above for ease of understanding of the present invention, the present invention is not necessarily limited to one that has all the configurations described above. One or more components of the embodiments can be replaced by other components or can be omitted.
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