US20200111799A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20200111799A1 US20200111799A1 US16/191,413 US201816191413A US2020111799A1 US 20200111799 A1 US20200111799 A1 US 20200111799A1 US 201816191413 A US201816191413 A US 201816191413A US 2020111799 A1 US2020111799 A1 US 2020111799A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 125000006850 spacer group Chemical group 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 description 29
- 238000000034 method Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- H01L27/11206—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the invention relates to a method for fabricating semiconductor device, and more particularly, to a method of fabricating fuse structure of a dynamic random access memory (DRAM) device.
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- a DRAM unit with buried gate structure includes a transistor device and a charge storage element to receive electrical signals from bit lines and word lines.
- a transistor device to receive electrical signals from bit lines and word lines.
- current DRAM units with buried gate structures still pose numerous problems due to limited fabrication capability. Hence, how to effectively improve the performance and reliability of current DRAM device has become an important task in this field.
- a semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI.
- the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion.
- the semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.
- a semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI and extended into part of the STI and part of the substrate, wherein the first gate structure comprises a T-shape.
- first gate structure further includes a horizontal portion on the STI and part of the substrate and a vertical portion extended into part of the STI and part of the substrate.
- FIGS. 1-4 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention.
- FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- FIGS. 1-4 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention.
- a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and a memory region 14 and an active region 16 are defined on the substrate 12 .
- a shallow trench isolation (STI) 18 made of silicon oxide is formed in the substrate 12 on the memory region 14 and a well region such as n-well or p-well could be formed in the substrate 12 on the active region 16 .
- STI shallow trench isolation
- a gate structure is formed on the substrate 12 .
- the gate dielectric layer 20 is preferably made of silicon oxide
- the gate material layer 22 is made of doped polysilicon
- the hard mask 24 is made of silicon oxide or silicon nitride.
- bit line fabrication process it would then be desirable to conduct a bit line fabrication process on the memory region 14 by using a photo-etching process to remove part of the hard mask 24 , part of the gate material layer 22 , part of the gate dielectric layer 20 , part of the STI 18 , and part of the substrate 12 between the memory region 14 and active region 16 to form a trench (not shown).
- a material layer 26 preferably made of silicon is formed on the hard mask 24 to fill the trench completely, and a planarizing process such as chemical mechanical polishing (CMP) and/or etching process is conducted to remove all of the hard mask 24 and part of the material layer 26 to expose the top surface of the gate material layer 22 so that the top surface of the remaining material layer 26 is even with top surface of the gate material layer 22 .
- CMP chemical mechanical polishing
- the material layer 26 and the gate material layer 22 were made of same material such as polysilicon, the material layer 26 embedded within the trench and the gate material layer 22 are preferably united into one unit after the planarizing process.
- the material layer 26 and the gate material layer 22 could also be made of different materials, such as the material layer 26 could include amorphous silicon while the gate material layer 22 include polysilicon, which is also within the scope of the present invention.
- another hard mask 28 is formed to cover the surface of the gate material layer 22 on both memory region 14 and active region 16 , and a photo-etching process is conducted to remove part of the hard mask 28 , part of the gate material layer 22 , and part of the material layer 26 to form a first gate structure 30 on the memory region 14 and a second gate structure 32 on the active region 16 at the same time.
- an ion implantation process is conducted to form doped regions 34 or lightly doped drains (LDDs) in the substrate 12 adjacent to two sides of the second gate structure 32 , and then a spacer is formed on the sidewalls of each of the first gate structure 30 and second gate structure 32 , including a spacer 36 and spacer 38 on sidewalls of the first gate structure 30 and spacer 40 and spacer 42 on sidewalls of the second gate structure 32 .
- another ion implantation process is conducted to form doped regions 44 , 46 or source/drain regions in the substrate 12 adjacent to two sides of the spacers 36 , 38 .
- each of the spacers 36 , 38 , 40 , 42 could be a single spacer or a composite spacer including an offset spacer and a main spacer, in which the offset spacer and the main spacer could be made of same material or different materials while both types of spacers could be selected from the group consisting of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbon nitride (SiCN).
- Each of the doped regions 34 , 44 , 46 could include dopants and/or epitaxial materials having different conductive types depending on the type of transistor being fabricated.
- the doped regions 34 , 44 , 46 formed on the memory region 14 and active region 16 in this embodiment preferably includes n-type dopants and the concentration of the doped region 34 is preferably less than the concentration of doped regions 44 , 46 .
- the semiconductor device includes a STI 18 disposed in the substrate 12 , a first gate structure 30 disposed on the STI 18 , a second gate structure 32 disposed on the substrate 12 adjacent to the first gate structure 30 , a hard masks 28 disposed on each of the first gate structure 30 and second gate structure 32 , a spacer 36 disposed on a sidewall of the first gate structure 30 and on the STI 18 , a spacer 38 disposed on another sidewall of the first gate structure 30 , a spacer 40 disposed on a sidewall of the second gate structure 32 , and a spacer 42 disposed on another sidewall of the second gate structure 32 .
- the top surface of each of the spacers 36 , 38 , 40 , 42 is preferably even with the top surface of the hard masks 28 .
- the first gate structure 30 or gate electrode 54 further includes a first horizontal portion 48 disposed on the STI 18 , a vertical portion 50 connected to the first horizontal portion 48 and extended into part of the STI 18 , and a second horizontal portion 52 connected to the vertical portion 50 , in which the vertical portion 50 directly contacts the spacer 38 , the first horizontal portion 48 , vertical portion 50 , and second horizontal portion 52 are preferably made of same material such as polysilicon, and all three portions 48 , 50 , 52 are monolithically formed or formed in unity.
- the spacer 38 disposed on a sidewall of the first gate structure 30 is also disposed directly on top of the second horizontal portion 52 while the bottom or more specifically the bottommost surface of the spacer 38 is lower than the bottom (or bottommost) surface of the spacer 36 .
- the semiconductor device also includes a doped region 44 disposed on one side of the STI 18 , a doped region 46 disposed on another side of the STI 18 and directly contacting the second horizontal portion 52 , a doped region 34 disposed on one side of the second gate structure 32 and directly under the spacer 40 , and another doped region 34 disposed on another side of the second gate structure 32 and directly under the spacer 42 .
- the doped region 46 is disposed between the second horizontal portion 52 and the spacer 40 and directly contacting the second horizontal portion 52 and the doped region 34 and the concentration of the doped regions 34 is preferably lower than the concentration of doped regions 44 , 46 .
- FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the semiconductor device preferably includes a STI 18 disposed in the substrate 12 , a first gate structure 30 disposed on the STI 18 , a second gate structure 32 disposed on the substrate 12 adjacent to the first gate structure 30 , a hard masks 28 disposed on each of the first gate structure 30 and second gate structure 32 , a spacer 36 disposed on a sidewall of the first gate structure 30 and on the STI 18 , a spacer 38 disposed on another sidewall of the first gate structure 30 , a spacer 40 disposed on a sidewall of the second gate structure 32 , and a spacer 42 disposed on another sidewall of the second gate structure 32 .
- the top surface of each of the spacers 36 , 38 , 40 , 42 is preferably even with the top surface of the hard masks 28 .
- the first gate structure 30 or gate electrode 54 further includes a first horizontal portion 48 disposed on the STI 18 , a vertical portion 50 connected to the first horizontal portion 48 and extended into part of the STI 18 , and a second horizontal portion 52 connected to the vertical portion 50 , in which the vertical portion 50 directly contacts the spacer 38 , the first horizontal portion 48 , vertical portion 50 , and second horizontal portion 52 are preferably made of same material such as polysilicon, and all three portions 48 , 50 , 52 are monolithically formed or formed in unity.
- the spacer 38 adjacent to the vertical portion 50 in this embodiment is not only disposed on top of the second horizontal portion 52 but also extended to the right and standing on part of the substrate 12 .
- an additional doped region 56 is disposed in the substrate 12 directly under the spacer 38 , in which the doped region 56 is connected and directly contacting the doped region 46 on the right and the second horizontal portion 52 on the left, and the concentration of doped region 56 is preferably equal to the concentration of doped region 34 but lower than the concentration of doped regions 44 , 46 .
- FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the semiconductor device preferably includes a STI 18 disposed in the substrate 12 , a first gate structure 30 disposed on the STI 18 , a second gate structure 32 disposed on the substrate 12 adjacent to the first gate structure 30 , a hard masks 28 disposed on each of the first gate structure 30 and second gate structure 32 , a spacer 36 disposed on a sidewall of the first gate structure 30 and on the STI 18 , a spacer 38 disposed on another sidewall of the first gate structure 30 , a spacer 40 disposed on a sidewall of the second gate structure 32 , and a spacer 42 disposed on another sidewall of the second gate structure 32 .
- the top surface of each of the spacers 36 , 38 , 40 , 42 is preferably even with the top surface of the hard masks 28 .
- the first gate structure 30 in this embodiment is disposed on the STI 18 and extended downward into part of the STI 18 and part of the substrate 12 as the first gate structure 30 or gate electrode 54 includes a T-shape cross-section.
- the first gate structure 30 or gate electrode 54 includes a horizontal portion 58 disposed on the STI 18 and part of the substrate 12 and a vertical portion 60 extended into and directly contacting part of the STI 18 and part of the substrate 12 .
- the horizontal portion 58 and vertical portion 60 of the first gate structure 30 are preferably made of same material layer such as polysilicon as the two portions 58 , 60 are monolithically formed or formed in unity.
- a doped region 56 is disposed in the substrate 12 directly under the spacer 38 , in which edges of the doped region 56 could be aligned with inner and outer sidewalls of the spacer 38 , the doped region 56 is connected and directly contacting the doped region 46 on the right, and the concentration of the doped region 56 is equal to the concentration of doped region 34 but lower than the concentration of doped regions 44 , 46 .
- the doped region 56 could also be extended to the left to directly contact the vertical portion 60 so that signals could be transmitted from the gate electrode 54 of the first gate structure 30 to the second gate structure 32 through the substrate 12 .
- the present invention preferably connects the transistors on memory region to transistors on active region through doped regions within the substrate without forming any contact plug or metal interconnection on the doped region between the transistor on the memory region and the transistor on the active region.
- no contact plug is formed to directly contact the doped region 46 in the aforementioned embodiments so that the doped region 46 preferably remains floating.
- the doped region 46 shown in FIG. 4 and the doped regions 46 , 56 shown in FIGS. 5-6 are preferably used as bridges for signal transmission between transistor on the memory region 14 and transistor on the active region 16 .
Abstract
Description
- The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of fabricating fuse structure of a dynamic random access memory (DRAM) device.
- As electronic products develop toward the direction of miniaturization, the design of dynamic random access memory (DRAM) units also moves toward the direction of higher integration and higher density. Since the nature of a DRAM unit with buried gate structures has the advantage of possessing longer carrier channel length within a semiconductor substrate thereby reducing capacitor leakage, it has been gradually used to replace conventional DRAM unit with planar gate structures.
- Typically, a DRAM unit with buried gate structure includes a transistor device and a charge storage element to receive electrical signals from bit lines and word lines. Nevertheless, current DRAM units with buried gate structures still pose numerous problems due to limited fabrication capability. Hence, how to effectively improve the performance and reliability of current DRAM device has become an important task in this field.
- According to an embodiment of the present invention, a semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI. Preferably, the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion. The semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.
- According to another aspect of the present invention, a semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI and extended into part of the STI and part of the substrate, wherein the first gate structure comprises a T-shape. Preferably, first gate structure further includes a horizontal portion on the STI and part of the substrate and a vertical portion extended into part of the STI and part of the substrate.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-4 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. -
FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. -
FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. - Referring to
FIGS. 1-4 ,FIGS. 1-4 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown inFIG. 1 , asubstrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and amemory region 14 and anactive region 16 are defined on thesubstrate 12. Preferably, a shallow trench isolation (STI) 18 made of silicon oxide is formed in thesubstrate 12 on thememory region 14 and a well region such as n-well or p-well could be formed in thesubstrate 12 on theactive region 16. - Next, at least a gate structure is formed on the
substrate 12. For instance, it would be desirable to sequentially form a gatedielectric layer 20, agate material layer 22, and ahard mask 22 on thesubstrate 12 on bothmemory region 14 andactive region 16, in which the gatedielectric layer 20 is preferably made of silicon oxide, thegate material layer 22 is made of doped polysilicon, and the hard mask 24 is made of silicon oxide or silicon nitride. - Next, as shown in
FIG. 2 , it would then be desirable to conduct a bit line fabrication process on thememory region 14 by using a photo-etching process to remove part of the hard mask 24, part of thegate material layer 22, part of the gatedielectric layer 20, part of theSTI 18, and part of thesubstrate 12 between thememory region 14 andactive region 16 to form a trench (not shown). Next, amaterial layer 26 preferably made of silicon is formed on the hard mask 24 to fill the trench completely, and a planarizing process such as chemical mechanical polishing (CMP) and/or etching process is conducted to remove all of the hard mask 24 and part of thematerial layer 26 to expose the top surface of thegate material layer 22 so that the top surface of theremaining material layer 26 is even with top surface of thegate material layer 22. - According to an embodiment of the present invention, if the
material layer 26 and thegate material layer 22 were made of same material such as polysilicon, thematerial layer 26 embedded within the trench and thegate material layer 22 are preferably united into one unit after the planarizing process. Nevertheless, according to another embodiment of the present invention, thematerial layer 26 and thegate material layer 22 could also be made of different materials, such as thematerial layer 26 could include amorphous silicon while thegate material layer 22 include polysilicon, which is also within the scope of the present invention. - Next, as shown in
FIG. 3 , anotherhard mask 28 is formed to cover the surface of thegate material layer 22 on bothmemory region 14 andactive region 16, and a photo-etching process is conducted to remove part of thehard mask 28, part of thegate material layer 22, and part of thematerial layer 26 to form afirst gate structure 30 on thememory region 14 and asecond gate structure 32 on theactive region 16 at the same time. It should be noted that when an etching process is conducted to remove part of thegate material layer 22 to form thefirst gate structure 30 andsecond gate structure 32 at this stage, it would be desirable to over-etch part of thematerial layer 26 between thememory region 14 and active region 16 (or more specifically the intersecting point of thememory region 14 and active region 16) so that a top surface between thememory region 14 andactive region 16 is slightly lower than the top surface of theSTI 18 andsubstrate 12. - Next, as shown in
FIG. 4 , an ion implantation process is conducted to form dopedregions 34 or lightly doped drains (LDDs) in thesubstrate 12 adjacent to two sides of thesecond gate structure 32, and then a spacer is formed on the sidewalls of each of thefirst gate structure 30 andsecond gate structure 32, including aspacer 36 andspacer 38 on sidewalls of thefirst gate structure 30 andspacer 40 andspacer 42 on sidewalls of thesecond gate structure 32. Next, another ion implantation process is conducted to form dopedregions substrate 12 adjacent to two sides of thespacers - In this embodiment, each of the
spacers doped regions doped regions memory region 14 andactive region 16 in this embodiment preferably includes n-type dopants and the concentration of thedoped region 34 is preferably less than the concentration of dopedregions - Referring again to
FIG. 4 , which further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 4 , the semiconductor device includes aSTI 18 disposed in thesubstrate 12, afirst gate structure 30 disposed on theSTI 18, asecond gate structure 32 disposed on thesubstrate 12 adjacent to thefirst gate structure 30, ahard masks 28 disposed on each of thefirst gate structure 30 andsecond gate structure 32, aspacer 36 disposed on a sidewall of thefirst gate structure 30 and on theSTI 18, aspacer 38 disposed on another sidewall of thefirst gate structure 30, aspacer 40 disposed on a sidewall of thesecond gate structure 32, and aspacer 42 disposed on another sidewall of thesecond gate structure 32. The top surface of each of thespacers hard masks 28. - Viewing from a more detailed perspective, the
first gate structure 30 orgate electrode 54 further includes a firsthorizontal portion 48 disposed on theSTI 18, avertical portion 50 connected to the firsthorizontal portion 48 and extended into part of theSTI 18, and a secondhorizontal portion 52 connected to thevertical portion 50, in which thevertical portion 50 directly contacts thespacer 38, the firsthorizontal portion 48,vertical portion 50, and secondhorizontal portion 52 are preferably made of same material such as polysilicon, and all threeportions spacer 38 disposed on a sidewall of thefirst gate structure 30 is also disposed directly on top of the secondhorizontal portion 52 while the bottom or more specifically the bottommost surface of thespacer 38 is lower than the bottom (or bottommost) surface of thespacer 36. - The semiconductor device also includes a
doped region 44 disposed on one side of theSTI 18, adoped region 46 disposed on another side of theSTI 18 and directly contacting the secondhorizontal portion 52, adoped region 34 disposed on one side of thesecond gate structure 32 and directly under thespacer 40, and anotherdoped region 34 disposed on another side of thesecond gate structure 32 and directly under thespacer 42. Preferably, thedoped region 46 is disposed between the secondhorizontal portion 52 and thespacer 40 and directly contacting the secondhorizontal portion 52 and thedoped region 34 and the concentration of thedoped regions 34 is preferably lower than the concentration of dopedregions - Referring to
FIG. 5 ,FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 5 , the semiconductor device preferably includes aSTI 18 disposed in thesubstrate 12, afirst gate structure 30 disposed on theSTI 18, asecond gate structure 32 disposed on thesubstrate 12 adjacent to thefirst gate structure 30, ahard masks 28 disposed on each of thefirst gate structure 30 andsecond gate structure 32, aspacer 36 disposed on a sidewall of thefirst gate structure 30 and on theSTI 18, aspacer 38 disposed on another sidewall of thefirst gate structure 30, aspacer 40 disposed on a sidewall of thesecond gate structure 32, and aspacer 42 disposed on another sidewall of thesecond gate structure 32. The top surface of each of thespacers hard masks 28. - Similar to the aforementioned embodiments, the
first gate structure 30 orgate electrode 54 further includes a firsthorizontal portion 48 disposed on theSTI 18, avertical portion 50 connected to the firsthorizontal portion 48 and extended into part of theSTI 18, and a secondhorizontal portion 52 connected to thevertical portion 50, in which thevertical portion 50 directly contacts thespacer 38, the firsthorizontal portion 48,vertical portion 50, and secondhorizontal portion 52 are preferably made of same material such as polysilicon, and all threeportions spacer 38 from the previous embodiment is completely disposed on top of the secondhorizontal portion 52, thespacer 38 adjacent to thevertical portion 50 in this embodiment is not only disposed on top of the secondhorizontal portion 52 but also extended to the right and standing on part of thesubstrate 12. Moreover, an additionaldoped region 56 is disposed in thesubstrate 12 directly under thespacer 38, in which thedoped region 56 is connected and directly contacting thedoped region 46 on the right and the secondhorizontal portion 52 on the left, and the concentration ofdoped region 56 is preferably equal to the concentration ofdoped region 34 but lower than the concentration ofdoped regions - Referring to
FIG. 6 ,FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 6 , the semiconductor device preferably includes aSTI 18 disposed in thesubstrate 12, afirst gate structure 30 disposed on theSTI 18, asecond gate structure 32 disposed on thesubstrate 12 adjacent to thefirst gate structure 30, ahard masks 28 disposed on each of thefirst gate structure 30 andsecond gate structure 32, aspacer 36 disposed on a sidewall of thefirst gate structure 30 and on theSTI 18, aspacer 38 disposed on another sidewall of thefirst gate structure 30, aspacer 40 disposed on a sidewall of thesecond gate structure 32, and aspacer 42 disposed on another sidewall of thesecond gate structure 32. The top surface of each of thespacers hard masks 28. - In contrast to the
first gate structure 30 from the aforementioned embodiments including two horizontal portions and a vertical portion, thefirst gate structure 30 in this embodiment is disposed on theSTI 18 and extended downward into part of theSTI 18 and part of thesubstrate 12 as thefirst gate structure 30 orgate electrode 54 includes a T-shape cross-section. Viewing from a more detailed perspective, thefirst gate structure 30 orgate electrode 54 includes ahorizontal portion 58 disposed on theSTI 18 and part of thesubstrate 12 and avertical portion 60 extended into and directly contacting part of theSTI 18 and part of thesubstrate 12. Similar to the aforementioned embodiments, thehorizontal portion 58 andvertical portion 60 of thefirst gate structure 30 are preferably made of same material layer such as polysilicon as the twoportions doped region 56 is disposed in thesubstrate 12 directly under thespacer 38, in which edges of thedoped region 56 could be aligned with inner and outer sidewalls of thespacer 38, thedoped region 56 is connected and directly contacting thedoped region 46 on the right, and the concentration of thedoped region 56 is equal to the concentration of dopedregion 34 but lower than the concentration ofdoped regions doped region 56 does not contact thevertical portion 60 directly in this embodiment, according to other embodiment of the present invention, thedoped region 56 could also be extended to the left to directly contact thevertical portion 60 so that signals could be transmitted from thegate electrode 54 of thefirst gate structure 30 to thesecond gate structure 32 through thesubstrate 12. - Overall, in contrast to connecting the transistor on memory region to transistors on active region through higher level metal interconnections, the present invention preferably connects the transistors on memory region to transistors on active region through doped regions within the substrate without forming any contact plug or metal interconnection on the doped region between the transistor on the memory region and the transistor on the active region. For instance, no contact plug is formed to directly contact the
doped region 46 in the aforementioned embodiments so that thedoped region 46 preferably remains floating. Specifically, thedoped region 46 shown inFIG. 4 and thedoped regions FIGS. 5-6 are preferably used as bridges for signal transmission between transistor on thememory region 14 and transistor on theactive region 16. By using this design it would be desirable to relax the pitch of metal interconnections in the entire area as bit line voltages are applied in the memory region. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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US8716828B2 (en) * | 2008-08-27 | 2014-05-06 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner |
US9659943B1 (en) * | 2016-03-08 | 2017-05-23 | Globalfoundries Singapore Pte. Ltd. | Programmable integrated circuits and methods of forming the same |
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US8716828B2 (en) * | 2008-08-27 | 2014-05-06 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner |
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