US20200083215A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20200083215A1 US20200083215A1 US16/255,949 US201916255949A US2020083215A1 US 20200083215 A1 US20200083215 A1 US 20200083215A1 US 201916255949 A US201916255949 A US 201916255949A US 2020083215 A1 US2020083215 A1 US 2020083215A1
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- Prior art keywords
- semiconductor layer
- electrode
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 198
- 239000012535 impurity Substances 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 10
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000012216 screening Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Definitions
- Embodiments relate to a semiconductor device.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- FIGS. 1A and 1B are schematic views showing a semiconductor device according to an embodiment
- FIG. 2 is a circuit diagram showing the semiconductor device according to the embodiment
- FIGS. 3A and 3B are schematic views showing the mounted configuration of the semiconductor device according to the embodiment.
- FIG. 4 is a schematic view showing a semiconductor device according to a modification of the embodiment.
- FIGS. 5A and 5B are schematic views showing a semiconductor device according to other modification of the embodiment
- a semiconductor device includes a semiconductor body, first to third electrodes and a control electrode.
- the first electrode is provided on the semiconductor body.
- the second electrode is provided on the semiconductor body with a first insulating film interposed.
- the second electrode is provided at a position surrounded with the first electrode when viewed from above, and is separated from the first electrode.
- the third electrode is provided on the semiconductor body at a position surrounded with the second electrode when viewed from above, and is separated from the second electrode.
- the control electrode is provided between the semiconductor body and the first electrode.
- the control electrode is electrically connected to the second electrode.
- the control electrode is electrically insulated from the semiconductor body with a second insulating film interposed, and is electrically insulated from the first electrode with a third insulating film interposed.
- the semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type.
- the second semiconductor layer is selectively provided between the first semiconductor layer and the first electrode.
- the third semiconductor layer is selectively provided between the second semiconductor layer and the first electrode.
- the third semiconductor layer is electrically connected to the first electrode.
- the fourth semiconductor layer includes a major portion and an outer edge portion. The major portion is provided between the first semiconductor layer and the second electrode and between the first semiconductor layer and the third electrode. The outer edge portion is provided between the first semiconductor layer and the first electrode.
- the fifth semiconductor layer is selectively provided in the fourth semiconductor layer.
- the fifth semiconductor layer is positioned between the outer edge portion of the fourth semiconductor layer and the first electrode, and includes a portion electrically connected to the first electrode.
- the sixth semiconductor layer is provided at a position away from the fifth semiconductor layer in the fourth semiconductor layer.
- the sixth semiconductor layer is positioned between the major portion of the fourth semiconductor layer and the third electrode, and includes a portion electrically connected to the third electrode.
- the control electrode is disposed at a position capable of facing the first semiconductor layer, the second semiconductor layer and the third semiconductor layer with the second insulating film interposed.
- FIGS. 1A and 1B are schematic views showing a semiconductor device 1 according to an embodiment.
- FIG. 1A is a schematic view showing a cross section along line A-A shown in FIG. 1B .
- FIG. 1B is a plan view showing a portion of the upper surface of the semiconductor device 1 .
- the semiconductor device 1 is, for example, a MOSFET.
- the semiconductor device 1 is not limited to this example, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor).
- the semiconductor device 1 includes a semiconductor body 10 , a drain electrode 20 , a source electrode 30 , and a gate electrode 40 .
- the semiconductor body 10 includes a transistor region TRR and a protection element region PER.
- the transistor region TRR is a region operating as a MOSFET; and the gate electrode 40 is disposed on the transistor region TRR.
- the protection element region PER includes, for example, a protection element preventing an overvoltage from being applied to the MOSFET.
- the drain electrode 20 is provided on the back surface of the semiconductor body 10 .
- the source electrode 30 is provided on the transistor region TRR.
- the gate electrode 40 is disposed between the transistor region TRR and the source electrode 30 .
- the semiconductor body 10 includes, for example, an n-type drift layer 11 , an n-type drain layer 13 , a p-type diffusion layer 15 , an n-type source layer 17 , and a p-type contact layer 19 .
- the n-type drain layer 13 is provided between the n-type drift layer 11 and the drain electrode 20 .
- the n-type drain layer 13 contacts the drain electrode 20 and includes an n-type impurity having a higher concentration than a concentration of the n-type impurity of the n-type drift layer 11 .
- the p-type diffusion layer 15 is provided between the n-type drift layer 11 and the source electrode 30 , and contacts, for example, the n-type drift layer 11 .
- a p-n junction is formed between the n-type drift layer 11 and the p-type diffusion layer 15 .
- the n-type source layer 17 is selectively provided between the p-type diffusion layer 15 and the source electrode 30 , and contacts the p-type diffusion layer 15 .
- the n-type source layer 17 is electrically connected to the source electrode 30 .
- the n-type source layer 17 includes an n-type impurity having a higher concentration than a concentration of the n-type impurity of the n-type drift layer 11 .
- the p-type contact layer 19 is selectively provided between the p-type diffusion layer 15 and the source electrode 30 , and is electrically connected to the p-type diffusion layer 15 and the source electrode 30 .
- the n-type source layer 17 and the p-type diffusion layer 15 are arranged in a direction along the front surface of the semiconductor body 10 .
- the p-type contact layer 19 includes a p-type impurity having a higher concentration than a concentration of the p-type impurity of the p-type diffusion layer 15 .
- the gate electrode 40 is disposed to face a portion of the n-type drift layer 11 , a portion of the p-type diffusion layer 15 , and a portion of the n-type source layer 17 with a gate insulating film 45 interposed. Also, the gate electrode 40 is electrically insulated from the source electrode 30 by an insulating film 47 . For example, the gate electrodes 40 are disposed to be away from each other in the X-direction; and the source electrode 30 is electrically connected to the n-type source layer 17 and the p-type contact layer 19 exposed between the mutually-adjacent gate electrodes 40 .
- the semiconductor device 1 further includes a gate pad 50 and a contact pad 60 .
- the gate pad 50 is provided on the protection element region PER with an insulating film 55 interposed.
- the gate pad 50 is electrically connected to the gate electrode 40 at a not-illustrated portion, and is electrically insulated from the semiconductor body 10 by the insulating film 55 .
- the semiconductor body 10 further includes a p-type semiconductor layer 21 , an n-type semiconductor layer 23 , and an n-type semiconductor layer 25 .
- the p-type semiconductor layer 21 is formed simultaneously with the p-type diffusion layer 15 , and includes a p-type impurity having the same concentration level as the p-type impurity of the p-type diffusion layer 15 .
- the n-type semiconductor layer 23 and the n-type semiconductor layer 25 are formed simultaneously with the n-type source layer 17 and include n-type impurities having the same concentration level as the n-type impurity of the n-type source layer 17 .
- the p-type semiconductor layer 21 is provided between the n-type drift layer 11 and the gate pad 50 and between the n-type drift layer 11 and the contact pad 60 . Also, the p-type semiconductor layer 21 includes a portion positioned between the n-type drift layer 11 and the source electrode 30 .
- the n-type semiconductor layer 23 is selectively provided inside the p-type semiconductor layer 21 , and is electrically connected to the source electrode 30 .
- the p-type semiconductor layer 21 includes a portion positioned between the n-type drift layer 11 and the source electrode 30 ; and the n-type semiconductor layer 23 is provided between the portion of the p-type semiconductor layer 21 and the source electrode 30 .
- the n-type semiconductor layer 23 is provided to be exposed at the bottom surface of a contact hole 57 provided in the insulating film 55 , and is electrically connected to a portion of the source electrode 30 extending into the contact hole 57 .
- the n-type semiconductor layer 25 is selectively provided in the p-type semiconductor layer 21 .
- the n-type semiconductor layer 25 is positioned between the p-type semiconductor layer 21 and the contact pad 60 , and is exposed at the front surface of the semiconductor body 10 .
- the n-type semiconductor layer 25 is exposed at the bottom surface of a contact hole 59 provided in the insulating film 55 ; and the contact pad 60 is electrically connected to the n-type semiconductor layer 25 via a portion extending into the contact hole 59 .
- the gate pad 50 is provided at a position surrounded with the source electrode 30 when viewed from above.
- the gate pad 50 includes an interconnect portion 50 f extending outside the source electrode 30 .
- the interconnect portion 50 f is electrically connected to the gate electrode 40 at a portion not-illustrated.
- the gate pad 50 is provided to be separated from the source electrode 30 , and is electrically insulated from the source electrode 30 .
- the contact pad 60 is provided to be separated from the gate pad 50 at the inner side of the gate pad 50 .
- a space is provided between the gate pad 50 and the contact pad 60 ; and the contact pad 60 is electrically insulated from the gate pad 50 .
- the n-type semiconductor layer 23 is disposed to surround the gate pad 50 when viewed from above.
- the n-type semiconductor layer 25 is provided to be positioned at the center of the gate pad 50 when viewed from above.
- the contact pad 60 is provided to be positioned at the center of the n-type semiconductor layer 25 when viewed from above.
- FIG. 2 is a circuit diagram showing the semiconductor device 1 according to the embodiment.
- the semiconductor device 1 includes the drain electrode 20 connected to the drain of the MOSFET, the source electrode 30 connected to the source thereof, and the gate pad 50 connected to the gate electrode 40 .
- the source electrode 30 is connected also to the back gate of the MOSFET.
- the source electrode 30 is connected to the p-type diffusion layer 15 via the p-type contact layer 19 (referring to FIG. 1A ).
- a screening voltage can be applied to the gate insulating film 45 via the source electrode 30 and the gate pad 50 .
- the source electrode 30 is connected to the contact pad 60 via a protection element PE.
- the protection element PE is, for example, a constant voltage element (e.g., a Zener diode) including the p-type semiconductor layer 21 , the n-type semiconductor layer 23 , and the n-type semiconductor layer 25 .
- semiconductor elements that include defects of the gate insulating film 45 are removed by screening in which a prescribed voltage is applied between the source electrode 30 and the gate pad 50 . Subsequently, the gate pad 50 and the contact pad 60 are electrically connected. Thereby, it is possible to prevent a voltage higher than the breakdown voltage of the protection element PE from being applied to the gate insulating film 45 . As a result, the damage of the gate insulating film 45 can be avoided; and the reliability can be increased.
- the breakdown voltage of the protection element PE can be controlled by a spacing LD between the n-type semiconductor layer 23 and the n-type semiconductor layer 25 (referring to FIG. 1A ).
- FIGS. 3A and 3B are schematic views showing the mounted configuration of the semiconductor device 1 according to the embodiment.
- FIG. 3A is a schematic view showing a portion of the upper surface of the semiconductor device 1 .
- FIG. 3B is a schematic view showing a cross section of the semiconductor device 1 .
- bonding wires (hereinbelow, metal wires 73 and 75 ) are bonded respectively on the source electrode 30 and the gate pad 50 .
- the metal wire 73 electrically connects the source electrode 30 and a ground terminal (not illustrated) of a mounting substrate.
- the metal wire 75 electrically connects the gate pad 50 and a gate terminal (not illustrated) of the mounting substrate.
- the metal wire 75 may connect the gate pad 50 to a gate circuit (not illustrated) provided on the mounting substrate.
- the contact pad 60 is positioned under the end portion of the metal wire 75 electrically connected to the gate pad 50 .
- the size of the contact pad 60 in the X-direction and the Y-direction is smaller than the size of the end portion of the metal wire 75 .
- the metal wire 75 is bonded to electrically connect the gate pad 50 to the external terminal or circuit and to be electrically connected to the contact pad 60 .
- the gate pad 50 and the contact pad 60 can be electrically connected merely by bonding the metal wire 75 on the gate pad 50 .
- the embodiment is not limited to a metal wire; for example, other bonded configuration may be used in which the gate pad and an external lead are connected using a connector.
- FIG. 4 is a schematic view showing a semiconductor device 2 according to a modification of the embodiment.
- FIG. 4 is a plan view showing a portion of the upper surface of the semiconductor device 2 .
- the semiconductor device 2 includes multiple contact pads 60 .
- the contact pads 60 each are disposed at positions surrounded with the gate pad 50 .
- the contact pads 60 are provided to be separated from the gate pad 50 and are electrically insulated from the gate pad 50 .
- the multiple contact pads 60 are electrically connected to the n-type semiconductor layer 25 (referring to FIG. 1A ).
- the gate pad 50 is electrically connected to one of the multiple contact pads 60 .
- FIGS. 5A and 5B are schematic views showing a semiconductor device 3 according to other modification of the embodiment.
- FIG. 5A is a schematic view showing a cross section of the semiconductor device 3 .
- FIG. 5B is a plan view showing a portion of the upper surface of the semiconductor device 3 .
- a p-type semiconductor layer 27 and an n-type semiconductor layer 29 are arranged alternately between the n-type semiconductor layer 23 and the n-type semiconductor layer 25 .
- the p-type semiconductor layer 27 and the n-type semiconductor layer 29 are selectively provided in the p-type semiconductor layer 21 .
- the p-type semiconductor layer 27 includes a p-type impurity having a higher concentration than a concentration of the p-type impurity in the p-type semiconductor layer 21 .
- the n-type semiconductor layer 23 is disposed to surround the gate pad 50 when viewed in the Z-direction. Also, the n-type semiconductor layer 25 is disposed at the center of the gate pad 50 . The p-type semiconductor layer 27 and the n-type semiconductor layer 29 each are provided to surround the n-type semiconductor layer 25 .
- the protection element PE (referring to FIG. 2 ) includes the n-type semiconductor layers 23 , 25 , and 29 and the p-type semiconductor layer 27 .
- the breakdown voltage of the protection element PE can be controlled by disposing the appropriate number of p-type semiconductor layers 27 and n-type semiconductor layers 29 between the n-type semiconductor layer 23 and the n-type semiconductor layer 25 .
- the protection element PE according to the embodiment is not limited to the example recited above; and it is sufficient for the protection element PE to have a configuration electrically connected to the source electrode 30 and the contact pad 60 and not to affect the operations of the transistor region TRR.
Abstract
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-168849, filed on Sep. 10, 2018; the entire contents of which are incorporated herein by reference.
- Embodiments relate to a semiconductor device.
- In the manufacturing processes of a semiconductor device, it is preferable to perform early-failure screening to avoid random failures during practical use. For example, it is possible in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to remove early failures of the gate insulating film by applying a high voltage between the gate electrode and the back gate exceeding the gate voltage rating. However, when the device is maintained to have the structure capable of applying the high voltage to the gate insulating film, it is not possible to prevent the gate insulating film from receiving damage due to a high voltage exceeding the rating that is applied thereto after the screening.
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FIGS. 1A and 1B are schematic views showing a semiconductor device according to an embodiment; -
FIG. 2 is a circuit diagram showing the semiconductor device according to the embodiment; -
FIGS. 3A and 3B are schematic views showing the mounted configuration of the semiconductor device according to the embodiment; -
FIG. 4 is a schematic view showing a semiconductor device according to a modification of the embodiment; and -
FIGS. 5A and 5B are schematic views showing a semiconductor device according to other modification of the embodiment - According to one embodiment, a semiconductor device includes a semiconductor body, first to third electrodes and a control electrode. The first electrode is provided on the semiconductor body. The second electrode is provided on the semiconductor body with a first insulating film interposed. The second electrode is provided at a position surrounded with the first electrode when viewed from above, and is separated from the first electrode. The third electrode is provided on the semiconductor body at a position surrounded with the second electrode when viewed from above, and is separated from the second electrode. The control electrode is provided between the semiconductor body and the first electrode. The control electrode is electrically connected to the second electrode. The control electrode is electrically insulated from the semiconductor body with a second insulating film interposed, and is electrically insulated from the first electrode with a third insulating film interposed. The semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer is selectively provided between the first semiconductor layer and the first electrode. The third semiconductor layer is selectively provided between the second semiconductor layer and the first electrode. The third semiconductor layer is electrically connected to the first electrode. The fourth semiconductor layer includes a major portion and an outer edge portion. The major portion is provided between the first semiconductor layer and the second electrode and between the first semiconductor layer and the third electrode. The outer edge portion is provided between the first semiconductor layer and the first electrode. The fifth semiconductor layer is selectively provided in the fourth semiconductor layer. The fifth semiconductor layer is positioned between the outer edge portion of the fourth semiconductor layer and the first electrode, and includes a portion electrically connected to the first electrode. The sixth semiconductor layer is provided at a position away from the fifth semiconductor layer in the fourth semiconductor layer. The sixth semiconductor layer is positioned between the major portion of the fourth semiconductor layer and the third electrode, and includes a portion electrically connected to the third electrode. The control electrode is disposed at a position capable of facing the first semiconductor layer, the second semiconductor layer and the third semiconductor layer with the second insulating film interposed.
- Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
- There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.
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FIGS. 1A and 1B are schematic views showing asemiconductor device 1 according to an embodiment.FIG. 1A is a schematic view showing a cross section along line A-A shown inFIG. 1B .FIG. 1B is a plan view showing a portion of the upper surface of thesemiconductor device 1. Thesemiconductor device 1 is, for example, a MOSFET. Thesemiconductor device 1 is not limited to this example, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor). - As shown in
FIG. 1A , thesemiconductor device 1 includes asemiconductor body 10, adrain electrode 20, asource electrode 30, and agate electrode 40. Thesemiconductor body 10 includes a transistor region TRR and a protection element region PER. Here, for example, the transistor region TRR is a region operating as a MOSFET; and thegate electrode 40 is disposed on the transistor region TRR. The protection element region PER includes, for example, a protection element preventing an overvoltage from being applied to the MOSFET. - The
drain electrode 20 is provided on the back surface of thesemiconductor body 10. Thesource electrode 30 is provided on the transistor region TRR. For example, thegate electrode 40 is disposed between the transistor region TRR and thesource electrode 30. - The
semiconductor body 10 includes, for example, an n-type drift layer 11, an n-type drain layer 13, a p-type diffusion layer 15, an n-type source layer 17, and a p-type contact layer 19. - The n-
type drain layer 13 is provided between the n-type drift layer 11 and thedrain electrode 20. The n-type drain layer 13 contacts thedrain electrode 20 and includes an n-type impurity having a higher concentration than a concentration of the n-type impurity of the n-type drift layer 11. - The p-
type diffusion layer 15 is provided between the n-type drift layer 11 and thesource electrode 30, and contacts, for example, the n-type drift layer 11. A p-n junction is formed between the n-type drift layer 11 and the p-type diffusion layer 15. The n-type source layer 17 is selectively provided between the p-type diffusion layer 15 and thesource electrode 30, and contacts the p-type diffusion layer 15. The n-type source layer 17 is electrically connected to thesource electrode 30. The n-type source layer 17 includes an n-type impurity having a higher concentration than a concentration of the n-type impurity of the n-type drift layer 11. The p-type contact layer 19 is selectively provided between the p-type diffusion layer 15 and thesource electrode 30, and is electrically connected to the p-type diffusion layer 15 and thesource electrode 30. - The n-
type source layer 17 and the p-type diffusion layer 15 are arranged in a direction along the front surface of thesemiconductor body 10. The p-type contact layer 19 includes a p-type impurity having a higher concentration than a concentration of the p-type impurity of the p-type diffusion layer 15. - The
gate electrode 40 is disposed to face a portion of the n-type drift layer 11, a portion of the p-type diffusion layer 15, and a portion of the n-type source layer 17 with agate insulating film 45 interposed. Also, thegate electrode 40 is electrically insulated from thesource electrode 30 by an insulatingfilm 47. For example, thegate electrodes 40 are disposed to be away from each other in the X-direction; and thesource electrode 30 is electrically connected to the n-type source layer 17 and the p-type contact layer 19 exposed between the mutually-adjacent gate electrodes 40. - The
semiconductor device 1 further includes agate pad 50 and acontact pad 60. Thegate pad 50 is provided on the protection element region PER with an insulatingfilm 55 interposed. Thegate pad 50 is electrically connected to thegate electrode 40 at a not-illustrated portion, and is electrically insulated from thesemiconductor body 10 by the insulatingfilm 55. - The
semiconductor body 10 further includes a p-type semiconductor layer 21, an n-type semiconductor layer 23, and an n-type semiconductor layer 25. For example, the p-type semiconductor layer 21 is formed simultaneously with the p-type diffusion layer 15, and includes a p-type impurity having the same concentration level as the p-type impurity of the p-type diffusion layer 15. For example, the n-type semiconductor layer 23 and the n-type semiconductor layer 25 are formed simultaneously with the n-type source layer 17 and include n-type impurities having the same concentration level as the n-type impurity of the n-type source layer 17. - The p-
type semiconductor layer 21 is provided between the n-type drift layer 11 and thegate pad 50 and between the n-type drift layer 11 and thecontact pad 60. Also, the p-type semiconductor layer 21 includes a portion positioned between the n-type drift layer 11 and thesource electrode 30. - The n-
type semiconductor layer 23 is selectively provided inside the p-type semiconductor layer 21, and is electrically connected to thesource electrode 30. The p-type semiconductor layer 21 includes a portion positioned between the n-type drift layer 11 and thesource electrode 30; and the n-type semiconductor layer 23 is provided between the portion of the p-type semiconductor layer 21 and thesource electrode 30. The n-type semiconductor layer 23 is provided to be exposed at the bottom surface of acontact hole 57 provided in the insulatingfilm 55, and is electrically connected to a portion of thesource electrode 30 extending into thecontact hole 57. - The n-
type semiconductor layer 25 is selectively provided in the p-type semiconductor layer 21. The n-type semiconductor layer 25 is positioned between the p-type semiconductor layer 21 and thecontact pad 60, and is exposed at the front surface of thesemiconductor body 10. The n-type semiconductor layer 25 is exposed at the bottom surface of acontact hole 59 provided in the insulatingfilm 55; and thecontact pad 60 is electrically connected to the n-type semiconductor layer 25 via a portion extending into thecontact hole 59. - As shown in
FIG. 1B , for example, thegate pad 50 is provided at a position surrounded with thesource electrode 30 when viewed from above. Thegate pad 50 includes aninterconnect portion 50 f extending outside thesource electrode 30. Theinterconnect portion 50 f is electrically connected to thegate electrode 40 at a portion not-illustrated. Thegate pad 50 is provided to be separated from thesource electrode 30, and is electrically insulated from thesource electrode 30. - The
contact pad 60 is provided to be separated from thegate pad 50 at the inner side of thegate pad 50. A space is provided between thegate pad 50 and thecontact pad 60; and thecontact pad 60 is electrically insulated from thegate pad 50. - For example, the n-
type semiconductor layer 23 is disposed to surround thegate pad 50 when viewed from above. Also, the n-type semiconductor layer 25 is provided to be positioned at the center of thegate pad 50 when viewed from above. For example, thecontact pad 60 is provided to be positioned at the center of the n-type semiconductor layer 25 when viewed from above. -
FIG. 2 is a circuit diagram showing thesemiconductor device 1 according to the embodiment. As shown inFIG. 2 , thesemiconductor device 1 includes thedrain electrode 20 connected to the drain of the MOSFET, thesource electrode 30 connected to the source thereof, and thegate pad 50 connected to thegate electrode 40. - The
source electrode 30 is connected also to the back gate of the MOSFET. In other words, thesource electrode 30 is connected to the p-type diffusion layer 15 via the p-type contact layer 19 (referring toFIG. 1A ). Thereby, it is possible to apply voltage stress to thegate insulating film 45 by applying a voltage between thesource electrode 30 and thegate pad 50. In other words, in thesemiconductor device 1, a screening voltage can be applied to thegate insulating film 45 via thesource electrode 30 and thegate pad 50. - Further, the
source electrode 30 is connected to thecontact pad 60 via a protection element PE. The protection element PE is, for example, a constant voltage element (e.g., a Zener diode) including the p-type semiconductor layer 21, the n-type semiconductor layer 23, and the n-type semiconductor layer 25. - In the manufacturing processes of the
semiconductor device 1, semiconductor elements that include defects of thegate insulating film 45 are removed by screening in which a prescribed voltage is applied between thesource electrode 30 and thegate pad 50. Subsequently, thegate pad 50 and thecontact pad 60 are electrically connected. Thereby, it is possible to prevent a voltage higher than the breakdown voltage of the protection element PE from being applied to thegate insulating film 45. As a result, the damage of thegate insulating film 45 can be avoided; and the reliability can be increased. For example, the breakdown voltage of the protection element PE can be controlled by a spacing LD between the n-type semiconductor layer 23 and the n-type semiconductor layer 25 (referring toFIG. 1A ). -
FIGS. 3A and 3B are schematic views showing the mounted configuration of thesemiconductor device 1 according to the embodiment.FIG. 3A is a schematic view showing a portion of the upper surface of thesemiconductor device 1.FIG. 3B is a schematic view showing a cross section of thesemiconductor device 1. - As shown in
FIGS. 3A and 3B , for example, bonding wires (hereinbelow,metal wires 73 and 75) are bonded respectively on thesource electrode 30 and thegate pad 50. For example, themetal wire 73 electrically connects thesource electrode 30 and a ground terminal (not illustrated) of a mounting substrate. For example, themetal wire 75 electrically connects thegate pad 50 and a gate terminal (not illustrated) of the mounting substrate. Also, themetal wire 75 may connect thegate pad 50 to a gate circuit (not illustrated) provided on the mounting substrate. - For example, the
contact pad 60 is positioned under the end portion of themetal wire 75 electrically connected to thegate pad 50. For example, the size of thecontact pad 60 in the X-direction and the Y-direction is smaller than the size of the end portion of themetal wire 75. Accordingly, themetal wire 75 is bonded to electrically connect thegate pad 50 to the external terminal or circuit and to be electrically connected to thecontact pad 60. In other words, in the embodiment, thegate pad 50 and thecontact pad 60 can be electrically connected merely by bonding themetal wire 75 on thegate pad 50. Thereby, the mounting process of thesemiconductor device 1 can be simplified; and the manufacturing efficiency can be improved. The embodiment is not limited to a metal wire; for example, other bonded configuration may be used in which the gate pad and an external lead are connected using a connector. -
FIG. 4 is a schematic view showing asemiconductor device 2 according to a modification of the embodiment.FIG. 4 is a plan view showing a portion of the upper surface of thesemiconductor device 2. - As shown in
FIG. 4 , thesemiconductor device 2 includesmultiple contact pads 60. Thecontact pads 60 each are disposed at positions surrounded with thegate pad 50. Also, thecontact pads 60 are provided to be separated from thegate pad 50 and are electrically insulated from thegate pad 50. Themultiple contact pads 60 are electrically connected to the n-type semiconductor layer 25 (referring toFIG. 1A ). In the example, for example, even in the case where the bonding position of the metal wire 75 (referring toFIG. 3A ) is shifted from the center position of thegate pad 50, thegate pad 50 is electrically connected to one of themultiple contact pads 60. -
FIGS. 5A and 5B are schematic views showing asemiconductor device 3 according to other modification of the embodiment.FIG. 5A is a schematic view showing a cross section of thesemiconductor device 3.FIG. 5B is a plan view showing a portion of the upper surface of thesemiconductor device 3. - In the protection element region PER of the
semiconductor device 3 as shown inFIG. 5A , a p-type semiconductor layer 27 and an n-type semiconductor layer 29 are arranged alternately between the n-type semiconductor layer 23 and the n-type semiconductor layer 25. The p-type semiconductor layer 27 and the n-type semiconductor layer 29 are selectively provided in the p-type semiconductor layer 21. For example, the p-type semiconductor layer 27 includes a p-type impurity having a higher concentration than a concentration of the p-type impurity in the p-type semiconductor layer 21. - As shown in
FIG. 5B , the n-type semiconductor layer 23 is disposed to surround thegate pad 50 when viewed in the Z-direction. Also, the n-type semiconductor layer 25 is disposed at the center of thegate pad 50. The p-type semiconductor layer 27 and the n-type semiconductor layer 29 each are provided to surround the n-type semiconductor layer 25. - In the example, the protection element PE (referring to
FIG. 2 ) includes the n-type semiconductor layers 23, 25, and 29 and the p-type semiconductor layer 27. The breakdown voltage of the protection element PE can be controlled by disposing the appropriate number of p-type semiconductor layers 27 and n-type semiconductor layers 29 between the n-type semiconductor layer 23 and the n-type semiconductor layer 25. - The protection element PE according to the embodiment is not limited to the example recited above; and it is sufficient for the protection element PE to have a configuration electrically connected to the
source electrode 30 and thecontact pad 60 and not to affect the operations of the transistor region TRR. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
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JP2018168849A JP7055534B2 (en) | 2018-09-10 | 2018-09-10 | Manufacturing method of semiconductor device |
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US11804527B2 (en) * | 2021-07-14 | 2023-10-31 | Nxp Usa, Inc. | Transistor with center fed gate |
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JPH11154746A (en) * | 1997-11-20 | 1999-06-08 | Toshiba Corp | Semiconductor device |
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JP2002118258A (en) | 2000-10-10 | 2002-04-19 | Sanyo Electric Co Ltd | Mosfet and protective circuit device using that |
JP3964819B2 (en) * | 2003-04-07 | 2007-08-22 | 株式会社東芝 | Insulated gate semiconductor device |
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JP6341331B2 (en) * | 2015-03-17 | 2018-06-13 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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2019
- 2019-01-09 CN CN201910018675.1A patent/CN110890419B/en active Active
- 2019-01-24 US US16/255,949 patent/US10600777B1/en active Active
Cited By (4)
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US20190326217A1 (en) * | 2018-04-20 | 2019-10-24 | Stmicroelectronics S.R.L. | Electronic device with short circuit protection element, fabrication method and design method |
US10818593B2 (en) * | 2018-04-20 | 2020-10-27 | Stmicroelectronics S.R.L. | Electronic device with short circuit protection element, fabrication method and design method |
US11469177B2 (en) | 2018-04-20 | 2022-10-11 | Stmicroelectronics S.R.L. | Electronic device with short circuit protection element, fabrication method and design method |
US11804527B2 (en) * | 2021-07-14 | 2023-10-31 | Nxp Usa, Inc. | Transistor with center fed gate |
Also Published As
Publication number | Publication date |
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US10600777B1 (en) | 2020-03-24 |
CN110890419A (en) | 2020-03-17 |
JP2020043200A (en) | 2020-03-19 |
CN110890419B (en) | 2024-02-02 |
JP7055534B2 (en) | 2022-04-18 |
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