US20200043945A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20200043945A1 US20200043945A1 US16/270,214 US201916270214A US2020043945A1 US 20200043945 A1 US20200043945 A1 US 20200043945A1 US 201916270214 A US201916270214 A US 201916270214A US 2020043945 A1 US2020043945 A1 US 2020043945A1
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- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H01L27/11807—CMOS gate arrays
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L2027/11864—Yield or reliability
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L2027/11874—Layout specification, i.e. inner core region
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11881—Power supply lines
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Definitions
- the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same.
- the size of the standard cell has been reduced and the degree of integration of the standard cell has been increased. Accordingly, the density of the logic device has been increased.
- the fin FET and the buried transistor structure have been applied to the standard cell for minimizing the short channel effect and providing various other process improvements such as to line edge roughness (LER).
- LER line edge roughness
- the LER may prevent an electric short between, neighboring patterns in spite of the reduction of the critical dimension (CD).
- a plurality of cutting patterns is arranged in the plurality of power areas and the plurality of cutting patterns extends in the first direction such that each of the plurality of gate structures and each of the plurality of junction layers in neighboring cell, areas a the plurality of cell areas are separated from each other by the cutting pattern.
- a method of manufacturing a semiconductor device includes forming a plurality of active fins in at least a pair of cell areas extending in a first direction. The pair of cell areas are separated from each other by a power area.
- a plurality of dummy gate structures and a plurality of gap fill patterns are formed to a line shape extending in a second direction, substantially perpendicular to the first direction, such that each of the plurality of dummy gate structures and each of the plurality of gap fill patterns covers the plurality of active fins, alternately with respect to each other in the first direction.
- FIGS. 2A to 2E are cross sectional views cut along lines A-A′, B-B′, C-C′, D-D′ and E-E′ of the semiconductor device depicted in FIG. 1 , respectively;
- FIG. 3 is a plan view illustrating a semiconductor device in accordance with an exemplary embodiment of the present inventive concept
- the gate line GL may be arranged exclusively in the cell area C and the gate line GL in the first cell area C 1 may be symmetrical with the gate line GL in the second cell area C 2 with respect to a gate cutting pattern CP.
- the gate structure 500 and the active fin 110 may function as a gate electrode of a cell transistor in the cell area C.
- the cutting pattern CP may include an insulation material such as silicon nitride (SiN), so the gate structures 500 in the first cell area C 1 may be electrically separated from die gate structures 500 in the second cell area C 2 by the cutting pattern CR
- the gate structures 500 in the first cell area C 1 may be separated from the gate structures 500 in the second cell area C 2 by the power area PA.
- a junction layer 300 may be arranged at both sides of the gate structure 500 .
- a space between the neighboring gate spacers 240 may be provided as an inter-space trench IST in the cell area C, and the junction layer 300 may be grown on the active fin 110 in the inter-space trench IST.
- the junction layers 300 on the neighboring active fins 110 may be connected with each other just like a line extending in the second direction II in the cell area C.
- the junction layer 300 around the power area PA may be grown along the side surface of the cutting pattern CP in the third direction III and may have a larger size than the junction layer 300 that is farther from the power area PA.
- the junction layer 300 around the power area. PA may have a flat portion A making contact with the cutting pattern CP and may have a larger size than that of the junction layer 300 that is farther from the cutting pattern CP along the same inter-spacer trench IST.
- junction layer 300 that is farther from the cutting pattern CP may have no growth restrictor such as the cutting pattern CP, so the junction layer 300 that is farther from the cutting pattern CP may be grown horizontally as well as grown vertically without any substantial limitations.
- the junction layer 300 may have a point portion B due to the non-restricted isotropic epitaxial growth behavior.
- the neighboring junction layer 300 may be bonded to each other in the second direction II due to the horizontal growth of the SEC process. Accordingly, the junction layer 300 may be shaped into a broken line extending in the second direction II.
- the junction layer 300 might not be grown vertically and may instead be formed to have the point portion B.
- the junction layer 300 having the point portion B may have a smaller size that that of the junction layer having the flat portion A. Therefore, the closer to the cutting pattern CP the larger the size of the junction layer 300 , and the closer to the separation area PNS the smaller the size of the junction pattern 300 .
- FIG. 3 is a plan view illustrating, a semiconductor device in accordance with an exemplary embodiment of the present inventive concept.
- FIGS. 4A to 4F are cross sectional views cut along lines E-E′ and F-F′ of the semiconductor device in FIG. 3 , respectively.
- the semiconductor device in FIG. 3 has substantially the same structures as the semiconductor device shown in FIG. 1 , except that a separation pattern SP may be further arranged in the separation area PNS in each cell area C.
- the same reference numerals in FIGS. 1 to 2E may be used to denote the same elements and to the extent that further descriptions of various elements is omitted, it may be assumed that these elements are at least similar to corresponding elements that have already been described.
- an insulation layer may be formed on the substrate 100 to a sufficient thickness to fill up the recess R and the insulation layer may be planarized until a top surface of the active fin 110 may be exposed.
- a preliminary dummy gate structure 200 a may be formed on the device isolation layer 120 as a line extending in the second direction II.
- the cutting trench CT may be formed in the whole power area PA, the cutting trench CT may be formed in a portion of the power area PA.
- the neighboring junction layer 300 on the neighboring active fins 110 may be connected to each other in the second direction II.
- the junction layer 300 may be formed into broken line pieces in the PMOS area P and the NMOS area N.
- the size of the flat portion A may be varied according to the process conditions of the SEG process. As described hereinafter, since the flat portion A may make contact with the power contact 620 , the contact resistance between the junction layer 300 and the contact structure 600 ay be reduced as the size of the flat portion A may increase.
- the dummy ate structure 200 may be removed from the substrate 100 and the device isolation layer 120 and the active tin 110 may be exposed through an opening defined by the gate spacer 240 and the cutting pattern CP, thereby forming the gate trench extending in the second direction II in the cell area C.
- the gate electrode layer, the work function control layer and the gate, insulation layer may be planarized until the upper surfaces of the insulation pattern 400 and the cutting pattern CP may be exposed, thereby forming a gate insulation pattern 510 , a work function control pattern 520 and a gate electrode 530 that may be sequentially formed on the active fin 110 and the device isolation layer 120 and may fill up the gate trench as the gate structure 500 .
- the gate electrode 530 may be at least partially enclosed by the work function control pattern 520 in the gate trench.
- the gate structure 500 may be arranged in the gate trench and may be formed into the gate line GL extending in the second direction II in the cell area C.
- a second interlayer dielectric layer may be formed on the contact structure 600 and the first interlayer dielectric pattern ILD 1 and may be partially removed from the power area PA in such, a way that the first interlayer dielectric pattern ILD 1 , the power contact 620 and the junction cutting pattern CP 2 may be exposed, thereby forming a second interlayer dielectric pattern ILD 2 having a power trench through which the power contact 620 and the junction cutting pattern CP 2 may be exposed.
- FIGS. 33 to 40F are views illustrating processing steps of a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present inventive concept.
- odd-numbered figures are plan views illustrating each processing step for the manufacturing method and even-numbered figures are cross sectional views corresponding to the odd-numbered figure.
- Each figure designated by the subscript ‘A’ in the drawing number is a cross-sectional view cut along a line A-A′ of the semiconductor device shown in FIG. 3
- each figure designated by the subscript ‘B’ in the drawing number is a cross-sectional view cut along a line B-B′ of the semiconductor device shown in FIG. 3 .
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Abstract
A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.
Description
- This application claims priority under 15 U.S.C. § 119 to Korean Patent Application No. 10-2018-0090472, filed on Aug. 2, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
- The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same.
- A logic device is a semiconductor device designed to perform a particular task. A logic device may be designed by combining a plurality of ready-made standard cells that each perform a limited number of logic functions.
- Each standard cell is an integrated circuit (IC) module that may be optimized for specific requirements and functions. Standard cells may include a basic cell such as a boolean logic function (e.g. AND, OR, NOR, inverters), a complex cell having a plurality of basic cells such as an OAI cell (OR/AND/inverter) and an AOI cell (AND/OR/inverter), and a storage element such as a master-slave flip flop and a latch. The logic device is made up of the basic cell, the complex cell, and the storage element that are optimally selected to perform a specific function.
- Over time, the size of the standard cell has been reduced and the degree of integration of the standard cell has been increased. Accordingly, the density of the logic device has been increased. For example, the fin FET and the buried transistor structure have been applied to the standard cell for minimizing the short channel effect and providing various other process improvements such as to line edge roughness (LER). The LER may prevent an electric short between, neighboring patterns in spite of the reduction of the critical dimension (CD).
- For example, some of the circuit lines of the recent standard cells tend to extend to the power area from the cell area, so that the integrated circuits are arranged in a portion of the power area and in the cell area and the density of the circuit lines are increased within the same size of the standard cell.
- However, since the neighboring cells are electrically separated by the power area, the reduction of the power area tends to cause an electric short between the neighboring cells. Accordingly, standard cells of a reduced size may be more susceptible to electric short between the neighboring cells therein.
- A semiconductor device includes a substrate having a plurality of cell areas and a plurality of power areas such that each of the plurality of cell areas are alternately arranged with each of the plurality of power areas, in a second direction. A plurality of gate structures extends in the second direction. Each of the plurality of gate structures is spaced apart from each other in a first direction that is substantially perpendicular to the second direction. A plurality of junction layers is arranged at both sides of each of the plurality of gate structures and is arranged in the second direction in such a configuration that each of the plurality of junction layer has a flat portion that is proximate to the power area. A plurality of cutting patterns is arranged in the plurality of power areas and the plurality of cutting patterns extends in the first direction such that each of the plurality of gate structures and each of the plurality of junction layers in neighboring cell, areas a the plurality of cell areas are separated from each other by the cutting pattern.
- A method of manufacturing a semiconductor device includes forming a plurality of active fins in at least a pair of cell areas extending in a first direction. The pair of cell areas are separated from each other by a power area. A plurality of dummy gate structures and a plurality of gap fill patterns are formed to a line shape extending in a second direction, substantially perpendicular to the first direction, such that each of the plurality of dummy gate structures and each of the plurality of gap fill patterns covers the plurality of active fins, alternately with respect to each other in the first direction. A cutting pattern is formed in the power area in a line shape extending in the first direction such that the plurality of dummy gate structures and the plurality of gap fill patterns are separated from each other by a unit of a cell area of the at least the pair of cell areas. A junction layer is formed in a gap space between neighboring dummy gate structures, of the plurality of dummy gate structures, such that the junction layer makes contact with the plurality of active fins in the at least the pair of cell areas and has a flat portion making contact with the cutting pattern.
- A more complete appreciation of the present disclosure and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
-
FIG. 1 is a plan view illustrating a semiconductor device in accordance with an exemplary embodiment of the present inventive concept; -
FIGS. 2A to 2E are cross sectional views cut along lines A-A′, B-B′, C-C′, D-D′ and E-E′ of the semiconductor device depicted inFIG. 1 , respectively; -
FIG. 3 is a plan view illustrating a semiconductor device in accordance with an exemplary embodiment of the present inventive concept; -
FIGS. 4A to 4F are cross sectional views cut along lines A-A′, B-B′, C-C′, D-D′, E-E′ and F-F′ of the semiconductor device depicted inFIG. 3 , respectively; -
FIGS. 5 to 32E are views illustrating processing steps of a method of manufacturing a semiconductor device in accordance with a exemplary embodiment of the present inventive concept; and -
FIGS. 33 to 40F are views illustrating processing steps of a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present inventive concept. - Reference will now be made to exemplary embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like components throughout the specification and the drawings.
-
FIG. 1 is a plan view illustrating a semiconductor device in accordance with an exemplary embodiment of the present inventive concept.FIGS. 2A to 2E are cross sectional views cut along lines A-A′, B-B′, C-C′, D-D′ and E-E′ of the semiconductor device inFIG. 1 , respectively. - Referring to
FIGS. 1 to 2E , a semiconductor device, in accordance with an exemplary embodiment of the present inventive concept, may include asubstrate 100 having a plurality of cell areas C and a plurality of power areas PA such that the cell areas C and the power areas PA may be alternately arranged in a second direction II. A plurality ofgate structures 500 extends in the second direction II and are spaced, apart from each other in a first direction I, which is substantially perpendicular to the second direction II. A plurality ofjunction layers 300 is arranged at both sides of thegate structures 500 and is arranged in the second direction II in such a configuration that each of the plurality ofjunction layer 100 may have a flat portion A around the power area PA. A plurality of cutting patterns CP is arranged in the power areas PA and these cutting patterns CP extend in the first direction I such that thegate structures 500 and thejunction layers 300 in neighboring cell areas may be separated from each other by the cutting pattern CP. - For example, the
substrate 100 may include a bulk substrate, e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, a gallium phosphorus (Ga-P) substrate, a gallium arsenide (Ga-As) substrate, a silicon antimony (Si-Sb) substrate, Thesubstrate 100 may alternatively include a multilayered substrate, e.g., a semiconductor on insulator (SOI) substrate, a germanium on insulator (GOI) substrate. - The
substrate 100 may include a plurality of cell areas C in which a plurality of cell transistors may be arranged and a power area PA in which apower rail 700 may be arranged, Hereinafter, the neighboring cell areas around the power area PA may be referred to as a first cell area C1 and a second cell area C2, and the first and the second cell areas C1 and C2 may be separated from each other by the power area PA. - According to an exemplary embodiment, each of the cell areas C may be divided into a PMOS area P and an NMOS area N that may be separated from each other by a separation area PNS. Thus, a plurality of PMOS transistors and NMOS transistors may be arranged in the cell area C and the PMOS transistor and the NMOS transistor may be separated from each other by the separation area PNS, so that CMOS transistors may be arranged in the cell areas C. Hereinafter, the separation area PNS in the first cell area C1 may be referred to as first separation area PNS1 and the separation area PNS in the second cell area C2 may be referred to as second separation area PNS2.
- A plurality of
active fins 110 may be arranged in the cell area C. Theactive fin 110 may extend in the first direction I and neighboringactive fins 110, of the plurality ofactive fins 110, may be spaced apart from each other in the second direction B. Theactive fin 110 may protrude from adevice isolation layer 120, so theactive fin 110 may be divided into alower fin 110 a that may be at least partially enclosed with thedevice isolation layer 120 and anupper fin 110 b that may extend from thedevice isolation layer 120. For example, a field area of thesubstrate 100 may be at least partially covered with thedevice isolation layer 210 and an active area of thesubstrate 100 may be provided as theactive fin 110 protruded from thedevice isolation layer 120. - A
gate structure 500 may be arranged on eachactive fin 110 and a plurality of thegate structures 500 along the second direction II may be formed into a gate line GL. A plurality of the gate lines GL may be spaced apart by the same gap distance in the first direction I. A side surface of the gate line GL may be at least partially covered by agate spacer 240 that may be shaped into a line in the second direction II. - For example, the gate line GL may discontinuously extend in the second direction II by the power area PA. For example, the gate line GL may extend in the first cell area C1 along the second direction II and may be broken or otherwise not arranged in the power area PA. The gate line GL may also extend in the second cell area C2 along the second direction II.
- Thus, the gate line GL may be arranged exclusively in the cell area C and the gate line GL in the first cell area C1 may be symmetrical with the gate line GL in the second cell area C2 with respect to a gate cutting pattern CP. The
gate structure 500 and theactive fin 110 may function as a gate electrode of a cell transistor in the cell area C. - The cutting pattern CP may include an insulation material such as silicon nitride (SiN), so the
gate structures 500 in the first cell area C1 may be electrically separated fromdie gate structures 500 in the second cell area C2 by the cutting pattern CR For example, thegate structures 500 in the first cell area C1 may be separated from thegate structures 500 in the second cell area C2 by the power area PA. - In an exemplary embodiment, the
gate structure 500 may include agate insulation pattern 510, a workfunction control pattern 520 and agate electrode 530 that may be sequentially stacked on theactive fin 110 and thedevice isolation layer 120 and may be defined by thegate spacer 240. A gate trench defined by the workfunction control pattern 520 may extend in the second direction II and thegate electrode 530 may fill up the gate trench. A gate signal may be transferred to the semiconductor device via thegate structure 500. - A
junction layer 300 may be arranged at both sides of thegate structure 500. A space between the neighboringgate spacers 240 may be provided as an inter-space trench IST in the cell area C, and thejunction layer 300 may be grown on theactive fin 110 in the inter-space trench IST. For example, when the neighboringactive fins 110 may be closely arranged in the inter-space trench IST, the junction layers 300 on the neighboringactive fins 110 may be connected with each other just like a line extending in the second direction II in the cell area C. - The
junction layer 300 may be grown on theactive fin 110 around thegate structure 500 by a selective epitaxial growth (SEG) process, so that an epitaxial pattern may be provided as thejunction layer 120. Thus, when the neighboringactive fins 110 may be closely arranged in the inter-space trench IST, the epitaxial pattern may be grown in the second direction II and be connected to each other. Thus, thejunction layer 300 may be selectively connected to each other and may be provided as a discontinuous line in the cell area C. - For example, the
junction layer 300 in the first cell area C1 may also be separated from thejunction layer 300 in the second cell area C2 by the power area PA, so that thejunction layer 300 in the first cell area C1 and thejunction layer 300 in the second cell area C2 may also be separated from each other by the cutting pattern CP in the power area PA. - Therefore, the
junction layer 300 in the first cell area C1 and thejunction layer 300 in the second cell area C2 do not make contact with each other in the SEG process due to the cutting pattern CP in the power area PA. For example, an electrical short of thejunction layer 300 between the first cell area C1 and the second area C2 may be substantially prevented by the cutting pattern CP in the power area PA. - The
junction layer 300 around the power area PA may be grown on theactive fin 110 horizontally toward the power area PA as well as grown vertically, so thejunction layer 300 may also be grown along a side surface of the cutting pattern CP in a third direction III. For example, the growth of thejunction layer 300 in the second direction H toward the power area PA may be prohibited by the cutting pattern CP. - Thus, the
junction layer 300 around the power area PA may be grown along the side surface of the cutting pattern CP in the third direction III and may have a larger size than thejunction layer 300 that is farther from the power area PA. For example, thejunction layer 300 around the power area. PA may have a flat portion A making contact with the cutting pattern CP and may have a larger size than that of thejunction layer 300 that is farther from the cutting pattern CP along the same inter-spacer trench IST. - The large size of the
junction layer 300 may reduce the contact resistance of thecontact structure 600, and the size of thejunction layer 300 may be changed according to the contact resistance. For example, the process conditions of the SEG may be controlled in such a way that the size of the flat portion A of thejunction layer 300 may be sufficiently sized to achieve a desired contact resistance. - The
junction layer 300 that is farther from the cutting pattern CP may have no growth restrictor such as the cutting pattern CP, so thejunction layer 300 that is farther from the cutting pattern CP may be grown horizontally as well as grown vertically without any substantial limitations. Thus, when the neighboringactive fins 110 may be sufficiently separated from each other in the second direction or theactive fin 110 may be arranged around the separation area PNS, thejunction layer 300 may have a point portion B due to the non-restricted isotropic epitaxial growth behavior. - For example, when the neighboring
active fins 110 may be closely arranged in the inter-space trench IST, the neighboringjunction layer 300 may be bonded to each other in the second direction II due to the horizontal growth of the SEC process. Accordingly, thejunction layer 300 may be shaped into a broken line extending in the second direction II. - When the growth restrictor is not be provided in the SEG process, the
junction layer 300 might not be grown vertically and may instead be formed to have the point portion B. Thus, thejunction layer 300 having the point portion B may have a smaller size that that of the junction layer having the flat portion A. Therefore, the closer to the cutting pattern CP the larger the size of thejunction layer 300, and the closer to the separation area PNS the smaller the size of thejunction pattern 300. - The inter-space trench IST may be filled up with the
conductive contact structure 600 making contact with thejunction layer 300, so that thecontact structure 600 may be shaped into a line extending in the second direction II. Further, the line-shapedContact structure 600 might not be positioned in the separation area PNS, so that thecontact structure 600 may be broken in the separation area PNS and may be discontinuous in the cell line C. - The
gate structure 500 may be at least partially covered by agate capping pattern 550 and a first interlayer dielectric pattern ILD1 and thejunction layer 300 around thegate structure 300 in the inter-space trench IST may be at least partially covered by thecontact structure 600 extending in the second direction II. For example, an upper surface of thecontact structure 600 may be substantially coplanar with an upper surface of thegate structure 500 or the gate line GL. - While the gate line GL may be continuous in the cell area C, the
contact structure 600 may be separated into anNMOS contact 612 and aPMOS 614 contact by aninsulation pattern 400 filling the separation area PNS. - For example, the
contact structure 600 may include acell contact 610 making contact. with thejunction layer 300 in the cell area C and apower contact 620 making a surface contact with the flat portion of thejunction layer 300 in the power area PA. Thecell contact 610 and thepower contact 620 may be provided in one body. Thecell contact 610 may include the NMOS contact and the PMOS contact and may be provided as a contact plug making contact with asingle junction layer 300 and may be provided as a contact line making contact with a plurality of the junction layers 300 in the second direction II. - The
power contact 620 may make surface contact with the flat portion A of thejunction layer 300 and may be positioned in a peripheral portion of the power area PA in such a configuration that thepower contact 620 may make surface contact with the side surface of the cutting pattern CP. A peripheral portion of the cutting pattern CP may be removed from thesubstrate 100 and a second contact hole CTH2 may be provided in such a configuration that the flat portion A of thejunction layer 300 and thedevice isolation layer 120 may be exposed through the second contact hole CTH2. Thepower contact 620 may be positioned in the second contact hole CTH2 in such a configuration that thepower contact 620 may be in contact with thedevice isolation layer 120 and an upper surface of thepower contact 620 may be coplanar with an upper surface of the cutting pattern CP. Since thepower contact 620 may make surface contact with the flat portion A of thejunction layer 300, the contact resistance between thejunction layer 300 and thecontact structure 600 may be sufficiently reduced in the semiconductor device. - Thus, the cutting pattern CP may include a gate cutting pattern CP1 cutting the gate line GL in the power area PA and having a first width w1 and a junction cutting pattern CP2 cutting the
junction layer 300 in the power area PA and having a second width w2 smaller than the first width w1. The gate cutting pattern CP1 and the junction cutting pattern CP2 may be alternately arranged along the first direction I in the power area PA. - The
power contact 620 in the first cell area C1 may be symmetrical with thepower contact 620 in the second cell area C2 with respect to the junction cutting pattern CP2, so that thepower contact 620 in the first cell area C1 may be substantially prevented from being connected with thepower contact 620 in the second cell area C2 by the junction cutting pattern CP2. For example, an electrical short of thejunction layer 120 between the first and the second cell areas C1 and C2 may be substantially prevented by the cutting pattern CP in the power area PA. - The
cell contact 610 may be separated into theNMOS contact 612 and thePMOS contact 614 by theinsulation pattern 400 in the cell area C. Thus, theNMOS contact 612 and thePMOS contact 614 may also be electrically separated from each other by theinsulation pattern 400 in the cell area C. - The
power contact 620 may be connected to apower rail 700 at least partially covering the power area PA. Since thepower rail 700 may be in contact with the upper surface of the cutting pattern CP and the upper surface of thepower contact 620 may be coplanar with the upper surface of the cutting pattern CP. Thepower rail 700 may also be in contact with thepower contact 620 at the peripheral portion of the power area PA. - The
power rail 700 may include apower plug 710 making contact with thepower contact 620 and extending upwards. Thepower rail 700 may additionally include apower line 720 making contact with thepower plug 710 and extending in the first direction I on the first interlayer dielectric pattern ILD1. In the present exemplary embodiment, thepower plug 710 and thepower line 720 may be provided in one body. - The
power plug 710 may be symmetrically arranged at both sides of the junction cutting pattern CP2 in such a configuration that a lower surface of thepower plug 710 may be in contact with thepower contact 620 and an upper surface of thepower plug 710 may be coplanar with an upper surface of the first interlayer dielectric pattern ILD1. Thepower line 720 may extend in the first direction I in such a configuration that a lower surface of thepower line 720 may be alternately in contact with thepower plug 710 and the first interlayer dielectric pattern ILD1 in the power area PA. - When a power signal may be applied to the
power rail 700 from an external power source, the power signal may be transferred to thejunction layer 300 via thepower contact 620. For example, the power signal may be simultaneously transferred to thejunction layer 300 of the first cell area C1 and thejunction layer 300 of the second cell area C2. Since thepower contact 620 in the first cell area C1 may be insulated from thepower contact 620 in the second cell area C2 by the junction cutting pattern CP2, the power signal may be individually transferred to thejunction layer 300 in both of the first cell, area C1 and the second cell area C2. - In addition, since the
cell contact 610 may be separated into theNMOS contact 612 and thePMOS contact 614 by theinsulation pattern 400 in the cell area C, the power signal may be transferred to one of theNMOS contact 612 and thePMOS contact 614. Thus, theNMOS contact 612 and thePMOS contact 614 in the same cell area C might not simultaneously receive the power signal from thesame power rail 700. Some of the power rails 700 may transfer the power signal to theNMOS contact 612 and the rest of the power rails 700 may transfer the power signal to thePMOS contact 614. - In the present, exemplary embodiment, a PMOS area P may be arranged around the
power rail 700 and an NMOS area N may be arranged apart from thepower rail 700 and disposed close to another power rail. Thus, the power signal may be transferred to thePMOS contact 614 through thepower rail 700 and transferred to theNMOS contact 612 through another power rail that may be spaced apart from thepower rail 700 in the second direction II. - A plurality of the power rails 700 may extend in the first direction I and may be spaced apart from each other in the second direction II. A second inter layer dielectric pattern ILD2 may be filled with the gap space between the neighboring power rails 700, so the neighboring power rails 700 may be insulated from each other by the second interlayer dielectric pattern ILD2.
- According to the present exemplary embodiment of the semiconductor device, the gate line GL and the
junction layer 300 extending in the second direction II may be cut by the cutting pattern CP that may be arranged in the power area PA, so the gate line GL and thejunction layer 300 may be separated by a unit of the cell area C. Thus, the gate line CCL and thejunction layer 300 in the first cell area C1 may be substantially prevented from being connected to the gate line C2 and thejunction layer 300 in the second cell area C2. Accordingly, electric short of the gate line GL and thejunction layer 300 may be substantially prevented between the first and the second cell areas C1 and C2. - Further, the
power contact 620 making contact with thejunction layer 300 may be arranged at both sides of the junction cutting, pattern CP2 symmetrically with respect to the junction cutting pattern CP2. Thus, the power signal may be individually and independently transferred to the first and second cell areas C1 and C2. For example, the power signal transferred to thePMOS contact 614 in the first cell area nay be prevented from leaking to thePMOS contact 614 in the second cell area C2, and the power signal transferred to thePMOS contact 614 in the second cell area C2 may be prevented from leaking to thePMOS contact 614 in the first cell area C1. - In addition, since the
power contact 620 may make surface contact with thejunction layer 300, the contact resistance between thejunction layer 300 and thecontact structure 600 may be sufficiently reduced in the semiconductor device. - Accordingly, when the power area PA may be reduced according to the size reduction of the recent semiconductor devices, an electric short of the gate line GL and the
junction layer 300 may be substantially prevented or minimized between the neighboring cell areas C that may be separated by the power area PA. For example, an electric short of the transistors between the neighboring cell areas C separated by the power area PA may be substantially prevented by the cutting pattern CA in the power area PA. - While the cutting pattern for preventing the neighboring transistors in different cell areas C may be arranged in the power area PA, an electric shorts of the neighboring transistors may also occur in the same cell area C via the separation area PNS. Thus, the cutting pattern may be further provided in the separation area PNS as well as the power area PA.
-
FIG. 3 is a plan view illustrating, a semiconductor device in accordance with an exemplary embodiment of the present inventive concept.FIGS. 4A to 4F are cross sectional views cut along lines E-E′ and F-F′ of the semiconductor device inFIG. 3 , respectively. The semiconductor device inFIG. 3 has substantially the same structures as the semiconductor device shown inFIG. 1 , except that a separation pattern SP may be further arranged in the separation area PNS in each cell area C. Thus, inFIGS. 3 to 4F , the same reference numerals inFIGS. 1 to 2E may be used to denote the same elements and to the extent that further descriptions of various elements is omitted, it may be assumed that these elements are at least similar to corresponding elements that have already been described. - Referring to
FIGS. 3 to 4F , aseparation pattern 300 may be arranged in the separation area PNS in such a way that the gate line GL and thejunction layer 300 in the PMOS area P might not be connected to the gate line GL and thejunction layer 300 in the NMOS area N. - Prior to the formation of the
gate structure 500, theinsulation pattern 400 may be removed form thesubstrate 100 and a separation hole SO inFIG. 33 may be formed in the separation area PNS. The separation hole may be formed in the whole separation area PNS or in a portion of the separation area PNS according to a layout of the semiconductor device. - In the present exemplary embodiment, the separation hole SO may extend in the first direction I through the
gate spacer 240 and may include the gate trench and the inter-space trench IST I in the first direction I. Thus, the separation pattern SP may extend in the first direction I in the cell area C and at least one gate line GL and at least onejunction layer 300 may be separated by the separation pattern SP in the cell area C. - The separation pattern SP may have substantially the same insulation material as the cutting pattern CP. For example, the separation pattern SP may include silicon nitride (SiN), silicon oxynitride (SiON), and/or silicon carbon oxynitride (SiOCN).
- Accordingly, the
gate structure 500 in the PMOS area P and thegate structure 500 in the NMOS area N may be electrically separated by the separation pattern SP in the cell area C. In the same way, thejunction layer 300 in the PMOS area P and thejunction layer 100 in the NMOS area N may also be electrically separated by the separation pattern SP in the cell area C. Thus, the PMOS transistor and the NMOS transistor may be sufficiently separated from each other by the separation pattern SP in the same cell area C although the size of the semiconductor device may be reduced. For example, the semiconductor device may be formed into a stable and reliable CMOS device. -
FIGS. 5 to 32E are views illustrating processing steps of a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present inventive concept. InFIGS. 5 to 32E , odd-numbered figures are plan views illustrating each processing step for the manufacturing method and even-numbered figures are cross sectional views corresponding to the odd-numbered figure. Each figure designated by the subscript ‘A’ in the drawing number is a cross-sectional view cut along a line A-A′ of the semiconductor device shown inFIG. 1 , and each figure designated by the subscript ‘B’ in the drawing number is a cross-sectional view cut alone a line B-B′ of the semiconductor device shown inFIG. 1 . In addition, each figure designated by the subscript ‘C’ in the drawing number is a cross-sectional view cut along a line C-C′ of the semiconductor device shown inFIG. 1 , and each figure designated by the subscript ‘D’ in the drawing number is a cross-sectional view cut along a line of the semiconductor device shown inFIG. 1 . Each figure designated by the subscript ‘E’ in the drawing number is a cross-sectional view cut along a line E-E′ of the semiconductor device shown inFIG. 1 . - Referring to
FIGS. 5 and 6A to 6B , an upper portion of thesubstrate 100 may be partially removed and a plurality of recesses R may be formed on thesubstrate 100 in such a way that a plurality ofactive fins 110 may be arranged on thesubstrate 100. The neighboringactive fins 110 may be spaced apart from each other by the recess R. - For example, the
substrate 100 may include a bulk substrate, e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, a gallium phosphorus (Ga-P) substrate, a gallium arsenide (Ga-As) substrate, a silicon antimony (Si-Sb) substrate. Alternatively, thesubstrate 100 may include a multilayered substrate, e.g., a semiconductor on insulator (SOI) substrate, a germanium on insulator (GOI) substrate. - A mask pattern for defining an active region of the
substrate 100 may be formed on thesubstrate 100 and a dry etching process may be conducted to thesubstrate 100 using the mask pattern as an etching mask, so that an upper portion of thesubstrate 100 may be partially removed to thereby form the recesses R on thesubstrate 100. An etched portion of thesubstrate 100 may function as a field region F of thesubstrate 100 and a non-etched portion of thesubstrate 100 may protrude upwards from the bottom of the recess R just like afin 110 and function as an active region A of thesubstrate 100. Thus, thesubstrate 100 may have the field region F corresponding to the recess R and the active region A corresponding to thefin 110. The active region A shaped into the fin is referred to asactive tin 110. In the present exemplary embodiment, theactive fin 110 may be formed into a line extending in the first direction I. - The
substrate 100 may include a plurality of cell areas C in which a plurality of cell transistors may be arranged and a power area PA in which thepower rail 700 such as a metal line may be arranged. The cell area C and the power area PA may be alternately arranged on thesubstrate 100 in the second direction II. For example, thecontact structure 600 may be formed in the power area PA and the power signal may be simultaneously transferred to the neighboring cell areas close to the power area PA. - The first cell area C1 may be separated from the second cell area C2 by the power area PA and may be, symmetrical to each other with respect to the power area PA. The power area PA may include a first power area PA1 for holding the
contact structure 600 through which the power signal may be transferred to the first cell area C1 and a second power area PA2 for holding thecontact structure 600 through which the power signal may be transferred to the second cell area C2. - Each of the cell area C may include the PMOS area P and the NMOS area N. A PMOS transistor may be formed on the PMOS area P and the NMOS transistor may be formed on the NMOS area N so that the CMOS transistor may be formed in each of the cell area C. For example, since the first and the second cell areas C1 and C2 may be symmetrical to each other with respect to the power area PA, the PMOS area P and the NMOS area N of the first cell area C1 may be folded onto the PMOS area P and the NMOS area N of the second cell area C2.
- Therefore, a first power signal may be simultaneously transferred to both of the PMOS transistors in the first and the second cell, areas C1 and C2 by the
power rail 700 in the power area. PA interposed between the first and the second cell areas C1 and C2. Then, a second power signal may be transferred to both of the NMOS transistors in the first and the second cell areas C1 and C2 by another power rail in another power area that may be arranged at a top portion of the first cell area C1 and at a bottom portion of the second cell area C2. - For example, the PMOS area P and the NMOS area N may be separated from each other by the separation area PNS in each cell area C. Thus, the NMOS transistor and the PMOS transistor may be electrically separated from each other by the
insulation pattern 400 in the separation area PNS of each cell area C. Thus, when only PMOS transistor or only NMOS transistor would be formed in the cell area C, the separation area PNS might not be provided with the cell area C. Hereinafter, the separation area PNS in the first cell area C1 is referred to as first separation area PNS1 and the separation area PNS in the second cell area C2 is referred to as second separation area PNS2 for convenience's sake. - The
active fin 110 may be formed into a line shape extending in the first direction in the PMOS area P and the NMOS area N. While a singleactive fin 110 may be formed in each of the PMOS area P and the NMOS area N as shown inFIG. 6A , the singleactive fin 110 represents a plurality of theactive fins 110 that may be spaced apart from each other in the second direction II. The configurations and the structures of the plurality of the active fins may be varied according to the layout of the semiconductor device. - Referring to
FIGS. 7 and 8A to 8B , thedevice isolation layer 120 may be formed on thesubstrate 100 in such a way that a lower portion of the active fin 110 (referred to aslower fin 110 a) may be surrounded on two sides by thedevice isolation layer 120 and an upper portion of the active fin 110 (referred to asupper fin 110 b) may protrude from thedevice isolation layer 120. - For example, an insulation layer may be formed on the
substrate 100 to a sufficient thickness to fill up the recess R and the insulation layer may be planarized until a top surface of theactive fin 110 may be exposed. - Then, a mask pattern may be formed on the
substrate 110 having the insulation layer in such a way that theactive fin 110 may be at least partially covered by the mask pattern. Then, the insulation pattern may be further removed by an etching process using the mask pattern as an etch mask until a top, surface of the insulation layer may be lower than the top surface of theactive fin 110, thereby forming theinsulation layer 120 in a lower portion of the recess R. For example, thedevice isolation layer 120 may cover the field region F at the lower portion of the recess R and an upper surface of thedevice isolation layer 120 may be lower than the top surface of theactive fin 110. For example, thedevice isolation layer 120 may include an insulation material such as silicon oxide (SiO). - Thus, an entire surface of the
substrate 100 may be covered by thedevice isolation layer 120, except for theactive fin 110. Thelower fin 110 a may be at least partially enclosed by thedevice isolation layer 120 and theupper fin 110 b may be exposed to surroundings. - While the present exemplary embodiment discloses that the
device isolation layer 120 may be formed through a deposition process, a planarization process and an etching process, thedevice isolation layer 120 may be formed through other processes. For example, thedevice isolation layer 120 may be formed through a selective epitaxial growth (SEG) process using the bottom of the recess R as a seed. - Referring to
FIGS. 9 and 10A to 10C , a preliminarydummy gate structure 200 a may be formed on thedevice isolation layer 120 as a line extending in the second direction II. - A dummy gate insulation layer may be formed on the
device isolation layer 120 along a surface profile of theupper tin 110 b and a dummy gate electrode layer may be formed on the dummy gate insulation layer to a sufficient thickness to fill up gap spaces between the neighboringupper fins 110 b. - For example, the dummy gate insulation layer may include an oxide such as silicon oxide, and the dummy gate electrode layer may include polysilicon. A deposition process such as a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be conducted for forming the dummy gate insulation layer and the dummy gate electrode layer,
- Then, a mask layer may be formed on the dummy gate electrode layer and may be partially removed from the dummy gate electrode layer by a photolithography process, thereby forming a line-shaped
mask pattern 230 extending in the second direction II on the dummy gate electrode layer. - The dummy gate insulation layer and the dummy gate electrode layer may be partially removed from the
device isolation layer 120 by an etching process using the line-shapedmask pattern 230 as an etch mask, thereby forming a dummygate insulation pattern 210 and a dummygate electrode pattern 220 into a line pattern extending in the second direction II. The line-shaped dummygate electrode pattern 220 and the dummygate insulation pattern 210 may be formed into, a preliminarydummy gate structure 200 a extending in the second direction II. The neighboring preliminarydummy gate structures 200 a may be spaced apart from each other by a gap distance in the first direction I. - Referring to
FIGS. 11 and 12A to 12C , agate spacer 240 may be formed on both sides of the preliminarydummy gate structure 200 a and adummy gate structure 200 defined by thegate spacer 240 may be formed on thedevice isolation layer 120 - A spacer layer may be formed on the preliminary
dummy gate structure 200 a and thedevice isolation layer 120. Then, the spacer layer may be partially removed from thedevice isolation layer 120 by an anisotropic etching process, thereby forming thegate spacer 240 at least partially covering the side surfaces of the dummygate insulation pattern 210 and the dummygate electrode pattern 220. For example, thegate spacer 240 may include a nitride such as silicon nitride (SiN) and silicon carbon oxynitride (SiOCN). - When the anisotropic etching process may be conducted to the spacer layer, the
mask pattern 230 may also be removed from the dummygate electrode pattern 220 and thus an upper surface of thegate spacer 240 may be coplanar with an upper surface of the dummygate electrode pattern 220. - Thus, the preliminary
dummy gate structure 200 a may be formed into the line-shapeddummy gate structure 200 having the dummygate insulation pattern 210 and the dummygate electrode pattern 220 and extending in the second direction II and both sides of thedummy gate structure 200 may be at least partially covered by thegate spacer 240. Thegate spacer 240 may be shaped into a line extending in the second direction II and thedevice isolation layer 120 and theactive fin 110 may be alternately exposed in the second direction II through a gap space between the neighboringgate spacers 240. Hereinafter, the gap space between the neighboringgate spacers 240 is referred to as the inter-space trench IST, so the inter-space trench IST may extend in the second direction II. - Referring to
FIGS. 13 and 14A to 14C , a gap-fill pattern 250 may be formed in the inter-space trench IST in such a way that thedevice isolation layer 120 and theactive fin 110 may be at least partially covered by the gap-fill pattern 250. - For example, a gap-fill layer may be formed on a whole surface of the
substrate 100 having thedummy gate structure 200 and thegate spacer 240 to a sufficient thickness for filling up the inter-space trench IST. Thus, thedummy gate structure 200 and thegate spacer 240 may be at least partially covered by the gap-fill layer. The gap-fill layer may include an oxide such as silicon oxide (SiO) and may be formed by a deposition process such as the CND process and the ALD process. - Then, the gap-fill layer may be planarized by a planarization process such as a chemical mechanical polishing (CMP) process and an etch-back process until the upper surface of the
dummy Rate structure 200 may be exposed, and thus the gap-fill layer may remain exclusively in the inter-spacer trench IST as the gap-fill pattern 250. Thegap fill pattern 250 may be shaped into a line extending in the second direction II and an upper surface of thegap fill pattern 250 may be substantially coplanar with the upper surface of the dummygate electrode pattern 220. - Referring to
FIGS. 13 and 16A to 16D , thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may be removed from thedevice isolation layer 120, thereby forming a cutting trench CT through which thedevice isolation layer 120 may be exposed in the power area PA along the first direction I. - For example, a power cutting mask may be formed on the
gap fill pattern 250 and thedummy gate structure 200 in such a way that the cell area C may be at least partially covered by the power cutting mask and the power area PA may be exposed through the power cutting mask. Then, thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may partially be removed from thedevice isolation layer 120 in the power area PA by aft etching process using the power cutting mask as an etch mask. - In the present exemplary embodiment, the gap till
pattern 250 may include silicon oxide and thegate spacer 240 may include silicon nitride and thedummy gate structure 200 may include silicon oxide and polysilicon. Thus, the process conditions of the etching process may be controlled in view of the oxide, the nitride and the polysilicon. Thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may be removed by the etching process. For example, thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may be removed along the power area PA and thedevice isolation layer 120 may be exposed along the power area PA through a trench defined by thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 in the cell area C in the first direction I. Thus, the cutting trench CT may be formed on thesubstrate 100 in the power area PA along the first direction I. - The cell area C may be separated into the first cell area C1 and the second cell area C2 by the cutting trench CT.
- While the present exemplary embodiment discloses, that the cutting trench CT may be formed in the whole power area PA, the cutting trench CT may be formed in a portion of the power area PA.
- In such a case, the
dummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may remain in a peripheral portion of the power area PA and the cutting trench CT may be formed exclusively in a central portion of the power area PA. - Referring to
FIGS. 17 and 18A to 18D , the cutting pattern CP may be formed in the cutting trench CT. - For example, a cutting layer may be formed on the
dummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 to a sufficient thickness for filling up the cutting trench CT and then may be planarized until top surfaces of thedummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may be exposed. Therefore, the cutting layer may remain exclusively in the cutting trench CT thereby forming the cutting pattern CP in the cutting trench CT. - The cutting layer may include a nitride such as silicon nitride (SiN), silicon oxynitride (SiON) and silicon carbon oxynitride (SiOCN). Thus, the cutting layer may have a sufficient etch selectivity with respect to the
gap fill pattern 250 comprising an oxide and the dummygate electrode pattern 220 comprising polysilicon. - The cutting layer may be planarized by one of the CMP process and the etch-back process until the top surfaces of the
dummy gate structure 200, thegate spacer 240 and thegap fill pattern 250 may be exposed. - Accordingly, the cutting pattern CP may be exposed in the power area PA and, the dummy
gate electrode pattern 220, thegate spacer 240 and thegap fill pattern 250 may be exposed in the first and the second cell areas C1 and C2. Thedummy gate structure 200, thegate spacer 240 and, thegap fill pattern 250 may be broken by the cutting pattern CP and may be separated by a unit of the cell area C. - Referring to
FIGS. 19 and 20A to 20D , thegap fill pattern 250 may be removed from thesubstrate 100 in the cell area C and theactive fin 110 and thedevice isolation layer 120 may be exposed through an inter-spacer hole ISH. - For example, the
gap fill pattern 250 may be removed from thesubstrate 100 by an etching process using the dummygate electrode pattern 220, thegate spacer 240 as an etch mask. Since the dummygate electrode pattern 220 may include polysilicon and thegate spacer 240 may include silicon nitride while thegap fill pattern 250 may include silicon oxide, the etching process may be conducted in such a way that the etch rate of the silicon oxide may be sufficiently higher than those of the polysilicon and the silicon nitride. - Therefore, the inter-spacer trench IST may be formed into the inter-spacer hole ISH that may be defined by the
gate spacer 240 in the cell area C and the cutting pattern CP in the power area PA. Theactive fin 110 and thedevice isolation layer 120 may be exposed through the inter-spacer hole ISH. - For example, the
active fin 110 in the inter-spacer hole ISH may be further etched away in the etching process for removing thegap fill pattern 250, so that an upper portion of theupper fin 110 b may be removed to thereby form an active recess AR. Thus, theupper fin 110 b of the inter-spacer hole ISH may have a height that is smaller than that of theupper fin 110 b of thedummy gate structure 200. - Referring to
FIGS. 21 and 22A to 22D , thejunction layer 300 may be formed on theactive fin 110 and thedevice isolation layer 120 in the inter-spacer hole ISH. - For example, a selective epitaxial growth (SEG) process may be conducted in the inter-spacer hole ISH by using the
upper fin 110 b as a seed, thereby forming epitaxial layer in the inter-spacer hole ISH as thejunction layer 300. - In an exemplary embodiment, a silicon source gas such as a disilane (Si2H6) gas and a carbon source gas such as a SiH3CH3 gas may be provided for the SEG process and a single crystalline silicon carbide (SiC) layer may be formed on the
active fin 110 and thedevice isolation layer 120 as thejunction layer 300. Otherwise, the silicon source gas may be provided exclusively for the SEG process, and a single crystalline silicon (Si) layer may be formed on theactive fin 110 and thedevice isolation layer 120 as thejunction layer 300. - In such a case, an n-type impurity source gas such as a phosphine (PH3) gas may be provided in the SEG process together with the silicon source gas and/or the carbon source gas, and the single crystalline silicon carbide (SiC) layer and the single crystalline silicon (Si) layer ay be doped with the n-type impurities. Therefore, the
junction layer 300 doped with the n-type impurities may function as source/drain electrodes for the NMOS transistor in the NMOS area N. - In an exemplary embodiment, a silicon source gas such as a dichlorosilane H2SiCl2) gas and a germanium source gas such as a germanium tetrahydride (GeH4) gas may be provided for the SEG process and a single crystalline silicon germanium (SiGe) layer may be formed on the
active fin 110 and thedevice isolation layer 120 as thejunction layer 300. - In such a case, a p-type impurity source gas such as a diborane (B2H6) gas may be provided in the SEG process together with the silicon source gas and the germanium source gas, and the single crystalline silicon germanium (SiGe) layer may be doped with the p-type impurities. Therefore, the
junction layer 300 doped with the p-type impurities may function as source/drain electrodes for the PMOS transistor in the PMOS area P. - The
junction layer 300 may be grown in an isotropic behavior along horizontally and vertically, so that thejunction layer 300 may substantially fill up the active recess AR as well as growing in the second direction II in the inter-spacer hole ISH. For example, the cross sectional surface of thejunction layer 300 may be formed into a pentagonal/hexagonal shape. - When the neighboring
active fins 110 may be sufficiently adjacent to each other in the PMOS area P and the NMOS area N, the neighboringjunction layer 300 on the neighboringactive fins 110 may be connected to each other in the second direction II. Thus, thejunction layer 300 may be formed into broken line pieces in the PMOS area P and the NMOS area N. - As described above, the single
active fin 110 in the PMOS area P and the NMOS area N represents a plurality of theactive fins 110 that may be spaced apart from each other in the second direction II. Therefore, thejunction layer 300 may be sparsely arranged on the active fin or may be arranged in a line across a plurality of theactive fins 110 in the second direction II. - The
junction layer 300 may be grown horizontally into the separation area PNS from the peripheral portion of the NMOS area N and the PMOS areas P in the second direction II. For example, thejunction layer 300 in the first cell area C1 may be grown horizontally into the first separation area PNS1 and thejunction layer 300 in the second cell area C2 may be grown horizontally into the second separation area PNS2 in the second direction II. - For example, when the
junction layer 300 may be grown in the second direction II around the power area PA, the horizontal growth may be restricted by the cutting pattern CP and may be forced to transform into the vertical growth along the side surface of the cutting pattern CP in the third direction III. - Thus, the
junction layer 300 around the power area PA, may be grown vertically to a greater extent than thejunction layer 300 that is farther from the power area PA, and as result, the size of the junction layer 309 may be greater around the power area PA than around the power area PA. In addition, thejunction layer 300 may have the flat portion A making surface contact with the cutting pattern CP. - For example, since the epitaxial growth may occur in the isotropic behavior, the
junction layer 300 may be slanted upwards from theactive fin 110 to the cutting pattern CP and an air gap AG may be generated between the cutting pattern CP and thejunction layer 300 adjacent to the cutting pattern CP. The air gap may also be generated between the neighboring junction layers 300 in the PMOS area P and the NMOS area N due to the isotropic behavior of the SEG process. - The size of the flat portion A may be varied according to the process conditions of the SEG process. As described hereinafter, since the flat portion A may make contact with the
power contact 620, the contact resistance between thejunction layer 300 and thecontact structure 600 ay be reduced as the size of the flat portion A may increase. - When the vertical epitaxial growth of the
junction layer 300 may be non-uniform or unstable along the side surface of the cutting pattern CP, the flat portion A of thejunction layer 300 may be formed non-uniformly along the side surface of the cutting pattern CP. For example, when the vertical epitaxial growth may be insufficiently conducted on the side surface of the cutting pattern CP, the flat portion A may make point contact with the cutting pattern CP. In such a case, the flat portion A may be composed of all the contact points between thejunction layer 300 and the cutting pattern CP. - Since the
junction layer 300 that is farther from the cutting pattern CP may have no growth restrictor such as the cutting pattern CP in the second direction II, thejunction layer 300 that is farther from the cutting pattern CP may be grown horizontally as well as grown vertically without any substantial limitations. Thus, the connecting portion between the neighboring junction layers 300 may have a smaller size than the fiat portion A between thejunction layer 300 and the cutting pattern CP. For example, when the neighboringactive fins 110 may be sufficiently spaced apart front each other in the second direction or theactive fin 110 may be arranged around the separation area PNS, thejunction layer 300 may have a point portion B due to the non-restricted isotropic epitaxial growth behavior. - In addition, since the
junction layer 300 around the cutting pattern CP may be connected to thepower rail 700 via thepower contact 620, which will be described in detail hereinafter, the size increase of thejunction layer 300 around the cutting pattern CP may increase the process margin for forming thepower contact 620. - When the conventional semiconductor devices are reduced in size according to the recent device trends, the power area PA may also be reduced in size, and as a result, the junction layers separated from each other by the power area PA may be interconnected to each other across the power area PA. However, according to an exemplary embodiment of the present invention, the junction layers 300 in the first and the second cell areas C1 and C2 may be sufficiently separated from each other by the cutting pattern CP in the power area PA although the size of the power area PA may be reduced in size. Accordingly, an electric short of the
junction layer 300 between the first and the second cell areas C1 and C2 may be substantially prevented in the semiconductor device, thereby increasing the yield of the semiconductor device. - Referring to
FIGS. 23 and 24A to 24D , thedummy gate structure 200 may be removed from thesubstrate 100, thereby forming a gate trench extending in the second direction II and defined by thegate spacer 240. - An insulation layer may be formed on the
substrate 100 having thejunction layer 300 to a sufficient thickness for filling up the inter-spacer hole ISH. Thus, thegate spacer 240 and thedummy gate structure 200 may be at least partially covered with the insulation layer. For example, the insulation layer may include an oxide such as silicon oxide (SiO). - Then, the insulation layer may be planarized by the CMP process or the etch-back process until the upper surfaces of the dummy
gate electrode pattern 220 and thegate spacer 240. Thus, the insulation layer may exclusively remain in the inter-spacer hole ISH and may be formed into theinsulation pattern 400. Thus, thejunction layer 300 may be at least partially covered with theinsulation pattern 400. - Due to the planarization process, an upper surface of the
insulation pattern 400 may be coplanar with the upper surface of the dummygate electrode pattern 220 and thegate spacer 240. - Thereafter, the dummy ate
structure 200 may be removed from thesubstrate 100 and thedevice isolation layer 120 and theactive tin 110 may be exposed through an opening defined by thegate spacer 240 and the cutting pattern CP, thereby forming the gate trench extending in the second direction II in the cell area C. - For example, since the dummy
gate electrode pattern 220 may include polysilicon and the dummygate insulation pattern 210 may include silicon oxide, a dry etching process or a wet etching process may be conducted for removing the dummygate electrode pattern 220 and the dummygate insulation pattern 210 by using thegate spacer 240 and the cutting pattern CP as an etch mask. In the etching process for removing the dummygate electrode pattern 220 and the dummygate insulation pattern 210, damage to thejunction layer 300 may be prevented from occurring due to theinsulation pattern 400. - The gate trench may be defined by the
gate spacer 240 in the first direction I and by the cutting pattern CP in the second direction II. Thedevice isolation layer 120 and theactive fin 110 may be exposed through the gate trench. - Referring to
FIGS. 25 and 26A to 26D thegate structure 500 may be formed in the gate trench. - For example, a gate insulation layer and a work function control layer may be sequentially formed on the
substrate 100 along a surface profile of the gate trench and a gate electrode layer may be formed on the work function control layer in such a way that the gate trench may be sufficiently filled with the gate electrode layer. In a modified exemplary embodiment, an interface layer may be further formed between theactive fin 110 and the gate insulation layer. - The gate insulation layer may include a high dielectric metal oxide such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2). The work function control layer may include a metal nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN) or a metal alloy such as titanium aluminide (TiAL). Further, the gate electrode layer may include a lower resistive metal and a nitride of the lower resistive metal. Examples of the low resistive metal may include aluminum (Al), copper (Cu), tantalum (Ta), titanium, (Ti), and other metals having similar electrical resistances. These may be used alone or in combinations thereof. The work function control layer and the gate electrode layer may be formed by one of the chemical vapor deposition (CVD) process, the atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. Thereafter, a heat treatment such as a rapid thermal annealing (RTA), a spike RTA, a flash RTA and a laser annealing may be further conducted to the gate electrode layer.
- Then, the gate electrode layer, the work function control layer and the gate, insulation layer may be planarized until the upper surfaces of the
insulation pattern 400 and the cutting pattern CP may be exposed, thereby forming agate insulation pattern 510, a workfunction control pattern 520 and agate electrode 530 that may be sequentially formed on theactive fin 110 and thedevice isolation layer 120 and may fill up the gate trench as thegate structure 500. Thegate electrode 530 may be at least partially enclosed by the workfunction control pattern 520 in the gate trench. Thegate structure 500 may be arranged in the gate trench and may be formed into the gate line GL extending in the second direction II in the cell area C. - The
gate structure 500 and thejunction layer 300 in the PMOS area P may constitute the PMOS transistor and thegate structure 500 and thejunction layer 300 in the NMOS area N may constitute the NMOS transistor. In the present exemplary embodiment, thegate structure 500 may protrude from thedevice isolation layer 120 for enlarging the channel area of transistor, and thus the PMPS transistor and the NMOS transistor may be provided as finFET devices. - The
gate structures 500 in the first and the second cell areas C1 and C2 may be separated from each other in the second direction II by the cutting pattern CP in the power area PA. As described above, thejunction layer 300 in the first and the second cell areas C1 and C2 may also be separated from each other in the second direction II by the cutting pattern CP in the power area PA. - Therefore, an electric short of the
gate structures 500 between the first and the second cell areas C1 and C2 may be substantially prevented by the cutting pattern CP and an electric short of the junction layers 300 between the first and the second cell areas C1 and C2 may also be substantially prevented by the same cutting pattern CP. - Referring to
FIGS. 27 and 28A to 28E , a first contact hole CTH1 may be formed in the cell area C and a second contact hole CTH2 may be formed in the power area PA. Thejunction layer 300 in the PMOS area P and the NMOS area N may be exposed through the first contact hole CTH1 and thedevice isolation layer 200 may be exposed through the second contact hole CTH2. - A gate capping layer and a first interlayer dielectric layer may be sequentially formed on the
insulation pattern 400, thegate structure 500 and the cutting pattern CP. Then, the gate capping layer and the first interlayer dielectric layer may be patterned into thegate capping pattern 550 and the first interlayer dielectric pattern ILD1 through which theinsulation pattern 400 and the cutting pattern CP may be exposed. For example, thegate structure 500 and thegate spacer 240 may be at least partially covered by thegate capping pattern 550 and thegate capping pattern 500 may be at least partially covered with the first interlayer dielectric pattern ILD1. - in the present exemplary embodiment, the
gate insulation pattern 510 may include a nitride such as silicon nitride (SiN) and the first interlayer dielectric pattern ILD1 may include substantially the same materials as theinsulation pattern 400. However, the first interlayer dielectric pattern ILD1 may include insulation materials different from theinsulation pattern 400. - Thereafter, a peripheral portion of the cutting pattern CP may be removed from a peripheral portion of the power area PA, thereby forming the second contact hole CTH2 through which the
device isolation layer 120 may be exposed in the power area PA. Thus, the cutting pattern CP may be formed into the junction cutting pattern CP2 having a reduced width as much as the size of the second contact hole CTH2. The junction cutting pattern CP2 may be arranged at a central portion of the power area PA close to theinsulation pattern 400. In contrast, the cutting pattern CP close to thegate structure 500 might not be removed from the power area PA, and thus the width of cutting pattern CP may be unchanged. The unreduced cutting pattern CP close to thegate structure 500 may be referred to as the gate cutting pattern CPI as compared with the junction cutting pattern CP2. - Thereafter, the
insulation pattern 400 may be partially removed from the NMOS area N and the PMOS area P, thereby forming the first contact hole CTH1 through which thejunction layer 300 may be exposed. Thus, the contact hole CTH1 may include a PMOS contact hole PCTH through which thejunction layer 300 in the PMOS area P may be exposed and a NMOS contact hole NCTH through which thejunction layer 300 in the NMOS area N may be exposed. - For example, the
insulation pattern 400 might not be removed from the separation area PNS of the cell area C. For example, theinsulation pattern 400 at least partially covering the separation area PNS may remain on thedevice isolation layer 120 of the separation area PNS. Therefore, the PMOS contact hole PCTH and the NMOS contact hole NCTH may be separated from each other by theinsulation pattern 400 in the separation area PNS. - In addition, since the junction cutting pattern CP2 may remain in the central portion of the power area PA. the second contact hole CTH2 may be arranged at both sides of the junction cutting pattern CP2. For example, the second contact hole CTH2 in the first cell area C1 may be symmetrical to the second contact hole CTH2 in the second cell area C2 with respect to the junction cutting pattern CP2.
- In a modified exemplary embodiment, a metal silicide layer may be further formed on the
junction layer 300 exposed through the first contact hole CTH1. - Referring to
FIGS. 29 and 30A to 30E , the first and the second contact holes CTH1 and CTH2 may be filled with conductive materials, thereby forming thecontact structure 600 in the first and the second contact holes CTH1 and CTH2. - For example, a barrier layer may be formed an the
insulation pattern 400, the first interlayer dielectric pattern ILD1 and bottom and side walls of the first and the second contact holes CTH1 and CTH2 along a surface profile of the first and the second contact holes CTH1 and CTH2. A conductive layer may be formed on the harrier layer to a sufficient thickness for filling up the first and the second contact holes CTH1 and CTH2. - The barrier layer may include a metal such as tantalum and titanium and a nitride thereof, and the conductive layer may include a low resistive metal such as tungsten (W), copper (Cu), and/or aluminum (Al).
- The conductive layer and the barrier layer may be planarized until an upper surface of the first interlayer dielectric pattern ILD1 may be exposed, thereby forming a conductive line filling up, the first and the second contact holes CTH1 and CTH2 and extending in the second direction II. Thus, the conductive line may pass the cell area C and the power area PA alternately with each other in the second direction II. Thereafter, the conductive line may be further planarized until upper surfaces of the
insulation pattern 400 and the junction cutting pattern CP2 may be exposed, thereby forming thecontact structure 600 in the PMOS area P and the NMOS area N in such a configuration that an upper surface of thecontact structure 600 may be coplanar with the upper surfaces of the upper surfaces of theinsulation pattern 400 and the junction cutting pattern CP2. - The
contact structure 600 may include thecell contact 610 making contact with thejunction layer 300 in the PMOS area P and the NMOS area N and thepower contact 620 making contact with thedevice isolation layer 120 in the power area PA and connected to thecell contact 610 in one body. - The
cell contact 610 may be connected to thejunction layer 300 in the NMOS area N and the PMOS area P and thepower contact 620 may extend to the power area PA from thecell contact 610. For example, a pair of thepower contacts 620 may be formed at both sides of the junction cutting pattern CP2 symmetrically with respect to the junction cutting pattern CP2. Thus, thepower contact 620 in the first cell area C1 may be separated from thepower contact 520 in the second cell area C2, and thejunction 300 in the first cell area C1 might not be connected to thepower contact 620 in the second cell area C2 although the power area PA may be reduced in size. - As described hereinafter, the
power contact 620 may make contact with thepower rail 700 from which the power signal may be transferred to the MAIDS transistors and the PMOS transistors. - Thus, the
junction 300 in the first cell area C1 may be sufficiently separated from thepower contact 620 in the second cell area C2 by the junction cutting pattern CP2 and a pair of thepower contacts 620 may be arranged in the power area PA in such a configuration that the power contact in the first cell area C1 and the power contact in the second cell area C2 may be simultaneously in contact with thepower rail 700. Thus, the power signal may be simultaneously transferred to the first cell area C1 and the second cell area C2 via a pair of thepower contacts 620. For example, the transistors in the first cell area C1 and the second cell area C2 may be simultaneously operated through thesingle power rail 700. - Referring to
FIGS. 31 and 32A to 32E , a second interlayer dielectric pattern ILD2 may be formed on thecontact structure 600 and the first interlayer dielectric pattern ILD1 and thepower rail 700 may be formed on the first interlayer dielectric pattern ILD1 and may make contact with thepower contact 620 and the junction cutting pattern CP2. - For example, a second interlayer dielectric layer may be formed on the
contact structure 600 and the first interlayer dielectric pattern ILD1 and may be partially removed from the power area PA in such, a way that the first interlayer dielectric pattern ILD1, thepower contact 620 and the junction cutting pattern CP2 may be exposed, thereby forming a second interlayer dielectric pattern ILD2 having a power trench through which thepower contact 620 and the junction cutting pattern CP2 may be exposed. - In the present exemplary embodiment, the second interlayer dielectric pattern ILD2 may include silicon oxide. In a modified exemplary embodiment, the second interlayer dielectric pattern ILD2 may include a low dielectric material such as silicon oxide doped with carbon (C), silicon oxide doped with fluorine (F), porous silicon oxide, an organic polymer and an inorganic polymer such as HSSQ and MSSQ.
- Then, a power conductive layer may be formed on the second interlayer dielectric pattern ILD2 to a sufficient thickness for filling up the power trench and may be planarized until upper surface of the second interlayer dielectric pattern ILD2 may be exposed, thereby forming the
power rail 700. - Thus, the
power rail 700 may include apower line 720 extending in the first direction I and arranged on the first interlayer dielectric pattern ILD1 and apower plug 710 extending downwards from thepower line 720 and making contact with thepower contact 620 and the junction cutting pattern CP2. - The
power plug 710 may be shaped into a vertical rod and an upper surface of thepower plug 710 may have the same level as an upper surface of the first interlayer dielectric pattern ILD1. Thepower line 720 may be arranged on the first interlayer dielectric pattern ILD1 and thepower plug 710 in the first direction I. An external power signal may be applied to thepower line 720 and may be transferred to the NMOS and PMOS transistors in the cell area C via thepower plug 710 and thepower contact 620. For example, the transistors in both of the first cell area C1 and the second cell area C2 may be simultaneously operated by a pair of thepower contacts 620. - A plurality of additional interlayer dielectric patterns may be further formed on the second interlayer dielectric pattern ILD2 and the
power rail 700 and additional contact structures and wirings may be further formed on the additional interlayer dielectric patterns so as to connect to the transistors in the cell area C. - According to the method of manufacturing the semiconductor devices, the cutting pattern CP may be formed in the power area PA and thus the horizontal growth of the
junction layer 300 may be restricted by the cutting pattern CP. Accordingly, thejunction layer 300 in the first cell area C1 may be substantially prevented from being connected with thejunction layer 300 in the second cell area C2 although the power area PA may be reduced in size, thereby preventing an electric short of thejunction layer 300 between the first and the second cell areas C1 and C2. - In addition, the
gate structure 500 in the first cell area C1 may also be sufficiently separated from thegate structure 500 in the second cell area C2 by the cutting pattern CP, so that thegate structure 500 in the first cell area C1 may be substantially prevented from being connected with thegate structure 500 in the second cell area C2 although the power area PA may be reduced in size, thereby preventing an electric short of thegate structure 500 between the first and the second cell areas C1 and C2. - Further, a pair of the
power contacts 620 may be formed at both sides of the junction cutting pattern CP2, symmetrically with respect to the junction cutting pattern CP2, and thus thepower contact 620 in the first cell area C1 may be sufficiently separated from thepower contact 620 in the second cell area C2. Therefore, thepower contact 620 in the first cell area C1 might not be connected to thepower contact 620 in the second cell area C2 due to the junction cutting pattern CP, thereby preventing electric short of thepower contacts 620. - Although the power area PA may be reduced in size in accordance with the size reduction, of the recent semiconductor devices, the
gate structure 500 and thejunction layer 300 in different cell area may be sufficiently separated by a unit of the cell area. Thus, air electric short of thegate structure 500 and thejunction layer 300 may be substantially prevented in spite of the size reduction of the power area PA. - While the present exemplary embodiment discloses the cutting pattern CP for sufficiently separating the
gate structure 500 and thejunction layer 300 by the cell area in spite of the size reduction of the power area PA, an electric short of thegate structure 500 and thejunction layer 300 may also occur in the separation area PNS in the cell area C. Thus, the separation of thegate structure 500 and thejunction layer 300 may also be used between the CMOS area N and the PMSO area P. -
FIGS. 33 to 40F are views illustrating processing steps of a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present inventive concept. InFIGS. 33 to 40F , odd-numbered figures are plan views illustrating each processing step for the manufacturing method and even-numbered figures are cross sectional views corresponding to the odd-numbered figure. Each figure designated by the subscript ‘A’ in the drawing number is a cross-sectional view cut along a line A-A′ of the semiconductor device shown inFIG. 3 , and each figure designated by the subscript ‘B’ in the drawing number is a cross-sectional view cut along a line B-B′ of the semiconductor device shown inFIG. 3 . In addition, each figure designated by the subscript ‘C’ in the drawing number is a cross-sectional view cut along a line C-C′ of the semiconductor device shown inFIG. 3 , and each figure designated by the subscript ‘D’ in the drawing number is a cross-sectional view cut along a fine D-D′ of the semiconductor device shown inFIG. 3 . Each figure designated by the subscript ‘E’ in the drawing number is a cross-sectional view cut along a line E-E′ of the semiconductor device shown inFIG. 3 , and each figure designated by the subscript ‘F’ in the drawing number is a cross-sectional view cut along a line F-F′ of the semiconductor device shown inFIG. 3 . - Referring to
FIGS. 33 and 34A to 34D , the gate trench may be formed on thesubstrate 100 by the same processes as described in detail with references toFIGS. 5 to 24D and then a separating opening SO may be formed in the separation area PNS. - For example, an additional mask pattern AMP may be formed on a whole surface of the
substrate 100 having the gate trench in such a way that the PMOS area P, the NMOS area N and the power area PA may be at least partially covered with the additional mask pattern AMP and the separation area PNS may be partially or wholly exposed through the additional mask pattern AMP. In such a case, the gate trench may be filled with the additional mask pattern AMP. - Then, the
gate spacer 240 and theinsulation pattern 400 may be partially or wholly removed from thesubstrate 100 by a dry etching process using the additional mask pattern AMP as an etch mask, thereby forming the separating opening SO through which thedevice isolation layer 120 may be exposed. - For example, the separating opening SO may be disposed across the gate trench and the
junction layer 300 in the first direction I. Thejunction layer 300 in the PMOS area P may extend in the separation area PNS and thejunction layer 300 in the NMOS area N may extend in the separation area PNS, and the separating opening SO may be formed in the gap space between a pair of the junction layers 300. - When the size of the cell area C may be reduced, the
gate structures 500 of the PMOS area P and the NMOS area N may be connected'to each other in the separation area PNS and the junction layers 300 of the PMOS area P and the NMOS area N may be connected to each other in the separation area PNS. Thus, when the cell area C may be reduced in size, an electric short of thegate structure 500 and thejunction layer 300 may occur in the separation area PNS. - However, according to exemplary embodiments of the present invention, a separation pattern SP may be provided in the separation area PNS for sufficiently separating the
gate structure 500 and thejunction layer 300 in the PMOS area P from thegate structure 500 and thejunction layer 300 in the NMOS area N, thereby preventing an electric short between thegate structures 500 and the junction layers 300 in different cell area C. - Referring to
FIGS. 35 and 36A to 36D , a separating pattern SP may be formed in the separating opening SO for separating the PMOS area P and the NMOS area N in the cell area C. - For example, an additional gap fill layer may be formed on the additional mask pattern AMP to a sufficient thickness for filling the separating opening SO, and then the additional gap fill layer may be planarized until upper surfaces of the
insulation pattern 400 and the cutting pattern CP may be exposed. Thus, the additional gap fill layer may remain exclusively in the separating opening SO, thereby forming the separating pattern SP in the separating opening SO and the PMOS area P and the NMOS area N may be sufficiently separated from each other by the separating pattern SP. - The separating pattern SP may include the same materials as the cutting pattern CP. Thus, the separating pattern SP may include silicon nitride (SiN), silicon oxynitride (SiON), and/or silicon carbon oxynitride (SiOCN).
- Thereafter, the additional mask pattern AMP may be removed from the
substrate 100 and the gate trench may be exposed again. - Referring to
FIGS. 37 and 38A to 38D , thegate structure 500 may be formed in the gate trench. - For example, a gate insulation layer and a work function control layer may be sequentially formed on the
substrate 100 along a surface profile of the gate trench and a gate electrode layer may be thrilled on the work function control layer in such a way that the gate trench may be sufficiently filled with the gate electrode layer. Thus, theactive fin 110, thedevice isolation layer 120, thegate spacer 240, theinsulation pattern 400, the cutting pattern CP and the separating pattern SF may be at least partially covered by the gate insulation layer, work function control layer, and the gate electrode layer. In a modified exemplary embodiment, an interface layer may be further formed between theactive fin 110 and the gate insulation layer. - Then, the gate electrode layer, the work function control layer and the gate insulation layer may be planarized until the upper surfaces of the
insulation pattern 400, the separating pattern SP and the cutting pattern CP may be exposed, thereby forming agate insulation pattern 510, a workfunction control pattern 520 and agate electrode 530 that may be sequentially formed on theactive fin 110 and thedevice isolation layer 120 and may fill up the gate trench as thegate structure 500. Thegate electrode 530 may be at least partially enclosed by the workfunction control pattern 520 in the gate trench. Thegate structure 500 may be arranged in the gate trench and may be formed into the gate line GL extending in the second direction in the cell area C. - For example, the
gate structure 500, extending from the PMOS area P, may be sufficiently separated from thegate structure 500, extending from the NMOS area N, by the separation pattern SP. Thus, an electric short of thegate structures 500 in the separation area. PNS may be substantially prevented by the separating pattern SP. - The
gate structure 500 may be formed substantially by the same processes as described above in detail with references toFIGS. 23 to 24D , so to the extent that any further detailed descriptions of various elements is omitted, it may be assumed that these elements are at least similar to corresponding elements that have already been described. - Thereafter, as illustrated in
FIGS. 39 and 40A to 40F , thecontact structure 600, the first interlayer dielectric pattern ILD1, the second interlayer dielectric pattern ILD2 and thepower rail 700 may be formed substantially by the same processes as described in detail with references toFIGS. 27 to 32E , so to the extent that any further detailed descriptions on the method of forming thecontact structure 600, the first interlayer dielectric pattern ILD1, the second interlayer dielectric pattern ILD2 and thepower rail 700, is omitted, it may be assumed that these elements are at least similar to corresponding elements that have already been described. - Therefore, the
gate structure 500 and thejunction layer 300 may be sufficiently separated from each other in the separation area PNS by the separating pattern SP. Thus, the NMOS transistor and the PMOS transistor may be sufficiently separated, from each other in the separation area PNS by the separating pattern SP in spite of the size reduction of the cell area C. - According to the exemplary embodiments of the present inventive concept, the cutting pattern CP may be formed in the power area PA and thus the horizontal growth of the
junction layer 300 may be restricted by the cutting pattern CP. Accordingly, thejunction layer 300 in the first cell area C1 may be sufficiently separated from thejunction layer 300 in the second cell area C2 although the power area PA may be reduced in size, thereby preventing an electric short of thejunction layer 300 between the first and the second cell areas C1 and C2. - In addition, the
gate structure 500 in the first cell area C1 may also be sufficiently separated from thegate structure 500 in the second cell area C2 by the cutting pattern CP, so that thegate structure 500 in the first cell area C1 may be, substantially prevented from being connected with thegate structure 500 in the second cell area C2 although the power area PA may be reduced in size, thereby preventing an electric short of thegate structure 500 between the first and the second cell areas C1 and C2. - Further, the
gate structure 500 and thejunction layer 300 may be sufficiently separated from each other in the separation area PNS by the separating pattern SR. Thus, the NMOS transistor and the PMOS transistor may be sufficiently separated from each other in the separation area PNS by the separating pattern SP in spite of the size reduction of the cell area C. The semiconductor device may be formed into a CMOS device with high reliability and stability - Furthermore, a pair of the
power contacts 620 may be formed at both sides of the junction cutting pattern CP2 symmetrically with respect to the junction cutting pattern CP2 and thus thepower contact 620 in the first cell area C1 may be sufficiently separated from thepower contact 620 in the second cell area C2. Therefore, thepower contact 520 in the first cell area C1 might not be connected to thepower contact 520 in the second cell area C2 due to the junction cutting pattern CP, thereby preventing electric short of thepower contacts 620. - Although the power area PA may be reduced in size in accordance with the size reduction of the recent semiconductor devices, the
gate structure 500 and thejunction layer 300 in different cell area may be sufficiently separated by a unit of the cell area. Thus, an electric short of thegate structure 500 and thejunction layer 300 may be substantially prevented in spite of the size reduction of the power area PA. - For example, when the CMOS device having the cutting pattern in the power area PA and/or the separating pattern SP in the separation area PNS may be stored into a standard cell library as a CMOS standard cell, the logic, device requiting CMOS cells may be stably manufactured with high reliability by using the CMOS standard cell and electric shorts in the power area PA and the separation area PNS may be sufficiently reduced in the logic device.
- The foregoing is illustrative of exemplary embodiments of the present invention and the present invention should not be construed as being limited to the embodiments shown. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments shown without materially departing from the novel teachings and aspects of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.
Claims (20)
1. A semiconductor device, comprising:
a substrate including a plurality of cell areas and a plurality of power areas such that each of the plurality of cell areas are alternately arranged with each of the plurality of power areas, in a second direction;
a plurality of gate structures extending in the second direction, each of the plurality of gate structures being spaced apart from each other in a first direction that is substantially perpendicular to the second direction;
a plurality of junction layers arranged at both sides of each of the plurality of gate structures and arranged in the second direction in such a configuration that each of the plurality of junction layer has a flat portion that is proximate to the power area; and
a plurality of cutting patterns arranged in the plurality of power areas and extending in the first direction such that each of the plurality of gate structures and each of the plurality of junction layers in neighboring cell areas of the plurality of cell areas are separated from each other by the cutting pattern.
2. The semiconductor device of claim 1 , wherein each oaf the plurality of junction layers includes an epitaxial layer grown in the second direction from a plurality of active fins extending in the first direction such that the epitaxial layer is largest around each of the plurality of power areas.
3. The semiconductor device of claim 2 , wherein the epitaxial layer includes a point portion that is spaced apart horn each of the plurality of power areas.
4. The semiconductor device of claim 1 , further comprising:
a power rail extending in the first direction on the cutting pattern and to which a power signal is applied; and
a contact structure in contact with the power rail and the plurality of junction layers and configured to transfer the power signal to the plurality of junction layers from the power rail.
5. The semiconductor device of claim 4 , wherein the contact structure includes:
a cell contact that is in contact with the junction layer in the cell area: and a power contact arranged at a side of the cutting pattern, in contact with the flat portion of each of the plurality of junction layers and the power rail.
6. The semiconductor device of claim 5 , wherein the cutting pattern includes a gate cutting pattern directly contacting each of the plurality of gate structures and having a first width, and a junction cutting, pattern that is spaced apart from the flat portion of each of the plurality of junction layers by a second contact bole and having a second width smaller than the first width, the gate cutting pattern and the junction cutting pattern being arranged alternately with each other in the first direction.
7. The semiconductor device of claim 6 , wherein the power contact is arranged in the second contact hole such that a bottom surface of the power contact is in contact with a device isolation layer and a side surface of the power contact is in contact with the flat portion of each of the plurality of junction layers.
8. The semiconductor device of claim 1 , wherein each of the plurality of cell areas includes a PMOS area in which at least one p-type MOS transistor is arranged, an NMOS area in which at least one n-type MOS transistor is arranged, and a separation area interposed between the PMOS area and the NMOS area and separating the PMOS area and the NMOS area from each other, wherein the cutting pattern includes a nitride.
9. The semiconductor device of claim 8 , further comprising a separation pattern disposed on the separation area of each of the plurality of cell areas such that the plurality of gate structures and the plurality of junction layers in the NMOS area are separated from the plurality of gate structures and the plurality of junction layers in the PMOS area.
10. The semiconductor device of claim 9 , wherein the separation pattern is arranged across at least one gate structure of the plurality of gate structures and at least one junction layer of the plurality of junction layers, in the first direction.
11. The semiconductor device of claim 10 , wherein the separation pattern includes a same material as the cutting pattern.
12. A method of manufacturing a semiconductor device, comprising:
forming a plurality of active fins in at least a pair of cell areas extending in a first direction, the pair of cell areas being separated from each other by a power area;
forming a plurality of dummy gate structures and a plurality of gap fill patterns to a line shape extending in a second direction, substantially perpendicular to the first direction, such that each of the plurality of dummy gate structures and each of the plurality of gap fill patterns covers the plurality of active fins, alternately with respect to each other in the first direction, forming a cutting pattern in the power area in a line shape extending in the first direction such that the plurality of dummy gate structures and the plurality of gap fill patterns are separated from each other by a unit of a cell area of the at least the pair of cell areas; and
forming a junction layer in a gap space between neighboring dummy gate structures, of the plurality of dummy gate structures, such that the junction layer makes contact with the plurality of active fins in the at least the pair of cell areas and has a flat portion making contact with the cutting pattern.
13. The method of claim 12 , wherein forming the cutting pattern includes:
partially removing each of the plurality of dummy gate structures, a gate spacer on side surfaces of each of the plurality of dummy gate structures and each of the plurality of gap fill patterns from the power area, thereby forming a cutting trench through which a device isolation layer is exposed;
forming a cutting layer on each of the plurality of dummy gate structures, the gate spacer and each of the plurality of gap fill patterns and the device isolation layer to a thickness for filling the cutting trench; and
planarizing the cutting layer until upper surfaces of each of the plurality of dummy gate structures, the gate spacer and each of the plurality of gap till patterns, so that the cutting layer remains exclusively in the cutting trench.
14. The method of claim 13 , wherein the cutting pattern includes silicon nitride (SiN), silicon oxynitride (SiON), and/or silicon carbon oxynitride (SiOCN).
15. The method of claim 13 , wherein forming the junction layer includes:
removing each of the plurality of gap fill patterns from the at least the pair of cell areas, thereby forming an inter-spacer hole defined by neighboring gate spacers of the plurality of dummy gate structures and the cutting pattern and through which the plurality of active fins and the device isolation layer are exposed; and
conducting a selective epitaxial growth (SEG) process using the plurality of active fins as a seed such that the junction layer is horizontally grown to the cutting pattern in the second direction and is vertically grown along a side surface of the cutting pattern in a third direction substantially perpendicular to the first and the second directions to thereby form the flat portion making contact with the cutting pattern.
16. The method of claim 15 , wherein an upper portion of each of the plurality of active fins is removed from the inter-spacer hole in removing the gap fill pattern to thereby form an active recess in the inter-spacer hole, so that the junction layer is protruded into the active recess.
17. The method of claim 12 , further comprising:
forming an insulation pattern at least partially covering the junction layer;
forming a gate trench extending in the second direction in the cell area by removing the plurality of dummy gate structures from the cell area;
forming a gate structure such that the gate trench is tilled with the gate structure;
forming a contact structure making contact with the junction layer; and
firming a power rail arranged on the cutting pattern and extending in the first direction such that the power rail makes contact with the contact structure.
18. The method of claim 17 , wherein forming the contact structure includes:
forming a first interlayer dielectric pattern on each of the plurality of gate structures and the cutting pattern in a line extending in the second direction such that the insulation pattern and the cutting pattern are exposed through the first interlayer dielectric pattern;
removing the insulation pattern from the cell area, thereby forming a first contact hole through which the junction layer under the insulation pattern is exposed;
removing a peripheral portion of the cutting pattern from the power area, thereby forming a second pattern through which a device isolation layer under the cutting pattern and a side surface of the flat portion of the junction layer is exposed and a junction cutting pattern having a width smaller than that of the cutting pattern under the first interlayer dielectric pattern; and
forming a cell contact in the first contact hole and a power contact in the second contact hole such that the cell contact makes contact with the junction layer in the cell area and the power contact makes contact with the device isolation layer.
19. The method of claim 17 , further comprising, after forming the gate trench, forming a separation pattern for separating an NMOS transistor and a PMOS transistor on a separation area between an NMOS in which the NMOS transistors are arranged area and a PMOS area in which the PMOS transistors are arranged in the cell area.
20. The method of clam 19, wherein forming the separation pattern includes:
forming an additional mask pattern on an entire surface of the substrate having the gate trench such that at least a portion of the separation area is exposed through the additional mask pattern;
forming a separation opening through which a device isolation layer surrounding the active fin is exposed by partially removing a gate spacer defining the gate trench and the insulation pattern at least partially covering the junction layer between the neighboring gate spacers, and
filling the separation opening with insulation materials.
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021173243A1 (en) * | 2020-02-24 | 2021-09-02 | Qualcomm Incorporated | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication |
TWI773277B (en) * | 2020-04-29 | 2022-08-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and method of manufacturing the same |
US20220336288A1 (en) * | 2021-04-16 | 2022-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US20220384250A1 (en) * | 2021-02-26 | 2022-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement material for backside gate cut feature |
US11532712B2 (en) | 2020-04-29 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company Limited | Interconnect structures for semiconductor devices and methods of manufacturing the same |
US11532703B2 (en) | 2020-05-27 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US11600639B2 (en) | 2018-08-02 | 2023-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
EP4345878A1 (en) * | 2022-09-30 | 2024-04-03 | INTEL Corporation | Forming metal gate cuts using multiple passes for depth control |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102020134570A1 (en) * | 2020-05-27 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR DEVICE AND METHOD |
Citations (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157768B2 (en) * | 2002-05-10 | 2007-01-02 | Infineon Technologies Ag | Non-volatile flash semiconductor memory and fabrication method |
US7352037B2 (en) * | 2005-07-22 | 2008-04-01 | Samsung Electronics Co., Ltd. | Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions |
US7723786B2 (en) * | 2007-04-11 | 2010-05-25 | Ronald Kakoschke | Apparatus of memory array using FinFETs |
US20120012937A1 (en) * | 2010-07-14 | 2012-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | interconnection structure for n/p metal gates |
US20140319623A1 (en) * | 2011-12-28 | 2014-10-30 | Curtis Tsai | Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process |
US20160056181A1 (en) * | 2014-08-19 | 2016-02-25 | International Business Machines Corporation | Methods of forming field effect transistors using a gate cut process following final gate formation |
US9331074B1 (en) * | 2015-01-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20160133632A1 (en) * | 2014-11-12 | 2016-05-12 | Hong-bae Park | Integrated circuit device and method of manufacturing the same |
US20160181425A1 (en) * | 2014-12-18 | 2016-06-23 | Keun Hee BAI | Method for manufacturing semiconductor device |
US20160233298A1 (en) * | 2013-12-19 | 2016-08-11 | Intel Corporation | Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same |
US20160247728A1 (en) * | 2015-02-23 | 2016-08-25 | Junggun YOU | Method of fabricating semiconductor device |
US20160300948A1 (en) * | 2015-04-07 | 2016-10-13 | Qualcomm Incorporated | Finfet with cut gate stressor |
US20160336183A1 (en) * | 2015-05-14 | 2016-11-17 | Globalfoundries Inc. | Methods, apparatus and system for fabricating finfet devices using continuous active area design |
US9520482B1 (en) * | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US20170062403A1 (en) * | 2015-08-28 | 2017-03-02 | Samsung Electronics Co., Ltd. | Semiconductor device |
US9601567B1 (en) * | 2015-10-30 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple Fin FET structures having an insulating separation plug |
US20170084723A1 (en) * | 2015-09-18 | 2017-03-23 | International Business Machines Corporation | Semiconductor device replacement metal gate with gate cut last in rmg |
US20170133379A1 (en) * | 2015-10-06 | 2017-05-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
US9653579B2 (en) * | 2014-05-19 | 2017-05-16 | Stmicroelectronics, Inc. | Method for making semiconductor device with filled gate line end recesses |
US9704860B1 (en) * | 2016-10-05 | 2017-07-11 | International Business Machines Corporation | Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation |
US9806166B2 (en) * | 2016-01-13 | 2017-10-31 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
US9911736B1 (en) * | 2017-06-14 | 2018-03-06 | Globalfoundries Inc. | Method of forming field effect transistors with replacement metal gates and contacts and resulting structure |
US9947592B2 (en) * | 2015-11-16 | 2018-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET devices and methods of forming the same |
US9954076B2 (en) * | 2015-11-04 | 2018-04-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20180261514A1 (en) * | 2017-03-10 | 2018-09-13 | Globalfoundries Inc. | Fin-type field effect transistors (finfets) with replacement metal gates and methods |
US10083961B2 (en) * | 2016-09-07 | 2018-09-25 | International Business Machines Corporation | Gate cut with integrated etch stop layer |
US10090402B1 (en) * | 2017-07-25 | 2018-10-02 | Globalfoundries Inc. | Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates |
US10115722B2 (en) * | 2016-05-17 | 2018-10-30 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for manufacturing the same |
US10176995B1 (en) * | 2017-08-09 | 2019-01-08 | Globalfoundries Inc. | Methods, apparatus and system for gate cut process using a stress material in a finFET device |
US10269802B2 (en) * | 2015-05-15 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20190165137A1 (en) * | 2017-11-29 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Structure Cutting Process and Structures Formed Thereby |
US10319720B2 (en) * | 2017-07-05 | 2019-06-11 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
US20190189452A1 (en) * | 2017-12-18 | 2019-06-20 | International Business Machines Corporation | Metal cut patterning and etching to minimize interlayer dielectric layer loss |
US10354997B2 (en) * | 2017-04-28 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing semiconductor device with replacement gates |
US10373879B2 (en) * | 2017-04-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with contracted isolation feature and formation method thereof |
US10483369B2 (en) * | 2017-10-30 | 2019-11-19 | Globalfoundries Inc. | Methods of forming replacement gate structures on transistor devices |
US10490458B2 (en) * | 2017-09-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of cutting metal gates and structures formed thereof |
US10497778B2 (en) * | 2017-11-30 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10504798B2 (en) * | 2018-02-15 | 2019-12-10 | Globalfoundries Inc. | Gate cut in replacement metal gate process |
US10505546B2 (en) * | 2018-02-28 | 2019-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device |
US20190393205A1 (en) * | 2018-06-25 | 2019-12-26 | Samsung Electronics Co., Ltd. | Integrated circuit including multi-height standard cell and method of designing the same |
US10553592B2 (en) * | 2017-03-07 | 2020-02-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Fabrication method of a semiconductor structure by a gate cutting process with multiple sidewall spacers formation in a dummy gate opening |
US10553700B2 (en) * | 2018-05-29 | 2020-02-04 | International Business Machines Corporation | Gate cut in RMG |
US10607896B2 (en) * | 2016-05-11 | 2020-03-31 | Imec Vzw | Method of forming gate of semiconductor device and semiconductor device having same |
US10636886B2 (en) * | 2018-03-27 | 2020-04-28 | Samsung Electronics Co., Ltd. | Semiconductor device |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100887017B1 (en) | 2007-05-18 | 2009-03-04 | 주식회사 동부하이텍 | Lateral dmos device structure and its fabrication method |
JP5221107B2 (en) | 2007-11-12 | 2013-06-26 | 花王株式会社 | Method for producing aliphatic carboxylic acid amide |
EP3117709B1 (en) | 2010-03-12 | 2018-08-01 | Genzyme Corporation | Combination therapy for treating breast cancer |
US9984076B2 (en) | 2013-09-27 | 2018-05-29 | Here Global B.V. | Method and apparatus for determining status updates associated with elements in a media item |
EP3134009B1 (en) | 2014-04-25 | 2020-07-15 | Sharp Fluidics LLC | Systems for increased operating room efficiency |
US10483389B2 (en) | 2014-07-02 | 2019-11-19 | Hestia Power Inc. | Silicon carbide semiconductor device |
US9431383B2 (en) | 2014-07-22 | 2016-08-30 | Samsung Electronics Co., Ltd. | Integrated circuit, semiconductor device based on integrated circuit, and standard cell library |
US20160058181A1 (en) | 2014-09-03 | 2016-03-03 | Qing Han | Systems and Methods for Securing and Temperature Regulating a Delivery Container |
US9245883B1 (en) * | 2014-09-30 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
US9583493B2 (en) | 2015-04-08 | 2017-02-28 | Samsung Electronics Co., Ltd. | Integrated circuit and semiconductor device |
KR102293185B1 (en) * | 2015-04-21 | 2021-08-24 | 삼성전자주식회사 | Semiconductor device having contact plugs and method of forming the same |
CN104752345B (en) | 2015-04-27 | 2018-01-30 | 深圳市华星光电技术有限公司 | Thin-film transistor array base-plate and preparation method thereof |
US9720836B2 (en) | 2015-05-11 | 2017-08-01 | International Business Machines Corporation | Preemptible-RCU CPU hotplugging while maintaining real-time response |
KR101785803B1 (en) * | 2015-05-29 | 2017-10-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Structure and formation method of semiconductor device structure |
KR102358571B1 (en) | 2015-07-29 | 2022-02-07 | 삼성전자주식회사 | Integrated circuit and standard cell library |
KR102406947B1 (en) * | 2015-10-08 | 2022-06-10 | 삼성전자주식회사 | Semiconductor Devices |
US20170148682A1 (en) | 2015-11-19 | 2017-05-25 | International Business Machines Corporation | Finfet with post-rmg gate cut |
KR102455869B1 (en) | 2015-12-23 | 2022-10-20 | 에스케이하이닉스 주식회사 | Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same |
US9904758B2 (en) | 2016-05-18 | 2018-02-27 | Samsung Electronics Co., Ltd. | Using deep sub-micron stress effects and proximity effects to create a high performance standard cell |
US10079289B2 (en) * | 2016-12-22 | 2018-09-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structure and methods thereof |
US10607696B2 (en) | 2018-01-16 | 2020-03-31 | Microsemi Soc Corp. | FPGA configuration cell utilizing NVM technology and redundancy |
KR102647231B1 (en) | 2018-08-02 | 2024-03-13 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
-
2018
- 2018-08-02 KR KR1020180090472A patent/KR102647231B1/en active IP Right Grant
-
2019
- 2019-02-07 US US16/270,214 patent/US20200043945A1/en not_active Abandoned
- 2019-04-23 CN CN201910331372.5A patent/CN110797306A/en active Pending
-
2020
- 2020-11-02 US US17/087,321 patent/US11600639B2/en active Active
-
2023
- 2023-02-28 US US18/176,463 patent/US20230215868A1/en active Pending
Patent Citations (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157768B2 (en) * | 2002-05-10 | 2007-01-02 | Infineon Technologies Ag | Non-volatile flash semiconductor memory and fabrication method |
US7352037B2 (en) * | 2005-07-22 | 2008-04-01 | Samsung Electronics Co., Ltd. | Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions |
US7723786B2 (en) * | 2007-04-11 | 2010-05-25 | Ronald Kakoschke | Apparatus of memory array using FinFETs |
US20120012937A1 (en) * | 2010-07-14 | 2012-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | interconnection structure for n/p metal gates |
US20140319623A1 (en) * | 2011-12-28 | 2014-10-30 | Curtis Tsai | Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process |
US20160233298A1 (en) * | 2013-12-19 | 2016-08-11 | Intel Corporation | Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same |
US9653579B2 (en) * | 2014-05-19 | 2017-05-16 | Stmicroelectronics, Inc. | Method for making semiconductor device with filled gate line end recesses |
US9373641B2 (en) * | 2014-08-19 | 2016-06-21 | International Business Machines Corporation | Methods of forming field effect transistors using a gate cut process following final gate formation |
US20160056181A1 (en) * | 2014-08-19 | 2016-02-25 | International Business Machines Corporation | Methods of forming field effect transistors using a gate cut process following final gate formation |
US20160133632A1 (en) * | 2014-11-12 | 2016-05-12 | Hong-bae Park | Integrated circuit device and method of manufacturing the same |
US20160181425A1 (en) * | 2014-12-18 | 2016-06-23 | Keun Hee BAI | Method for manufacturing semiconductor device |
US9331074B1 (en) * | 2015-01-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20160247728A1 (en) * | 2015-02-23 | 2016-08-25 | Junggun YOU | Method of fabricating semiconductor device |
US20160300948A1 (en) * | 2015-04-07 | 2016-10-13 | Qualcomm Incorporated | Finfet with cut gate stressor |
US20160336183A1 (en) * | 2015-05-14 | 2016-11-17 | Globalfoundries Inc. | Methods, apparatus and system for fabricating finfet devices using continuous active area design |
US10269802B2 (en) * | 2015-05-15 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20170062403A1 (en) * | 2015-08-28 | 2017-03-02 | Samsung Electronics Co., Ltd. | Semiconductor device |
US20170084723A1 (en) * | 2015-09-18 | 2017-03-23 | International Business Machines Corporation | Semiconductor device replacement metal gate with gate cut last in rmg |
US20170133379A1 (en) * | 2015-10-06 | 2017-05-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
US9601567B1 (en) * | 2015-10-30 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple Fin FET structures having an insulating separation plug |
US9954076B2 (en) * | 2015-11-04 | 2018-04-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9520482B1 (en) * | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9947592B2 (en) * | 2015-11-16 | 2018-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET devices and methods of forming the same |
US9806166B2 (en) * | 2016-01-13 | 2017-10-31 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
US10607896B2 (en) * | 2016-05-11 | 2020-03-31 | Imec Vzw | Method of forming gate of semiconductor device and semiconductor device having same |
US10115722B2 (en) * | 2016-05-17 | 2018-10-30 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for manufacturing the same |
US10083961B2 (en) * | 2016-09-07 | 2018-09-25 | International Business Machines Corporation | Gate cut with integrated etch stop layer |
US9704860B1 (en) * | 2016-10-05 | 2017-07-11 | International Business Machines Corporation | Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation |
US10553592B2 (en) * | 2017-03-07 | 2020-02-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Fabrication method of a semiconductor structure by a gate cutting process with multiple sidewall spacers formation in a dummy gate opening |
US20180261514A1 (en) * | 2017-03-10 | 2018-09-13 | Globalfoundries Inc. | Fin-type field effect transistors (finfets) with replacement metal gates and methods |
US10373879B2 (en) * | 2017-04-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with contracted isolation feature and formation method thereof |
US10354997B2 (en) * | 2017-04-28 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing semiconductor device with replacement gates |
US9911736B1 (en) * | 2017-06-14 | 2018-03-06 | Globalfoundries Inc. | Method of forming field effect transistors with replacement metal gates and contacts and resulting structure |
US10319720B2 (en) * | 2017-07-05 | 2019-06-11 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
US10090402B1 (en) * | 2017-07-25 | 2018-10-02 | Globalfoundries Inc. | Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates |
US10176995B1 (en) * | 2017-08-09 | 2019-01-08 | Globalfoundries Inc. | Methods, apparatus and system for gate cut process using a stress material in a finFET device |
US10490458B2 (en) * | 2017-09-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of cutting metal gates and structures formed thereof |
US10483369B2 (en) * | 2017-10-30 | 2019-11-19 | Globalfoundries Inc. | Methods of forming replacement gate structures on transistor devices |
US20190165137A1 (en) * | 2017-11-29 | 2019-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Structure Cutting Process and Structures Formed Thereby |
US10497778B2 (en) * | 2017-11-30 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20190189452A1 (en) * | 2017-12-18 | 2019-06-20 | International Business Machines Corporation | Metal cut patterning and etching to minimize interlayer dielectric layer loss |
US10504798B2 (en) * | 2018-02-15 | 2019-12-10 | Globalfoundries Inc. | Gate cut in replacement metal gate process |
US10505546B2 (en) * | 2018-02-28 | 2019-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10636886B2 (en) * | 2018-03-27 | 2020-04-28 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10553700B2 (en) * | 2018-05-29 | 2020-02-04 | International Business Machines Corporation | Gate cut in RMG |
US20190393205A1 (en) * | 2018-06-25 | 2019-12-26 | Samsung Electronics Co., Ltd. | Integrated circuit including multi-height standard cell and method of designing the same |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11600639B2 (en) | 2018-08-02 | 2023-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2021173243A1 (en) * | 2020-02-24 | 2021-09-02 | Qualcomm Incorporated | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication |
US11295991B2 (en) * | 2020-02-24 | 2022-04-05 | Qualcomm Incorporated | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication |
TWI773277B (en) * | 2020-04-29 | 2022-08-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and method of manufacturing the same |
US11532712B2 (en) | 2020-04-29 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company Limited | Interconnect structures for semiconductor devices and methods of manufacturing the same |
US11532703B2 (en) | 2020-05-27 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US20220384250A1 (en) * | 2021-02-26 | 2022-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement material for backside gate cut feature |
US11894260B2 (en) * | 2021-02-26 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Replacement material for backside gate cut feature |
US20220336288A1 (en) * | 2021-04-16 | 2022-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US11728218B2 (en) * | 2021-04-16 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
EP4345878A1 (en) * | 2022-09-30 | 2024-04-03 | INTEL Corporation | Forming metal gate cuts using multiple passes for depth control |
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KR102647231B1 (en) | 2024-03-13 |
KR20200015112A (en) | 2020-02-12 |
US11600639B2 (en) | 2023-03-07 |
US20230215868A1 (en) | 2023-07-06 |
CN110797306A (en) | 2020-02-14 |
US20210074729A1 (en) | 2021-03-11 |
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