US20190074362A1 - Semiconductor devices including recessed source/drain silicides and methods of forming the same - Google Patents
Semiconductor devices including recessed source/drain silicides and methods of forming the same Download PDFInfo
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- US20190074362A1 US20190074362A1 US15/999,191 US201815999191A US2019074362A1 US 20190074362 A1 US20190074362 A1 US 20190074362A1 US 201815999191 A US201815999191 A US 201815999191A US 2019074362 A1 US2019074362 A1 US 2019074362A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 193
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 125000006850 spacer group Chemical group 0.000 claims description 55
- 230000004888 barrier function Effects 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 44
- 239000002086 nanomaterial Substances 0.000 abstract description 8
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 20
- 238000010586 diagram Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 150000001875 compounds Chemical class 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000010410 layer Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 239000002135 nanosheet Substances 0.000 description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- UNASZPQZIFZUSI-UHFFFAOYSA-N methylidyneniobium Chemical compound [Nb]#C UNASZPQZIFZUSI-UHFFFAOYSA-N 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000011038 discontinuous diafiltration by volume reduction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- CNEOGBIICRAWOH-UHFFFAOYSA-N methane;molybdenum Chemical compound C.[Mo] CNEOGBIICRAWOH-UHFFFAOYSA-N 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- VSSLEOGOUUKTNN-UHFFFAOYSA-N tantalum titanium Chemical compound [Ti].[Ta] VSSLEOGOUUKTNN-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 150000003498 tellurium compounds Chemical class 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
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Definitions
- the present inventive concept relates to a semiconductor device. More particularly, the present inventive concept relates to a semiconductor device having a gate all-around structure.
- a gate all-around structure can include a nanowire-shaped silicon on a substrate and a gate that is formed to wrap-around the silicon body.
- Embodiments according to the present inventive concept can provide a semiconductor device including recessed source/drain silicides which may enable a reduction in a contact resistance between the source/drain and a contact thereon.
- Embodiments according to the present inventive concept can provide methods of forming of forming recessed source/drain silicides which may enable a reduction in a contact resistance between the source/drain and a contact thereon.
- a gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate.
- a gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode.
- a contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.
- a semiconductor device can include first, second, and third wire patterns that are spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate.
- a gate electrode can be wrapped around the first, second, and third wire patterns.
- a semiconductor pattern can be disposed on one side of the gate electrode over the substrate and an interlayer insulating film can be on the semiconductor pattern.
- a contact can be in the interlayer insulating film and embedded in the semiconductor pattern.
- a silicide film can extend along a profile of the contact between the contact and the semiconductor pattern, where the first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film can be located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- a semiconductor device can include first, second, and third wire patterns spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate.
- a gate spacer can define a gate trench in the substrate and a gate electrode can wrap around the first, second, and third wire patterns in the gate trench.
- a semiconductor pattern can be on one side of the gate electrode on the substrate.
- An interlayer insulating film can wrap around a sidewall of the gate spacer on the semiconductor pattern.
- a contact can be in the semiconductor pattern and in the interlayer insulating film, where the contact can include a first portion and a second portion on the first portion.
- a silicide film can be between the contact and the semiconductor pattern, where a width of the first portion of the contact away from a boundary between the first portion of the contact and the second portion of the contact can be less than a width of the second portion of the contact, at the boundary.
- the first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film is located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- a semiconductor device can include first, second, and third wire patterns spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate.
- a gate spacer can define a gate trench in the substrate and a gate electrode can wrap around the first, second, and third wire patterns in the gate trench.
- a semiconductor pattern can be on one side of the gate electrode on the substrate and an interlayer insulating film can wrap around a sidewall of the gate spacer on the semiconductor pattern.
- a contact can include a barrier conductive film and a filling conductive film on the barrier conductive film, in the semiconductor pattern and in the interlayer insulating film, where the contact includes a first portion, and a second portion on the first portion.
- a width of the first portion of the contact away from a boundary between the first portion of the contact and the second portion of the contact may be less than a width of the second portion of the contact, at the boundary and the filling conductive film can be absent from the first portion of the contact.
- a method of forming a semiconductor device can be provided by forming a semiconductor pattern on a substrate and forming first, second, and third wire patterns connected to the semiconductor pattern in numerical order on the substrate in a channel region of the semiconductor device.
- a gate electrode can be formed to wrap the first to third wire patterns.
- An interlayer insulating film can be formed on the gate electrode and a contact trench can be formed in the interlayer insulating film and in the semiconductor pattern, the contact trench can include a first portion and a second portion on the first portion, where a width of the first portion of the contact trench away from a boundary between the first portion and the second portion of the contact trench can be less than a width of the second portion of the contact trench at the boundary.
- a silicide film can be formed along part of the contact trench.
- a contact can be formed on the silicide film, to fill the contact trench, where the first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film can be located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- FIG. 1 is a plan view for explaining a semiconductor device according to some embodiments of the present inventive concept
- FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 ;
- FIG. 3 is an enlarged view of a part P of FIG. 2 ;
- FIG. 4 is a cross-sectional view taken along line B-B′ of FIG. 1 ;
- FIGS. 5 a to 5 e are various cross-sectional views of a first wire pattern of FIG. 1 taken along line B-B′;
- FIGS. 6 a to 6 c and 7 are various cross-sectional views of the first wire pattern of FIG. 1 taken along line A-A′;
- FIG. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept.
- FIG. 9 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.
- FIG. 10 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.
- FIG. 1 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept
- FIG. 12 a is a diagram illustrating a barrier conductive film of FIG. 11 ;
- FIG. 12 b is a cross-sectional view taken along line C-C′ of FIG. 12 a;
- FIG. 13 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept.
- FIG. 14 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept.
- FIGS. 15 to 23 are intermediate step diagrams taken along cross-sectional line D-D′ of FIG. 15 for explaining a method for fabricating the semiconductor device according to some embodiments of the present inventive concept.
- FIGS. 24 and 25 are intermediate step diagrams taken along cross-sectional line D-D′ of FIG. 15 for explaining a method for fabricating the semiconductor device according to some embodiments of the present inventive concept.
- a gate all-around transistor including a nanowire-shaped or a nanosheet-shaped channel region is illustrated as an example, but the present disclosure is not limited thereto.
- the term “nanosheet,” “nanosheet-shaped” can include a two-dimensional nanostructure with thickness in a scale ranging from 1 to 100 nm. Nanosheets are also described in, for example, U.S. Pat. No. 9,490,323, entitled “Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width,” which is commonly assigned to the present assignee and the disclosure of which is incorporated herein by reference in its entirety.
- nanostructure can include a semiconductor pattern based nanosheet or nanowire included in a GAA FET device.
- first, second, third etc. indicate a numerical sequence wherein lesser numbers precede greater numbers in the sequence.
- other structures in a numerical sequence may be intervening in the sequence.
- other structures may be inserted in the sequence without changing the numerical relationship between the first to third structures.
- the semiconductor device may include a tunneling transistor (FET), a bipolar junction transistor, a lateral double diffused transistor (LDMOS) or the like.
- FET tunneling transistor
- LDMOS lateral double diffused transistor
- FIG. 1 is a plan view for explaining a semiconductor device according to some embodiments of the present inventive concept.
- FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 .
- FIG. 3 is an enlarged view of a part P of FIG. 2 .
- FIG. 4 is a cross-sectional view taken along line B-B′ of FIG. 1 .
- FIGS. 5 a to 5 e are various cross-sectional views of a first wire pattern of FIG. 1 taken along line B-B′.
- an interlayer insulating film 190 is not illustrated in FIG. 1 .
- a semiconductor device may include a substrate 100 , a plurality of wire patterns 110 , 210 , and 310 , a gate electrode 120 , a semiconductor pattern 150 , a silicide film 160 , and a contact 170 .
- the substrate 100 may be a bulk silicon or a silicon-on-insulator (SOI).
- the substrate 100 may be a silicon substrate or may include other materials, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but the present disclosure is not limited thereto.
- a fin-like protrusion 100 P may protrude from the substrate 100 .
- the fin-like protrusion 100 P may extend long in a first direction X 1 .
- the fin-like protrusion 100 P may be formed by etching a part of the substrate 100 , and may include an epitaxial layer that is grown from the substrate 100 .
- the fin-like protrusion 100 P may include silicon or germanium which is an elemental semiconductor material. Further, the fin-like protrusion 100 P may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.
- the group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with group IV elements.
- the group III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga) and indium (In) as a group III element and at least one of phosphorus (P), arsenic (As) and antimonium (Sb) as a group V element.
- the field insulating film 105 may be formed on the substrate 100 .
- the field insulating film 105 may wrap at least a part of the sidewall of the fin-like protrusion 100 P.
- the fin-like protrusion 100 P may be defined by the field insulating film 105 .
- the sidewalls of the fin-like protrusion 100 P are illustrated as being entirely wrapped by the field insulating film 105 , but this is for the sake of convenience of explanation, and the present disclosure is not limited thereto.
- the field insulating film 105 may include, for example, one of an oxide film, a nitride film, an oxynitride film, or a combination thereof. Further, the field insulating film 105 may further include at least one or more field liner films formed between the fin-like protrusion 100 P and the field insulating film 105 . When the field insulating film 105 further includes the field liner film, the field liner film may include at least one of polysilicon, amorphous silicon, silicon oxynitride, silicon nitride, and silicon oxide.
- Three or more wire patterns may be formed on the substrate 100 in numerical order starting from the surface of the substrate and progressing toward the gate electrode 120 .
- the first wire pattern 110 may be the lowermost wire pattern that is located closest to the surface of the substrate in the channel region of the semiconductor device.
- the number of wire patterns formed on the substrate 100 is illustrated as three, this is for the sake of convenience of explanation, and the present disclosure is not limited thereto.
- the first to third wire patterns 110 , 210 , and 310 may be sequentially formed on the substrate 100 .
- the first to third wire patterns 110 , 210 , and 310 may be sequentially disposed on the fin-like protrusion 100 P.
- the first to third wire patterns 110 , 210 , and 310 may be formed to extend in the first direction X 1 , as in the fin-like protrusion 100 P.
- the first to third wire patterns 110 , 210 , and 310 may be sequentially arranged in a third direction Z 1 .
- the first wire pattern 110 may be formed to be spaced apart from the substrate 100 .
- the first wire pattern 110 may be formed to be spaced apart from the fin-like protrusion 100 P.
- the first wire pattern 110 may vertically overlap the fin-like protrusion 100 P.
- the first wire pattern 110 may not be formed on the field insulating film 105 but may be formed on the fin-like protrusion 100 P.
- the second wire pattern 210 may be formed to be spaced apart from the first wire pattern 110 .
- the third wire pattern 310 may be formed to be spaced apart from the second wire pattern 210 . Since the first wire pattern 110 is formed to be spaced apart from the substrate 100 and the fin-like protrusion 100 P, the second wire pattern 210 and the third wire pattern 310 may also be formed to be spaced apart from the fin-like protrusion 100 P.
- a wire pattern extending in the first direction X 1 may not be further formed between the first wire pattern 110 and the fin-like protrusion 100 P. That is, the first wire pattern 110 may be a wire pattern closest to the substrate 100 among a plurality of wire patterns sequentially disposed on the substrate 100 .
- Each of the first to third wire patterns 110 , 210 , and 310 may include silicon or germanium which is an elemental semiconductor material.
- each of the first to third wire patterns 110 , 210 , and 310 may include compound semiconductors, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.
- Each of the first to third wire patterns 110 , 210 , and 310 may be used as a channel region of a transistor.
- Each of the first to third wire patterns 110 , 210 , and 310 may contain the same material or may contain other materials.
- Each of the first to third wire patterns 110 , 210 , and 310 may include the same material as the fin-like protrusion 100 P, and may include a material different from the fin-like protrusion 100 P.
- a gate spacer 140 may extend in a second direction Y 1 .
- the gate spacer 140 may intersect with the first to third wire patterns 110 , 210 , and 310 .
- the gate spacer 140 may be located at both terminal ends of each of the first to third wire patterns 110 , 210 , and 310 extending in the first direction X 1 .
- the gate spacer 140 may be formed to face each other on both sides of the first to third wire patterns 110 , 210 , and 310 .
- the gate spacer 140 may include a penetration portion through which each of the first to third wire patterns 110 , 210 , and 310 penetrates.
- Each of the first to third wire patterns 110 , 210 , and 310 may pass through the gate spacer 140 .
- the gate spacer 140 may make overall contact with the circumferences of the terminal ends of each of the first to third wire patterns 110 , 210 , and 310 .
- the gate spacer 140 may include an inner spacer 141 and an outer spacer 142 .
- the inner spacer 141 may be disposed between the fin-like protrusion 100 P and the first wire pattern 110 , between the first wire pattern 110 and the second wire pattern 210 , and between the second wire pattern 210 and the third wire pattern 310 .
- the inner spacer 141 may be formed at a position which vertically overlaps the first to third wire patterns 110 , 210 , and 310 .
- the inner spacer 141 may not be formed on the field insulation film 105 which does not overlap the first to third wire patterns 110 , 210 , and 310 . That is, the outer spacer 142 may be formed on the upper surface of the field insulating film 105 .
- the outer spacer 142 may be positioned on the third wire pattern 310 .
- the gate spacer 140 may define a gate trench 140 t that intersects with the first to third wire patterns 110 , 210 , and 310 .
- the inner spacer 141 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof.
- the outer spacer 142 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof.
- the inner spacer 141 and the outer spacer 142 may be the same material or different materials.
- the gate insulating film 130 may be formed along the circumferences of each of the first to third wire patterns 110 , 210 , and 310 .
- the gate insulating film 130 may wrap each of the first to third wire patterns 110 , 210 , and 310 .
- the gate insulating film 130 may also be formed on the upper surface of the field insulating film 105 and on the fin-like protrusion 100 P.
- the gate insulating film 130 may extend along the inner wall of the gate spacer 140 .
- the gate insulating film 130 may extend along the sidewalls and the bottom surface of the gate trench 140 t and the circumferences of the first to third wire patterns 110 , 210 , and 310 .
- An interfacial layer may be formed between the gate insulating film 130 and the first wire pattern 110 , between the gate insulating film 130 and the second wire pattern 210 , between the gate insulating film 130 and the third wire pattern 310 , and between the gate insulating film 130 and the fin-like protrusion 100 P.
- the interfacial layer may be formed to be the same as the profile of the gate insulating film 130 .
- the gate insulating film 130 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.
- the high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.
- the gate electrode 120 may intersect with the first to third wire patterns 110 , 210 , and 310 formed to be spaced apart from the substrate 100 and the fin-like protrusion 100 P.
- the gate electrode 120 may wrap around (i.e., all-around) the first to third wire patterns 110 , 210 , and 310 .
- the gate electrode 120 may also be formed in a spaced space between the first wire pattern 110 and the fin-like protrusion 100 P.
- a wire pattern wrapping around the gate electrode 120 may not be disposed between the substrate 100 and the first wire pattern 110 .
- the gate electrode 120 may be disposed between the gate spacers 140 .
- the gate electrode 120 may be formed on the gate insulating film 130 .
- the gate electrode 120 may fill the gate trench 140 t and extend in the second direction Y 1 .
- the gate electrode 120 may include at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAIN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), ni
- the semiconductor pattern 150 may be disposed on at least one side of the gate electrode 120 .
- the semiconductor pattern 150 may be disposed on both sides of the gate electrode 120 .
- the semiconductor pattern 150 may be an epitaxial pattern formed through an epitaxial growth process.
- the semiconductor pattern 150 may be connected to each of the first to third wire patterns 110 , 210 , and 310 .
- the semiconductor pattern 150 may be formed on, for example, the fin-like protrusion 100 P.
- the semiconductor pattern 150 may be included in a source/drain of the transistor which uses the first to third wire patterns 110 , 210 , and 310 as a channel region.
- the interlayer insulating film 190 may be formed on the semiconductor pattern 150 .
- the interlayer insulating film 190 may wrap the sidewalls of the gate spacer 140 .
- the interlayer insulating film 190 may include a lower interlayer insulating film 191 and an upper interlayer insulating film 192 .
- the upper interlayer insulating film 192 may be formed on the upper surface of the gate spacer 140 and the upper surface of the gate electrode 120 .
- the lower interlayer insulating film 191 and the upper interlayer insulating film 192 may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride.
- An etching stop film 195 may be formed, for example, between the semiconductor pattern 150 and the interlayer insulating film 190 , and between the gate spacer 140 and the interlayer insulating film 190 .
- the etching stop film 195 may include a material having an etching selectivity to the lower interlayer insulating film 191 . In some embodiments, the etching stop film 195 may be omitted.
- the contact 170 may be formed in the interlayer insulating film 190 and the semiconductor pattern 150 .
- the contact 170 passes through the interlayer insulating film 190 , but does not pass entirely through the semiconductor pattern 150 .
- the contact 170 may extend in the third direction Z 1 . A part of the contact 170 is formed in the semiconductor pattern 150 .
- the contact 170 may include a barrier conductive film 171 and a filling conductive film 172 .
- the filling conductive film 172 may be formed on the barrier conductive film 171 .
- the filling conductive film 172 may fill a recessed space defined by the barrier conductive film 171 .
- the cross-section of the contact 170 intersecting with the X 1 -Y 1 plane is illustrated as a circular shape in FIG. 1 , this is for the sake of convenience of description, and the present disclosure is not limited thereto.
- the barrier conductive film 171 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), and tungsten carbonitride (WCN).
- the filling conductive film 172 may include, for example, at least one of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and doped polysilicon.
- the contact 170 may include a first portion 170 a and a second portion 170 b .
- the second portion 170 b of the contact may be disposed on the first portion 170 a of the contact.
- the barrier conductive film 171 may include a first sidewall portion 171 a extending in a direction away from the substrate 100 , a connecting portion 171 bb extending in a direction aligned with the upper surface of the substrate 100 , and a second sidewall portion 171 bs extending in a direction away from the substrate 100 .
- the upper portion 171 b of the barrier conductive film may include the connecting portion 171 bb of the barrier conductive film, and the second sidewall portion 171 bs of the barrier conductive film.
- a lower portion of the barrier conductive film 171 may include the first sidewall portion 171 a of the barrier conductive film.
- a boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be, for example, a boundary between the connecting portion 171 bb of the barrier conductive film and the first sidewall portion 171 a of the barrier conductive film.
- the first portion 170 a of the contact may include first sidewall portions 171 a of the barrier conductive film, and a filling conductive film 172 between the first sidewall portions 171 a of the barrier conductive film.
- the second portion 170 b of the contact may include the upper portion 171 b of the barrier conductive film, and a filling conductive film 172 between the second sidewall portions 171 bs of the barrier conductive film.
- boundary can refer to a line that demarks two different regions of one structure, material, or layer regardless of whether the boundary is created by a physical object (such as a layer, a change in material, or a change in material composition) or is a an virtual demarcation used to define at least two different regions within a unitary structure, material, or layer.
- a width W 11 of the first portion 170 a of the contact is less than a width W 12 of the second portion 170 b of the contact.
- the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be lower than the upper surface of the gate spacer 140 and the upper surface of the gate electrode 120 .
- the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be lower than the upper surface of the semiconductor pattern 150 .
- a height h 14 from the bottom surface of the semiconductor pattern 150 to the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact is less than a height h 15 from the bottom surface of the semiconductor pattern 150 to the upper surface of the semiconductor pattern 150 .
- At least a part of the first portion 170 a of the contact may be disposed in the semiconductor pattern 150 .
- the first portion 170 a of the contact may be disposed in the semiconductor pattern 150 .
- the sidewall of the first portion 170 a of the contact may be wrapped by the semiconductor pattern 150 .
- a part of the second portion 170 b of the contact may be disposed in the semiconductor pattern 150 .
- the second portion 170 b of the contact may be wrapped by the semiconductor pattern 150 and the interlayer insulating film 190 .
- a silicide film 160 may be formed between the semiconductor pattern 150 and the contact 170 .
- the silicide film 160 may be formed along the boundary between the semiconductor pattern 150 and the contact 170 .
- the silicide film 160 may be in contact with the semiconductor pattern 150 .
- the silicide film 160 may include, for example, at least one of titanium silicide (TiSi), tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), and tantalum silicide (TaSi).
- TiSi titanium silicide
- WSi tungsten silicide
- CoSi cobalt silicide
- NiSi nickel silicide
- MoSi molybdenum silicide
- TaSi tantalum silicide
- the silicide film 160 may extend along the profile of the contact 170 .
- the silicide film 160 may be formed along the profile of the contact 170 recessed into the semiconductor pattern 150 .
- the silicide film 160 may extend along at least a part of the profile of the first portion 170 a of the contact, between the first portion 170 a of the contact and the semiconductor pattern 150 .
- a part of the silicide film 160 may extend along the profile of the first portion 170 a of the contact.
- the remainder of the silicide film 160 may extend along the profile of the second portion 170 b of the contact.
- the silicide film 160 connects the first portion 161 and the second portion 162 extending in a direction away from the substrate 100 , and a third portion 163 which connects the first portion 161 and the second portion 162 and extends in a direction aligned with the upper surface of the substrate 100 .
- the width W 21 of the first portion 161 of the silicide film is greater than the width W 22 of the second portion 162 of the silicide film.
- the first portion 161 of the silicide film extends along the first sidewall portion 171 a of the barrier conductive film, and the second portion 162 of the silicide film extends along the second sidewall portion 171 bs of the barrier conductive film.
- the third portion 163 of the silicide film extends along the connecting portion 171 bb of the barrier conductive film.
- the height h 15 from the bottom surface of the semiconductor pattern 150 to the uppermost part of the silicide film 160 may be greater than the height h 14 from the bottom surface of the semiconductor pattern to the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact.
- the silicide film 160 may be spaced apart from the first to third wire patterns 110 , 210 , and 310 by the semiconductor pattern 150 .
- a part of the semiconductor pattern 150 may be interposed between the first wire pattern 110 and the silicide film 160 , between the second wire pattern 210 and the silicide film 160 , and between the third wire pattern 310 and the silicide film 160 . Since the semiconductor pattern 150 is interposed between each of the first to third wire patterns 110 , 210 , and 310 and the silicide film 160 , an effective contact area between the contact 170 and the first to third wire patterns 110 , 210 , and 310 may increase.
- the lowermost part of the silicide film 160 may be located between the uppermost part of the first wire pattern 110 and the lowermost part of the second wire pattern 210 .
- the height h 13 from the bottom surface of the semiconductor pattern 150 to the lowermost part of the silicide film 160 is greater than the height h 11 from the bottom surface of the semiconductor pattern 150 to the uppermost part of the first wire pattern 110 .
- the height h 13 from the bottom surface of the semiconductor pattern 150 to the lowermost part of the silicide film 160 is less than the height h 12 from the bottom surface of the semiconductor pattern 150 to the lowermost part of the second wire pattern 210 .
- the contact area increases, and the contact resistance may decrease.
- the volume of the semiconductor pattern 150 decreases. Since the volume of the semiconductor pattern 150 decreases, stress applied to the first to third wire patterns 110 , 210 , and 310 serving as the channel region may also decrease.
- the contact resistance between the contact 170 and the semiconductor pattern 150 may be reduced.
- stress relaxation due to volume reduction of the semiconductor pattern 150 may also be reduced.
- the outer wall of the second portion 170 b of the contact wrapped by the interlayer insulating film 190 and the etching stop film 195 is illustrated as not being aligned with one sidewall of the silicide film 160 facing the barrier conductive film 171 , but the present disclosure is not limited thereto.
- the transverse section of the first wire pattern 110 will be described with reference to FIGS. 5 a to 5 e .
- the description of the first wire pattern 110 may be applied to the second and third wire patterns 210 and 310 .
- a transverse section 110 S of the first wire pattern 110 may be a figure including a combination of straight lines 110 m .
- the transverse section 110 S of the first wire pattern 110 may be, for example, a rectangle.
- the width L 1 of the first wire pattern 110 and the height L 2 of the first wire pattern 110 may be different from each other in the transverse section 110 S of the first wire pattern 110 .
- the transverse section 110 S of the first wire pattern 110 may be a rectangle, but it is not limited thereto.
- the width L 1 of the first wire pattern 110 and the height L 2 of the first wire pattern 110 may be the same in the transverse section 110 S of the first wire pattern 110 .
- the transverse section 110 S of the first wire pattern 110 may be a square, but is not limited thereto.
- the width L 11 of one side of the first wire pattern 110 and the width L 12 of the other side of the first wire pattern 110 opposite to each other may be different from each other in the transverse section 110 S of the first wire pattern 110 .
- the transverse section 110 S of the first wire pattern 110 may be trapezoidal, but is not limited thereto.
- the transverse section 110 S of the first wire pattern 110 may be a figure including a combination of a straight line 110 m and a curve 110 n .
- the transverse section 110 S of the first wire pattern 110 may be, for example, a rectangle with rounded corners.
- the transverse section 110 S of the first wire pattern 110 may be a figure including a combination of curves 110 n to provide a generally circular shape.
- the transverse section 110 S of the first wire pattern 110 may be one of a figure including a combination of straight lines, a figure including a combination of a straight line and a curve, and a figure including a combination of curves.
- a longitudinal section of the first wire pattern 110 will be described with reference to FIGS. 6 a to 6 c .
- the description of the first wire pattern 110 may be applied to the second and third wire patterns 210 and 310 .
- the thickness of the first wire pattern 110 may be substantially the same as it is farther away from the semiconductor pattern 150 and the gate spacer 140 .
- a thickness t 1 _ a of the terminal end portion of the first wire pattern 110 adjacent to the semiconductor pattern 150 may be substantially the same as a thickness t 1 _ b of the central portion of the first wire pattern 110 .
- the thickness of the first wire pattern 110 may decrease as it is farther away from the semiconductor pattern 150 and the gate spacer 140 .
- the thickness t 1 _ a of the terminal end portion of the first wire pattern 110 adjacent to the semiconductor pattern 150 may be thicker than the thickness t 1 _ b of the central portion of the first wire pattern 110 .
- the thickness of the first wire pattern 110 may increase as it is farther away from the semiconductor pattern 150 and the gate spacer 140 .
- the thickness t 1 _ a of the terminal end portion of the first wire pattern 110 adjacent to the semiconductor pattern 150 may be less than the thickness t 1 _ b of the central portion of the first wire pattern 110 .
- the thickness of the first wire pattern 110 may be changed continuously as it is farther away from the semiconductor pattern 150 and the gate spacer 140 .
- a longitudinal section of the first wire pattern 110 will be described with reference to FIG. 7 .
- the description of the first wire pattern 110 may be applied to the second and third wire patterns 210 and 310 .
- the first wire pattern 110 may be a trimmed wire pattern.
- the first wire pattern 110 may include a first portion 110 a and a second portion 110 b .
- the second portion 110 b of the first wire pattern 110 may be disposed on both sides around the first portion 110 a of the first wire pattern 110 .
- the second portion 110 b of the first wire pattern 110 may be a portion overlapping the gate spacer 140
- the first portion 110 a of the first wire pattern 110 may be a portion overlapping the gate insulating film 130 and the gate electrode 120 .
- the thickness t 12 of the second portion 110 b of the first wire pattern 110 is greater than the thickness t 11 of the first portion 110 a of the first wire pattern 110 .
- a connecting portion between the second portion 110 b of the first wire pattern 110 and the first portion 110 a of the first wire pattern 110 may be rounded.
- the width of the first portion 110 a of the first wire pattern 110 is illustrated as being constant regardless of the location, this is for the sake of convenience of description, and the present disclosure is not limited thereto.
- the width of the first portion 110 a of the first wire pattern 110 may change as illustrated in FIG. 6 b or FIG. 6 c.
- FIG. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept.
- FIG. 9 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.
- FIG. 10 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference to FIGS. 1 to 4 will be mainly described.
- the second portion 170 b of the contact may not be disposed in the semiconductor pattern 150 .
- the first portion 170 a of the contact may not protrude upward from the upper surface of the semiconductor pattern 150 .
- the sidewalls of the second portion 170 b of the contact may be wrapped by the interlayer insulating film 190 .
- the sidewalls of the first portion 170 a of the contact may be wrapped by the semiconductor pattern 150 .
- the silicide film 160 may include a first portion 161 extending along the first sidewall portion 171 a of the barrier conductive film, and a third portion 163 extending along the connecting portion 171 bb of the barrier conductive film.
- the silicide film 160 may not include a portion extending along the second sidewall portion 171 bs of the barrier conductive film.
- the uppermost part of the silicide film 160 may not protrude upward from the upper surface of the semiconductor pattern 150 .
- a boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be the same as or higher than the upper surface of the semiconductor pattern 150 .
- a part of the first portion 170 a of the contact may protrude upward beyond the upper surface of the semiconductor pattern 150 .
- a part of the sidewall of the first portion 170 a of the contact may be wrapped by the interlayer insulating film 190 .
- the silicide film 160 may include only a portion extending along the first sidewall portion 171 a of the barrier conductive film.
- the silicide film 160 may extend along a part of the profile of the first portion 170 a of the contact.
- the silicide film 160 does not include a portion that extends along the profile of the upper portion 171 b of the barrier conductive film.
- a boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be higher than the upper surface of the semiconductor pattern 150 and may be lower than the upper surface of the gate spacer 140 .
- the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be higher than the uppermost part of the silicide film 160 .
- a part of the first portion 170 a of the contact may protrude upward from the upper surface of the gate spacer 140 .
- the silicide film 160 may include only a portion extending along the first sidewall portion 171 a of the barrier conductive film.
- the silicide film 160 does not include a portion extending along the profile of the upper portion 171 b of the barrier conductive film.
- the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be higher than the upper surface of the semiconductor pattern 150 , and may be higher than the upper surface of the gate spacer 140 and the upper surface of the gate electrode 120 .
- the boundary between the first portion 170 a of the contact and the second portion 170 b of the contact may be located at the same height as the upper surface of the gate spacer 140 and the upper surface of the gate electrode 120 .
- FIG. 1 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.
- FIG. 12 a is a diagram illustrating the barrier conductive film of FIG. 11 .
- FIG. 12 b is a cross-sectional view taken along line C-C of FIG. 12 b .
- FIGS. 1 to 4 differ from those described with reference to FIGS. 1 to 4 will be mainly described.
- the first portion 170 a of the contact may not include the filling conductive film 172 .
- the first portion 170 a of the contact may include only the first sidewall portion 171 a of the barrier conductive film, and may not include the filling conductive film 172 .
- the first sidewall portion 171 a of the barrier conductive film which is a lower portion of the barrier conductive film may be rod shaped and extend in a direction away from the substrate 100 . Therefore, the first sidewall portion 171 a of the barrier conductive film does not include a recessed space in which the filling conductive film 172 may be filled.
- the second portion 170 b of the contact may include an upper portion 171 b of the barrier conductive film, and a filling conductive film 172 on the upper portion 171 b of the barrier conductive film.
- the upper portion 171 b of the barrier conductive film may include a contact recess 171 r defined by the connecting portion 171 bb of the barrier conductive film and the second sidewall portion 171 bs of the barrier conductive film.
- the second portion 170 b of the contact may include a contact recess 171 r defined by the barrier conductive film 171 .
- the bottom surface of the contact recess 171 r is defined by the connecting portion 171 bb of the barrier conductive film, and the sidewall of the contact recess 171 r may be defined by the second sidewall portion 171 bs of the barrier conductive film.
- the filling conductive film 172 may fill the contact recess 171 r.
- FIG. 13 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference to FIGS. 11 to 12B will be mainly described.
- the contact 170 may include an air gap 170 g .
- air gap can include gaps that include other gases besides air or can be a void.
- the air gap 170 g may be included in the first portion 170 a of the contact.
- the air gap 170 g may be wrapped by, for example, the barrier conductive film 171 .
- FIG. 14 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference to FIGS. 1 to 4 will be mainly described.
- the semiconductor device may further include a capping pattern 145 .
- the gate electrode 120 may fill a part of the gate trench 140 t .
- the capping pattern 145 may be formed on the gate electrode 120 .
- the capping pattern 145 may fill the remainder of the gate trench 140 t which is left after the gate electrode 120 is formed.
- FIG. 14 illustrates the configuration in which the gate insulating film 130 is not formed between the gate spacer 140 and the capping pattern 145 , this is only for the sake of convenience of explanation, and the present disclosure is not limited thereto.
- the upper surface of the capping pattern 145 may be placed on the same plane as the upper surface of the lower interlayer insulating film 191 .
- the capping pattern 145 may include, for example, a material having an etching selectivity to the lower interlayer insulating film 191 .
- the capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.
- FIGS. 15 to 23 are intermediate step diagrams for explaining a method for fabricating a semiconductor device according to some embodiments of the present inventive concept.
- FIGS. 16 to 23 illustrate the fabricating method performed using the cross-sectional view taken along the line D-D of FIG. 15 , respectively.
- the semiconductor device fabricated using FIGS. 15 to 23 may be those described with reference to FIGS. 1 to 4 .
- a fin-like structure F may be formed on the substrate 100 .
- the fin-like structure F may extend long in the first direction X 1 .
- the fin-like structure F may include a fin-like protrusion 100 P, a sacrificial pattern 111 , an active pattern 112 , a sacrificial pattern 111 , an active pattern 112 , a sacrificial pattern 111 , and an active pattern 112 which are sequentially laminated on the substrate 100 . Since the fin structure F extends in the first direction X 1 , each of the sacrificial pattern 111 and the active pattern 112 may extend in the first direction X 1 .
- the active pattern 112 may include a material having an etching selectivity to the sacrificial pattern 111 .
- a field insulating film 105 which covers at least a part of the sidewalls of the fin-like structure F may be formed on the substrate 100 .
- the active pattern 112 is illustrated as being located on the uppermost part of the fin-like structure F, the present disclosure is not limited thereto.
- the fin-like structure F is illustrated to include three active patterns 112 formed on the substrate 100 , the present disclosure is not limited thereto.
- a dummy gate electrode 120 p intersecting with the fin-like structure F and extending in the second direction (Y 1 of FIG. 15 ) may be formed.
- a dummy gate insulating film 130 p may be formed between the dummy gate electrode 120 p and the fin-like structure F.
- a hard mask pattern 2101 may be located on the dummy gate electrode 120 p.
- An outer spacer 142 may be formed on the sidewall of the dummy gate electrode 120 p .
- a part of the fin-like structure F may be removed by utilizing the dummy gate electrode 120 p and the outer spacer 142 as a mask.
- an inner spacer 141 is formed between the active pattern 112 and the fin-like protrusion 100 P.
- An inner spacer 141 is also formed between the active patterns 112 on the fin-like protrusions 100 P. Therefore, the gate spacer 140 is formed.
- the inner spacer 141 may be formed on a portion from which a part of the sacrificial pattern 111 is removed.
- the semiconductor patterns 150 may be formed on the substrate 100 on both sides of the dummy gate electrode 120 p and the gate spacer 140 .
- the semiconductor pattern 150 may be formed on the fin-like protrusion 100 P.
- the semiconductor pattern 150 may be connected to the active pattern 112 .
- an etching stop film 195 may be formed on the sidewalls of the semiconductor pattern 150 and the outer spacer 142 .
- a lower interlayer insulating film 191 may be formed on the etching stop film 195 .
- the dummy gate electrode 120 p may be exposed by the lower interlayer insulating film 191 .
- the hard mask pattern 2101 may be removed.
- the first to third wire patterns 110 , 210 , and 310 sequentially disposed on the substrate 100 may be formed.
- the first wire pattern 110 may be formed to be spaced apart from the fin-like protrusion 100 P.
- the gate trench 140 t defined by the gate spacer 140 may be formed by removing the dummy gate electrode 120 p , the dummy gate insulating film 130 p , and the sacrificial pattern 111 .
- the gate insulating film 130 and the gate electrode 120 are formed on the substrate 100 .
- the gate insulating film 130 may be formed along the sidewalls and the bottom surface of the gate trench 140 t and the circumferences of the first to third wire patterns 110 , 210 and 310 .
- the gate electrode 120 is formed on the gate insulating film 130 and may fill the gate trench 140 t .
- the gate electrode 120 may wrap around the first to third wire patterns 110 , 210 , and 310 .
- a wire pattern in which the gate electrode 120 wraps around the circumference may not be disposed between the substrate 100 and the first wire pattern 110 .
- An upper interlayer insulating film 192 is formed on the gate electrode 120 and the lower interlayer insulating film 191 .
- a pre-contact trench 170 pt may be formed in the interlayer insulating film 190 .
- the pre-contact trench 170 pt may extend into the semiconductor pattern 150 to expose the semiconductor pattern 150 .
- trench liners 175 may be formed along the sidewalls of the pre-contact trench 170 pt.
- the area of the exposed semiconductor pattern 150 decreases.
- a part of the semiconductor pattern 150 may be removed, using the trench liner 175 . Since a part of the exposed semiconductor pattern 150 is removed by the trench liner 175 , a first portion 170 ta of the contact trench may be formed.
- a second portion 170 tb of the contact trench may be a pre-contact trench ( 170 pt of FIG. 20 ) in which the trench liner 175 is formed.
- the contact trench 170 t includes a first portion 170 ta of the contact trench, and a second portion 170 tb of the contact trench on the first portion 170 ta of the contact trench.
- the width W 31 of the first portion 170 ta of the contact trench is smaller than the width W 32 of the second portion 170 tb of the contact trench.
- the trench liner 175 disposed along the second portion 170 tb of the contact trench is removed.
- a silicide film 160 is formed along at least a part of the contact trench 170
- the contact boundary between the silicide film 160 and the semiconductor pattern 150 may be expanded further than the first portion 170 ta of the contact trench.
- the lowermost part of the silicide film 160 may be located between the uppermost part of the first wire pattern 110 and the lowermost part of the second wire pattern 210 .
- a contact 170 which fills the contact trench 170 t may be formed on the silicide film 160 .
- FIGS. 24 and 25 are intermediate step diagrams for explaining a method for fabricating a semiconductor device according to some embodiments of the present inventive concept.
- FIG. 24 may be a fabricating method performed after FIG. 18 .
- FIGS. 24 and 25 may be an example for fabricating the semiconductor device described with reference to FIG. 8 .
- a pre-contact trench 170 pt may be formed in the interlayer insulating film 190 and the semiconductor pattern 150 .
- the pre-contact trench 170 pt penetrates through the interlayer insulating film 190 and may extend into the semiconductor pattern 150 .
- the height h 16 from the bottom surface of the semiconductor pattern 150 to the bottom surface of the pre-contact trench 170 pt may be greater than the height h 11 from the bottom surface of the semiconductor pattern 150 to the uppermost part of the first wire pattern, and may be less than the height h 12 from the bottom surface of the semiconductor pattern 150 to the lowermost part of the second wire pattern 210 .
- the height h 16 from the bottom surface of the semiconductor pattern 150 to the bottom of the pre-contact trench 170 pt may be less than the height h 11 from the bottom surface of the semiconductor pattern 150 to the uppermost part of the first wire pattern 110 , depending on the thickness of the semiconductor liner ( 155 of FIG. 25 ).
- a semiconductor liner 155 may be formed along the pre-contact trench 170 pt defined by the semiconductor pattern 150 .
- a first portion 170 ta of the contact trench may be formed by the semiconductor liner 155 .
- the second portion 170 tb of the contact trench may be a portion of the pre-contact trench ( 170 pt of FIG. 24 ) defined by the interlayer insulating film 190 .
- the semiconductor liner 155 may include the same material as the semiconductor pattern 150 , or may include different materials.
- a silicide film 160 may be formed using the semiconductor liner 155 .
Abstract
Description
- This application claims priority from Korean Patent Application No. 10-2017-0111745 filed on Sep. 1, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
- The present inventive concept relates to a semiconductor device. More particularly, the present inventive concept relates to a semiconductor device having a gate all-around structure.
- A gate all-around structure can include a nanowire-shaped silicon on a substrate and a gate that is formed to wrap-around the silicon body.
- Since such a gate all-around structure uses three-dimensional channels, scaling may be less difficult. Further, the current control capability can be improved without increasing the length of the gate. Additionally, it is possible to effectively suppress a short channel effect (SCE) in which potential of a channel region is affected by drain voltage.
- Embodiments according to the present inventive concept can provide a semiconductor device including recessed source/drain silicides which may enable a reduction in a contact resistance between the source/drain and a contact thereon.
- Embodiments according to the present inventive concept can provide methods of forming of forming recessed source/drain silicides which may enable a reduction in a contact resistance between the source/drain and a contact thereon.
- Pursuant to these embodiments, a gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.
- In some embodiments, a semiconductor device can include first, second, and third wire patterns that are spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate. A gate electrode can be wrapped around the first, second, and third wire patterns. A semiconductor pattern can be disposed on one side of the gate electrode over the substrate and an interlayer insulating film can be on the semiconductor pattern. A contact can be in the interlayer insulating film and embedded in the semiconductor pattern. A silicide film can extend along a profile of the contact between the contact and the semiconductor pattern, where the first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film can be located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- In some embodiments, a semiconductor device can include first, second, and third wire patterns spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate. A gate spacer can define a gate trench in the substrate and a gate electrode can wrap around the first, second, and third wire patterns in the gate trench. A semiconductor pattern can be on one side of the gate electrode on the substrate. An interlayer insulating film can wrap around a sidewall of the gate spacer on the semiconductor pattern. A contact can be in the semiconductor pattern and in the interlayer insulating film, where the contact can include a first portion and a second portion on the first portion. A silicide film can be between the contact and the semiconductor pattern, where a width of the first portion of the contact away from a boundary between the first portion of the contact and the second portion of the contact can be less than a width of the second portion of the contact, at the boundary. The first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film is located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- In some embodiments, a semiconductor device can include first, second, and third wire patterns spaced apart from one another in numerical order in a channel region of the semiconductor device above a substrate. A gate spacer can define a gate trench in the substrate and a gate electrode can wrap around the first, second, and third wire patterns in the gate trench. A semiconductor pattern can be on one side of the gate electrode on the substrate and an interlayer insulating film can wrap around a sidewall of the gate spacer on the semiconductor pattern. A contact can include a barrier conductive film and a filling conductive film on the barrier conductive film, in the semiconductor pattern and in the interlayer insulating film, where the contact includes a first portion, and a second portion on the first portion. A width of the first portion of the contact away from a boundary between the first portion of the contact and the second portion of the contact may be less than a width of the second portion of the contact, at the boundary and the filling conductive film can be absent from the first portion of the contact.
- In some embodiments, a method of forming a semiconductor device can be provided by forming a semiconductor pattern on a substrate and forming first, second, and third wire patterns connected to the semiconductor pattern in numerical order on the substrate in a channel region of the semiconductor device. A gate electrode can be formed to wrap the first to third wire patterns. An interlayer insulating film can be formed on the gate electrode and a contact trench can be formed in the interlayer insulating film and in the semiconductor pattern, the contact trench can include a first portion and a second portion on the first portion, where a width of the first portion of the contact trench away from a boundary between the first portion and the second portion of the contact trench can be less than a width of the second portion of the contact trench at the boundary. A silicide film can be formed along part of the contact trench. A contact can be formed on the silicide film, to fill the contact trench, where the first wire pattern can include a lowermost wire pattern in the channel region and a lowermost part of the silicide film can be located between an uppermost part of the first wire pattern and a lowermost part of the second wire pattern.
- The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
-
FIG. 1 is a plan view for explaining a semiconductor device according to some embodiments of the present inventive concept; -
FIG. 2 is a cross-sectional view taken along line A-A′ ofFIG. 1 ; -
FIG. 3 is an enlarged view of a part P ofFIG. 2 ; -
FIG. 4 is a cross-sectional view taken along line B-B′ ofFIG. 1 ; -
FIGS. 5a to 5e are various cross-sectional views of a first wire pattern ofFIG. 1 taken along line B-B′; -
FIGS. 6a to 6c and 7 are various cross-sectional views of the first wire pattern ofFIG. 1 taken along line A-A′; -
FIG. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept; -
FIG. 9 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept; -
FIG. 10 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept; -
FIG. 1 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept; -
FIG. 12a is a diagram illustrating a barrier conductive film ofFIG. 11 ; -
FIG. 12b is a cross-sectional view taken along line C-C′ ofFIG. 12 a; -
FIG. 13 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept; -
FIG. 14 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept; -
FIGS. 15 to 23 are intermediate step diagrams taken along cross-sectional line D-D′ ofFIG. 15 for explaining a method for fabricating the semiconductor device according to some embodiments of the present inventive concept; and -
FIGS. 24 and 25 are intermediate step diagrams taken along cross-sectional line D-D′ ofFIG. 15 for explaining a method for fabricating the semiconductor device according to some embodiments of the present inventive concept. - In the drawings of the semiconductor device according to some embodiments of the present inventive concept, a gate all-around transistor (GAA FET) including a nanowire-shaped or a nanosheet-shaped channel region is illustrated as an example, but the present disclosure is not limited thereto. It will be understood that the term “nanosheet,” “nanosheet-shaped” can include a two-dimensional nanostructure with thickness in a scale ranging from 1 to 100 nm. Nanosheets are also described in, for example, U.S. Pat. No. 9,490,323, entitled “Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width,” which is commonly assigned to the present assignee and the disclosure of which is incorporated herein by reference in its entirety. It will be further understood that the term “nanostructure” can include a semiconductor pattern based nanosheet or nanowire included in a GAA FET device. It will be further understood that the terms first, second, third etc. indicate a numerical sequence wherein lesser numbers precede greater numbers in the sequence. However, in some embodiments, other structures in a numerical sequence may be intervening in the sequence. For example, in a sequence of first to third structures, other structures may be inserted in the sequence without changing the numerical relationship between the first to third structures.
- The semiconductor device according to some embodiments of the present inventive concept may include a tunneling transistor (FET), a bipolar junction transistor, a lateral double diffused transistor (LDMOS) or the like.
-
FIG. 1 is a plan view for explaining a semiconductor device according to some embodiments of the present inventive concept.FIG. 2 is a cross-sectional view taken along line A-A′ ofFIG. 1 .FIG. 3 is an enlarged view of a part P ofFIG. 2 .FIG. 4 is a cross-sectional view taken along line B-B′ ofFIG. 1 .FIGS. 5a to 5e are various cross-sectional views of a first wire pattern ofFIG. 1 taken along line B-B′. For the sake of convenience of explanation, aninterlayer insulating film 190 is not illustrated inFIG. 1 . - Referring to
FIGS. 1 to 4 , a semiconductor device according to some embodiments of the present inventive concept may include asubstrate 100, a plurality ofwire patterns gate electrode 120, asemiconductor pattern 150, asilicide film 160, and acontact 170. - The
substrate 100 may be a bulk silicon or a silicon-on-insulator (SOI). Alternatively, thesubstrate 100 may be a silicon substrate or may include other materials, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but the present disclosure is not limited thereto. - A fin-
like protrusion 100P (sometimes referred to herein as a fin-shaped protrusion) may protrude from thesubstrate 100. The fin-like protrusion 100P may extend long in a first direction X1. The fin-like protrusion 100P may be formed by etching a part of thesubstrate 100, and may include an epitaxial layer that is grown from thesubstrate 100. - The fin-
like protrusion 100P may include silicon or germanium which is an elemental semiconductor material. Further, the fin-like protrusion 100P may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. - The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with group IV elements. For example, the group III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga) and indium (In) as a group III element and at least one of phosphorus (P), arsenic (As) and antimonium (Sb) as a group V element.
- The
field insulating film 105 may be formed on thesubstrate 100. Thefield insulating film 105 may wrap at least a part of the sidewall of the fin-like protrusion 100P. The fin-like protrusion 100P may be defined by thefield insulating film 105. InFIG. 4 , the sidewalls of the fin-like protrusion 100P are illustrated as being entirely wrapped by thefield insulating film 105, but this is for the sake of convenience of explanation, and the present disclosure is not limited thereto. - The
field insulating film 105 may include, for example, one of an oxide film, a nitride film, an oxynitride film, or a combination thereof. Further, thefield insulating film 105 may further include at least one or more field liner films formed between the fin-like protrusion 100P and thefield insulating film 105. When thefield insulating film 105 further includes the field liner film, the field liner film may include at least one of polysilicon, amorphous silicon, silicon oxynitride, silicon nitride, and silicon oxide. - Three or more wire patterns may be formed on the
substrate 100 in numerical order starting from the surface of the substrate and progressing toward thegate electrode 120. For example, thefirst wire pattern 110 may be the lowermost wire pattern that is located closest to the surface of the substrate in the channel region of the semiconductor device. In the following description, although the number of wire patterns formed on thesubstrate 100 is illustrated as three, this is for the sake of convenience of explanation, and the present disclosure is not limited thereto. - The first to
third wire patterns substrate 100. For example, the first tothird wire patterns like protrusion 100 P. - The first to
third wire patterns like protrusion 100P. The first tothird wire patterns - The
first wire pattern 110 may be formed to be spaced apart from thesubstrate 100. For example, thefirst wire pattern 110 may be formed to be spaced apart from the fin-like protrusion 100P. Thefirst wire pattern 110 may vertically overlap the fin-like protrusion 100P. Thefirst wire pattern 110 may not be formed on thefield insulating film 105 but may be formed on the fin-like protrusion 100P. - The
second wire pattern 210 may be formed to be spaced apart from thefirst wire pattern 110. Thethird wire pattern 310 may be formed to be spaced apart from thesecond wire pattern 210. Since thefirst wire pattern 110 is formed to be spaced apart from thesubstrate 100 and the fin-like protrusion 100P, thesecond wire pattern 210 and thethird wire pattern 310 may also be formed to be spaced apart from the fin-like protrusion 100P. - A wire pattern extending in the first direction X1 may not be further formed between the
first wire pattern 110 and the fin-like protrusion 100P. That is, thefirst wire pattern 110 may be a wire pattern closest to thesubstrate 100 among a plurality of wire patterns sequentially disposed on thesubstrate 100. - Each of the first to
third wire patterns third wire patterns - Each of the first to
third wire patterns third wire patterns third wire patterns like protrusion 100P, and may include a material different from the fin-like protrusion 100P. - A
gate spacer 140 may extend in a second direction Y1. Thegate spacer 140 may intersect with the first tothird wire patterns - The
gate spacer 140 may be located at both terminal ends of each of the first tothird wire patterns gate spacer 140 may be formed to face each other on both sides of the first tothird wire patterns gate spacer 140 may include a penetration portion through which each of the first tothird wire patterns - Each of the first to
third wire patterns gate spacer 140. Thegate spacer 140 may make overall contact with the circumferences of the terminal ends of each of the first tothird wire patterns - The
gate spacer 140 may include aninner spacer 141 and anouter spacer 142. Theinner spacer 141 may be disposed between the fin-like protrusion 100P and thefirst wire pattern 110, between thefirst wire pattern 110 and thesecond wire pattern 210, and between thesecond wire pattern 210 and thethird wire pattern 310. - The
inner spacer 141 may be formed at a position which vertically overlaps the first tothird wire patterns inner spacer 141 may not be formed on thefield insulation film 105 which does not overlap the first tothird wire patterns outer spacer 142 may be formed on the upper surface of thefield insulating film 105. Theouter spacer 142 may be positioned on thethird wire pattern 310. - The
gate spacer 140 may define agate trench 140 t that intersects with the first tothird wire patterns - The
inner spacer 141 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof. Theouter spacer 142 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof. InFIG. 2 , theinner spacer 141 and theouter spacer 142 may be the same material or different materials. - The
gate insulating film 130 may be formed along the circumferences of each of the first tothird wire patterns gate insulating film 130 may wrap each of the first tothird wire patterns - The
gate insulating film 130 may also be formed on the upper surface of thefield insulating film 105 and on the fin-like protrusion 100P. Thegate insulating film 130 may extend along the inner wall of thegate spacer 140. - The
gate insulating film 130 may extend along the sidewalls and the bottom surface of thegate trench 140 t and the circumferences of the first tothird wire patterns - An interfacial layer may be formed between the
gate insulating film 130 and thefirst wire pattern 110, between thegate insulating film 130 and thesecond wire pattern 210, between thegate insulating film 130 and thethird wire pattern 310, and between thegate insulating film 130 and the fin-like protrusion 100P. In addition, depending on the method for forming the interfacial layer, the interfacial layer may be formed to be the same as the profile of thegate insulating film 130. - The
gate insulating film 130 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. - The
gate electrode 120 may intersect with the first tothird wire patterns substrate 100 and the fin-like protrusion 100P. Thegate electrode 120 may wrap around (i.e., all-around) the first tothird wire patterns gate electrode 120 may also be formed in a spaced space between thefirst wire pattern 110 and the fin-like protrusion 100P. A wire pattern wrapping around thegate electrode 120 may not be disposed between thesubstrate 100 and thefirst wire pattern 110. - The
gate electrode 120 may be disposed between thegate spacers 140. Thegate electrode 120 may be formed on thegate insulating film 130. Thegate electrode 120 may fill thegate trench 140 t and extend in the second direction Y1. - The
gate electrode 120 may include at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAIN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Thegate electrode 120 may be formed through, but is not limited to, for example, a replacement process (or a gate last process). - The
semiconductor pattern 150 may be disposed on at least one side of thegate electrode 120. For example, thesemiconductor pattern 150 may be disposed on both sides of thegate electrode 120. Thesemiconductor pattern 150 may be an epitaxial pattern formed through an epitaxial growth process. Thesemiconductor pattern 150 may be connected to each of the first tothird wire patterns semiconductor pattern 150 may be formed on, for example, the fin-like protrusion 100P. Thesemiconductor pattern 150 may be included in a source/drain of the transistor which uses the first tothird wire patterns - The
interlayer insulating film 190 may be formed on thesemiconductor pattern 150. Theinterlayer insulating film 190 may wrap the sidewalls of thegate spacer 140. Theinterlayer insulating film 190 may include a lowerinterlayer insulating film 191 and an upperinterlayer insulating film 192. The upperinterlayer insulating film 192 may be formed on the upper surface of thegate spacer 140 and the upper surface of thegate electrode 120. The lowerinterlayer insulating film 191 and the upperinterlayer insulating film 192 may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride. - An
etching stop film 195 may be formed, for example, between thesemiconductor pattern 150 and theinterlayer insulating film 190, and between thegate spacer 140 and theinterlayer insulating film 190. Theetching stop film 195 may include a material having an etching selectivity to the lowerinterlayer insulating film 191. In some embodiments, theetching stop film 195 may be omitted. - The
contact 170 may be formed in theinterlayer insulating film 190 and thesemiconductor pattern 150. Thecontact 170 passes through theinterlayer insulating film 190, but does not pass entirely through thesemiconductor pattern 150. Thecontact 170 may extend in the third direction Z1. A part of thecontact 170 is formed in thesemiconductor pattern 150. - The
contact 170 may include a barrierconductive film 171 and a fillingconductive film 172. The fillingconductive film 172 may be formed on the barrierconductive film 171. - The filling
conductive film 172 may fill a recessed space defined by the barrierconductive film 171. Although the cross-section of thecontact 170 intersecting with the X1-Y1 plane is illustrated as a circular shape inFIG. 1 , this is for the sake of convenience of description, and the present disclosure is not limited thereto. - The barrier
conductive film 171 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), and tungsten carbonitride (WCN). The fillingconductive film 172 may include, for example, at least one of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and doped polysilicon. - The
contact 170 may include afirst portion 170 a and asecond portion 170 b. Thesecond portion 170 b of the contact may be disposed on thefirst portion 170 a of the contact. - The barrier
conductive film 171 may include afirst sidewall portion 171 a extending in a direction away from thesubstrate 100, a connectingportion 171 bb extending in a direction aligned with the upper surface of thesubstrate 100, and asecond sidewall portion 171 bs extending in a direction away from thesubstrate 100. Theupper portion 171 b of the barrier conductive film may include the connectingportion 171 bb of the barrier conductive film, and thesecond sidewall portion 171 bs of the barrier conductive film. A lower portion of the barrierconductive film 171 may include thefirst sidewall portion 171 a of the barrier conductive film. - A boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be, for example, a boundary between the connectingportion 171 bb of the barrier conductive film and thefirst sidewall portion 171 a of the barrier conductive film. Thefirst portion 170 a of the contact may includefirst sidewall portions 171 a of the barrier conductive film, and a fillingconductive film 172 between thefirst sidewall portions 171 a of the barrier conductive film. Thesecond portion 170 b of the contact may include theupper portion 171 b of the barrier conductive film, and a fillingconductive film 172 between thesecond sidewall portions 171 bs of the barrier conductive film. - As used herein, the term “boundary,” can refer to a line that demarks two different regions of one structure, material, or layer regardless of whether the boundary is created by a physical object (such as a layer, a change in material, or a change in material composition) or is a an virtual demarcation used to define at least two different regions within a unitary structure, material, or layer.
- In the semiconductor device according to some embodiments of the present inventive concept, at the boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact, a width W11 of thefirst portion 170 a of the contact is less than a width W12 of thesecond portion 170 b of the contact. - The boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be lower than the upper surface of thegate spacer 140 and the upper surface of thegate electrode 120. For example, the boundary between thefirst portion 170 a of the contact and thesecond portion 170 b of the contact may be lower than the upper surface of thesemiconductor pattern 150. A height h14 from the bottom surface of thesemiconductor pattern 150 to the boundary between thefirst portion 170 a of the contact and thesecond portion 170 b of the contact is less than a height h15 from the bottom surface of thesemiconductor pattern 150 to the upper surface of thesemiconductor pattern 150. - At least a part of the
first portion 170 a of the contact may be disposed in thesemiconductor pattern 150. For example, thefirst portion 170 a of the contact may be disposed in thesemiconductor pattern 150. The sidewall of thefirst portion 170 a of the contact may be wrapped by thesemiconductor pattern 150. A part of thesecond portion 170 b of the contact may be disposed in thesemiconductor pattern 150. Thesecond portion 170 b of the contact may be wrapped by thesemiconductor pattern 150 and theinterlayer insulating film 190. - A
silicide film 160 may be formed between thesemiconductor pattern 150 and thecontact 170. Thesilicide film 160 may be formed along the boundary between thesemiconductor pattern 150 and thecontact 170. Thesilicide film 160 may be in contact with thesemiconductor pattern 150. - The
silicide film 160 may include, for example, at least one of titanium silicide (TiSi), tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), and tantalum silicide (TaSi). - The
silicide film 160 may extend along the profile of thecontact 170. For example, thesilicide film 160 may be formed along the profile of thecontact 170 recessed into thesemiconductor pattern 150. - The
silicide film 160 may extend along at least a part of the profile of thefirst portion 170 a of the contact, between thefirst portion 170 a of the contact and thesemiconductor pattern 150. For example, a part of thesilicide film 160 may extend along the profile of thefirst portion 170 a of the contact. The remainder of thesilicide film 160 may extend along the profile of thesecond portion 170 b of the contact. - The
silicide film 160 connects thefirst portion 161 and thesecond portion 162 extending in a direction away from thesubstrate 100, and a third portion 163 which connects thefirst portion 161 and thesecond portion 162 and extends in a direction aligned with the upper surface of thesubstrate 100. For example, the width W21 of thefirst portion 161 of the silicide film is greater than the width W22 of thesecond portion 162 of the silicide film. Thefirst portion 161 of the silicide film extends along thefirst sidewall portion 171 a of the barrier conductive film, and thesecond portion 162 of the silicide film extends along thesecond sidewall portion 171 bs of the barrier conductive film. The third portion 163 of the silicide film extends along the connectingportion 171 bb of the barrier conductive film. - For example, the height h15 from the bottom surface of the
semiconductor pattern 150 to the uppermost part of thesilicide film 160 may be greater than the height h14 from the bottom surface of the semiconductor pattern to the boundary between thefirst portion 170 a of the contact and thesecond portion 170 b of the contact. - The
silicide film 160 may be spaced apart from the first tothird wire patterns semiconductor pattern 150. A part of thesemiconductor pattern 150 may be interposed between thefirst wire pattern 110 and thesilicide film 160, between thesecond wire pattern 210 and thesilicide film 160, and between thethird wire pattern 310 and thesilicide film 160. Since thesemiconductor pattern 150 is interposed between each of the first tothird wire patterns silicide film 160, an effective contact area between thecontact 170 and the first tothird wire patterns - In the semiconductor device according to some embodiments of the present inventive concept, the lowermost part of the
silicide film 160 may be located between the uppermost part of thefirst wire pattern 110 and the lowermost part of thesecond wire pattern 210. For example, the height h13 from the bottom surface of thesemiconductor pattern 150 to the lowermost part of thesilicide film 160 is greater than the height h11 from the bottom surface of thesemiconductor pattern 150 to the uppermost part of thefirst wire pattern 110. Further, the height h13 from the bottom surface of thesemiconductor pattern 150 to the lowermost part of thesilicide film 160 is less than the height h12 from the bottom surface of thesemiconductor pattern 150 to the lowermost part of thesecond wire pattern 210. - As the depth at which the
silicide film 160 and thecontact 170 are formed becomes deeper, the contact area increases, and the contact resistance may decrease. On the other hand, as the depth at which thesilicide film 160 and thecontact 170 are formed becomes deeper, the volume of thesemiconductor pattern 150 decreases. Since the volume of thesemiconductor pattern 150 decreases, stress applied to the first tothird wire patterns - By locating the lowermost part of the
silicide film 160 between the uppermost part of thefirst wire pattern 110 and the lowermost part of thesecond wire pattern 210, the contact resistance between thecontact 170 and thesemiconductor pattern 150 may be reduced. At the same time, by locating the lowermost part of thesilicide film 160 between the uppermost part of thefirst wire pattern 110 and the lowermost part of thesecond wire pattern 210, stress relaxation due to volume reduction of thesemiconductor pattern 150 may also be reduced. - In
FIGS. 2 and 3 , the outer wall of thesecond portion 170 b of the contact wrapped by theinterlayer insulating film 190 and theetching stop film 195 is illustrated as not being aligned with one sidewall of thesilicide film 160 facing the barrierconductive film 171, but the present disclosure is not limited thereto. - The transverse section of the
first wire pattern 110 will be described with reference toFIGS. 5a to 5e . The description of thefirst wire pattern 110 may be applied to the second andthird wire patterns - In
FIG. 5a , atransverse section 110S of thefirst wire pattern 110 may be a figure including a combination ofstraight lines 110 m. Thetransverse section 110S of thefirst wire pattern 110 may be, for example, a rectangle. The width L1 of thefirst wire pattern 110 and the height L2 of thefirst wire pattern 110 may be different from each other in thetransverse section 110S of thefirst wire pattern 110. For example, thetransverse section 110S of thefirst wire pattern 110 may be a rectangle, but it is not limited thereto. - Unlike
FIG. 5a , inFIG. 5b , the width L1 of thefirst wire pattern 110 and the height L2 of thefirst wire pattern 110 may be the same in thetransverse section 110S of thefirst wire pattern 110. For example, thetransverse section 110S of thefirst wire pattern 110 may be a square, but is not limited thereto. - Unlike
FIG. 5a , inFIG. 5c , the width L11 of one side of thefirst wire pattern 110 and the width L12 of the other side of thefirst wire pattern 110 opposite to each other may be different from each other in thetransverse section 110S of thefirst wire pattern 110. For example, thetransverse section 110S of thefirst wire pattern 110 may be trapezoidal, but is not limited thereto. - Unlike
FIG. 5a , inFIG. 5d , thetransverse section 110S of thefirst wire pattern 110 may be a figure including a combination of astraight line 110 m and acurve 110 n. Thetransverse section 110S of thefirst wire pattern 110 may be, for example, a rectangle with rounded corners. - Unlike
FIG. 5a , inFIG. 5e , thetransverse section 110S of thefirst wire pattern 110 may be a figure including a combination ofcurves 110 n to provide a generally circular shape. - In
FIGS. 5a to 5e , thetransverse section 110S of thefirst wire pattern 110 may be one of a figure including a combination of straight lines, a figure including a combination of a straight line and a curve, and a figure including a combination of curves. - A longitudinal section of the
first wire pattern 110 will be described with reference toFIGS. 6a to 6c . The description of thefirst wire pattern 110 may be applied to the second andthird wire patterns - In
FIG. 6a , the thickness of thefirst wire pattern 110 may be substantially the same as it is farther away from thesemiconductor pattern 150 and thegate spacer 140. For example, a thickness t1_a of the terminal end portion of thefirst wire pattern 110 adjacent to thesemiconductor pattern 150 may be substantially the same as a thickness t1_b of the central portion of thefirst wire pattern 110. - In
FIG. 6b , the thickness of thefirst wire pattern 110 may decrease as it is farther away from thesemiconductor pattern 150 and thegate spacer 140. For example, the thickness t1_a of the terminal end portion of thefirst wire pattern 110 adjacent to thesemiconductor pattern 150 may be thicker than the thickness t1_b of the central portion of thefirst wire pattern 110. - In
FIG. 6c , the thickness of thefirst wire pattern 110 may increase as it is farther away from thesemiconductor pattern 150 and thegate spacer 140. For example, the thickness t1_a of the terminal end portion of thefirst wire pattern 110 adjacent to thesemiconductor pattern 150 may be less than the thickness t1_b of the central portion of thefirst wire pattern 110. - In
FIGS. 6b and 6c , the thickness of thefirst wire pattern 110 may be changed continuously as it is farther away from thesemiconductor pattern 150 and thegate spacer 140. - A longitudinal section of the
first wire pattern 110 will be described with reference toFIG. 7 . The description of thefirst wire pattern 110 may be applied to the second andthird wire patterns - The
first wire pattern 110 may be a trimmed wire pattern. Thefirst wire pattern 110 may include afirst portion 110 a and asecond portion 110 b. Thesecond portion 110 b of thefirst wire pattern 110 may be disposed on both sides around thefirst portion 110 a of thefirst wire pattern 110. Thesecond portion 110 b of thefirst wire pattern 110 may be a portion overlapping thegate spacer 140, and thefirst portion 110 a of thefirst wire pattern 110 may be a portion overlapping thegate insulating film 130 and thegate electrode 120. - The thickness t12 of the
second portion 110 b of thefirst wire pattern 110 is greater than the thickness t11 of thefirst portion 110 a of thefirst wire pattern 110. - Unlike the configuration illustrated in
FIG. 7 , it is a matter of course that a connecting portion between thesecond portion 110 b of thefirst wire pattern 110 and thefirst portion 110 a of thefirst wire pattern 110 may be rounded. InFIG. 7 , although the width of thefirst portion 110 a of thefirst wire pattern 110 is illustrated as being constant regardless of the location, this is for the sake of convenience of description, and the present disclosure is not limited thereto. The width of thefirst portion 110 a of thefirst wire pattern 110 may change as illustrated inFIG. 6b orFIG. 6 c. -
FIG. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present inventive concept.FIG. 9 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.FIG. 10 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference toFIGS. 1 to 4 will be mainly described. - Referring to
FIGS. 3 and 8 , in the semiconductor device according to some embodiments of the present inventive concept, thesecond portion 170 b of the contact may not be disposed in thesemiconductor pattern 150. Thefirst portion 170 a of the contact may not protrude upward from the upper surface of thesemiconductor pattern 150. - The sidewalls of the
second portion 170 b of the contact may be wrapped by theinterlayer insulating film 190. The sidewalls of thefirst portion 170 a of the contact may be wrapped by thesemiconductor pattern 150. - The
silicide film 160 may include afirst portion 161 extending along thefirst sidewall portion 171 a of the barrier conductive film, and a third portion 163 extending along the connectingportion 171 bb of the barrier conductive film. Thesilicide film 160 may not include a portion extending along thesecond sidewall portion 171 bs of the barrier conductive film. - Unlike the illustrated configuration, the uppermost part of the
silicide film 160 may not protrude upward from the upper surface of thesemiconductor pattern 150. - A boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be the same as or higher than the upper surface of thesemiconductor pattern 150. - Referring to
FIGS. 3 and 9 , in the semiconductor device according to some embodiments of the present inventive concept, a part of thefirst portion 170 a of the contact may protrude upward beyond the upper surface of thesemiconductor pattern 150. - For example, a part of the sidewall of the
first portion 170 a of the contact may be wrapped by theinterlayer insulating film 190. - The
silicide film 160 may include only a portion extending along thefirst sidewall portion 171 a of the barrier conductive film. Thesilicide film 160 may extend along a part of the profile of thefirst portion 170 a of the contact. Thesilicide film 160 does not include a portion that extends along the profile of theupper portion 171 b of the barrier conductive film. - A boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be higher than the upper surface of thesemiconductor pattern 150 and may be lower than the upper surface of thegate spacer 140. The boundary between thefirst portion 170 a of the contact and thesecond portion 170 b of the contact may be higher than the uppermost part of thesilicide film 160. - Referring to
FIGS. 3 and 10 , in the semiconductor device according to some embodiments of the present inventive concept, a part of thefirst portion 170 a of the contact may protrude upward from the upper surface of thegate spacer 140. - The
silicide film 160 may include only a portion extending along thefirst sidewall portion 171 a of the barrier conductive film. Thesilicide film 160 does not include a portion extending along the profile of theupper portion 171 b of the barrier conductive film. - The boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be higher than the upper surface of thesemiconductor pattern 150, and may be higher than the upper surface of thegate spacer 140 and the upper surface of thegate electrode 120. - Unlike the illustrated configuration, the boundary between the
first portion 170 a of the contact and thesecond portion 170 b of the contact may be located at the same height as the upper surface of thegate spacer 140 and the upper surface of thegate electrode 120. -
FIG. 1 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept.FIG. 12a is a diagram illustrating the barrier conductive film ofFIG. 11 .FIG. 12b is a cross-sectional view taken along line C-C ofFIG. 12b . For the sake of convenience of explanation, differences from those described with reference toFIGS. 1 to 4 will be mainly described. - Referring to
FIGS. 3 and 11 to 12 b, in the semiconductor device according to some embodiments of the present inventive concept, thefirst portion 170 a of the contact may not include the fillingconductive film 172. Thefirst portion 170 a of the contact may include only thefirst sidewall portion 171 a of the barrier conductive film, and may not include the fillingconductive film 172. - Unlike the configuration illustrated in
FIG. 3 , thefirst sidewall portion 171 a of the barrier conductive film which is a lower portion of the barrier conductive film may be rod shaped and extend in a direction away from thesubstrate 100. Therefore, thefirst sidewall portion 171 a of the barrier conductive film does not include a recessed space in which the fillingconductive film 172 may be filled. - The
second portion 170 b of the contact may include anupper portion 171 b of the barrier conductive film, and a fillingconductive film 172 on theupper portion 171 b of the barrier conductive film. - The
upper portion 171 b of the barrier conductive film may include acontact recess 171 r defined by the connectingportion 171 bb of the barrier conductive film and thesecond sidewall portion 171 bs of the barrier conductive film. Thesecond portion 170 b of the contact may include acontact recess 171 r defined by the barrierconductive film 171. The bottom surface of thecontact recess 171 r is defined by the connectingportion 171 bb of the barrier conductive film, and the sidewall of thecontact recess 171 r may be defined by thesecond sidewall portion 171 bs of the barrier conductive film. The fillingconductive film 172 may fill thecontact recess 171 r. -
FIG. 13 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference toFIGS. 11 to 12B will be mainly described. - Referring to
FIG. 13 , in the semiconductor device according to some embodiments of the present inventive concept, thecontact 170 may include anair gap 170 g. It will be understood that the term “air gap” can include gaps that include other gases besides air or can be a void. - The
air gap 170 g may be included in thefirst portion 170 a of the contact. Theair gap 170 g may be wrapped by, for example, the barrierconductive film 171. -
FIG. 14 is a diagram for explaining the semiconductor device according to some embodiments of the present inventive concept. For the sake of convenience of explanation, differences from those described with reference toFIGS. 1 to 4 will be mainly described. - Referring to
FIG. 14 , the semiconductor device according to some embodiments of the present inventive concept may further include acapping pattern 145. - The
gate electrode 120 may fill a part of thegate trench 140 t. Thecapping pattern 145 may be formed on thegate electrode 120. Thecapping pattern 145 may fill the remainder of thegate trench 140 t which is left after thegate electrode 120 is formed. - Although
FIG. 14 illustrates the configuration in which thegate insulating film 130 is not formed between thegate spacer 140 and thecapping pattern 145, this is only for the sake of convenience of explanation, and the present disclosure is not limited thereto. - The upper surface of the
capping pattern 145 may be placed on the same plane as the upper surface of the lowerinterlayer insulating film 191. Thecapping pattern 145 may include, for example, a material having an etching selectivity to the lowerinterlayer insulating film 191. Thecapping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. -
FIGS. 15 to 23 are intermediate step diagrams for explaining a method for fabricating a semiconductor device according to some embodiments of the present inventive concept. For reference,FIGS. 16 to 23 illustrate the fabricating method performed using the cross-sectional view taken along the line D-D ofFIG. 15 , respectively. In addition, the semiconductor device fabricated usingFIGS. 15 to 23 may be those described with reference toFIGS. 1 to 4 . - Referring to
FIG. 15 , a fin-like structure F may be formed on thesubstrate 100. The fin-like structure F may extend long in the first direction X1. - The fin-like structure F may include a fin-
like protrusion 100P, asacrificial pattern 111, anactive pattern 112, asacrificial pattern 111, anactive pattern 112, asacrificial pattern 111, and anactive pattern 112 which are sequentially laminated on thesubstrate 100. Since the fin structure F extends in the first direction X1, each of thesacrificial pattern 111 and theactive pattern 112 may extend in the first direction X1. - The
active pattern 112 may include a material having an etching selectivity to thesacrificial pattern 111. - A
field insulating film 105 which covers at least a part of the sidewalls of the fin-like structure F may be formed on thesubstrate 100. - In
FIG. 15 , although theactive pattern 112 is illustrated as being located on the uppermost part of the fin-like structure F, the present disclosure is not limited thereto. In addition, although the fin-like structure F is illustrated to include threeactive patterns 112 formed on thesubstrate 100, the present disclosure is not limited thereto. - Referring to
FIG. 16 , adummy gate electrode 120 p intersecting with the fin-like structure F and extending in the second direction (Y1 ofFIG. 15 ) may be formed. - A dummy
gate insulating film 130 p may be formed between thedummy gate electrode 120 p and the fin-like structure F. Ahard mask pattern 2101 may be located on thedummy gate electrode 120 p. - An
outer spacer 142 may be formed on the sidewall of thedummy gate electrode 120 p. A part of the fin-like structure F may be removed by utilizing thedummy gate electrode 120 p and theouter spacer 142 as a mask. - After removing a part of the fin-like structure F, an
inner spacer 141 is formed between theactive pattern 112 and the fin-like protrusion 100P. Aninner spacer 141 is also formed between theactive patterns 112 on the fin-like protrusions 100P. Therefore, thegate spacer 140 is formed. - It is possible to remove at least a part of the
sacrificial pattern 111 overlapping theouter spacer 142, for example, using the etching selectivity between theactive pattern 112 and thesacrificial pattern 111. Theinner spacer 141 may be formed on a portion from which a part of thesacrificial pattern 111 is removed. - The
semiconductor patterns 150 may be formed on thesubstrate 100 on both sides of thedummy gate electrode 120 p and thegate spacer 140. Thesemiconductor pattern 150 may be formed on the fin-like protrusion 100P. Thesemiconductor pattern 150 may be connected to theactive pattern 112. - Referring to
FIGS. 16 and 17 , anetching stop film 195 may be formed on the sidewalls of thesemiconductor pattern 150 and theouter spacer 142. A lowerinterlayer insulating film 191 may be formed on theetching stop film 195. Thedummy gate electrode 120 p may be exposed by the lowerinterlayer insulating film 191. During the formation of the lowerinterlayer insulating film 191, thehard mask pattern 2101 may be removed. - By removing the
dummy gate electrode 120 p, the dummygate insulating film 130 p, and thesacrificial pattern 111, the first tothird wire patterns substrate 100 may be formed. Thefirst wire pattern 110 may be formed to be spaced apart from the fin-like protrusion 100P. - The
gate trench 140 t defined by thegate spacer 140 may be formed by removing thedummy gate electrode 120 p, the dummygate insulating film 130 p, and thesacrificial pattern 111. - Referring to
FIG. 18 , thegate insulating film 130 and thegate electrode 120 are formed on thesubstrate 100. Thegate insulating film 130 may be formed along the sidewalls and the bottom surface of thegate trench 140 t and the circumferences of the first tothird wire patterns - The
gate electrode 120 is formed on thegate insulating film 130 and may fill thegate trench 140 t. Thegate electrode 120 may wrap around the first tothird wire patterns gate electrode 120 wraps around the circumference may not be disposed between thesubstrate 100 and thefirst wire pattern 110. - An upper
interlayer insulating film 192 is formed on thegate electrode 120 and the lowerinterlayer insulating film 191. - Referring to
FIG. 19 , apre-contact trench 170 pt may be formed in theinterlayer insulating film 190. Thepre-contact trench 170 pt may extend into thesemiconductor pattern 150 to expose thesemiconductor pattern 150. - Referring to
FIG. 20 ,trench liners 175 may be formed along the sidewalls of thepre-contact trench 170 pt. - Since the
trench liner 175 is formed, the area of the exposedsemiconductor pattern 150 decreases. - Referring to
FIG. 21 , a part of thesemiconductor pattern 150 may be removed, using thetrench liner 175. Since a part of the exposedsemiconductor pattern 150 is removed by thetrench liner 175, afirst portion 170 ta of the contact trench may be formed. - A
second portion 170 tb of the contact trench may be a pre-contact trench (170 pt ofFIG. 20 ) in which thetrench liner 175 is formed. - The
contact trench 170 t includes afirst portion 170 ta of the contact trench, and asecond portion 170 tb of the contact trench on thefirst portion 170 ta of the contact trench. - For example, at the boundary between the
first portion 170 ta of the contact trench and thesecond portion 170 tb of the contact trench, the width W31 of thefirst portion 170 ta of the contact trench is smaller than the width W32 of thesecond portion 170 tb of the contact trench. - Referring to
FIG. 22 , thetrench liner 175 disposed along thesecond portion 170 tb of the contact trench is removed. - Referring to
FIG. 23 , asilicide film 160 is formed along at least a part of thecontact trench 170 - t. Since the
silicide film 160 uses a part of thesemiconductor pattern 150, the contact boundary between thesilicide film 160 and thesemiconductor pattern 150 may be expanded further than thefirst portion 170 ta of the contact trench. - At this time, the lowermost part of the
silicide film 160 may be located between the uppermost part of thefirst wire pattern 110 and the lowermost part of thesecond wire pattern 210. - Next, a
contact 170 which fills thecontact trench 170 t may be formed on thesilicide film 160. -
FIGS. 24 and 25 are intermediate step diagrams for explaining a method for fabricating a semiconductor device according to some embodiments of the present inventive concept. -
FIG. 24 may be a fabricating method performed afterFIG. 18 .FIGS. 24 and 25 may be an example for fabricating the semiconductor device described with reference toFIG. 8 . - Referring to
FIG. 24 , apre-contact trench 170 pt may be formed in theinterlayer insulating film 190 and thesemiconductor pattern 150. - The
pre-contact trench 170 pt penetrates through theinterlayer insulating film 190 and may extend into thesemiconductor pattern 150. - For example, the height h16 from the bottom surface of the
semiconductor pattern 150 to the bottom surface of thepre-contact trench 170 pt may be greater than the height h11 from the bottom surface of thesemiconductor pattern 150 to the uppermost part of the first wire pattern, and may be less than the height h12 from the bottom surface of thesemiconductor pattern 150 to the lowermost part of thesecond wire pattern 210. - However, the height h16 from the bottom surface of the
semiconductor pattern 150 to the bottom of thepre-contact trench 170 pt may be less than the height h11 from the bottom surface of thesemiconductor pattern 150 to the uppermost part of thefirst wire pattern 110, depending on the thickness of the semiconductor liner (155 ofFIG. 25 ). - Referring to
FIG. 25 , asemiconductor liner 155 may be formed along thepre-contact trench 170 pt defined by thesemiconductor pattern 150. - A
first portion 170 ta of the contact trench may be formed by thesemiconductor liner 155. Thesecond portion 170 tb of the contact trench may be a portion of the pre-contact trench (170 pt ofFIG. 24 ) defined by theinterlayer insulating film 190. - The
semiconductor liner 155 may include the same material as thesemiconductor pattern 150, or may include different materials. - Next, a
silicide film 160 may be formed using thesemiconductor liner 155. - While the present inventive concept has been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.
Claims (22)
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Also Published As
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KR102283024B1 (en) | 2021-07-27 |
US20200343350A1 (en) | 2020-10-29 |
KR20190025281A (en) | 2019-03-11 |
US10714579B2 (en) | 2020-07-14 |
CN109427875A (en) | 2019-03-05 |
CN109427875B (en) | 2023-12-26 |
US10998412B2 (en) | 2021-05-04 |
SG10201804486SA (en) | 2019-04-29 |
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