US20180316339A1 - High-resolution fet vds zero-volt-crossing timing detection scheme in a wireless power transfer system - Google Patents

High-resolution fet vds zero-volt-crossing timing detection scheme in a wireless power transfer system Download PDF

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US20180316339A1
US20180316339A1 US15/498,385 US201715498385A US2018316339A1 US 20180316339 A1 US20180316339 A1 US 20180316339A1 US 201715498385 A US201715498385 A US 201715498385A US 2018316339 A1 US2018316339 A1 US 2018316339A1
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Prior art keywords
comparator
signal
edge
output
transistor
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US15/498,385
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US10116294B1 (en
Inventor
Jingwei Xu
Vijayalakshmi Devarajan
Gangqiang Zhang
Angelo William Pereira
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Texas Instruments Inc
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Texas Instruments Inc
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Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PEREIRA, ANGELO WILLIAM, DEVARAJAN, VIJAYALAKSHMI, XU, JINGWEI, ZHANG, GANGQIANG
Priority to JP2019558720A priority patent/JP2020519092A/en
Priority to EP18792274.5A priority patent/EP3616321B1/en
Priority to PCT/US2018/029609 priority patent/WO2018200843A1/en
Priority to CN201880027648.4A priority patent/CN110574291B/en
Priority to US16/128,038 priority patent/US10382028B2/en
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1536Zero-crossing detectors
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J7/025
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/1508Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of delay lines
    • H02J2007/105
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007Regulation of charging or discharging current or voltage
    • H02J7/00711Regulation of charging or discharging current or voltage with introduction of pulses during the charging process
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0048Circuits or arrangements for reducing losses
    • H02M1/0054Transistor switching losses
    • H02M1/0058Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the V gs comparator has at least one output configured to provide a V gs edge transition signal indicative of V gs crossing the V gs threshold.
  • the at least one latching element has a data input, a clock input, and an output.
  • the data input is operably coupled to receive a V ds edge transition signal from the V ds comparator
  • the clock input is operably coupled to receive a V gs edge transition signal from the V gs comparator, such that the V gs edge transition signal serves to latch the V ds edge transition signal to the latch output.
  • FIG. 5 is a timing diagram timing showing timing relationships for various signals in a comparator system such as that shown in FIG. 4 in accordance with illustrative timing and control schemes of the present disclosure.
  • Illustrative aspects of the present disclosure are directed to techniques for achieving accurate and efficient zero-volt crossing detection in a high-frequency zero-volt-switching system.
  • the zero-volt-crossing detection methods of the present disclosure will be described with respect to an A4WP wireless power transfer and charging system.
  • aspects of the present disclosure are applicable to substantially any system that employs zero-volt switching.
  • transistor Q 1 To illustrate aspects of switching control in accordance with the present disclosure, the operation and control of transistor Q 1 will now be described. It is to be understood that this description regarding transistor Q 1 also pertains to the other primary-side transistors Q 2 -Q 4 , as well as, in many respects, the secondary-side transistors Q 5 -Q 8 .
  • the drain-to-source voltage signal V ds of transistor Q 1 is complex due to the ringing generated by the bond wires of the transistor.
  • the additional voltage resulting from L primary (dI P /dt) can be greater than I ds R ds .
  • a ZVS detection circuit in the primary-side control module 110 detects if the V ds of the corresponding transistor Q 1 is above or below a predetermined threshold V TH-ds .
  • both the ON_LATE and OFF_LATE signals are averaged over multiple (for example, eight) PWM cycles to obtain the average value over a longer time period and thereby reduce noise sensitivity. It is again noted that, while this switching control scheme is described with respect to transistor Q 1 , the same or similar principles apply to the other primary-side transistor Q 2 -Q 4 , as well as to the secondary-side transistors Q 5 -Q 8 .
  • the drain-to-source voltage V ds is still less than the threshold voltage V T M, and therefore the OFF_LATE flag goes low, indicating that the gate-driver signal turned the transistor off early, i.e., before the V ds signal has gone high.
  • a PWM state machine in the primary-side control module 110 uses the latched outputs from the V ds comparators corresponding to each of the primary-side transistors Q 1 -Q 4 to regulate control bits to the phase-locked loop.
  • a PWM state machine in the secondary-side control module 120 uses the latched outputs from the V ds comparators corresponding to each of the secondary-side transistors Q 5 -Q 8 to regulate control bits to the phase-locked loop.
  • the PWM state machines employ control algorithms that seek to obtain locking positions for the rising and falling edges of the gate-driver waveforms. These algorithms illustratively employ an initial pulse-width value for the gate-driver waveforms.
  • the output latches and averaging logic module 460 receives the delay-adjusted outputs of the V ds comparator 410 and V gs comparator 420 from the delay matching/trimming module 430 .
  • the output latches and averaging logic module 460 implements the latching of the outputs of the V ds comparator 410 at times dictated by the rising and falling edges of the V gs signal as represented by the outputs of the V gs comparator 420 .
  • the latching of the ON_LATE and ON_LATE flags is implemented using two D flip-flops 465 and 470 .
  • the PWM signal is illustratively generated by the pulse-width-modulation state machine and provided to the gate-driver circuit, which generates a gate-driver signal based on said PWM signal.
  • the gate-to-source voltage V gs is representative of the gate-driver signal provided to the gate of the transistor by the gate-driver circuit.
  • the PWM signal goes high.
  • the gate-to-source voltage V gs crosses the transistor turn on threshold V TH-gs , which in the illustrative embodiment of FIG. 5 , is 2.5V, at a time t 2 .
  • the ON_CLK output of the V gs comparator 420 goes high at a time t 4 in response to the V, signal crossing the V TH-gs threshold at time t 2 .
  • the drain-to-source voltage V ds of the transistor crosses the drain-to-source voltage threshold V TH-ds , which in the illustrative embodiment of FIG. 5 is set at 1 V.
  • the FALL_P output of the V ds comparator 410 goes high at a time t 5 in response to the V ds signal crossing the V TH-ds threshold at time t 3 .

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

Description

    BACKGROUND
  • Zero-volt switching (ZVS) is a switching scheme wherein a field-effect transistor (FET) delivering power to a load is switched on or off only when the drain-source voltage is at or near zero volts. Zero-volt switching uses pulse width modulation (PWM), but with an additional separate phase to the PWM timing to allow for ZVS operation. Zero-volt switching enables the voltage regulator to engage in “soft switching,” thus avoiding the switching losses that are typically incurred during conventional PWM operation and timing.
  • Zero-volt switching can be employed in a variety of power conversion systems that require high switching frequencies at higher input voltages and voltage drops. Wireless power transfer and charging systems are an example of a technology that can benefit greatly from zero-volt switching. The Alliance For Wireless Power (A4WP) is an industry standard group that uses the principles of magnetic resonance to develop a wireless energy transfer system over distance. A4WP wireless power transfer uses directed and controlled magnetic fields to replace traditional power cords. To do this, the transmitter utilizes one or more primary windings in order to induce an even magnetic field above its surface. A receiver in the magnetic field uses a secondary winding which captures the magnetic energy and converts it back to electrical energy. In A4WP wireless power transfer, the switching frequencies are multiples of 6.78 MHz. Accurate zero-voltage crossing (ZVC) detection is the starting point for high efficiency ZVS control. With such high-frequency switching, the timing accuracy of the zero-volt switching needs to be on the order of a nanosecond. Conventional zero-voltage crossing detection methods employ very fast comparators and gate drivers that have very little delay. However, typical comparator delay is already above the aforementioned nanosecond range.
  • SUMMARY
  • Illustrative aspects of the present disclosure are directed to a control module for controlling a field-effect transistor. The control module includes a comparator and control circuitry. The comparator receives the drain-to-source voltage of the transistor and compares it to a threshold voltage. The comparator has a clock input that receives a gate voltage of the transistor, such that the received gate voltage is used to latch a result of the comparison to an output of the comparator. The control circuitry receives the comparator output and performs a control function with respect to the transistor based on the value of the comparator output.
  • Other illustrative aspects of the present disclosure are directed to a control module for controlling a field-effect transistor. The control module includes a drain-to-source voltage comparator, a gate-to-source voltage comparator, and at least one latching element. The drain-to-source voltage comparator receives the drain-to-source voltage (Vds) of the transistor and compares it to a Vds threshold. The Vds comparator has at least one output configured to provide a Vds edge transition signal indicative of Vds crossing the Vds threshold. The gate-to-source voltage comparator receives the gate-to-source voltage (Vgs) of the transistor and compares it to a Vgs threshold. The Vgs comparator has at least one output configured to provide a Vgs edge transition signal indicative of Vgs crossing the Vgs threshold. The at least one latching element has a data input, a clock input, and an output. The data input is operably coupled to receive a Vds edge transition signal from the Vds comparator, and the clock input is operably coupled to receive a Vgs edge transition signal from the Vgs comparator, such that the Vgs edge transition signal serves to latch the Vds edge transition signal to the latch output.
  • Other illustrative aspects of the present disclosure are directed to a method of controlling a field-effect transistor. Pursuant to this illustrative method, a comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic block diagram of an illustrative wireless power transfer system.
  • FIG. 2 is a functional block diagram representing a comparator for use in a zero-volt switching detection circuit in accordance with illustrative embodiments of the present disclosure.
  • FIG. 3 is a timing diagram demonstrating timing relationships between the Vds signal, the Vgs signal, the ON_LATE flag, and the OFF_LATE flag in accordance with illustrative embodiments of the present disclosure.
  • FIG. 4 is a functional block diagram representing a comparator system capable of implementing a comparator such as the comparator described with respect FIG. 2 in accordance with illustrative embodiments of the present disclosure.
  • FIG. 5 is a timing diagram timing showing timing relationships for various signals in a comparator system such as that shown in FIG. 4 in accordance with illustrative timing and control schemes of the present disclosure.
  • FIG. 6 is a flowchart representing a method of controlling a field-effect transistor in accordance with illustrative embodiments of the present disclosure.
  • DETAILED DESCRIPTION
  • Illustrative aspects of the present disclosure are directed to techniques for achieving accurate and efficient zero-volt crossing detection in a high-frequency zero-volt-switching system. For purposes of illustration, the zero-volt-crossing detection methods of the present disclosure will be described with respect to an A4WP wireless power transfer and charging system. However, it will be appreciated by those of skill in the art that aspects of the present disclosure are applicable to substantially any system that employs zero-volt switching.
  • FIG. 1 is a schematic block diagram of an illustrative wireless power transfer system 100. The primary side 105 of the wireless power transfer system 100 includes a primary-side control module 110, which illustratively comprises an integrated circuit controller. The primary-side control module 110 generates control signals and provides them to external switches Q1, Q2, Q3 and Q4. In the illustrative embodiment shown in FIG. 1, the switches Q1, Q2, Q4 and Q4 are metal-oxide-semiconductor field-effect transistors (MOSFETs) and the control signals provided by the primary-side control module 110 are gate-driver signals. The junction of switches Q1 and Q3 define a tank node N1, and the junction of switches Q2 and Q4 define a tank node N2. Specifically, in the illustrative embodiment of FIG. 1, tank node N1 is defined by the junction of the source of transistor Q1 and the drain of transistor Q3. Tank node N2 is defined by the junction of the source of transistor Q2 and the drain of transistor Q4. The drains of transistors Q1 and Q2 are coupled to an input voltage Vin. The sources of transistors Q3 and 04 are coupled to ground. Tank nodes N1 and N2 are coupled to a primary-side LC tank circuit comprising primary-side capacitor Cprimary and primary-side inductor Lprimary. The tank node N1 is coupled to a first terminal of primary-side capacitor Cprimary. The primary-side inductor Lprimary is coupled between the second terminal of capacitor Cprimary and tank node N2.
  • Primary-side inductor Lprimary inductively coupled across air gap M to secondary-side inductor Lsecondary. On the secondary side 115 of the wireless power transfer system 100, an LC tank circuit comprising secondary-side inductor Lsecondary and secondary-side capacitor Csecondary is coupled to tank nodes N3 and N4. The tank node N3 is coupled to a first terminal of the secondary-side inductor Lsecondary. The secondary-side capacitor Csecondary is coupled between the second terminal of inductor Lsecondary and tank node N4. A secondary-side control module 120, which in an illustrative embodiment comprises an integrated circuit controller, generates control signals and provides them to external switches Q5, Q6, Q7 and Q8 arranged in an H-bridge configuration. In illustrative embodiments, the primary-side control module 110 and the secondary-side control module 120 are part of a single integrated circuit. In the illustrative embodiment shown in FIG. 1, the switches Q5, Q6, Q7 and Q8 are MOSFETs and the control signals provided by the secondary-side control module 120 are gate-driver signals. The junction of switches Q5 and Q7 define tank node N3, and the junction of switches Q6 and Q8 define tank node N4. Specifically, in the illustrative embodiment of FIG. 1, tank node N3 is defined by the junction of the source of transistor Q5 and the drain of transistor Q7. Tank node N4 is defined by the junction of the source of transistor Q6 and the drain of transistor Q8. The sources of transistors Q7 and Q8 are coupled to ground. The drains of transistors Q5 and Q6 define an output node NO that provides an output voltage VBRIDGE _ OUT.
  • In illustrative embodiments, an integrated phase-locked loop (PLL) (not shown) locks onto an external high-frequency crystal oscillator (also not shown). The phase-locked loop is illustratively integrated on the same integrated circuit as the primary-side control module 110 and the secondary-side control module 120. The primary-side control module 110 includes a digital pulse-width modulation (PWM) generation state machine that works in tandem with the phase-locked loop to generate the driving waveforms that drive four gate-driver circuits in the primary-side control module 110. The four gate-driver circuits, in turn, drive the gates of the primary-side transistors Q1, Q2, Q3 and Q4 and the series LC resonant tank in order to transmit power across the air gap M. On the secondary side 115, the recovered signal captured across the resonator capacitor Csecondary is sliced to generate the digital reference signal for the phase-locked loop. The secondary-side control module 120 includes a PWM generation state machine seeks to drive the gates of the transistors Q5, Q6, Q7 and Q8 of the secondary-side H-bridge for synchronous rectification. In order to maximize efficiency on the primary side 105 and the secondary side 115, it is important to optimize the switching times for the transistors Q1-Q8. Zero-volt switching (ZVS) is an effective means of optimizing these switching times. Precise zero-volt crossing (ZVC) detection is crucial for maximizing the efficiency of a ZVS scheme.
  • A zero-volt switching event determines the turn-on event of each of the primary-side transistors Q1-Q4. The turn-off edge is conveniently synced to the reference clock, which sets up the timing reference of the whole system. On the secondary side 115, the timing reference is based on the current waveform IP through the primary-side inductor Lprimary. The secondary-side control module 120 performs synchronous rectification that emulates a full bridge diode rectifier. Zero-volt switching conditions are detected for both turn-on and turn-off edges of the secondary-side transistors Q5-Q8.
  • To illustrate aspects of switching control in accordance with the present disclosure, the operation and control of transistor Q1 will now be described. It is to be understood that this description regarding transistor Q1 also pertains to the other primary-side transistors Q2-Q4, as well as, in many respects, the secondary-side transistors Q5-Q8. The drain-to-source voltage signal Vds of transistor Q1 is complex due to the ringing generated by the bond wires of the transistor. The additional voltage resulting from Lprimary(dIP/dt) can be greater than IdsRds. A ZVS detection circuit in the primary-side control module 110 detects if the Vds of the corresponding transistor Q1 is above or below a predetermined threshold VTH-ds. In an illustrative embodiment, the ZVS detection circuit includes a comparator that compares Vds to the predetermined threshold VTH-ds. FIG. 2 is a functional block diagram representing a comparator 200 for use in such a ZVS detection circuit in accordance with illustrative aspects of the present disclosure. In illustrative embodiments, there is a comparator such as the comparator 200 of FIG. 2 corresponding to each of the external transistors Q1-Q8. Ideally, the threshold VTH-ds would be set at 0 V. But in an illustrative embodiment, VTH-ds is set at a value which is still reasonably close to ZVS condition, but relatively immune to parasitic effects, such as 1 V. The gate-to-source voltage Vgs of the transistor is used as a clock to latch the comparator output. The comparator 200 has two outputs which will be referred to herein as ON_LATE and OFF_LATE. The latched outputs, ON_LATE and OFF_LATE, indicate whether the switching edge is early or late relative to ZVS condition. The primary-side control module 105 uses the ON_LATE and OFF_LATE flags to adjust the timing control of the gate-driver signal provided to transistor Q1 to minimize the delay between the transistor switching time and the Vds zero-crossing time. The flags are illustratively used by the PWM state machine to generate desired switching waveforms. In illustrative embodiments, both the ON_LATE and OFF_LATE signals are averaged over multiple (for example, eight) PWM cycles to obtain the average value over a longer time period and thereby reduce noise sensitivity. It is again noted that, while this switching control scheme is described with respect to transistor Q1, the same or similar principles apply to the other primary-side transistor Q2-Q4, as well as to the secondary-side transistors Q5-Q8.
  • When the Vgs signal transitions from low to high, as indicated by the Vgs crossing a gate-to-source threshold voltage VTH-gs, the result of the comparison of the Vds signal to the drain-to-source threshold voltage VTH-ds is latched to the ON_LATE output of the comparator 200. If the drain-to-source voltage Vds is less than the threshold voltage when the Vgs signal goes high (thereby latching the comparator output), the ON_LATE output signal becomes (or remains) 1 (logic-high), indicating that the gate-driver signal went high (turning the transistor Q1 on) after the Vds signal dropped to zero. Thus it can be said that the gate-driver signal turned the transistor Q1 on late. If, on the other hand, the drain-to-source voltage Vds is still greater than the threshold voltage when the Vgs signal goes high, the ON_LATE output signal becomes (or remains) 0 (logic-low), indicating that the gate-driver signal went high before the Vds signal dropped to zero. Note that the Vds signal can change earlier than, or later than, the gate-driver signal switches the transistor on or off due to the effects of current driven through the LC tank circuit by the associated load. In either case, Vds will become low before Vgs becomes high. For maximum switching efficiency, it is desirable that the gate-driver signal (and therefore the Vgs signal) goes high and the Vds signal goes low as close to simultaneously as possible.
  • When the Vgs signal transitions from high to low, the result of the comparison of the Vds signal to the threshold voltage VTH-ds is latched to the OFF_LATE output of the comparator 200. If the drain-to-source voltage Vds starts to rise and crosses the threshold voltage VTH-ds immediately after the Vgs signal goes low (thereby latching the comparator output), the OFF_LATE output signal becomes (or remains) 1 (logic-high), indicating that the gate-driver signal held the transistor Q1 on and kept Vds low, otherwise the LC tank circuit would have driven Vds high (to its off-state voltage level). Thus it can be said that the gate-driver signal turned the transistor Q1 off late. If, on the other hand, the drain-to-source voltage Vds doesn't immediately rise when the Vgs signal goes low, the OFF_LATE output signal becomes 0 (logic-low), indicating that the gate-driver signal went low before the Vds signal dropped to zero. For maximum switching efficiency, it is desirable that the gate-driver signal (and therefore the V, signal) goes low and the Vds signal goes high as close to simultaneously as possible.
  • FIG. 3 is a timing diagram demonstrating illustrative timing relationships between the Vds signal, the Vgs signal, the ON_LATE flag, and the OFF_LATE flag. For purposes of demonstrating the use of the Vgs signal to latch the Vds comparator, the timing diagram of FIG. 3 represents an ideal system without taking into account various system delays that exist in real-world systems. Such delays will be described and accounted for later in this disclosure. As previously explained, the gate-to-source voltage Vgs is used to latch the outputs of the comparator 200. When the Vgs signal goes high, the result of the comparison of the drain-to-source voltage Vds to the threshold voltage VTH-ds is latched to the ON_LATE output. At a time t1 in FIG. 3, the Vgs signal goes high, by virtue of the gate-driver signal provided by the primary-side control module 110 (or, for secondary-side transistors Q5-Q8, by the secondary-side control module). As can be seen in FIG. 3, at time t1, the drain-to-source voltage Vds has already dropped below the comparator threshold voltage VTH-ds, which in the illustrative embodiment of FIG. 3 is shown to be approximately 1V. Thus Vds is less than VTH-ds and the ON_LATE flag goes high, indicating that the gate-driver signal turned the transistor on late, i.e., after the Vds signal has already gone low.
  • As mentioned above, when the Vgs signal goes low, the result of the comparison of the drain-to-source voltage Vds to the threshold voltage VTH-ds is latched to the OFF_LATE output. At a time t2 in FIG. 3, the Vgs signal goes low, by virtue of the gate-driver signal provided by the primary-side control module 110 (or, for secondary-side transistors Q5-Q8, by the secondary-side control module). As can be seen in FIG. 3, at time t2, the drain-to-source voltage Vds starts to rise and crosses the threshold voltage VTH-ds immediately after the Vgs signal goes low. Thus the OFF_LATE flag goes high, indicating that the gate-driver signal turned the transistor off late.
  • At a time t3 in FIG. 3, the Vgs signal goes high again. As can be seen in FIG. 3, at time t3, the drain-to-source voltage Vds is still greater than the threshold voltage VTH, and therefore the ON_LATE flag goes low, indicating that the gate-driver signal turned the transistor on early, i.e., before the Vds signal has gone low. At a time t4 in FIG. 3, the Vgs signal goes low again. At time t3, the drain-to-source voltage Vds is still less than the threshold voltage VTM, and therefore the OFF_LATE flag goes low, indicating that the gate-driver signal turned the transistor off early, i.e., before the Vds signal has gone high.
  • In illustrative embodiments, a PWM state machine in the primary-side control module 110 uses the latched outputs from the Vds comparators corresponding to each of the primary-side transistors Q1-Q4 to regulate control bits to the phase-locked loop. Similarly, a PWM state machine in the secondary-side control module 120 uses the latched outputs from the Vds comparators corresponding to each of the secondary-side transistors Q5-Q8 to regulate control bits to the phase-locked loop. The PWM state machines employ control algorithms that seek to obtain locking positions for the rising and falling edges of the gate-driver waveforms. These algorithms illustratively employ an initial pulse-width value for the gate-driver waveforms. For example, in an illustrative embodiment, the hard-coded values for the initial pulse widths at the beginning of the search algorithm are set to ˜40% DC on the primary side and ˜10% DC on the secondary side. During operation, the pulse widths are then adjusted dynamically based on the values of the ON_LATE and OFF_LATE flags (illustratively averaged over multiple PWM cycles) in order to maximize the alignment of the Vds and Vgs signals.
  • In an illustrative embodiment, the primary-side PWM state machine and the secondary-side PWM state machine each first seeks to lock the rising edge of the gate-driver waveform to the ON_LATE flag. This is done by successively shifting the position of the rising edge of the gate-driver signal until the ON_LATE flag changes state. In illustrative embodiments, the time period between position changes is programmable via non-volatile memory (NVM) and can be tuned based on the bandwidth requirements of the system. The PWM state machine next repeats the process for the falling edge. The PWM state machine performs this process with respect to all four external transistors (transistors Q1-Q4 for the primary-side PWM state machine and transistors Q5-Q8 for the secondary-side PWM state machine). When both the rising and falling edges for all four external transistors have attained optimal positions for zero-volt switching, the state machine toggles the edges around those positions.
  • FIG. 4 is a functional block diagram representing a comparator system 400 that implements a comparator such as the comparator 200 described with respect FIGS. 2 and 3 in accordance with illustrative embodiments of the present invention. The comparator system 400 implements the timing control scheme, described with respect to FIGS. 2 and 3, whereby the Vgs signal is used as a clock signal controlling the latching of the outputs of the comparator 200 (or the outputs of the comparator system 400). The comparator system 400 also accounts for some of the aforementioned timing delays present in a real-world system. As can be seen in FIG. 4, the comparator system 400 actually employs two comparators—a Vgs comparator 410 and a Vgs comparator 420. Vds comparator 410 receives the drain-to-source voltage Vds and compares it to the predetermined threshold VTH-ds. As mentioned with respect to FIG. 2, ideally, the threshold VTH-ds would be set at 0 V. But in an illustrative embodiment, VTH-ds is set at a value, such as 1 Vgs which is still reasonably close to ZVS condition, but relatively immune to parasitic effects. The Vds comparator 410 has two outputs, referred to herein as RISE_P and FALL_P. The RISE_P output responds to the rising edge of the Vds signal by going high when the Vds signal rises above the voltage threshold VTH-ds. The FALL_P output responds to the falling edge of the Vds signal by going high when the Vds signal drops below the voltage threshold VTH-ds.
  • Vgs comparator 420 receives the gate-to-source voltage Vds and compares it to a predetermined value that corresponds to the turn-on threshold voltage of the associated transistor. In an illustrative embodiment, the Vgs input of the Vgs comparator 420 is coupled directly to the gate-up and gate-down pins of the gate-driver circuit. The Vgs comparator 420 has two outputs, referred to herein as ON_CLK and OFF_CK. The ON_CLK output responds to the rising edge of the Vds signal by going high when the Vgs signal rises above the voltage threshold VTH-gs. The OFF_CLK output responds to the failing edge of the Vds signal by going high when the Vgs signal drops below the voltage threshold VTH-gs.
  • The Vds comparator 410 and Vgs comparator 420 are both subject to an inherent amount of delay. That is, there is an inherent amount of delay between the time that the Vds signal changes state (i.e., rises above, or drops below, the voltage threshold VTH-ds) and the time that the corresponding Vds output (RISE_P or FALL_P) changes state (i.e., goes high or goes low). Likewise, there is an inherent amount of delay between the time that the Vgs signal changes state (i.e., rises above, or drops below, the voltage threshold VTH-gs) and the time that the corresponding Vds output changes state. The amount of delay introduced by the Vds comparator 410 and Vgs comparator 420 can vary from part to part, and also in response to process variance. The delay matching/trimming module 430 includes circuitry that accounts for and adjusts for these inherent delays. Each of the outputs of both the Vds comparator 410 and the Vgs comparator 420 are provided to a delay element in the delay matching/trimming module 430. Specifically, the RISE_P signal is provided to delay element 435, the FALL_P signal is provided to delay element 440, the OFF_CLK signal is provided to delay element 445, and the ON_CLK signal is provided to delay element 450. Each of the delay elements 435-450 also includes a trim input (not shown) for receiving a trim value that dictates an amount of delay that is to be introduced by the corresponding delay element. These trim values can be determined during or after manufacture by various methods that can include testing. In an illustrative embodiment, the trim values are stored in non-volatile memory. In this way, the delay matching/trimming module 430 can compensate for the delays inherent in the Vds comparator 410 and Vgs comparator 420. In illustrative embodiments, the delay matching/trimming module 430 also compensates for the delay that exists between the time that the PWM signal controlling the gate-driver circuit changes state and the time that the gate voltage changes in response thereto.
  • The delay matching/trimming module 430 thus produces delay-adjusted versions of the signals received from the Vds comparator 410 and Vgs comparator 420. Specifically, delay element 435 outputs a signal referred to herein as RISE_P_DLY, delay element 440 outputs a signal referred to herein as FALL_P_DLY, delay element 445 outputs a signal referred to herein as OFF_CLK_DLY, and delay element 450 outputs a signal referred to herein as ON_CLK_DLY.
  • The output latches and averaging logic module 460 receives the delay-adjusted outputs of the Vds comparator 410 and Vgs comparator 420 from the delay matching/trimming module 430. The output latches and averaging logic module 460 implements the latching of the outputs of the Vds comparator 410 at times dictated by the rising and falling edges of the Vgs signal as represented by the outputs of the Vgs comparator 420. In the illustrative embodiment represented by FIG. 4, the latching of the ON_LATE and ON_LATE flags is implemented using two D flip- flops 465 and 470. D flip-flop 470 receives the FALL_P_DLY signal from the delay matching/trimming module 430 at its D input and receives the ON.CLK.DLY signal at its clock input. Thus, when the ON_CLK_DLY signal goes high, indicating that the gate-to-source voltage V, has gone high, the value existing at the D input, i.e., the value of the FALL_P_DLY signal, is latched to the output Q as the ON_LATE flag. This value will be a digital 1 (logic-high) if the Vds voltage dropped below the Vds threshold VTH-ds before the Vgs signal rose above the Vgs threshold VTH-gs. In other words, ON_LATE=1 indicates that the transistor turned on “late,” i.e., after the drain-to-source voltage dropped below its threshold VTH-ds.
  • D flip-flop 465 receives the RISE_P_DLY signal from the delay matching/trimming module 430 at its D input and receives the OFF.CLK.DLY signal at its clock input. Thus, when the OFF_CLK_DLY signal goes high, indicating that the gate-to-source voltage Vgs has gone low, the value existing at the D input, i.e., the value of the RISE_P_DLY signal, is latched to the output Q as the OFF_LATE flag. This value will be a digital 1 (logic-high) if the Vds voltage rose above the Vds threshold VTH-ds before the Vgs signal dropped below the Vgs threshold VTH-gs. In other words, OFF_LATE=1 indicates that the transistor turned off “late,” i.e., after the drain-to-source voltage rose above its threshold VTH-ds.
  • As explained above with respect to FIGS. 2 and 3, the PWM state machines of the primary-side control module 110 and secondary-side control module 120 use the ON_LATE and OFF_LATE flags to generate desired switching waveforms, by, for example, iteratively adjusting, based on said ON_LATE and OFF_LATE flags, the positions of the rising and failing edges of the PWM signals used to generate the gate driver signals that are provided to transistors Q1-Q8. In illustrative embodiments, the output latches and averaging logic module 460 includes averaging logic that serves to average the ON_LATE and OFF_LATE signals over multiple (for example, eight) PWM cycles to obtain the average value over a longer time period and thereby reduce noise sensitivity.
  • FIG. 5 is a timing diagram timing showing timing relationships for various signals in a comparator system such as comparator system 400 of FIG. 4 in accordance with illustrative timing and control schemes of the present disclosure. The timing diagram of FIG. 5 shows the PWM control signal, the gate-to-source voltage Vgs, the drain-to-source voltage Vds, the ON_CLK signal, the ON_CLK_DLY signal, the FALL_P signal, the FALL_P_DLY signal, and the ON_LATE flag. These signals are described above with respect to FIG. 4. The PWM/Vgs plot shows both the pulse-width modulation signal PWM and the gate-to-source voltage Vgs. The PWM signal is illustratively generated by the pulse-width-modulation state machine and provided to the gate-driver circuit, which generates a gate-driver signal based on said PWM signal. The gate-to-source voltage Vgs is representative of the gate-driver signal provided to the gate of the transistor by the gate-driver circuit. At a time t1 in FIG. 5, the PWM signal goes high. After a driver delay 500, the gate-to-source voltage Vgs crosses the transistor turn on threshold VTH-gs, which in the illustrative embodiment of FIG. 5, is 2.5V, at a time t2. After a Vgs comparator delay 510, the ON_CLK output of the Vgs comparator 420 goes high at a time t4 in response to the V, signal crossing the VTH-gs threshold at time t2. At a time t3, the drain-to-source voltage Vds of the transistor crosses the drain-to-source voltage threshold VTH-ds, which in the illustrative embodiment of FIG. 5 is set at 1 V. After a Vds comparator delay 520, the FALL_P output of the Vds comparator 410 goes high at a time t5 in response to the Vds signal crossing the VTH-ds threshold at time t3.
  • As can be seen in FIG. 5, there is a delay mismatch between the Vgs comparator delay 510 and the Vds comparator delay 520. That is, in the illustrative example of FIG. 5, the Vgs comparator 420 is subject to a longer delay than the Vds comparator 410. The delay matching/trimming module 430 compensates for this delay mismatch by performing delay matching on the ON_CLK and FALL_P signals. Specifically, the delay elements 440 and 450 apply a delay to the FALL_P and ON_CLK signals, respectively. The amount of delay applied is defined by the trim value that is supplied to the delay elements 440 and 450. The trim values are based on the amount of delay that is inherent in each of the comparators 410 and 420 as determined, illustratively, during and after manufacture via testing and other means. The output of delay element 440, referred to as FALL_P_DLY, constitutes the delay-adjusted version of the FALL_P signal, and the output of delay element 450, referred to as ON_CLK_DLY, constitutes the delay-adjusted version of the ON_CLK signal. In accordance with the implemented delay adjustments, the FALL_P_DLY signal goes high at a time t6 and the ON_CLK_DLY signal goes high at a time t7. The FALL_P_DLY signal is provided to the D-flip-flop 470 of the output latches and averaging logic module 460, and the ON_CLK_DLY signal is provided to the clock input of D flip-flop 470. Thus when the ON_CLK_DLY signal goes high at time t7, the value present at the D input is latched to the Q output of the flip-flop, which provides the ON_LATE flag. Since the FALL_P_DLY signal is high at time t7, the ON_LATE flag goes accordingly. Due to a small delay inherent in the D flip-flop 460, the ON_LATE goes high at time t8, reflecting the fact that the Vgs signal went high, thereby turning the transistor on, late, that is, after the drain-to-source voltage Vgs dropped below the VTH-ds.
  • FIG. 6 is a flowchart representing a method of controlling a field-effect transistor in accordance with illustrative embodiments of the present disclosure. At block 600, a comparator compares a drain-to source voltage of the transistor to a threshold voltage. At block 610, a gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. At block 620, a control function with respect to the transistor is performed based on the value of the comparator output.
  • While some examples of a zero-volt-crossing detection scheme using a Vds comparator that uses the gate voltage of the transistor as a clock input to latch the comparator output have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art. For example, while aspects of the disclosure are described herein with respect to wireless power transfer system, aspects of the disclosure can also be implemented with regards to substantially any system that employs zero-volt switching.

Claims (20)

What is claimed is:
1. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:
a comparator operable to receive the drain-to-source voltage of the transistor and compare it to a threshold voltage, the comparator comprising a clock input operable to receive a gate voltage of the transistor, wherein said received gate voltage is used to latch a result of said comparison to an output of the comparator; and
control circuitry operable to receive said comparator output and to perform a control function with respect to the transistor based on the value of the comparator output.
2. The control module of claim 1 wherein the comparator comprises:
a first output configured to provide an on-late flag indicative of whether the gate voltage turned the transistor on before or after the drain-to-source voltage went from high to low, wherein a rising edge of said received gate voltage is used to latch a result of said comparison to said first output of the comparator; and
a second output configured to provide an off-late flag indicative of whether the gate voltage turned the transistor off before or after the drain-to-source voltage went from low to high, wherein a falling edge of said received gate voltage is used to latch a result of said comparison to said second output of the comparator.
3. The control module of claim 2 wherein the control circuitry is operable to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.
4. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the gate driver signal based on the value of the off-late flag.
5. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the PWM signal based on the value of the off-late flag.
6. The control module of claim 5 wherein the control circuitry is operable to average the value of the on-late flag over a plurality of PWM cycles and to average the value of the off-late flag over a plurality of PWM cycles, and to adjust the timing of the rising edge of the PWM signal based on the average value of the on-late flag and to adjust the timing of the falling edge of the PWM signal based on the average value of the off-late flag.
7. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:
a drain-to-source voltage comparator operable to receive the drain-to-source voltage (Vds) of the transistor and compare it to a Vds threshold, the Vds comparator having at least one output configured to provide a Vds edge transition signal indicative of Vds crossing the Vds threshold;
a gate-to-source voltage comparator operable to receive the gate-to-source voltage (Vgs) of the transistor and compare it to a Vgs threshold, the Vgs comparator having at least one output configured to provide a Vgs edge transition signal indicative of Vgs crossing the Vgs threshold;
at least one latching element having a data input, a clock input, and an output, the data input operably coupled to receive a Vds edge transition signal from the Vds comparator and the clock input operably coupled to receive a Vgs edge transition signal from the Vgs comparator such that the Vgs edge transition signal serves to latch the Vds edge transition signal to the latch output.
8. The control module of claim 7 further comprising a delay-matching module operably coupled to receive the Vds edge transition signal from the Vds comparator and the Vgs edge transition signal from the Vgs comparator, apply a matching delay to at least one of the Vds edge transition signal and the Vgs edge transition signal to compensate for any disparity in delays inherent in the Vds comparator and the Vgs comparator, and to provide a delay-adjusted Vds edge transition signal to the data input of the at least one latching element and a delay-adjusted Vgs edge transition signal to the clock input of the at least one latching element.
9. The control module of claim 7 further comprising control circuitry operable to receive the output of the at least one latching element and to perform a control function with respect to the transistor based on the value of said output of the at least one latching element.
10. The control module of claim 7 wherein the at least one latching element comprises at least one D flip-flop.
11. The control module of claim 7 wherein:
the Vds comparator comprises first and second outputs, the first output configured to provide a Vds rising-edge signal indicative of Vds rising above the Vds threshold, the second output configured to provide a Vds falling-edge signal indicative of Vds falling below the Vds threshold; and
the Vgs comparator comprises first and second outputs, the first output configured to provide a Vgs rising-edge signal indicative of Vgs rising above the Vgs threshold, the second output configured to provide a Vgs falling-edge signal indicative of Vgs falling below the Vgs threshold.
12. The control module of claim 11 wherein the at least one latching element comprises:
a first latching element having a data input, a clock input, and an output, the data input operably coupled to receive the Vds falling-edge signal from the Vds comparator and the clock input operably coupled to receive the Vgs rising-edge signal from the Vgs comparator such that the Vgs rising-edge signal serves to latch the Vds falling-edge signal to the latch output, the latch output thus serving as an on-late flag indicative of whether the Vgs signal turned the transistor on before or after the drain-to-source voltage went from high to low; and
a second latching element having a data input, a clock input, and an output, the data input operably coupled to receive the Vds rising-edge signal from the Vds comparator and the clock input operably coupled to receive the Vgs falling-edge signal from the Vgs comparator such that the Vgs falling-edge signal serves to latch the Vds rising-edge signal to the latch output, the latch output thus serving as an off-late flag indicative of whether the Vgs signal turned the transistor off before or after the drain-to-source voltage went from low to high.
13. The control module of claim 12 further comprising control circuitry operable to receive the on-late flag and the off-late flag and to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.
14. The control module of claim 12 further comprising:
a first delay-matching element operable to apply a matching delay to the Vds rising-edge signal to compensate for any disparity in delays inherent in the Vds comparator and the Vgs comparator, and to provide a delay-adjusted Vds rising-edge signal to the data input of the second latching element;
a second delay-matching element operable to apply a matching delay to the Vds falling-edge signal to compensate for any disparity in delays inherent in the Vds comparator and the Vgs comparator, and to provide a delay-adjusted Vds falling-edge signal to the data input of the first latching element;
a third delay-matching element operable to apply a matching delay to the Vgs falling-edge signal to compensate for any disparity in delays inherent in the Vds comparator and the Vgs comparator, and to provide a delay-adjusted Vgs falling-edge signal to the clock input of the second latching element; and
a fourth delay-matching element operable to apply a matching delay to the Vgs rising-edge signal to compensate for any disparity in delays inherent in the Vds comparator and the Vgs comparator, and to provide a delay-adjusted Vgs rising-edge signal to the clock input of the first latching element.
15. A method of controlling a field-effect transistor, comprising:
comparing, with a comparator, a drain-to source voltage of the transistor to a threshold voltage;
providing a gate voltage signal of the transistor to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator; and
performing a control function with respect to the transistor based on the value of the comparator output.
16. The method of claim 15 further comprising:
providing, at a first output of the comparator, an on-late flag indicative of whether the gate voltage signal turned the transistor on before or after the drain-to-source voltage went from high to low;
providing, at a second output of the comparator, an off-late flag indicative of whether the gate voltage signal turned the transistor off before or after the drain-to-source voltage went from low to high;
latching a result of said comparison to said first output of the comparator in response to receiving a rising edge of the gate voltage signal at said clock input; and
latching a result of said comparison to said second output of the comparator in response to receiving a falling edge of the gate voltage signal at said clock input.
17. The method of claim 16 wherein said performing a control function comprises performing at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.
18. The method of claim 17 wherein said performing a control function comprises adjusting the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the gate driver signal based on the value of the off-late flag.
19. The method of claim 18 wherein said performing a control function comprises adjusting the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the PWM signal based on the value of the off-late flag.
20. The method of claim 19 wherein said performing a control function comprises averaging the value of the on-late flag over a plurality of PWM cycles, averaging the value of the off-late flag over a plurality of PWM cycles, adjusting the timing of the rising edge of the PWM signal based on the average value of the on-late flag, and adjusting the timing of the falling edge of the PWM signal based on the average value of the off-late flag.
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CN201880027648.4A CN110574291B (en) 2017-04-26 2018-04-26 High resolution FET VDS zero volt crossing timing detection scheme
EP18792274.5A EP3616321B1 (en) 2017-04-26 2018-04-26 Control module and method for high-resolution fet vds zero-volt-crossing timing detection
PCT/US2018/029609 WO2018200843A1 (en) 2017-04-26 2018-04-26 High-resolution fet vds zero-volt-crossing timing detection scheme
JP2019558720A JP2020519092A (en) 2017-04-26 2018-04-26 High resolution FET VDS Zero volt crossing timing detection system
US16/128,038 US10382028B2 (en) 2017-04-26 2018-09-11 VDS comparator rise P, fall P, on late, off late outputs for ZVC timing
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