JP4672443B2 - Step-down switching regulator, its control circuit, and electronic equipment using the same - Google Patents

Description

  The present invention relates to a step-down switching regulator, and more particularly to a control technology for a synchronous rectification switching regulator.

Various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years are equipped with microcomputers that perform digital signal processing. The power supply voltage required for driving such a microcomputer has been reduced with the miniaturization of the semiconductor manufacturing process, and there is one that operates at a low voltage of 1.5 V or less.
On the other hand, a battery such as a lithium ion battery is mounted on such an electronic device as a power source. Since the voltage output from the lithium ion battery is about 3 V to 4 V, if this voltage is supplied to the microcomputer as it is, useless power consumption occurs. Therefore, a step-down switching regulator or a series regulator is used. In general, the battery voltage is stepped down to a constant voltage and supplied to a microcomputer.

As a step-down switching regulator, there are a method using a rectifying diode (hereinafter referred to as a diode rectifying method) and a method using a rectifying transistor instead of a diode (hereinafter referred to as a synchronous rectifying method). In the former case, there is an advantage that high efficiency can be obtained when the load current flowing through the load is low. However, since a diode is required in addition to the inductor and the capacitor outside the control circuit, the circuit area becomes large. In the latter case, the efficiency when the current supplied to the load is small is inferior to the former, but since a transistor is used instead of a diode, it can be integrated inside the LSI, and the circuit area including peripheral components As a result, downsizing is possible. When an electronic device such as a cellular phone is required to be downsized, a switching regulator using a rectifying transistor (hereinafter referred to as a synchronous rectification switching regulator) is often used.
For example, Patent Documents 1 and 2 disclose synchronous rectification type and diode rectification type switching regulators.

JP 2004-32875 A JP 2002-252971 A

  Here, when a load connected to the step-down switching regulator is temporarily short-circuited, an overcurrent flows. This overcurrent is supplied to the load via the inductor. When a large current flows through the inductor, the inductor cannot hold any more magnetic flux, that is, becomes saturated. When the inductor is saturated, the inductance component decreases and approaches a simple conductor. At this time, the current flowing through the inductor flows through the switching transistor, and if the predetermined threshold current is exceeded, the reliability of the switching transistor and the load is affected.

  The present invention has been made in view of such problems, and an object thereof is to provide a control circuit for a step-down switching regulator capable of detecting and protecting an overcurrent state. Another object of the present invention is to provide a control circuit for a step-down switching regulator that can easily check the operating state of an overcurrent protection circuit.

  One embodiment of the present invention relates to a control circuit for a step-down switching regulator. The control circuit includes a switching transistor and a synchronous rectification transistor connected in series between the input terminal and the ground, an output stage that outputs the voltage at the connection point of the two transistors to the switching regulator output circuit as a switching voltage, and switching First and second gate voltages to be applied to the gates of the switching transistor and the synchronous rectification transistor based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the regulator output circuit approaches a predetermined reference voltage Compares the voltage across the switching transistor with a predetermined threshold voltage and outputs a comparison signal of a predetermined level when the voltage across the switching transistor exceeds the predetermined threshold voltage And the comparison signal output from the comparator Pitch to and a latch circuit for outputting. The driver circuit forcibly turns off the switching transistor while the comparison signal is latched at a predetermined level in the latch circuit.

“Compare the voltage at both ends of the switching transistor with a predetermined threshold voltage” means that the voltage at both ends of the switching transistor is indirectly compared with the case where the voltage at both ends of the switching transistor is directly compared with the threshold voltage. This includes the case of comparison with threshold voltage.
The control circuit detects the current flowing through the switching transistor by monitoring the voltage across the switching transistor. The circuit can be protected by determining that the voltage across the switching transistor exceeds the threshold voltage as an overcurrent state and forcibly turning off the switching of the switching transistor. According to this aspect, by latching the detection signal, the switching transistor can be prevented from being turned on and off many times within one period of the pulse width modulation signal.

The comparison unit is connected in series between the drain and source of the switching transistor so as to form a path parallel to the switching transistor, the detection transistor and the detection resistor having the first gate voltage input to the gate, and both ends of the detection resistor. A voltage comparator for comparing the voltage and the threshold voltage. The comparison unit may output the output of the voltage comparator as a comparison signal.
By providing a detection transistor and a detection resistor in parallel with the switching transistor, and monitoring the voltage drop at the detection resistor, the current flowing through the switching transistor can be indirectly monitored, and an overcurrent state can be suitably detected. it can.

  The on-resistance of the detection transistor may be set higher than the on-resistance of the switching transistor. By setting the on-resistance of the detection transistor high, the current flowing to the detection transistor can be set lower than the current flowing to the switching transistor.

  The resistance value of the detection resistor may be set higher than the on-resistance of the detection transistor. In this case, the overcurrent state can be accurately detected even when the resistance value of the detection resistor varies.

  The latch circuit may be reset for each cycle of the pulse width modulation signal. By resetting the latch circuit for each cycle of the pulse width modulation signal, the switching transistor is forcibly turned off only within one cycle. Therefore, it is possible to quickly return from the overcurrent state to the normal current state. It can be carried out.

  The latch circuit may include a flip-flop that is set by a comparison signal output from the comparison unit and is reset by an output signal of an oscillator used to generate a pulse width modulation signal.

The control circuit may further include a switch element capable of independently controlling on / off of the switching transistor and the detection transistor.
When the control circuit checks whether the comparison signal output from the comparison unit is at a predetermined level when the voltage across the switching transistor exceeds the threshold voltage, the switching circuit turns off the switching transistor by the switch element, and the detection transistor In the normal operation in which the step-down operation is performed, the switching transistor and the detection transistor may be switched based on the first gate voltage by the switch element.
According to this aspect, at the time of inspection, it is possible to inspect whether the overcurrent protection function functions normally without passing a large current by turning off the switching transistor and turning on only the detection transistor.

  The protection circuit may turn off the switching transistor by changing the logic value of the pulse width modulation signal. By changing the logic value of the pulse width modulation signal, that is, the high and low levels, the first gate voltage generated based on the pulse width modulation signal can be changed, and the switching transistor can be turned off.

  The control circuit may be integrated on a single semiconductor substrate.

Another aspect of the present invention is a step-down switching regulator. This step-down switching regulator includes a capacitor having one end grounded, an inductor having one end connected to the other end of the capacitor, and the above-described control circuit that supplies a switching voltage to the other end of the inductor. The voltage at the other end is output.
According to this aspect, when the load connected to the step-down switching regulator is short-circuited, it is possible to prevent the overcurrent from constantly flowing.

Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery and the above-described step-down switching regulator that steps down and outputs the voltage of the battery.
According to this aspect, the step-down switching regulator can be protected from overcurrent, and heat generation of the entire electronic device can be suppressed.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the step-down switching regulator control circuit of the present invention, overcurrent protection can be realized.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an electronic device equipped with the step-down switching regulator according to the first embodiment. The electronic device 300 is, for example, a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360.
The battery 310 is a lithium ion battery, for example, and outputs about 3 to 4 V as the battery voltage Vbat.
The analog circuit 330 includes high-frequency circuits such as a power amplifier, an antenna switch, an LNA (Low Noise Amplifier), a mixer, and a PLL (Phase Locked Loop), and includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. . The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V.
The microcomputer 350 is a block that comprehensively controls the entire electronic device 300 and operates with a power supply voltage of 1.5V.
The LED 360 includes RGB three-color LEDs (Light Emitting Diodes) and is used as a liquid crystal backlight or illumination, and a driving voltage of 4 V or more is required for driving.

The power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel. For the analog circuit 330, digital circuit 340, microcomputer 350, and LED 360, Supply an appropriate power supply voltage.
The step-down switching regulator according to this embodiment can be suitably used for such a power supply device 320. Hereinafter, the configuration of the step-down switching regulator according to the present embodiment will be described in detail.

FIG. 2 is a circuit diagram showing a configuration of the step-down switching regulator 200 according to the first embodiment. The step-down switching regulator 200 is a synchronous rectification step-down switching regulator, and includes a control circuit 100 and a switching regulator output circuit 110. The control circuit 100 is an LSI chip integrated on a single semiconductor substrate, and a switching transistor M1 functioning as a switching element and a synchronous rectification transistor M2 are incorporated in the control circuit 100.
The switching regulator output circuit 110 includes an output capacitor C1 and an inductor L1. One end of the output capacitor C1 is grounded, and the other end is connected to the load RL and the inductor L1. The inductor L1 is connected to the control circuit 100 and applied with the switching voltage Vsw.

The step-down switching regulator 200 controls the current flowing through the inductor L1 by the control circuit 100, steps down the battery voltage Vbat by charging the output capacitor C1, and supplies the voltage appearing at the output capacitor C1 to the load RL. .
Hereinafter, the voltage supplied to the load RL is referred to as an output voltage Vout, and the current flowing through the load RL is referred to as a load current IL.

  The control circuit 100 includes an input terminal 102, a switching terminal 104, and a voltage feedback terminal 106 as input / output terminals. A battery 310 is connected to the input terminal 102, and a battery voltage Vbat is input as an input voltage. The switching terminal 104 is connected to the inductor L1 and outputs a switching voltage Vsw generated inside the control circuit 100. The voltage feedback terminal 106 is a terminal to which the output voltage Vout applied to the load RL is fed back.

  The control circuit 100 includes a driver circuit 10, a PWM control unit 20, a comparison unit 30, a latch circuit 40, a forced off transistor 42 that is a protection circuit, a switching transistor M1, and a synchronous rectification transistor M2.

The switching transistor M1 is a P-channel MOS transistor, and has a source connected to the input terminal 102 and a drain connected to the switching terminal 104. The synchronous rectification transistor M2 is an N-channel MOS transistor, the source is grounded, and the drain is connected to the drain of the switching transistor M1 and the switching terminal 104. The back gate of the synchronous rectification transistor M2 is grounded.
The switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the input terminal 102 to which the battery voltage Vbat is applied and the ground, and the control circuit 100 uses the voltage at the connection point of the two transistors as the switching voltage Vsw. Is applied to one end of an inductor L1 connected to the outside via a switching terminal 104.

The PWM control unit 20 controls a pulse width modulation signal (hereinafter referred to as “duty ratio”) that defines the duty ratio of the ON period of the switching transistor M1 and the synchronous rectification transistor M2 so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined reference voltage. PWM signal Vpwm). The output voltage Vout of the step-down switching regulator 200 is input to the PWM control unit 20 via the voltage feedback terminal 106.
The resistors R1 and R2 divide the output voltage Vout, and output the output voltage Vout ′ multiplied by R2 / (R1 + R2) to the inverting input terminal of the error amplifier 22. The reference voltage Vref is input to the non-inverting input terminal of the error amplifier 22, and an error between the output voltage Vout ′ and the reference voltage Vref is amplified and output as an error voltage Verr.

  The oscillator 26 oscillates at a predetermined frequency and outputs a periodic voltage Vosc having a triangular wave shape or a sawtooth wave shape. The first comparator 24 compares the periodic voltage Vosc and the error voltage Verr, and outputs a PWM signal Vpwm that is at a low level when Vosc> Verr and at a high level when Vosc <Verr. This PWM signal Vpwm is a pulse width modulated signal having a constant cycle time and a period of high level and low level changing according to the output voltage Vout ′.

Based on the PWM signal Vpwm output from the PWM control unit 20, the driver circuit 10 includes a first gate voltage Vg1 to be applied to the gate of the switching transistor M1 and a second gate voltage to be applied to the gate of the synchronous rectification transistor M2. Vg2 is generated. In the present embodiment, the first gate voltage Vg1 and the second gate voltage Vg2 are generated by inverting the logic value of the PWM signal Vpwm.
The switching transistor M1 is turned on when the first gate voltage Vg1 is at a low level and turned off when the first gate voltage Vg1 is at a high level. The synchronous rectification transistor M2 is turned on when the second gate voltage Vg2 is at a high level, and turned off when the second gate voltage Vg2 is at a low level.
As described above, the driver circuit 10 sets the ratio of the time during which the switching transistor M1 and the synchronous rectification transistor M2 are turned on based on the high-level and low-level duty ratios of the PWM signal Vpwm, and alternates the two transistors. Turn on and off. In order to prevent the switching transistor M1 and the synchronous rectification transistor M2 from being turned on at the same time and causing a through current to flow, the driver circuit 10 sets a period (dead time) during which the switching transistor M1 and the synchronous rectification transistor M2 are simultaneously turned off. You may provide for every period.

The comparison unit 30 receives the switching voltage Vsw and the battery voltage Vbat. The comparison unit 30 includes a second comparator 32 and a voltage source 34. The voltage source 34 generates a predetermined threshold voltage Vth. A voltage (Vbat−Vth) is input to the + input terminal of the second comparator 32. The switching voltage Vsw is input to the negative input terminal of the second comparator 32. The comparison unit 30 compares the voltage across the switching transistor M1 (hereinafter referred to as the monitoring voltage) ΔV = (Vbat−Vsw) with the threshold voltage Vth. When the monitoring voltage ΔV exceeds the threshold voltage Vth, the comparison unit 30 The comparison signal Vcmp is output.
The monitoring voltage ΔV is given by the product of the on-resistance Ron1 of the switching transistor M1 and the current Ipeak flowing through the switching transistor M1. That is, ΔV = Ron1 × Ipeak is established. Since Ipeak = ΔV / Ron1, the comparison unit 30 can detect a state where the current Ipeak flowing through the switching transistor M1 exceeds the threshold current given by Ith = Vth / Ron1. The threshold current Ith is set according to the allowable current of the switching transistor M1. For example, when the maximum value of the current flowing through the switching transistor M1 during normal operation is about Ipeak = 500 mA, the threshold current Ith is set to about 1A.

  The latch circuit 40 is a D flip-flop, and the comparison signal Vcmp output from the second comparator 32 is input to the data terminal, and the periodic voltage Vosc output from the oscillator 26 is input to the clock terminal. The latch circuit 40 latches the comparison signal Vcmp output from the comparison unit 30, is reset by the periodic voltage Vosc that is an output signal of the oscillator 26 used for generating the PWM signal Vpwm, and latches the comparison signal Vcmp again. The latch circuit 40 can also be configured using an RS flip-flop or the like. The output signal SIG1 of the latch circuit 40 is input to the gate of the forced off transistor 42.

The forced off transistor 42 is an N-channel MOS transistor whose drain is connected to the output of the error amplifier 22 and whose source is grounded. When the output signal SIG1 of the latch circuit 40 is at a high level, the forced off transistor 42 is turned on, and at this time, the output voltage of the error amplifier 22, that is, the error voltage Verr becomes 0V. When the error voltage Verr becomes 0V, the PWM signal Vpwm output from the first comparator 24 becomes a low level.
As described above, the driver circuit 10 generates the first gate voltage Vg1 and the second gate voltage Vg2 based on the duty ratio of the PWM signal Vpwm. When the PWM signal Vpwm is at a high level, the switching transistor M1 is turned on. Therefore, the driver circuit 10 forcibly turns off the switching transistor M1 while the comparison signal Vcmp is latched at a high level in the latch circuit 40.

Hereinafter, the operation of the control circuit 100 according to the present embodiment will be described with reference to FIG. FIG. 3 is a time chart showing an operation state of the control circuit 100 according to the present embodiment. The time chart of FIG. 3 explains the operation in an overcurrent state where the load current IL is very large. FIG. 3 shows, in order from the top, the error voltage Verr and the periodic voltage Vosc, the PWM signal Vpwm, the monitoring voltage ΔV, the comparison signal Vcmp, the output signal SIG1 of the latch circuit 40, and the first gate voltage Vg1.
The switching transistor M1 is turned off when the first gate voltage Vg1 is at a high level, and turned on when the first gate voltage Vg1 is at a low level. That is, in the figure, Ton1 indicates a period during which the switching transistor M1 is on.

  The duty ratio of the PWM signal Vpwm is controlled so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined voltage, and becomes a high level when Verr> Vosc, and a low level when Verr <Vosc. The first gate voltage Vg1 is generated based on the PWM signal Vpwm. The on / off state of the switching transistor M1 is controlled by the first gate voltage Vg1, and the switching voltage Vsw repeats a high level and a low level. During the period from time T0 to time T1, the driver circuit 10 drives the switching transistor M1 and the synchronous rectification transistor M2 based on the PWM signal Vpwm.

  At time T1, the load RL is short-circuited and the load current IL increases. Along with this, the monitoring voltage Δ increases. When the monitoring voltage ΔV exceeds the threshold voltage Vth at time T2, the comparison signal Vcmp output from the comparison unit 30 becomes high level. When the comparison signal Vcmp becomes high level, the latch circuit 40 is set and its output signal SIG1 becomes high level. When the output signal SIG1 of the latch circuit 40 becomes a high level and the forced-off transistor 42 is turned on, the error voltage Verr is fixed near 0V, and the PWM signal Vpwm is forced to a low level. That is, the high time TH of the pulse width signal Vpwm is shorter than the on-time TH ′ when it is generated based on the error voltage Verr ′ indicated by the broken line. This means that the ON time Ton1 of the switching transistor M1 is shortened and the ON time of the synchronous rectification transistor M2 is increased. When the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on at time T2, the monitoring voltage ΔV starts to drop.

  When the monitoring voltage ΔV becomes lower than the threshold voltage Vth at time T3, the comparison signal Vcmp becomes low level. When the periodic voltage Vosc, which is the output of the oscillator 26, rises to the level Vx at time T4, the latch circuit 40 is reset, and the output signal SIG1 becomes a low level. When the output signal SIG1 of the latch circuit 40 becomes a low level, the forced-off transistor 42 is turned off, and the error voltage Verr is released from the fixed state of 0V. Thereafter, when Verr <Vosc at time T5, the PWM signal Vpwm becomes high level, and the driver circuit 10 sets the first gate voltage Vg1 to low level and turns on the switching transistor M1.

Thus, the control circuit 100 according to the present embodiment monitors the monitoring voltage ΔV that is the voltage across the switching transistor M1. Since the monitoring voltage ΔV is proportional to the current flowing through the switching transistor M1, an overcurrent state can be detected by comparing with the threshold voltage Vth. At this time, if ΔV> Vth and an overcurrent state is detected, the switching transistor M1 is forcibly turned off and the current supply path is cut off, so that the switching transistor M1 itself, the inductor L1 or the load RL is suitably protected. can do.
Further, the forced off state of the switching transistor M1 in the overcurrent state is canceled for each cycle by the periodic voltage Vosc output from the oscillator 26. For this reason, even when the load is short-circuited momentarily and a large current flows, overcurrent detection and overcurrent protection are performed every cycle. Can return.

(Second Embodiment)
FIG. 4 is a circuit diagram showing a configuration of the control circuit 100 according to the second embodiment. In the subsequent drawings, the same or equivalent components as those already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
In the first embodiment described above, the voltage across the switching transistor M1 is directly monitored as the monitoring voltage ΔV. However, in the second embodiment, the detection transistor M3 and the detection resistor R3 are used in parallel with the switching transistor M1. A path to be formed is provided, and a current flowing through this path is monitored.

The comparison unit 30 includes a detection resistor R3 and a detection transistor M3 in addition to the second comparator 32 and the voltage source 34. A detection transistor M3 and a detection resistor R3 are connected in series between the drain and source of the switching transistor M1. The detection transistor M3 is a PNP-type MOS transistor like the switching transistor M1, and has a drain and a gate commonly connected to the switching transistor M1. The transistor size of the detection transistor M3 is set smaller than that of the switching transistor M1, and the on-resistance Ron3 of the detection transistor M3 is set sufficiently higher than the on-resistance Ron1 of the switching transistor M1. The resistance value of the detection resistor R3 is set sufficiently higher than the on-resistance Ron3 of the detection transistor M3. That is, the impedance of the path including the detection transistor M3 and the detection resistor R3 is set sufficiently higher than the impedance of the switching transistor M1, and Ron3 + R3 >> Ron1 is established.
The second comparator 32 indirectly monitors the voltage ΔV ′ across the switching transistor M1 by monitoring the voltage across the detection resistor R3 as the monitoring voltage ΔV ′, and detects an overcurrent state.

  The operation of the control circuit 100 configured as described above will be described. If the current flowing through the switching transistor M1 is Im1, and the current flowing through the detection transistor M3 is Im3, then Im1 >> Im3 because of the impedance relationship of the two paths described above. The voltage ΔV across the switching transistor M1 is given by Im1 × Ron1, and this voltage is applied to the detection resistor R3 and the detection transistor M3. Therefore, the voltage across the detection resistor R3, that is, the monitoring voltage ΔV ′ is ΔV ′ = Im1 × Ron1 × R3 / (R3 + Ron3). That is, the monitoring voltage ΔV ′ is proportional to the current Im1 flowing through the switching transistor M1.

When the load RL is short-circuited and an overcurrent flows through the switching transistor M1, the voltage ΔV across the switching transistor M1 increases, and accordingly, the voltage ΔV ′ across the detection resistor R3 increases. When the monitoring voltage ΔV ′ exceeds the threshold voltage Vth, the comparison signal Vcmp output from the second comparator 32 becomes high level, the latch circuit 40 is set, and the first gate voltage Vg1 output from the driver circuit 10 is set. Becomes high level, and the switching transistor M1 and the detection transistor M3 are forcibly turned off.
Thus, in the control circuit 100 according to the present embodiment, by monitoring the voltage ΔV ′ across the detection resistor R3, it is possible to indirectly monitor the voltage ΔV across the switching transistor M1, thereby overcurrent. The circuit can be protected by detecting the state.

The control circuit 100 according to the present embodiment further has the following advantages.
FIG. 5 is a diagram showing a circuit state when the control circuit 100 according to the present embodiment is inspected. In FIG. 5, a part of the circuit diagram of FIG. 4 is simplified or omitted. This check is performed to determine whether overcurrent protection functions effectively at a predetermined threshold current.
A first switch SW1 and a third switch SW3 are provided between the gates of the switching transistor M1 and the detection transistor M3 and the driver circuit 10, respectively. The first switch SW1 and the third switch SW3 are provided for independently controlling the on / off states of the switching transistor M1 and the detection transistor M3.
At the time of inspection, the constant current source 400 is connected to the switching terminal 104. A test voltage Vtest is applied to the input terminal 102. The test voltage Vtest is set to a value close to the battery voltage Vbat.

Hereinafter, the operation at the time of inspection of the control circuit 100 will be described. At the time of inspection, the gate voltage of the switching transistor M1 is fixed to a high level by the first switch SW1 and is turned off. In addition, the gate voltage of the detection transistor M3 is fixed at a low level and is turned on. In this state, a constant current Itest is generated by the constant current source 400 connected to the switching terminal 104. Since the switching transistor M1 is turned off, the constant current Itest flows through the detection transistor M3 and the detection resistor R3.
At the time of inspection, the voltage across the detection resistor R3, that is, the monitoring voltage ΔV ′ is Itest × R3. Therefore, when Itest> Vth / R3, if the output of the second comparator 32 becomes high level, it can be confirmed that the overcurrent protection is operating normally. In order to monitor the output of the second comparator 32, the control circuit 100 may include a test circuit 50 as shown in FIG.

As described above, since R3 + Ron3 >> Ron1, when the step-down switching regulator 200 of FIG. 3 is configured by the control circuit 100 according to the present embodiment, the path including the detection resistor R3 and the detection transistor M3 in the step-down operation state. The current Im3 flowing through the switching transistor M1 is much smaller than the current Im1 flowing through the switching transistor M1. Therefore, when determining whether or not the overcurrent protection functions normally at the time of inspection, the current Itest to be generated by the constant current source 400 is set to be very small compared to the current that actually flows through the switching transistor M1. be able to.
If an overcurrent state is detected without providing the detection resistor R3 and the detection transistor M3, it is necessary to pass a current close to 1 A to the switching transistor M1 during the overcurrent protection test. It is not realistic to supply such a large current. On the other hand, in the control circuit 100 according to the present embodiment, at the time of inspection, if a current Itest of only a few mA is caused to flow by the constant current source 400, the state of actual operation by the detection transistor M3 and the detection resistor R3 is changed. It can be reproduced, and it can be determined whether overcurrent detection is normally performed.

Further, when the first switch SW1 and the third switch SW3 are not provided, the switching transistor M1 and the detection transistor M3 cannot be turned on and off independently. Therefore, when the switching transistor M1 is turned off at the time of inspection, the detection transistor M3 is also turned off. . In this case, in order to pass the constant current Itest only to the detection resistor R3, it is necessary to provide a test pad at the connection point between the detection resistor R3 and the detection transistor M3, and to connect the constant current source 400 to the test pad. The circuit area becomes large.
On the other hand, in the control circuit 100 according to the present embodiment, at the time of inspection, the constant current source 400 is used to turn on the detection transistor M3 while turning off the switching transistor M1 using the first switch SW1 and the third switch SW3. The switching terminal 104 can be used as it is as a test pad to be connected, and an increase in circuit area can be suppressed.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the error voltage Verr is controlled to forcibly turn off the switching transistor M1 when an overcurrent state is detected. However, the present invention is not limited to this. For example, the output signal SIG1 of the latch circuit 40 is input to the driver circuit 10, and the output signal SIG1 and the PWM signal Vpwm are logically operated inside the driver circuit 10, thereby controlling the first gate voltage Vg1 and the switching transistor. M1 may be forcibly turned off.

  In the embodiment, the case where the control circuit 100 is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are provided as discrete elements or chip components outside the LSI. Or you may comprise by several LSI. What part and how much to integrate can be determined by cost, occupied area, and the like.

  Further, in the present embodiment, the setting of high level and low level logical values is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.

It is a block diagram which shows the structure of the electronic device carrying the pressure | voltage fall type switching regulator which concerns on 1st Embodiment. 1 is a circuit diagram showing a configuration of a step-down switching regulator according to a first embodiment. It is a time chart which shows the operation state of the control circuit of FIG. It is a circuit diagram which shows the structure of the control circuit which concerns on 2nd Embodiment. It is a figure which shows the circuit state at the time of the test | inspection of the control circuit of FIG.

Explanation of symbols

  100 control circuit, 102 input terminal, 104 switching terminal, 106 voltage feedback terminal, 110 switching regulator output circuit, 200 step-down switching regulator, 10 driver circuit, 20 PWM control unit, 26 oscillator, 30 comparison unit, 40 latch circuit, L1 Inductor, Vg1 first gate voltage, Vg2 second gate voltage, M1 switching transistor, M2 synchronous rectification transistor, M3 detection transistor, R3 detection resistor, SW1 first switch, SW3 third switch, 300 electronic device, 310 battery.

Claims (10)

A step-down switching regulator control circuit,
An output stage including a switching transistor and a synchronous rectifying transistor connected in series between the input terminal and the ground, and outputting a voltage at a connection point of the two transistors as a switching voltage to the switching regulator output circuit;
Based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator output circuit approaches a predetermined reference voltage, the first to be applied to the gates of the switching transistor and the synchronous rectification transistor, A driver circuit for generating a second gate voltage;
A comparison unit that compares a voltage across the switching transistor with a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the voltage across the switching transistor exceeds the threshold voltage , A detection transistor and a detection resistor connected in series so as to form a path parallel to the switching transistor between a drain and a source of the switching transistor, and a voltage across the detection resistor And a voltage comparator that compares the threshold voltage, and a comparator that outputs the output of the voltage comparator as the comparison signal ;
A latch circuit that latches and outputs a comparison signal output from the comparison unit;
A protection circuit for forcibly turning off the switching transistor during a period in which the comparison signal is latched at the predetermined level in the latch circuit;
A switch circuit capable of independently controlling on / off of the switching transistor and the detection transistor;
A control circuit comprising: The control circuit of claim 1 wherein the on resistance of the sensing transistor, characterized in that it is set higher than the on-resistance of the switching transistor. Wherein the resistance value of the sense resistor, the control circuit according to claim 1 or 2, characterized in that it is set higher than the on-resistance of the detection transistor.   The control circuit according to claim 1, wherein the latch circuit is reset for each period of the pulse width modulation signal. The latch circuit is
3. The control circuit according to claim 1, further comprising a flip-flop that is set by a comparison signal output from the comparison unit and reset by an output signal of an oscillator used to generate the pulse width modulation signal. . When the voltage across the switching transistor exceeds the threshold voltage, the switch circuit turns off the switching transistor to check whether the comparison signal output from the comparison unit is at the predetermined level. While turning on the detection transistor,
The control circuit according to claim 1 , wherein the switching transistor and the detection transistor are switched based on the first gate voltage by the switch circuit during a normal operation in which a step-down operation is performed. The protection circuit includes a control circuit according to any one of claims 1 to 6, characterized by turning off the switching transistor by changing the logical value of the pulse width modulation signal. Wherein the control circuit, the control circuit according to claim 1, wherein 7 to be integrated on a single semiconductor substrate. A capacitor with one end grounded;
An inductor having one end connected to the other end of the capacitor;
The control circuit according to any one of claims 1 to 8 , wherein a switching voltage is supplied to the other end of the inductor;
And a voltage at the other end of the capacitor is output. Battery,
The step-down switching regulator according to claim 9 , wherein the voltage of the battery is stepped down and output.
An electronic device comprising:

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