US20180315863A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US20180315863A1
US20180315863A1 US15/766,114 US201615766114A US2018315863A1 US 20180315863 A1 US20180315863 A1 US 20180315863A1 US 201615766114 A US201615766114 A US 201615766114A US 2018315863 A1 US2018315863 A1 US 2018315863A1
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type cathode
cathode layer
semiconductor device
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US10355142B2 (en
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Fumihito MASUOKA
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a semiconductor device.
  • V F -E REC trade-off characteristics vary largely depending on the irradiation angle with the irradiated object, the temperature or the like during the electron/ion beam irradiation.
  • problems such as fluctuations in electrical characteristics caused by changes in the lattice defects due to self-heating during powered chip operation, and thermal runaway during high-temperature operation caused by a large leak current due to the lattice defects.
  • the present invention was made to solve the problem described above and it is an object of the invention to obtain a semiconductor device capable of adjusting the V F -E REC trade-off characteristics without relying on lifetime control.
  • a semiconductor device includes: a drift layer; first and second p-type anode layers provided side by side on the drift layer; n-type cathode layer and p-type cathode layer provided side by side below the drift layer; and an n-type buffer layer provided between the drift layer and the n-type cathode layer and between the drift layer and the p-type cathode layer, wherein the first p-type anode layer has a greater diffusion depth than a diffusion depth of the second p-type anode layer, the first p-type anode layer has a greater impurity concentration than an impurity concentration of the second p-type anode layer, the n-type cathode layer has a greater diffusion depth than a diffusion depth of the p-type cathode layer, and the n-type cathode layer has a greater impurity concentration than an impurity concentration of the p-type cathode layer.
  • the first p-type anode layer has a greater diffusion depth than a diffusion depth of the second p-type anode layer
  • the first p-type anode layer has a greater impurity concentration than an impurity concentration of the second p-type anode layer
  • the n-type cathode layer has a greater diffusion depth than a diffusion depth of the p-type cathode layer
  • the n-type cathode layer has a greater impurity concentration than an impurity concentration of the p-type cathode layer. Therefore, the V F -E REC trade-off characteristics can be adjusted over a wide range without having to rely on the lifetime control.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view illustrating a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 3 is a cross-sectional view illustrating a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • First and second p-type anode layers 2 and 3 are formed side by side on an n ⁇ -type drift layer 1 .
  • An anode electrode 4 is connected in ohmic contact with the first and second p-type anode layers 2 and 3 .
  • N-type cathode layers 5 and p-type cathode layers 6 are formed side by side below the n ⁇ -type drift layer 1 .
  • An n-type buffer layer 7 is formed between the n ⁇ -type drift layer 1 and the n-type cathode layers 5 and between the n ⁇ -type drift layer 1 and p-type cathode layers 6 .
  • a cathode electrode 8 is connected in ohmic contact with the n-type cathode layers 5 and p-type cathode layers 6 .
  • the n-type cathode layers 5 and p-type cathode layers 6 are short-circuited via the cathode electrode 8 .
  • the first p-type anode layers 2 have a greater diffusion depth xp 2 than the diffusion depth xp 3 of the second p-type anode layers 3 (xp 2 >xp 3 ).
  • the first p-type anode layers 2 have a greater impurity concentration cp 2 than the impurity concentration cp 3 of the second p-type anode layers 3 (cp 2 >cp 3 ).
  • the n-type cathode layers 5 have a greater diffusion depth xn 2 than the diffusion depth xp 1 of the p-type cathode layers 6 (xn 2 >xp 1 ).
  • the n-type cathode layers 5 have a greater impurity concentration cn 2 than the impurity concentration cp 1 of the p-type cathode layers 6 (cn 2 >cp 1 ).
  • the backside p/n pitch which is the pitch of one cycle made by the n-type cathode layer 5 and p-type cathode layer 6 .
  • V F increases
  • E REC decreases.
  • the V F -E REC trade-off curve shifts to the high-speed side. Therefore, as a free-wheeling diode to he integrated in inverters adopted to various purposes, it is desirable that the V F -E REC trade-off characteristics be adjustable by changing the backside p/n pitch.
  • the backside p/n pitch is designed too small, the snap-off tolerance will decrease. Conversely, if the pitch is designed too large, the recovery tolerance will he lowered.
  • the settings of the diffusion depth and impurity concentration of this embodiment allow such a trade-off to be avoided.
  • the backside p/n short-circuit ratio which is the ratio of the p-type cathode layers 6 relative to the backside p/n pitch
  • V F increases
  • E REC decreases.
  • the V F -E REC trade-off curve shifts to the high-speed side, Therefore, as a free-wheeling diode to be integrated in inverters adopted to various purposes, it is desirable that the V F -E REC trade-off characteristics be adjustable by changing the backside p/n short-circuit ratio.
  • the backside p/n short-circuit ratio is designed too small, the snap-off tolerance will decrease while the cross point will increase. Conversely, if the ratio is designed too large, the recovery tolerance will be lowered.
  • the anode structure design of this embodiment allows such a trade-off to be avoided.
  • V F concentration of the p-type anode layers
  • E REC decreases. Namely, the V F -E REC trade-off curve shifts to the high-speed side.
  • the carrier concentration on the ON-state anode side will decrease so that Irr of the recovery waveform is reduced, which relatively enhances the carrier concentration on the cathode side, whereby the snap-off tolerance can be improved.
  • the concentration of the p-type anode layers is reduced too much, the breakdown voltage will be lowered.
  • the anode structure design of this embodiment allows such a trade-off to be avoided.
  • the V F -E REC trade-off characteristics can be adjusted over a wide range without having to rely on the conventional lifetime control.
  • the snap-off which is a voltage surge toward the end of the turn-off operation, and oscillation triggered by the snap-off can be prevented.
  • cutoff performance such as controllable current density and tolerable cutoff speed during the turn-off operation can be improved.
  • FIG. 2 is a cross-sectional view illustrating a semiconductor device according to Embodiment 2 of the present invention.
  • the first p-type anode layers 2 have a smaller pitch than that of the n-type cathode layers 5 .
  • the maximum cutoff current density at recovery is lowered in diodes having a vertically parasitic bipolar transistor structure as compared to diodes without such a structure.
  • the pitch of the first p-type anode layers 2 as in this embodiment, the operation of the vertically parasitic bipolar transistor is inhibited, so that the maximum controllable current density at recovery can he prevented from decreasing. Similar effects as those of Embodiment 1 can also be achieved.
  • FIG. 3 is a cross-sectional view illustrating a semiconductor device according to Embodiment 3 of the present invention.
  • the first p-type anode layers 2 a above the n-type cathode layers 5 have a smaller pitch than that of the first p-type anode layers 2 b above the p-type cathode layers 6 . This inhibits the operation of the vertically parasitic bipolar transistor, so that the maximum controllable current density at recovery can be prevented from decreasing. Similar effects as those of Embodiment 1 can also be achieved.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor device according to Embodiment 4 of the present invention.
  • the pitch of one cycle made by the first p-type anode layer 2 and second p-type anode layer 3 is smaller than the pitch of one cycle made by the n-type cathode layer 5 and p-type cathode layer 6 .
  • Embodiments 1 to 4 have, been described with respect to a diode that forms a high-breakdown-voltage power module ( ⁇ 600 V) as one example, the present invention can be applied also to a range of diodes such as RC-IGBTs regardless of breakdown voltage class and semiconductor material, with the effects described above.
  • the semiconductor device is not limited to a device formed of silicon, but instead may he formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon.
  • the wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond.
  • a power semiconductor device formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized, The use of such a miniaturized semiconductor device enables the miniaturization and high integration of the semiconductor module in which the semiconductor device is incorporated.
  • the semiconductor device since the semiconductor device has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor module. Further, since the semiconductor device has a low power loss and a high efficiency, a highly efficient semiconductor module can be achieved.

Abstract

First and second p-type anode layers (2,3) are provided side by side on a drift layer (1). N-type cathode layer (5) and p-type cathode layer (6) are provided side by side below the drift layer (1). An n-type buffer layer (7) is provided between the drift layer (1) and the n-type cathode layer (5) and between the drift layer (1) and the p-type cathode layer (6). The first p-type anode layer (2,2 a, 2 b) has a greater diffusion depth than a diffusion depth of the second p-type anode layer (3). The first p-type anode layer (2,2 a, 2 b) has a greater impurity concentration than an impurity concentration of the second p-type anode layer (3). The n-type cathode layer (5) has a greater diffusion depth than a diffusion depth of the p-type cathode layer (6). The n-type cathode layer (5) has a greater impurity concentration than an impurity concentration of the p-type cathode layer (6).

Description

    FIELD
  • The present invention relates to a semiconductor device.
    • BACKGROUND
  • Semiconductor diodes have been developed in recent years (see, for example, PTL 1), Conventionally, as a method of controlling the VF-EREC trade-off characteristics of semiconductor diodes, lifetime control that uses heavy metal diffusion or electron/ion beam irradiation techniques has been adopted.
    • CITATION LIST Patent Literature
  • [PTL1] Japanese Patent Application Laid-open No. H02-86173
    • SUMMARY Technical Problem
  • With lifetime control, however, the VF-EREC trade-off characteristics vary largely depending on the irradiation angle with the irradiated object, the temperature or the like during the electron/ion beam irradiation. There were also other problems, such as fluctuations in electrical characteristics caused by changes in the lattice defects due to self-heating during powered chip operation, and thermal runaway during high-temperature operation caused by a large leak current due to the lattice defects.
  • The present invention was made to solve the problem described above and it is an object of the invention to obtain a semiconductor device capable of adjusting the VF-EREC trade-off characteristics without relying on lifetime control.
    • Solution to Problem
  • A semiconductor device according to the present invention includes: a drift layer; first and second p-type anode layers provided side by side on the drift layer; n-type cathode layer and p-type cathode layer provided side by side below the drift layer; and an n-type buffer layer provided between the drift layer and the n-type cathode layer and between the drift layer and the p-type cathode layer, wherein the first p-type anode layer has a greater diffusion depth than a diffusion depth of the second p-type anode layer, the first p-type anode layer has a greater impurity concentration than an impurity concentration of the second p-type anode layer, the n-type cathode layer has a greater diffusion depth than a diffusion depth of the p-type cathode layer, and the n-type cathode layer has a greater impurity concentration than an impurity concentration of the p-type cathode layer.
    • Advantageous Effects of Invention
  • In the present invention, the first p-type anode layer has a greater diffusion depth than a diffusion depth of the second p-type anode layer, the first p-type anode layer has a greater impurity concentration than an impurity concentration of the second p-type anode layer, the n-type cathode layer has a greater diffusion depth than a diffusion depth of the p-type cathode layer, and the n-type cathode layer has a greater impurity concentration than an impurity concentration of the p-type cathode layer. Therefore, the VF-EREC trade-off characteristics can be adjusted over a wide range without having to rely on the lifetime control.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view illustrating a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 3 is a cross-sectional view illustrating a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor device according to Embodiment 4 of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • A semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may he omitted.
    • Embodiment 1
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. First and second p- type anode layers 2 and 3 are formed side by side on an n−-type drift layer 1. An anode electrode 4 is connected in ohmic contact with the first and second p- type anode layers 2 and 3.
  • N-type cathode layers 5 and p-type cathode layers 6 are formed side by side below the n−-type drift layer 1. An n-type buffer layer 7 is formed between the n−-type drift layer 1 and the n-type cathode layers 5 and between the n−-type drift layer 1 and p-type cathode layers 6. A cathode electrode 8 is connected in ohmic contact with the n-type cathode layers 5 and p-type cathode layers 6. The n-type cathode layers 5 and p-type cathode layers 6 are short-circuited via the cathode electrode 8.
  • In this embodiment, the first p-type anode layers 2 have a greater diffusion depth xp2 than the diffusion depth xp3 of the second p-type anode layers 3 (xp2>xp3). The first p-type anode layers 2 have a greater impurity concentration cp2 than the impurity concentration cp3 of the second p-type anode layers 3 (cp2>cp3). The n-type cathode layers 5 have a greater diffusion depth xn2 than the diffusion depth xp1 of the p-type cathode layers 6 (xn2>xp1). The n-type cathode layers 5 have a greater impurity concentration cn2 than the impurity concentration cp1 of the p-type cathode layers 6 (cn2>cp1).
  • If the backside p/n pitch, which is the pitch of one cycle made by the n-type cathode layer 5 and p-type cathode layer 6, is made smaller, VF increases, while EREC decreases. Namely, the VF-EREC trade-off curve shifts to the high-speed side. Therefore, as a free-wheeling diode to he integrated in inverters adopted to various purposes, it is desirable that the VF-EREC trade-off characteristics be adjustable by changing the backside p/n pitch. However, if the backside p/n pitch is designed too small, the snap-off tolerance will decrease. Conversely, if the pitch is designed too large, the recovery tolerance will he lowered. The settings of the diffusion depth and impurity concentration of this embodiment allow such a trade-off to be avoided.
  • If the backside p/n short-circuit ratio, which is the ratio of the p-type cathode layers 6 relative to the backside p/n pitch, is made smaller, VF increases, while EREC decreases. Namely, the VF-EREC trade-off curve shifts to the high-speed side, Therefore, as a free-wheeling diode to be integrated in inverters adopted to various purposes, it is desirable that the VF-EREC trade-off characteristics be adjustable by changing the backside p/n short-circuit ratio. However, if the backside p/n short-circuit ratio is designed too small, the snap-off tolerance will decrease while the cross point will increase. Conversely, if the ratio is designed too large, the recovery tolerance will be lowered. The anode structure design of this embodiment allows such a trade-off to be avoided.
  • If the concentration of the p-type anode layers is reduced, VF increases, while EREC decreases. Namely, the VF-EREC trade-off curve shifts to the high-speed side. As a side effect, the carrier concentration on the ON-state anode side will decrease so that Irr of the recovery waveform is reduced, which relatively enhances the carrier concentration on the cathode side, whereby the snap-off tolerance can be improved. On the other hand, if the concentration of the p-type anode layers is reduced too much, the breakdown voltage will be lowered. The anode structure design of this embodiment allows such a trade-off to be avoided.
  • By setting the diffusion depth and impurity concentration as in this embodiment, the VF-EREC trade-off characteristics can be adjusted over a wide range without having to rely on the conventional lifetime control. Thus the snap-off, which is a voltage surge toward the end of the turn-off operation, and oscillation triggered by the snap-off can be prevented. This way, cutoff performance such as controllable current density and tolerable cutoff speed during the turn-off operation can be improved.
    • Embodiment 2
  • FIG. 2 is a cross-sectional view illustrating a semiconductor device according to Embodiment 2 of the present invention. The first p-type anode layers 2 have a smaller pitch than that of the n-type cathode layers 5.
  • The maximum cutoff current density at recovery is lowered in diodes having a vertically parasitic bipolar transistor structure as compared to diodes without such a structure. By setting the pitch of the first p-type anode layers 2 as in this embodiment, the operation of the vertically parasitic bipolar transistor is inhibited, so that the maximum controllable current density at recovery can he prevented from decreasing. Similar effects as those of Embodiment 1 can also be achieved.
    • Embodiment 3
  • FIG. 3 is a cross-sectional view illustrating a semiconductor device according to Embodiment 3 of the present invention. The first p-type anode layers 2 a above the n-type cathode layers 5 have a smaller pitch than that of the first p-type anode layers 2 b above the p-type cathode layers 6. This inhibits the operation of the vertically parasitic bipolar transistor, so that the maximum controllable current density at recovery can be prevented from decreasing. Similar effects as those of Embodiment 1 can also be achieved.
    • Embodiment 4
  • FIG. 4 is a cross-sectional view illustrating a semiconductor device according to Embodiment 4 of the present invention. The pitch of one cycle made by the first p-type anode layer 2 and second p-type anode layer 3 is smaller than the pitch of one cycle made by the n-type cathode layer 5 and p-type cathode layer 6. This inhibits the operation of the vertically parasitic bipolar transistor, so that the maximum controllable current density at recovery can be prevented from decreasing. Similar effects as those of Embodiment 1 can also be achieved.
  • While Embodiments 1 to 4 have, been described with respect to a diode that forms a high-breakdown-voltage power module (≥600 V) as one example, the present invention can be applied also to a range of diodes such as RC-IGBTs regardless of breakdown voltage class and semiconductor material, with the effects described above.
  • The semiconductor device is not limited to a device formed of silicon, but instead may he formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A power semiconductor device formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized, The use of such a miniaturized semiconductor device enables the miniaturization and high integration of the semiconductor module in which the semiconductor device is incorporated. Further, since the semiconductor device has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor module. Further, since the semiconductor device has a low power loss and a high efficiency, a highly efficient semiconductor module can be achieved.
    • REFERENCE SIGNS LIST
  • 1 n−-type drift layer; 2,2 a,2 b first p-type anode layer; 3 second p-type anode layer; 5 n-type cathode layer; 6 p-type cathode layer; 7 n-type buffer layer

Claims (4)

1. A semiconductor device comprising:
a drift layer;
first and second p-type anode layers provided side by side on the drift layer;
n-type cathode layer and p-type cathode layer provided side by side below the drift layer; and
an n-type buffer layer provided between the drift layer and the n-type cathode layer and between the drift layer and the p-type cathode layer,
wherein the first p-type anode layer has a greater diffusion depth than a diffusion depth of the second p-type anode layer,
the first p-type anode layer has a greater impurity concentration than an impurity concentration of the second p-type anode layer,
the n-type cathode layer has a greater diffusion depth than a diffusion depth of the p-type cathode layer, and
the n-type cathode layer has a greater impurity concentration than an impurity concentration of the p-type cathode layer.
2. The semiconductor device according to claim 1, wherein the first p-type anode layer has a smaller pitch than a pitch of the n-type cathode layer.
3. The semiconductor device according to claim 1, wherein the first p-type anode layer above the n-type cathode layer has a smaller pitch than a pitch of the first p-type anode layer above the p-type cathode layer.
4. The semiconductor device according to claim 1, wherein a pitch of one cycle made by the first p-type anode layer and the second p-type anode layer is smaller than a pitch of one cycle made by the n-type cathode layer and the p-type cathode layer.
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