US20180164351A1 - Power Supply Glitch Detector - Google Patents
Power Supply Glitch Detector Download PDFInfo
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- US20180164351A1 US20180164351A1 US15/831,287 US201715831287A US2018164351A1 US 20180164351 A1 US20180164351 A1 US 20180164351A1 US 201715831287 A US201715831287 A US 201715831287A US 2018164351 A1 US2018164351 A1 US 2018164351A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
- G01R19/16547—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies voltage or current in AC supplies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0276—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being rise time
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17768—Structural details of configuration resources for security
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
Definitions
- the present invention relates to electronic circuits. More particularly, the present invention relates to detection circuits and to power supply glitch detector circuits that detect any kind of positive or negative voltage glitch on a power supply and provide signals as outputs in response to these glitches.
- Sensitive information in electronic devices is usually protected using various encryption methods. Even though encryption protects the primary channels of the device from hackers, several secondary channels are still prone to attacks.
- Typical side channel attacks are aimed to gain information from the device by targeting these secondary channels of the device like the hardware, timing information, electromagnetic radiation, without limitation.
- Typical side channel attacks can include: attacking the cache implemented by monitoring the cache; timing attacks implemented by measuring the computation timing of different tasks; power monitoring attacks implemented by measuring the varying nature of device power consumption; electromagnetic attacks implemented by measuring electromagnetic radiation leaked from the device; fault injection attacks implemented by placing the device in abnormal conditions such as abruptly raising or lowering power supply voltage: and/or tampering with the clock, device temperature, without limitation.
- a power supply glitch detector is a circuit that detects any kind of voltage glitch on the supply.
- One embodiment of a circuit in accordance with the present invention detects both positive and negative voltage glitches on the supply and provides active high or low signals as outputs in response to detection of any of these glitches.
- a glitch detector includes a glitch coupling circuit, a bias generating circuit, a glitch detection circuit in the form of a comparator coupled to the bias generating circuit and the glitch coupling circuit, and a pulse stretching circuit.
- the glitch detector may include two detector cores: one for positive glitch detection and the other for negative glitch detection.
- the magnitude of the supply glitch that needs to be detected and responded to by the circuit can be configured by applying different control settings.
- FIGS. 1A and 1B are graphs of voltage vs. time that represent power supply waveforms including, respectively, idealized representations of positive and negative glitch pulses;
- FIG. 2 is a block diagram showing a glitch detector in accordance with one aspect of the present invention.
- FIG. 3 is a schematic diagram showing an illustrative circuit implementation of the glitch detector of FIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a positive-going glitch;
- FIG. 4 is a schematic diagram showing an illustrative circuit implementation of the glitch detector of FIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a negative-going glitch;
- FIG. 5 is a schematic diagram of an exemplary circuit that can be used to implement the RC filter of the circuits shown in FIGS. 3 and 4 ;
- FIG. 6 is a schematic diagram of an exemplary circuit that can be used to implement the pulse stretching inverter of the circuits shown in FIGS. 3 and 4 .
- FIGS. 1A and 1B are graphs of voltage vs. time that represent power supply waveforms including, respectively, idealized representations of positive and negative glitch pulses.
- the waveforms have nominal steady-state values.
- an illustrative positive-going glitch is indicated at reference numeral 10 and has rise/fall times of 100 ps and a duration of 2 ns.
- an illustrative negative-going glitch is indicated at reference numeral 12 and has rise/fall times of 100 ps and a duration of 2 ns.
- Persons of ordinary skill in the art will appreciate that these waveforms are illustrative only and the present invention is not limited to detection of glitches having the exact characteristics that are shown in FIGS. 1A and 1B .
- FIG. 2 is a block diagram showing a glitch detector 20 in accordance with the present invention.
- Glitch detector 20 includes a glitch coupling circuit 22 coupled to a power supply line 24 on which glitches are to be detected.
- the glitch is coupled from the output of the glitch coupling circuit 22 to the input of detection circuit 26 , which can be an inverter biased at a voltage level V bias using bias generator circuit 28 .
- the detection circuit 26 outputs a pulse having the approximate duration of the input glitch pulse that is stretched using pulse stretcher circuit 30 .
- the output of pulse stretcher circuit 30 at line 32 is the output of the glitch detector circuit 20 .
- This output may be used to raise a flag that will drive one or more circuits to allow the system to take an appropriate action (generate an interrupt, reset or other action without limitation) for the device so as to prevent the hacker from extracting/monitoring the characteristics of the power supply or injecting any fault, thus preventing side channel attacks.
- the glitch detector 20 may be configured to detect positive glitches, negative glitches, or both positive and negative glitches.
- Glitch coupling circuit 22 is coupled between the voltage supply voltage line 24 , also known as power supply node 24 and the input of the detection circuit 26 , which input is called a sensing node.
- the glitch coupling circuit 22 transfers any voltage glitch occurring on the voltage supply line 24 to the sensing node at the input of the detection circuit 26 .
- the output is at a first logic state (e.g., logic 1 also referred to as high logic state), indicative that no glitch has been detected. If the input voltage level is above the trip-point V trip of the detection circuit 26 , the output transitions to a second logic state opposite the first logic state (e.g., logic 0 also referred to as low logic state), indicative that a glitch has been detected.
- a first logic state e.g., logic 1 also referred to as high logic state
- the output transitions to a second logic state opposite the first logic state (e.g., logic 0 also referred to as low logic state), indicative that a glitch has been detected.
- the input of the glitch detection circuit 26 is biased by bias generator circuit 28 to a voltage level of V bias where it remains under steady-state conditions.
- V bias is set to be lower than V trip by a certain preset known voltage ( ⁇ V).
- ⁇ V a certain preset known voltage
- a glitch occurring on the voltage supply line 24 will be coupled to the input of the glitch detection circuit 26 . If the glitch raises the input voltage of the glitch detection circuit 26 by more than the preset voltage ⁇ V, then V bias +V glitch >V trip and it will cause the detection circuit 26 to trip and its output transitions from the first logic state to the second logic state (e.g., logic 0).
- V bias +V glitch >V trip and it will cause the detection circuit 26 to trip and its output transitions from the first logic state to the second logic state (e.g., logic 0).
- the input voltage to the detection circuit 26 returns to its quiescent value V bias . Since now V bias ⁇ V trip , the output of the detection circuit 26 returns to the first logic state. In this process the output of the detection circuit generates a short pulse (e.g., going from logic 1 ⁇ 0 ⁇ 1). This pulse can be stretched using a pulse stretching circuit 30 to generate the output of the glitch detector 20 .
- the trip-point V trip of the detection circuit 26 is set to be below the steady-state voltage level to the input of the glitch detection circuit 26 .
- the output of the detection circuit 26 is at a first logic level (e.g., logic 0), indicative that no glitch has been detected. If the input voltage level to the glitch detection circuit 26 drops below the trip-point V trip of the detection circuit 26 , the output of the glitch detection circuit 26 transitions to the second logic state (e.g., logic 1), indicative that a glitch has been detected.
- the input of the glitch detection circuit 26 is biased by bias generator circuit 28 to a voltage level of V bias under steady-state conditions.
- V bias is set to be higher than V trip by a certain preset known voltage ( ⁇ V). Under the steady-state condition the output of the detection circuit 26 is at the first logic level.
- a glitch will be coupled to the input of the glitch detection circuit 26 . If the glitch lowers the input voltage of the glitch detection circuit 26 by more than the preset voltage ⁇ V, then V bias ⁇ V glitch ⁇ V trip and it will cause the output of the detection circuit 26 to transition from the first logic state to the second logic state.
- the input voltage to the detection circuit 26 returns to V bias . Since now V bias >V trip , the output of the detection circuit 26 returns to the first logic state. In this process the output of the detection circuit generates a short pulse (e.g., going from logic 0 ⁇ 1 ⁇ 0). This pulse can be stretched using a pulse stretching circuit 30 to generate the output of the glitch detector 20 .
- FIG. 3 a schematic diagram shows an illustrative circuit implementation of the glitch detector of FIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a positive-going glitch.
- the detection circuit 40 shown in FIG. 3 monitors the voltage on V supply line 42 .
- a first capacitor 44 is coupled between the V supply line 42 and the input of sensing inverter 46 .
- a second capacitor 48 is coupled between the input of sensing inverter 46 and ground.
- Capacitors 44 and 48 act as a voltage divider for the glitch pulse, with capacitor 44 also acting to block the DC voltage present on V supply line 42 .
- the capacitance ratio of capacitors 44 and 48 is variable and is dependent on the level of the power supply.
- a adjustable voltage biasing circuit (shown within dashed lines 50 ) is used to bias the input of the detection circuit to a voltage level V bias to a predetermined level below V trip in steady state, with a steady state difference of ⁇ V.
- the adjustable voltage biasing circuit 50 employs an inverter 52 having its input connected to its output. This connection sets the output of inverter 52 at its trip point V trip .
- Inverter 52 is matched to sensing inverter 46 so that both inverters 46 and 52 have the same trip point voltage V trip .
- the trip point of the inverter 52 is set to be the same as the trip point of the sensing inverter 46 in order to allow the bias circuit 50 to set the bias of the sensing inverter 46 accordingly.
- a series string of resistors R 1 , R 2 , R 3 , R 4 , R 5 , and R 6 are coupled between the output of inverter 52 and an n-channel current bias transistor 66 .
- N-channel current bias transistor 66 has its gate set at a voltage to cause a constant current bias to flow through the series string of resistors.
- a first bias transistor 68 is coupled between the common connection of resistors R 3 and R 4 and the input of sensing inverter 46 . Its gate is coupled to a control signal thresh_ctrl _ 1 .
- a second bias transistor 70 is coupled between the common connection of resistors R 4 and R 5 and the input of sensing inverter 46 . Its gate is coupled to a control signal thresh_ctrl_ 2 .
- a third bias transistor 72 is coupled between the common connection of resistors R 5 and R 6 and the input of sensing inverter 46 . Its gate is coupled to a control signal thresh_ctrl_ 3 .
- a fourth bias transistor 74 is coupled between the common connection of resistor R 6 and the drain of current bias transistor 66 and the input of sensing inverter 46 . Its gate is coupled to a control signal thresh_ctrl_ 4 .
- R 1 through R 3 are formed separately to keep the unit resistor value the same throughout the ladder to ensure good resistor matching.
- the several voltage bias levels generated inside the adjustable voltage biasing circuit 50 are calculated as follows:
- V bias1 V trip ⁇ I bias *( R 1 +R 2 +R 3 ) (1)
- V bias2 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 ) (2)
- V bias3 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 +R 5 ) (3)
- V bias4 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 +R 5 +R 6 ) (4)
- One of the control inputs, thresh_ctrl_ 1 , thresh_ctrl_ 2 , thresh_ctrl_ 3 , and thresh_ctrl_ 4 , is activated to provide any of the above four bias levels to the input of the sensing inverter 46 through one of bias transistors 68 , 70 , 72 , and 74 .
- the signals used to drive the gates of transistors 68 , 70 , 72 , and 74 may be provided by a one-of-four decoder as is known in the art.
- the resistance values of resistors R 1 -R 6 are selected to provide control for the bias voltage supplied to the sensing inverter 46 .
- the resistance values of resistors R 1 -R 6 are selected to provide selectable glitch amplitude thresholds ( ⁇ V) for V bias1 through V bias4 of +15%, +20%, +25%, and +30% of V supply respectively.
- any positive glitch of magnitude V glitch
- it gets coupled to the input of sensing inverter 46 through capacitor 44 . This positive glitch causes V bias to temporarily become V bias +V glitch .
- V bias +V glitch >V trip
- the sensing inverter 46 trips and generates a short pulse the duration of which is essentially equal to the time that the glitch maintains V bias +V glitch at a voltage level higher than V trip .
- Inverter 76 and buffer 78 along with a glitch width filter 80 , illustrated without limitation as an RC filter 80 , and a pulse stretching circuit 84 in FIG. 3 are used to stretch the pulse and generate an output of the glitch detector circuit 40 .
- Pulse stretching circuit 84 further acts as an inverter for the output pulse.
- Width Width_Control input 82 to the RC filter sets the desired minimum glitch width below which no glitch is intended to be detected.
- the inverters 46 and 76 are supplied by regulated supplies. Inverters 46 and 76 may be powered using different voltage supplies. For example, the sensing inverter 46 may be driven by 1.5V regulated supply and the inverter 76 may driven by a higher supply voltage level (e.g., 1.8V).
- the sensing inverter 46 should preferably be driven by same supply as the biasing inverter 52 to set the proper bias.
- the power supply for inverter 76 may be at a higher voltage level to strengthen it for better switching characteristics.
- Inverter 76 and buffer 78 along with RC filter 80 and pulse stretching circuit 84 in FIG. 3 are used to stretch the pulse and generate an output of the glitch detector circuit 40 .
- Width_Control input 82 to the RC filter sets the desired minimum width below which no glitch is intended to be detected.
- the inverters 46 and 76 are supplied by regulated supplies. Inverters 46 and 76 may be powered using different voltage supplies.
- the sensing inverter 46 may be driven by 1.5V regulated supply and the inverter 76 may driven by a higher supply voltage level (e.g., 1.8V).
- the sensing inverter 46 should preferably be driven by same supply as the biasing inverter 52 to set the proper bias.
- the power supply for inverter 76 may be at a higher voltage level to strengthen it for better switching characteristics. This is because the detector sensing inverter 46 may switch weakly depending on the magnitude of the incoming glitch. For example, this may happen if the glitch magnitude is just slightly above/below the trip point and the sensing inverter 46 in this case may not provide a clean 0/1 as its output.
- the subsequent inverter 76 being driven at a higher supply helps to resolve the next stages.
- FIG. 4 a schematic diagram shows an illustrative circuit implementation of the glitch detector of FIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a negative-going glitch.
- the detection circuit 90 shown in FIG. 4 monitors the voltage on V supply line 92 , acting as a power supply node.
- a first capacitor 94 is coupled between the V supply line 92 and the input of sensing inverter 96 , acting as a sensing node.
- a second capacitor 98 is coupled between the input of sensing inverter 96 and ground.
- Capacitors 94 and 98 act as a voltage divider for the glitch pulse, with capacitor 94 also acting to block the DC voltage present on V supply line 92 .
- An adjustable voltage biasing circuit (shown within dashed lines 100 ) is used to bias the input of the detection circuit to a voltage level V bias which is set to be ⁇ V volts below V trip in steady state.
- the adjustable voltage biasing circuit 100 employs a current mirror 102 formed from p-channel transistors 104 and 106 .
- a voltage 110 at the gate of an n-channel transistor 108 sets the current value i bias flowing though transistor 104 , which is mirrored by p-channel transistor 106 .
- inverter 112 has its input connected to its output. This connection sets the output of inverter 112 at its trip point V trip .
- inverter 112 is preferably matched to sensing inverter 96 so that both inverters 96 and 112 have the same trip point voltage V trip .
- the bias generation circuit 100 of FIG. 4 sets the steady-state V bias voltage to a level which is above the voltage V trip of sensing inverter 96 by the preset known amount 4V.
- a series string of resistors R 1 , R 2 , R 3 , R 4 , R 5 , and R 6 are coupled between the output of inverter current mirror 102 and inverter 112 .
- a constant current i bias set by transistor 108 , and mirrored by current mirror 102 flows through the series string of resistors.
- the inverter 112 sets the voltage at the bottom end of resistor R 6 at V trip .
- a first bias transistor 126 is coupled between the common connection of resistors R 3 and R 4 and the input of sensing inverter 96 . Its gate is coupled to a control signal thresh — ctrl — 1 .
- a second bias transistor 128 is coupled between the common connection of resistors R 4 and R 5 and the input of sensing inverter 96 . Its gate is coupled to a control signal thresh — ctrl — 2 .
- a third bias transistor 130 is coupled between the common connection of resistors R 5 and R 6 and the input of sensing inverter 96 . Its gate is coupled to a control signal thresh — ctrl — 3 .
- a fourth bias transistor 132 is coupled between the common connection of resistor R 6 and the output of inverter 112 and the input of sensing inverter 96 . Its gate is coupled to a control signal thresh_ctrl_ 4 .
- the several voltage bias levels generated inside the adjustable voltage biasing circuit 100 are calculated as follows:
- V bias1 V trip ⁇ I bias *( R 1 +R 2 +R 3 ) (1)
- V bias2 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 ) (2)
- V bias3 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 +R 5 ) (3)
- V bias4 V trip ⁇ I bias *( R 1 +R 2 +R 3 +R 4 +R 5 +R 6 ) (4)
- a control circuitry (not shown) activates one of thresh_ctrl_ 1 , thresh_ctrl_ 2 , thresh — ctrl — 3 , and thresh — ctrl — 4 , to provide any of the above four bias levels to the input of the sensing inverter 96 through one of bias transistors 126 , 128 , 130 , and 132 .
- the signals used to drive the gates of transistors 126 , 128 , 130 , and 132 may be provided by a one-of-four decoder as is known in the art.
- the resistance values of resistors R 1 -R 6 are selected to provide control for the voltage supplied to the sensing inverter 96 .
- the resistance values of resistors R 1 -R 6 are selected to provide different glitch amplitude thresholds for V bias1 through V bias4 of ⁇ 15%, ⁇ 20%, ⁇ 25%, and ⁇ 30% of V supply , respectively.
- V bias V trip +I bias *(R 1 +R 2 +R 3 ).
- V glitch the negative glitch
- V bias ⁇ V glitch ⁇ V trip the sensing inverter 96 trips and generates a short pulse the duration of which is essentially equal to the time that the glitch maintains V bias at a voltage level lower than V trip .
- Similar analyses that will be well understood by persons of ordinary skill in the art apply for turning on other ones of transistors 128 , 130 , and 132 .
- Inverters 134 , 136 , and buffer 138 along with glitch width filter 140 , illustrated without limitation as an RC filter 140 , and pulse stretching circuit 144 in FIG. 4 are used to stretch the pulse and generate an output of the glitch detector circuit 90 .
- Pulse stretching circuit 144 further acts as an inverter. Width_Control input 142 to the RC filter sets the desired minimum glitch width below which no glitch is intended to be detected
- FIG. 5 a schematic diagram shows an exemplary circuit that can be used to implement the glitch width filter filter 80 and 140 , respectively, of the circuits shown in FIGS. 3 and 4 as variable pulse width filters.
- the RC filter 80 ( 140 ) functions as a glitch width filter and is used to filter out any unintended glitches that have pulse widths below a minimum width that a user desires to detect.
- An input node 152 is connected to the input of an inverter 154 .
- the output of inverter 154 is connected to the input of an inverter 156 through resistor 158 .
- the output of inverter 156 is connected to an output node 160 .
- the Width_Control 82 ( 142 ) includes four bit inputs 162 , 164 , 166 , and 168 , that are used select an appropriate capacitance value for the RC filter.
- the RC filter inserts the capacitance in the common node 170 that is both the output of inverter 154 and the input of inverter 156 .
- Width control bit input 162 is connected to series connected inverters 172 and 174 that are used to control a passgate 176 .
- Passgate 176 is formed from n-channel transistor 178 and p-channel transistor 180 . The gate of n-channel transistor 178 is connected to the output of inverter 172 and the gate of p-channel transistor 180 is connected to the output of inverter 174 .
- the passgate 176 connects capacitor 182 to common node 170 .
- width control bit input 164 is connected to series connected inverters 184 and 186 that are used to control a passgate 188 .
- Passgate 188 is formed from n-channel transistor 190 and p-channel transistor 192 .
- the gate of n-channel transistor 190 is connected to the output of inverter 184 and the gate of p-channel transistor 192 is connected to the output of inverter 186 .
- the passgate 188 connects capacitor 194 to common node 170 .
- Width control bit input 166 is connected to series connected inverters 196 and 198 that are used to control a passgate 200 .
- Passgate 200 is formed from n-channel transistor 202 and p-channel transistor 204 .
- n-channel transistor 202 is connected to the output of inverter 196 and the gate of p-channel transistor 204 is connected to the output of inverter 198 .
- the passgate 200 connects capacitor 206 to common node 170 .
- Width control bit input 168 is connected to series connected inverters 208 and 210 that are used to control a passgate 212 .
- Passgate 212 is formed from n-channel transistor 214 and p-channel transistor 216 .
- the gate of n-channel transistor 214 is connected to the output of inverter 208 and the gate of p-channel transistor 216 is connected to the output of inverter 210 .
- the passgate 212 connects capacitor 218 to common node 170 .
- one or more of capacitors 182 , 194 , 206 , and 218 can be connected to common node 170 to form the RC filter in cooperation with resistor 158 .
- the width control bit inputs 160 , 162 , 164 , and 166 can be controlled by a one-of four decoder to turn on only one of passgates 176 , 188 , 200 , and 212 or may be individually controlled to turn on any number of passgates 176 , 188 , 200 , and 212 .
- the RC filter 80 ( 140 ) is used to filter out any glitches that are not intended to be detected.
- capacitors 182 , 194 , 206 , and 218 are readily enabled to choses the values for capacitors 182 , 194 , 206 , and 218 accordingly.
- resistor 158 having a resistance value of 16K ohms
- a capacitance value of 100 fF will filter out 1.6 ns glitches
- a capacitance value of 200 fF will filter out 3.2 ns glitches
- a capacitance value of 300 fF will filter out 4.8 ns glitches.
- FIG. 6 a schematic diagram shows an exemplary circuit that can be used to implement the pulse stretching circuits 84 and 140 , respectively, of the circuits shown in FIGS. 3 and 4 .
- a p-channel transistor 222 and n-channel transistor 224 are connected in series with a resistor 226 in series with their drains.
- the source of the p-channel transistor 222 is connected to a voltage supply VDD and the source of the n-channel transistor 224 is connected to VSS (ground).
- the gates of p-channel transistor 222 and n-channel transistor 224 are connected together to the input 228 , which represents the output of the RC filter 80 ( 140 ).
- the common connection of the drain of p-channel transistor 222 and the resistor 226 forms the output node 230 of the pulse stretching circuit 84 ( 144 ).
- a capacitor 232 is connected between the output node 230 and the source of the n-channel transistor 224 .
- the pulse stretching circuit 84 ( 144 ) provides a weak pull-down/pull-up path to delay the switching of the input signal.
- the pull-down path through n-channel transistor 224 is made more resistive by adding the resistor 226 in series with the n-channel transistor 226 .
- the pull-up path through p-channel transistor 222 is shunted by capacitor 232 to provide a delayed rising of the output.
Abstract
Description
- This application claims priority from Indian Patent Application No. 201621042167 filed Dec. 9, 2016, the contents of which are incorporated in this disclosure by reference in their entirety.
- The present invention relates to electronic circuits. More particularly, the present invention relates to detection circuits and to power supply glitch detector circuits that detect any kind of positive or negative voltage glitch on a power supply and provide signals as outputs in response to these glitches.
- Sensitive information in electronic devices is usually protected using various encryption methods. Even though encryption protects the primary channels of the device from hackers, several secondary channels are still prone to attacks.
- Side channel attacks are aimed to gain information from the device by targeting these secondary channels of the device like the hardware, timing information, electromagnetic radiation, without limitation. Typical side channel attacks can include: attacking the cache implemented by monitoring the cache; timing attacks implemented by measuring the computation timing of different tasks; power monitoring attacks implemented by measuring the varying nature of device power consumption; electromagnetic attacks implemented by measuring electromagnetic radiation leaked from the device; fault injection attacks implemented by placing the device in abnormal conditions such as abruptly raising or lowering power supply voltage: and/or tampering with the clock, device temperature, without limitation.
- Side channel attacks involving power supplies of the device come under the category of fault injection. Glitching the supply voltage (higher or lower) may affect the device in certain ways, some of which include changes to the logic outputs of the circuits affecting further control operations, affecting the on-going device operations like programming/reading from a memory location, without limitation, essentially leaving the device corrupted.
- In view of the availability of these power supply side channel hacking procedures, there is a long standing need for the device to be capable of detecting such power supply attacks and take preventive actions against these attacks.
- A power supply glitch detector is a circuit that detects any kind of voltage glitch on the supply. One embodiment of a circuit in accordance with the present invention detects both positive and negative voltage glitches on the supply and provides active high or low signals as outputs in response to detection of any of these glitches.
- In accordance with the present invention, a glitch detector includes a glitch coupling circuit, a bias generating circuit, a glitch detection circuit in the form of a comparator coupled to the bias generating circuit and the glitch coupling circuit, and a pulse stretching circuit.
- According to one aspect of the invention, the glitch detector may include two detector cores: one for positive glitch detection and the other for negative glitch detection.
- According to another aspect of the invention, the magnitude of the supply glitch that needs to be detected and responded to by the circuit can be configured by applying different control settings.
- The invention will be explained in more detail in the following with reference to embodiments and to the drawing in which are shown:
-
FIGS. 1A and 1B are graphs of voltage vs. time that represent power supply waveforms including, respectively, idealized representations of positive and negative glitch pulses; -
FIG. 2 is a block diagram showing a glitch detector in accordance with one aspect of the present invention; -
FIG. 3 is a schematic diagram showing an illustrative circuit implementation of the glitch detector ofFIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a positive-going glitch; -
FIG. 4 is a schematic diagram showing an illustrative circuit implementation of the glitch detector ofFIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a negative-going glitch; -
FIG. 5 is a schematic diagram of an exemplary circuit that can be used to implement the RC filter of the circuits shown inFIGS. 3 and 4 ; and -
FIG. 6 is a schematic diagram of an exemplary circuit that can be used to implement the pulse stretching inverter of the circuits shown inFIGS. 3 and 4 . - Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
- Referring first of all to
FIGS. 1A and 1B are graphs of voltage vs. time that represent power supply waveforms including, respectively, idealized representations of positive and negative glitch pulses. In bothFIGS. 1A and 1B , the waveforms have nominal steady-state values. InFIG. 1A , an illustrative positive-going glitch is indicated atreference numeral 10 and has rise/fall times of 100 ps and a duration of 2 ns. InFIG. 1B , an illustrative negative-going glitch is indicated atreference numeral 12 and has rise/fall times of 100 ps and a duration of 2 ns. Persons of ordinary skill in the art will appreciate that these waveforms are illustrative only and the present invention is not limited to detection of glitches having the exact characteristics that are shown inFIGS. 1A and 1B . -
FIG. 2 is a block diagram showing aglitch detector 20 in accordance with the present invention.Glitch detector 20 includes aglitch coupling circuit 22 coupled to apower supply line 24 on which glitches are to be detected. The glitch is coupled from the output of theglitch coupling circuit 22 to the input ofdetection circuit 26, which can be an inverter biased at a voltage level Vbias usingbias generator circuit 28. Thedetection circuit 26 outputs a pulse having the approximate duration of the input glitch pulse that is stretched usingpulse stretcher circuit 30. The output ofpulse stretcher circuit 30 atline 32 is the output of theglitch detector circuit 20. This output may be used to raise a flag that will drive one or more circuits to allow the system to take an appropriate action (generate an interrupt, reset or other action without limitation) for the device so as to prevent the hacker from extracting/monitoring the characteristics of the power supply or injecting any fault, thus preventing side channel attacks. In accordance with different aspects of the invention, theglitch detector 20 may be configured to detect positive glitches, negative glitches, or both positive and negative glitches. -
Glitch coupling circuit 22 is coupled between the voltagesupply voltage line 24, also known aspower supply node 24 and the input of thedetection circuit 26, which input is called a sensing node. Theglitch coupling circuit 22 transfers any voltage glitch occurring on thevoltage supply line 24 to the sensing node at the input of thedetection circuit 26. - Considering the case of a positive glitch detector, if the input voltage level is below the trip-point Vtrip of the
detection circuit 26, the output is at a first logic state (e.g.,logic 1 also referred to as high logic state), indicative that no glitch has been detected. If the input voltage level is above the trip-point Vtrip of thedetection circuit 26, the output transitions to a second logic state opposite the first logic state (e.g., logic 0 also referred to as low logic state), indicative that a glitch has been detected. - In an embodiment where the
glitch detector circuit 26 has a trip point of Vtrip, the input of theglitch detection circuit 26 is biased bybias generator circuit 28 to a voltage level of Vbias where it remains under steady-state conditions. Vbias is set to be lower than Vtrip by a certain preset known voltage (ΔV). Under the steady-state condition the output of thedetection circuit 26 is at the first logic state (e.g., logic 1). - A glitch occurring on the
voltage supply line 24 will be coupled to the input of theglitch detection circuit 26. If the glitch raises the input voltage of theglitch detection circuit 26 by more than the preset voltage ΔV, then Vbias+Vglitch>Vtrip and it will cause thedetection circuit 26 to trip and its output transitions from the first logic state to the second logic state (e.g., logic 0). - When the voltage glitch on the supply terminates, the input voltage to the
detection circuit 26 returns to its quiescent value Vbias. Since now Vbias<Vtrip, the output of thedetection circuit 26 returns to the first logic state. In this process the output of the detection circuit generates a short pulse (e.g., going fromlogic 1→0→1). This pulse can be stretched using apulse stretching circuit 30 to generate the output of theglitch detector 20. - Considering the case of a negative glitch detector, the trip-point Vtrip of the
detection circuit 26 is set to be below the steady-state voltage level to the input of theglitch detection circuit 26. Under this steady state condition, the output of thedetection circuit 26 is at a first logic level (e.g., logic 0), indicative that no glitch has been detected. If the input voltage level to theglitch detection circuit 26 drops below the trip-point Vtrip of thedetection circuit 26, the output of theglitch detection circuit 26 transitions to the second logic state (e.g., logic 1), indicative that a glitch has been detected. - In a negative glitch detector embodiment where the
glitch detector circuit 26 has a trip point of Vtrip, the input of theglitch detection circuit 26 is biased bybias generator circuit 28 to a voltage level of Vbias under steady-state conditions. Vbias is set to be higher than Vtrip by a certain preset known voltage (ΔV). Under the steady-state condition the output of thedetection circuit 26 is at the first logic level. - A glitch will be coupled to the input of the
glitch detection circuit 26. If the glitch lowers the input voltage of theglitch detection circuit 26 by more than the preset voltage ΔV, then Vbias−Vglitch<Vtrip and it will cause the output of thedetection circuit 26 to transition from the first logic state to the second logic state. - When the voltage glitch on the supply terminates, the input voltage to the
detection circuit 26 returns to Vbias. Since now Vbias>Vtrip, the output of thedetection circuit 26 returns to the first logic state. In this process the output of the detection circuit generates a short pulse (e.g., going from logic 0→1→0). This pulse can be stretched using apulse stretching circuit 30 to generate the output of theglitch detector 20. - Referring now to
FIG. 3 , a schematic diagram shows an illustrative circuit implementation of the glitch detector ofFIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a positive-going glitch. Thedetection circuit 40 shown inFIG. 3 monitors the voltage on Vsupply line 42. Afirst capacitor 44 is coupled between the Vsupply line 42 and the input of sensinginverter 46. Asecond capacitor 48 is coupled between the input of sensinginverter 46 and ground.Capacitors capacitor 44 also acting to block the DC voltage present on Vsupply line 42. While a single DC blocking capacitor could be used, employing two capacitors as a voltage divider scales down the magnitude of the incoming glitch (which is a function of the power supply voltage level) and thus provides the ability to use the same detection circuit to detect glitches on any power supply level. The capacitance ratio ofcapacitors - A adjustable voltage biasing circuit (shown within dashed lines 50) is used to bias the input of the detection circuit to a voltage level Vbias to a predetermined level below Vtrip in steady state, with a steady state difference of ΔV. The adjustable
voltage biasing circuit 50 employs aninverter 52 having its input connected to its output. This connection sets the output ofinverter 52 at its trip point Vtrip. Inverter 52 is matched to sensinginverter 46 so that bothinverters inverter 52 is set to be the same as the trip point of thesensing inverter 46 in order to allow thebias circuit 50 to set the bias of thesensing inverter 46 accordingly. - A series string of resistors R1, R2, R3, R4, R5, and R6, identified respectively by
reference numerals inverter 52 and an n-channelcurrent bias transistor 66. N-channelcurrent bias transistor 66 has its gate set at a voltage to cause a constant current bias to flow through the series string of resistors. - A
first bias transistor 68 is coupled between the common connection of resistors R3 and R4 and the input of sensinginverter 46. Its gate is coupled to a control signal thresh_ctrl _1. Asecond bias transistor 70 is coupled between the common connection of resistors R4 and R5 and the input of sensinginverter 46. Its gate is coupled to a control signal thresh_ctrl_2. Athird bias transistor 72 is coupled between the common connection of resistors R5 and R6 and the input of sensinginverter 46. Its gate is coupled to a control signal thresh_ctrl_3. Afourth bias transistor 74 is coupled between the common connection of resistor R6 and the drain ofcurrent bias transistor 66 and the input of sensinginverter 46. Its gate is coupled to a control signal thresh_ctrl_4. Persons of ordinary skill in the art will appreciate that R1 through R3 are formed separately to keep the unit resistor value the same throughout the ladder to ensure good resistor matching. - The several voltage bias levels generated inside the adjustable
voltage biasing circuit 50 are calculated as follows: -
V bias1 =V trip −I bias*(R 1 +R 2 +R 3) (1) -
V bias2 =V trip −I bias*(R 1 +R 2 +R 3 +R 4) (2) -
V bias3 =V trip −I bias*(R 1 +R 2 +R 3 +R 4 +R 5) (3) -
V bias4 =V trip −I bias*(R 1 +R 2 +R 3 +R 4 +R 5 +R 6) (4) - One of the control inputs, thresh_ctrl_1, thresh_ctrl_2, thresh_ctrl_3, and thresh_ctrl_4, is activated to provide any of the above four bias levels to the input of the
sensing inverter 46 through one ofbias transistors transistors sensing inverter 46. In one exemplary non-limiting embodiment of the invention, the resistance values of resistors R1-R6 are selected to provide selectable glitch amplitude thresholds (ΔV) for Vbias1 through Vbias4 of +15%, +20%, +25%, and +30% of Vsupply respectively. - As an example, assume that thresh_ctrl_1 is set to active so as to turn on
transistor 68 and thereby apply Vbias1 to the input of sensinginverter 46. Therefore Vbias=Vtrip−Ibias*(R1+R2+R3)=Vbias1. In case there is any positive glitch (of magnitude Vglitch) on the voltage supply, it gets coupled to the input of sensinginverter 46 throughcapacitor 44. This positive glitch causes Vbias to temporarily become Vbias+Vglitch. - If Vbias+Vglitch>Vtrip, the
sensing inverter 46 trips and generates a short pulse the duration of which is essentially equal to the time that the glitch maintains Vbias+Vglitch at a voltage level higher than Vtrip. Similar analyses that will be well understood by persons of ordinary skill in the art apply for turning on other ones oftransistors -
Inverter 76 andbuffer 78 along with aglitch width filter 80, illustrated without limitation as anRC filter 80, and apulse stretching circuit 84 inFIG. 3 are used to stretch the pulse and generate an output of theglitch detector circuit 40.Pulse stretching circuit 84 further acts as an inverter for the output pulse.Width Width_Control input 82 to the RC filter sets the desired minimum glitch width below which no glitch is intended to be detected. Theinverters Inverters sensing inverter 46 may be driven by 1.5V regulated supply and theinverter 76 may driven by a higher supply voltage level (e.g., 1.8V). Thesensing inverter 46 should preferably be driven by same supply as the biasinginverter 52 to set the proper bias. The power supply forinverter 76 may be at a higher voltage level to strengthen it for better switching characteristics.Inverter 76 andbuffer 78 along withRC filter 80 andpulse stretching circuit 84 inFIG. 3 are used to stretch the pulse and generate an output of theglitch detector circuit 40.Width_Control input 82 to the RC filter sets the desired minimum width below which no glitch is intended to be detected. Theinverters Inverters sensing inverter 46 may be driven by 1.5V regulated supply and theinverter 76 may driven by a higher supply voltage level (e.g., 1.8V). Thesensing inverter 46 should preferably be driven by same supply as the biasinginverter 52 to set the proper bias. The power supply forinverter 76 may be at a higher voltage level to strengthen it for better switching characteristics. This is because thedetector sensing inverter 46 may switch weakly depending on the magnitude of the incoming glitch. For example, this may happen if the glitch magnitude is just slightly above/below the trip point and thesensing inverter 46 in this case may not provide a clean 0/1 as its output. Thesubsequent inverter 76 being driven at a higher supply helps to resolve the next stages. - Referring now to
FIG. 4 , a schematic diagram shows an illustrative circuit implementation of the glitch detector ofFIG. 2 where the bias generator circuit and the glitch detection circuit are configured to detect a negative-going glitch. - The
detection circuit 90 shown inFIG. 4 monitors the voltage on Vsupply line 92, acting as a power supply node. Afirst capacitor 94 is coupled between the Vsupply line 92 and the input of sensinginverter 96, acting as a sensing node. Asecond capacitor 98 is coupled between the input of sensinginverter 96 and ground.Capacitors capacitor 94 also acting to block the DC voltage present on Vsupply line 92. - An adjustable voltage biasing circuit (shown within dashed lines 100) is used to bias the input of the detection circuit to a voltage level Vbias which is set to be ΔV volts below Vtrip in steady state. The adjustable
voltage biasing circuit 100 employs acurrent mirror 102 formed from p-channel transistors voltage 110 at the gate of an n-channel transistor 108 sets the current value ibias flowing thoughtransistor 104, which is mirrored by p-channel transistor 106. - An
inverter 112 has its input connected to its output. This connection sets the output ofinverter 112 at its trip point Vtrip. As explained above with reference to the positive glitch detector ofFIG. 3 .inverter 112 is preferably matched to sensinginverter 96 so that bothinverters FIG. 4 and the circuit discussed with reference toFIG. 3 is that thebias generation circuit 100 ofFIG. 4 sets the steady-state Vbias voltage to a level which is above the voltage Vtrip of sensinginverter 96 by the preset known amount 4V. - A series string of resistors R1, R2, R3, R4, R5, and R6, identified respectively by
reference numerals current mirror 102 andinverter 112. A constant current ibias set bytransistor 108, and mirrored bycurrent mirror 102, flows through the series string of resistors. Theinverter 112 sets the voltage at the bottom end of resistor R6 at Vtrip. - A
first bias transistor 126 is coupled between the common connection of resistors R3 and R4 and the input of sensinginverter 96. Its gate is coupled to a control signal thresh— ctrl— 1. Asecond bias transistor 128 is coupled between the common connection of resistors R4 and R5 and the input of sensinginverter 96. Its gate is coupled to a control signal thresh— ctrl— 2. Athird bias transistor 130 is coupled between the common connection of resistors R5 and R6 and the input of sensinginverter 96. Its gate is coupled to a control signal thresh— ctrl— 3. Afourth bias transistor 132 is coupled between the common connection of resistor R6 and the output ofinverter 112 and the input of sensinginverter 96. Its gate is coupled to a control signal thresh_ctrl_4. - The several voltage bias levels generated inside the adjustable
voltage biasing circuit 100 are calculated as follows: -
V bias1 =V trip −I bias*(R 1 +R 2 +R 3) (1) -
V bias2 =V trip −I bias*(R 1 +R 2 +R 3 +R 4) (2) -
V bias3 =V trip −I bias*(R 1 +R 2 +R 3 +R 4 +R 5) (3) -
V bias4 =V trip −I bias*(R 1 +R 2 +R 3 +R 4 +R 5 +R 6) (4) - A control circuitry (not shown) activates one of thresh_ctrl_1, thresh_ctrl_2, thresh—
ctrl — 3, and thresh—ctrl — 4, to provide any of the above four bias levels to the input of thesensing inverter 96 through one ofbias transistors transistors sensing inverter 96. In one exemplary non-limiting embodiment of the invention, the resistance values of resistors R1-R6 are selected to provide different glitch amplitude thresholds for Vbias1 through Vbias4 of −15%, −20%, −25%, and −30% of Vsupply, respectively. - As an example, assume that thresh— ctrl _1 is applied to the gate of
transistor 126 to turn it on and apply Vbias1 to the input of sensinginverter 96. Therefore Vbias=Vtrip+Ibias*(R1+R2+R3). In case there is any negative glitch (of magnitude Vglitch) on the voltage supply, it gets coupled to the input of sensinginverter 96 throughcapacitor 94. This negative glitch causes Vbias to temporarily become Vbias−Vglitch. - If Vbias−Vglitch<Vtrip, the
sensing inverter 96 trips and generates a short pulse the duration of which is essentially equal to the time that the glitch maintains Vbias at a voltage level lower than Vtrip. Similar analyses that will be well understood by persons of ordinary skill in the art apply for turning on other ones oftransistors -
Inverters glitch width filter 140, illustrated without limitation as anRC filter 140, andpulse stretching circuit 144 inFIG. 4 are used to stretch the pulse and generate an output of theglitch detector circuit 90.Pulse stretching circuit 144 further acts as an inverter.Width_Control input 142 to the RC filter sets the desired minimum glitch width below which no glitch is intended to be detected - Referring now to
FIG. 5 , a schematic diagram shows an exemplary circuit that can be used to implement the glitchwidth filter filter FIGS. 3 and 4 as variable pulse width filters. The RC filter 80 (140) functions as a glitch width filter and is used to filter out any unintended glitches that have pulse widths below a minimum width that a user desires to detect. - An
input node 152 is connected to the input of aninverter 154. The output ofinverter 154 is connected to the input of aninverter 156 throughresistor 158. The output ofinverter 156 is connected to anoutput node 160. - In the embodiment of the RC filter shown in
FIG. 5 , the Width_Control 82 (142) includes fourbit inputs - The RC filter inserts the capacitance in the
common node 170 that is both the output ofinverter 154 and the input ofinverter 156. Widthcontrol bit input 162 is connected to series connectedinverters passgate 176.Passgate 176 is formed from n-channel transistor 178 and p-channel transistor 180. The gate of n-channel transistor 178 is connected to the output ofinverter 172 and the gate of p-channel transistor 180 is connected to the output ofinverter 174. Thepassgate 176 connectscapacitor 182 tocommon node 170. - Similarly, width
control bit input 164 is connected to series connectedinverters channel transistor 190 and p-channel transistor 192. The gate of n-channel transistor 190 is connected to the output ofinverter 184 and the gate of p-channel transistor 192 is connected to the output ofinverter 186. The passgate 188 connectscapacitor 194 tocommon node 170. Widthcontrol bit input 166 is connected to series connectedinverters passgate 200.Passgate 200 is formed from n-channel transistor 202 and p-channel transistor 204. The gate of n-channel transistor 202 is connected to the output ofinverter 196 and the gate of p-channel transistor 204 is connected to the output ofinverter 198. Thepassgate 200 connectscapacitor 206 tocommon node 170. Widthcontrol bit input 168 is connected to series connectedinverters passgate 212.Passgate 212 is formed from n-channel transistor 214 and p-channel transistor 216. The gate of n-channel transistor 214 is connected to the output ofinverter 208 and the gate of p-channel transistor 216 is connected to the output ofinverter 210. Thepassgate 212 connectscapacitor 218 tocommon node 170. - At any one time, one or more of
capacitors common node 170 to form the RC filter in cooperation withresistor 158. As will be appreciated by persons of ordinary skill in the art, the widthcontrol bit inputs passgates passgates capacitors resistor 158 having a resistance value of 16K ohms, a capacitance value of 100 fF will filter out 1.6 ns glitches, a capacitance value of 200 fF will filter out 3.2 ns glitches, and a capacitance value of 300 fF will filter out 4.8 ns glitches. - Referring now to
FIG. 6 , a schematic diagram shows an exemplary circuit that can be used to implement thepulse stretching circuits FIGS. 3 and 4 . - A p-
channel transistor 222 and n-channel transistor 224 are connected in series with aresistor 226 in series with their drains. The source of the p-channel transistor 222 is connected to a voltage supply VDD and the source of the n-channel transistor 224 is connected to VSS (ground). The gates of p-channel transistor 222 and n-channel transistor 224 are connected together to theinput 228, which represents the output of the RC filter 80 (140). The common connection of the drain of p-channel transistor 222 and theresistor 226 forms theoutput node 230 of the pulse stretching circuit 84 (144). Acapacitor 232 is connected between theoutput node 230 and the source of the n-channel transistor 224. - The pulse stretching circuit 84 (144) provides a weak pull-down/pull-up path to delay the switching of the input signal. The pull-down path through n-
channel transistor 224 is made more resistive by adding theresistor 226 in series with the n-channel transistor 226. The pull-up path through p-channel transistor 222 is shunted bycapacitor 232 to provide a delayed rising of the output. As an example, R and C values of R=200KΩ, C=128 fF will together give a delay of ˜25 ns. - While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
Claims (19)
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Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025981A (en) | 1998-11-04 | 2000-02-15 | Mosel Vitelic Inc. | Flexible voltage transient detector circuit |
DE10120147B4 (en) | 2001-04-25 | 2010-08-05 | Nxp B.V. | Circuit for detecting short voltage dips in a supply voltage |
KR100440451B1 (en) | 2002-05-31 | 2004-07-14 | 삼성전자주식회사 | Circuit For Detecting A Volatage Glitch, An Integrated Circuit Device Having The Same, And An Apparatus And Method For Securing An Integrated Circuit Device From A Voltage Glitch Attack |
US7570468B2 (en) * | 2006-07-05 | 2009-08-04 | Atmel Corporation | Noise immune RC trigger for ESD protection |
US8390360B2 (en) * | 2011-01-12 | 2013-03-05 | Advanced Micro Devices, Inc. | Electronic component protection power supply clamp circuit |
US8908341B2 (en) * | 2012-04-04 | 2014-12-09 | Globalfoundries Singapore Pte. Ltd. | Power clamp for high voltage integrated circuits |
CN104811171B (en) * | 2014-01-26 | 2018-01-09 | 京微雅格(北京)科技有限公司 | The electrification reset circuit of zero current |
-
2017
- 2017-12-04 US US15/831,287 patent/US10156595B2/en active Active
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