US20180068934A1 - Package for die-bridge capacitor - Google Patents

Package for die-bridge capacitor Download PDF

Info

Publication number
US20180068934A1
US20180068934A1 US15/258,819 US201615258819A US2018068934A1 US 20180068934 A1 US20180068934 A1 US 20180068934A1 US 201615258819 A US201615258819 A US 201615258819A US 2018068934 A1 US2018068934 A1 US 2018068934A1
Authority
US
United States
Prior art keywords
transistor
capacitor
leadframe segment
leadframe
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/258,819
Other versions
US9922912B1 (en
Inventor
Eung San Cho
Danny Clavette
Darryl Galipeau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Priority to US15/258,819 priority Critical patent/US9922912B1/en
Assigned to Infineon Technologies Americas Corp. reassignment Infineon Technologies Americas Corp. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, EUNG SAN, CLAVETTE, DANNY, Galipeau, Darryl
Priority to DE102017215480.2A priority patent/DE102017215480A1/en
Priority to CN201710795026.3A priority patent/CN107799511A/en
Publication of US20180068934A1 publication Critical patent/US20180068934A1/en
Application granted granted Critical
Publication of US9922912B1 publication Critical patent/US9922912B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49589Capacitor integral with or on the leadframe
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This disclosure relates to semiconductor packaging, and more specifically, to semiconductor packages for power electronics.
  • a half-bridge circuit may include two analog devices or switches. Half-bridge circuits may be used in power supplies for motors, in rectifiers, and for power conversion. Each half-bridge circuit package has several contacts and may include several conductive paths to connect the contacts to each other and to external components.
  • a half-bridge circuit may experience ringing if the circuit is underdamped. The ringing may occur approximately when one device of the half-bridge circuit closes and the other device opens.
  • One method for minimizing the impact of ringing is to reduce the turn-on times of the devices.
  • Another method to minimize the ringing is to reduce the size of a package for the half-bridge circuit and implement a decoupling capacitor attached to the printed-circuit-board voltage input.
  • This disclosure describes techniques for a device comprising a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment.
  • the device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment.
  • the device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor.
  • the device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.
  • a method comprises electrically connecting a first transistor to a first leadframe segment, and electrically connecting a second transistor to a second leadframe segment.
  • the method further comprises electrically connecting a conductive element to the first transistor and the second transistor.
  • the method further comprises electrically connecting a first end of a capacitor to the first leadframe segment, and electrically connecting a second end of the capacitor to the second leadframe segment.
  • a power converter device comprises an input-voltage leadframe segment, a reference-voltage leadframe segment, and a high-side transistor, wherein a high-side drain terminal of the high-side transistor is electrically connected to the input-voltage leadframe segment.
  • the power converter device further comprises a low-side transistor, wherein a low-side source terminal of the low-side transistor is electrically connected to the reference-voltage leadframe segment.
  • the power converter device further comprises a conductive element, wherein the conductive element is electrically connected to a high-side source terminal of the high-side transistor and a low-side drain terminal of the low-side transistor.
  • the power converter device further comprises a capacitor, wherein a high side of the capacitor is electrically connected to the input-voltage leadframe segment, a low side of the capacitor is electrically connected to the reference-voltage leadframe segment, a first distance between the high-side drain terminal and the high side of the capacitor is less than approximately four hundred micrometers, and a second distance between the low-side source terminal and the low side of the capacitor is less than approximately four hundred micrometers.
  • FIG. 1 is a circuit diagram of a half-bridge circuit including a capacitor between an input node and a reference node, in accordance with some examples of this disclosure.
  • FIG. 2 is a block diagram of a device including a capacitor on a top-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 3 is a block diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 4 is a diagram of a device including a capacitor on a top-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 5 is a diagram of a device including a capacitor on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 6 is a diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 7 is a diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 8 is a side-view diagram of a device including a discrete capacitor on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 9 is a top-view diagram of a device including discrete capacitors on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 11 is a block diagram of a device including an integrated capacitor, in accordance with some examples of this disclosure.
  • FIG. 12 is a flowchart depicting a process of constructing a circuit, in accordance with some examples of this disclosure.
  • FIG. 13 is a conceptual block diagram of device circuit including two drain-down transistors, in accordance with some examples of this disclosure.
  • a half-bridge circuit may include parasitic capacitances and parasitic inductances defined by the components and connections of the half-bridge circuit.
  • a capacitor connected between the input-voltage node and the reference-voltage node may reduce the effect of parasitics on the half-bridge circuit.
  • the distance between each transistor of the half-bridge circuit and the capacitor may influence the effectiveness of the capacitor.
  • connecting the capacitor directly to the transistor leadframe segments may substantially improve the operation of the half-bridge circuit at high frequencies by reducing the ringing and resonant peaks that may occur when switching between transistors.
  • the circuit may be designed to include transistors with lower breakdown voltages, lower resistances, and lower power consumption, while maintaining or improving performance.
  • FIG. 1 is a circuit diagram of a half-bridge circuit including a capacitor 6 between an input node 8 and a reference node 16 , in accordance with some examples of this disclosure.
  • power converter 2 may comprise a half-bridge direct-current-to-direct-current (DC-to-DC) buck converter for converting an input DC signal to an output DC signal with a lower voltage.
  • DC-to-DC buck converter power converter 2 may operate as a voltage regulator in a variety of applications.
  • a voltage amplitude of an input DC signal may be higher than a voltage amplitude of an output DC signal.
  • the techniques of this disclosure may apply to other circuits and configurations, such as other power converters, including multi-phase power converters.
  • Power converter 2 may include device 4 , which may include an integrated circuit (IC) or discrete components. Power converter 2 may include transistors 10 A, 10 B, inductor 18 , capacitor 22 , and pulse-width modulation (PWM) control and driver 12 . In some examples, power converter 2 may contain more or fewer components than the components depicted in FIG. 1 . Power converter 2 may include input node 8 , reference node 16 , and output node 20 , as well as other nodes not shown in FIG. 1 . Nodes 8 , 16 , 20 may be configured to connect to external components.
  • IC integrated circuit
  • PWM pulse-width modulation
  • input node 8 may connect to an input voltage such as a power supply
  • output node 20 may connect to an electronic device
  • reference node 16 may connect to a reference voltage, such as reference ground.
  • PWM control and driver 12 may connect to an external circuit to a node (not shown in FIG. 1 ).
  • transistors 10 A, 10 B may include, but not limited to, any type of field-effect transistor (FET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a high-electron-mobility transistor (HEMT), a gallium-nitride (GaN) based transistor, or another element that uses voltage for its control.
  • FET field-effect transistor
  • BJT bipolar junction transistor
  • IGBT insulated-gate bipolar transistor
  • HEMT high-electron-mobility transistor
  • GaN gallium-nitride
  • Transistors 10 A, 10 B may comprise n-type transistors or p-type transistors, and transistors 10 A, 10 B may comprise vertical power transistors.
  • the source terminal and the drain terminal may be on opposite sides or opposite surfaces of the transistor. Current in a vertical power transistor may flow through the transistor from top to bottom or from bottom to top.
  • transistors 10 A, 10 B may comprise other analog devices such as diodes.
  • Transistors 10 A, 10 B may also include freewheeling diodes connected in parallel with transistors to prevent reverse breakdown of transistors 10 A, 10 B.
  • transistors 10 A, 10 B may operate as switches or as analog devices.
  • transistors 10 may include more than two transistors, such as in multi-phase power converters or other more complex power circuits.
  • power converter 2 may have one high-side transistor and one low-side transistor for each phase. Therefore, a multi-phase power converter may include one or more replications of power converter 2 as depicted in FIG. 1 .
  • FIG. 1 depicts transistors 10 A, 10 B with three terminals: drain (D), source (S), and gate (G).
  • Current may flow between the drain and source of transistors 10 A, 10 B, based on the voltage at the gate.
  • Current may flow from input node 8 to switch node 14 , through the drain and source of transistor 10 A, based on the voltage at the gate of transistor 10 A.
  • Current may flow from switch node 14 to reference node 16 , through the drain and source of transistor 10 B, based on the voltage at the gate of transistor 10 B.
  • Transistor 10 A may comprise a high-side transistor
  • transistor 10 B may comprise a low-side transistor because transistor 10 B is connected to reference node 16 .
  • Transistors 10 A, 10 B may comprise various material compounds, such as silicon (Si), silicon carbide (SiC), Gallium Nitride (GaN), or any other combination of one or more semiconductor materials.
  • Si silicon
  • SiC silicon carbide
  • GaN Gallium Nitride
  • Transistors 10 A, 10 B may comprise various material compounds, such as silicon (Si), silicon carbide (SiC), Gallium Nitride (GaN), or any other combination of one or more semiconductor materials.
  • Si silicon
  • SiC silicon carbide
  • GaN Gallium Nitride
  • PWM control and driver 12 may deliver signals and/or voltages to the control terminals of transistors 10 A, 10 B.
  • FIG. 1 depicts PWM control and driver 12 as one component, but the PWM control circuit and the driver circuit may be separate components. In some examples, PWM control and driver 12 , only the PWM control circuit, or only the driver circuit may be located outside of power converter 2 or outside of device 4 .
  • Inductor 18 may comprise an optional coil inductor that is outside of device 4 . Inductor 18 may connect to switch node 14 and output node 20 . Inductor 18 may impede the flow of alternating-current (AC) electricity, while allowing DC electricity to flow between switch node 14 and output node 20 .
  • AC alternating-current
  • Capacitors 6 , 22 may comprise discrete capacitors, integrated silicon capacitors, film capacitors, electrolytic capacitors, ceramic capacitors, or any other suitable type of capacitors. Capacitor 6 may be inside of device 4 , and capacitor 22 may be an optional component in power converter 2 outside of device 4 . A first end of capacitor 6 may electrically connect to input node 8 , and a second end of capacitor 6 may electrically connect to reference node 16 , and capacitor 22 may connect to output node 20 and reference node 16 . Capacitors 6 , 22 may impede the flow of DC electricity, while allowing AC electricity to flow between nodes. Capacitor 22 may act as a smoothing capacitor for the voltage at output node 20 to moderate fluctuations in the voltage at output node 20 .
  • capacitor 6 may reduce the ringing in loop 24 comprising input node 8 , transistors 10 A, 10 B, switch node 14 , and reference node 16 .
  • the ringing may be based on parasitic capacitances and parasitic inductances throughout device 4 , such as at switch node 14 between transistors 10 A, 10 B.
  • capacitor 6 may be electrically connected to the drain terminal of transistor 10 A and the source terminal of transistor 10 B.
  • the effectiveness of capacitor 6 in cancelling the parasitics may be based on the distance between the drain terminal of transistor 10 A through capacitor 6 to the source terminal of transistor 10 B.
  • capacitor 6 may reduce or eliminate the ringing at switch node 14 , thereby allowing faster switching speeds and lower power consumption for device 4 and power converter 2 in some examples.
  • transistors 10 A, 10 B may be designed with lower breakdown voltages because the resonant voltage peaks at switching may be reduced or eliminated. With lower breakdown voltages, transistors 10 A, 10 B may have lower drain-to-source resistance when each transistor is closed or conducting current. The lower drain-to-source resistances may improve the performance of transistors 10 A, 10 B, allowing transistors 10 A, 10 B to conduct more current at the same voltages. The lower drain-to-source resistances may also reduce the power consumption of transistors 10 A, 10 B.
  • FIG. 2 is a block diagram of a device 50 including a capacitor 56 on a top-etched leadframe 54 A, 54 B, in accordance with some examples of this disclosure.
  • Device 50 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 52 A, 52 B may comprise discrete vertical transistors such as vertical power FETs. Current may travel from one side of each of transistors 52 A, 52 B to an opposite side of transistors 52 A, 52 B.
  • Transistors 52 A, 52 B may each have a control terminal and two load terminals. Each of the load terminals of transistors 52 A, 52 B may comprise a pad or area at the surface of transistors 52 A, 52 B to form external electrical connections. Transistor 52 A may function as a high-side transistor in a manner similar to transistor 10 A in FIG. 1 , and transistor 52 B may function as a low-side transistor in a manner similar to transistor 10 B in FIG. 1 . In some examples, transistors 52 A, 52 B may be MOSFETs, BJTs, IGBTs, and/or any suitable type of transistor. If transistors 52 A, 52 B are bipolar transistors, each control terminal may be a base and the load terminals may be emitters and collectors.
  • Transistors 52 A, 52 B may be electrically connected to conductive element 58 , which may act as a switch node.
  • Conductive element 58 may comprise a metallization layer, a clip, a ribbon, a die paddle, a wire bond, a copper pillar, a through-silicon via, and/or any other suitable conductive material.
  • Transistor 52 A may also be electrically connected to leadframe segment 54 A
  • transistor 52 B may be electrically connected to leadframe segment 54 B.
  • Capacitor 56 may also be electrically connected to leadframe segments 54 A and/or 54 B.
  • Conductive element 58 may be electrically connected to leadframe segment 54 C.
  • Leadframe segments 54 A, 54 B, 54 C may comprise die paddles, metallization layers, and/or any other suitable conductive material.
  • device 50 may include embedded metal layers in addition to or instead of leadframe segments, such as in a high frequency fusion device.
  • the embedded layers may include copper and/or any other suitable conductive material.
  • the electrical connections between transistors 52 A, 52 B and conductive element 58 and between transistors 52 A, 52 B and leadframe segments 54 A, 54 B may be formed by soldering.
  • the electrical connections between capacitor 56 and leadframe segments 54 A, 54 B may also be formed by soldering.
  • Soldering components to form electrical connections may include placing solder between the components, applying heat to melt the solder, and allowing the solder to cool to form the electrical connection.
  • the components of device 50 may also be glued or adhered together with conductive paste, conductive tape, conductive epoxy, and/or metal sintering.
  • the connections between transistors 52 A, 52 B, leadframe segments 54 A, 54 B, conductive element 58 (depicted as shaded layers in FIG.
  • Diffusion bonding may include direct bonding between transistors 52 A, 52 B, each of which may be a semiconductor die, and leadframe segments 54 A, 54 B and conductive element 58 .
  • device 50 may be fully or partially encapsulated in a molding compound and/or any other suitable insulating material.
  • Transistors 52 A, 52 B, leadframe segments 54 A, 54 B, 54 C, and capacitor 56 may be fully encapsulated, while conductive element 58 may be partially encapsulated to allow for thermal dissipation and/or electrical connection between conductive element 58 and an external device.
  • capacitor 56 may be partially encapsulated to allow external electrical connections and/or thermal dissipation.
  • the devices depicted in any of FIGS. 2-11 may implement soldering, adhering, and/or encapsulation as described herein.
  • Capacitor 56 may be electrically connected to leadframe segments 54 A, 54 B.
  • Capacitor 56 may comprise one or more capacitors connected in parallel to function similar to a single capacitor. A first end of each capacitor of capacitor 56 may be electrically connected to leadframe segment 54 B, and a second end of each capacitor of capacitor 56 may be electrically connected to leadframe segment 54 A.
  • Each of leadframe segments 54 A, 54 B may be etched, carved, and/or drilled to remove a space for capacitor 56 to be positioned on top of each of leadframe segments 54 A, 54 B.
  • Leadframe segments 54 A, 54 B, as depicted in FIG. 2 may be referred to as “top-etched” because the etching, carving, or drilling may remove more of the top portions of leadframe segments 54 A, 54 B than the bottom portions of leadframe segments 54 A, 54 B.
  • Leadframe segments 54 A, 54 B as depicted in FIG.
  • Capacitor 56 may be positioned partially between transistors 52 A, 52 B, such that a portion of capacitor 56 may extend into the space between transistors 52 A, 52 B.
  • Capacitor 56 may reduce the ringing at conductive element 58 during transitions when one transistor of transistors 52 A, 52 B opens and the other transistor of transistors 52 A, 52 B closes.
  • the effectiveness of capacitor 56 between leadframe segments 54 A, 54 B may be based on the circumference of loop 57 including capacitor 56 , leadframe segments 54 A, 54 B, transistors 52 A, 52 B, and conductive element 58 .
  • device 50 may reduce distance 55 and the circumference of loop 57 .
  • loop 57 may include a distance from transistor 52 A through leadframe segment 54 A, capacitor 56 , and leadframe segment 54 B to transistor 52 B that is less than or equal to approximately one millimeter.
  • a distance in loop 57 may be measured by tracing an electrical path through each of the components in loop 57 .
  • FIG. 3 is a block diagram of a device 60 including a capacitor 66 on a bottom-etched leadframe 64 , in accordance with some examples of this disclosure.
  • Device 60 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 62 A, 62 B may be electrically connected to conductive element 68 , which may act as a switch node.
  • Transistor 62 A may also be electrically connected to leadframe segment 64 A, and transistor 62 B may be electrically connected to leadframe segment 64 B.
  • Capacitor 66 may be electrically connected to leadframe segments 64 A, 64 B.
  • Each of leadframe segments 64 A, 64 B may be etched, carved, and/or drilled to remove a space for capacitor 66 to be positioned on the bottom of each of leadframe segments 64 A, 64 B.
  • Leadframe segments 64 A, 64 B, as depicted in FIG. 3 may be referred to as “bottom-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 64 A, 64 B than the top portions of leadframe segments 64 A, 64 B.
  • Leadframe segments 64 A, 64 B as depicted in FIG.
  • soldering may include double-sided reflow to form the electrical connections for capacitor 66 .
  • each of leadframe segments 64 A, 64 B may have a thickness greater than one hundred micrometers and less than approximately three hundred micrometers.
  • the thickness of capacitor 66 may be greater than one hundred micrometers and less than approximately two hundred micrometers.
  • the thickness of a component may be measured in a vertical direction as depicted in FIG. 3 .
  • a distance from transistor 62 A to the end of capacitor 66 that is electrically connected to leadframe segment 64 A may be less than approximately four hundred micrometers.
  • a distance from transistor 62 B to the end of capacitor 66 that is electrically connected to leadframe segment 64 B may be less than approximately four hundred micrometers.
  • the distance may be as small as one hundred micrometers for two-hundred-micrometer half-etched leadframes.
  • the distance from one of transistors 62 A, 62 B to an end of capacitor 66 may be measured by tracing an electrical path through loop 67 that may include one of leadframe segments 64 A, 64 B.
  • a short distance from each of transistors 62 A, 62 B to the ends of capacitor 66 may reduce the effect of parasitics in loop 67 .
  • the distances described herein may apply to the devices in any of FIGS. 2-11 . As used herein, “approximately” may indicate a tolerance of ten percent for distances and dimensions.
  • each of leadframe segments 64 A, 64 B may be configured to attach to an optional printed circuit board (PCB) or an optional printed wiring board (PWB) (not shown in FIG. 3 ).
  • Capacitor 66 may be configured to attach to the PCB or the PWB.
  • Leadframe segments 64 A, 64 B and capacitor 66 may be electrically connected to traces in the PCB or the PWB.
  • Capacitor 66 may reduce the ringing at conductive element 68 during transitions when one transistor of transistors 62 A, 62 B opens and the other transistor of transistors 62 A, 62 B closes.
  • the effectiveness of capacitor 66 between leadframe segments 64 A, 64 B may be based on the circumference of loop 67 including capacitor 66 , leadframe segments 64 A, 64 B, transistors 62 A, 62 B, and conductive element 68 .
  • device 60 may reduce distance 65 and the circumference of loop 67 .
  • distance 65 may be shorter than distance 55 depicted in FIG. 2
  • the circumference of loop 67 may be shorter than the circumference of loop 57 depicted in FIG. 3 .
  • Loop 67 may include an inductance of less than approximately three hundred nanofarads.
  • loop 67 may include a distance from transistor 62 A through leadframe segment 64 A, capacitor 66 , and leadframe segment 64 B to transistor 62 B that is less than or equal to approximately one millimeter.
  • a distance in loop 67 may be measured by tracing an electrical path through each of the components in loop 67 . The distances described herein may apply to the devices in any of FIGS. 2-11 .
  • FIG. 4 is a diagram of a device 70 including a capacitor 76 on a top-etched leadframe 74 , in accordance with some examples of this disclosure.
  • Device 70 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 72 A, 72 B may be electrically connected to conductive element 78 , which may act as a switch node.
  • Transistor 72 A may also be electrically connected to leadframe segment 74 A, and transistor 72 B may be electrically connected to leadframe segment 74 B.
  • Capacitor 76 may be electrically connected to leadframe segments 74 A, 74 B. Electrically connecting an end of capacitor 76 to one of leadframe segments 74 A, 74 B may include etching a portion of one or both of leadframe segments 74 A, 74 B. Leadframe segments 74 A, 74 B, as depicted in FIG. 4 , may be referred to as “top-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 74 A, 74 B than the top portions of leadframe segments 74 A, 74 B. Leadframe segments 74 A, 74 B, as depicted in FIG.
  • Capacitor 76 may be positioned partially between transistors 72 A, 72 B, such that a portion of capacitor 76 may extend into the space between transistors 72 A, 72 B.
  • FIG. 5 is a diagram of a device 80 including a capacitor 86 on a leadframe 84 , in accordance with some examples of this disclosure.
  • Device 80 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 82 A, 82 B may be electrically connected to conductive element 88 , which may act as a switch node.
  • Transistor 82 A may also be electrically connected to leadframe segment 84 A, and transistor 82 B may be electrically connected to leadframe segment 84 B.
  • Capacitor 86 may be electrically connected to leadframe segments 84 A, 84 B, 84 D, 84 E.
  • Leadframe segments 84 A, 84 B as depicted in FIG.
  • top-etched and/or “bottom-etched” because the etching, carving, or drilling may remove bottom portions and top portions of leadframe segments 84 A, 84 B.
  • a distance between one of transistors 82 A, 82 B and an end of capacitor 86 may include an electrical path that does not necessarily include one of leadframe segments 84 A, 84 B.
  • FIG. 6 is a diagram of a device including a capacitor 96 on a bottom-etched leadframe 94 , in accordance with some examples of this disclosure.
  • Device 90 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 92 A, 92 B may be electrically connected to conductive element 98 , which may act as a switch node.
  • Transistor 92 A may also be electrically connected to leadframe segment 94 A, and transistor 92 B may be electrically connected to leadframe segment 94 B.
  • Capacitor 96 may be electrically connected to transistors 92 A, 92 B and leadframe segments 94 A, 94 B.
  • Leadframe segments 94 A, 94 B as depicted in FIG.
  • Leadframe segments 94 A, 94 B may also be referred to as “opposite-etched.”
  • FIG. 7 is a diagram of a device including a capacitor 106 on a bottom-etched leadframe 104 , in accordance with some examples of this disclosure.
  • Device 100 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 102 A, 102 B may be electrically connected to conductive element 108 , which may act as a switch node.
  • Transistor 102 A may also be electrically connected to leadframe segment 104 A, and transistor 102 B may be electrically connected to leadframe segment 104 B.
  • Capacitor 106 may be electrically connected to leadframe segments 104 A, 104 B.
  • Leadframe segments 104 A, 104 B as depicted in FIG.
  • Leadframe segments 104 A, 104 B may also be referred to as “opposite-etched.”
  • Capacitor 106 may be electrically connected to transistors 102 A, 102 B through conductive paths 110 A, 110 B.
  • conductive paths 110 A, 110 B may be pre-formed through leadframe segments 104 A, 104 B by first creating a hole in each of leadframe segments 104 A, 104 B and then placing or forming conductive paths 110 A, 110 B in the respective holes of leadframe segments 104 A, 104 B.
  • Conductive paths 110 A, 110 B may be formed through leadframe segments 104 A, 104 B by drilling, etching, or carving a hole or path through leadframe segments 104 A, 104 B and filling the hole or path with conductive material, such as copper or solder.
  • Conductive paths 110 A, 110 B may comprise the same conductive materials as the respective source terminal or drain terminal of transistors 102 A, 102 B and/or any other suitable conductive material. By using the same conductive material as the respective terminals of transistors 102 A, 102 B, the connection between conductive paths 110 A, 110 B and transistors 102 A, 102 B and capacitor 106 may not need soldering.
  • FIG. 8 is a side-view diagram of a device 120 including a discrete capacitor 126 A on a leadframe 128 , in accordance with some examples of this disclosure.
  • Device 120 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 122 A, 122 B may be electrically connected to conductive element 128 , which may act as a switch node.
  • Transistor 122 A may also be electrically connected to leadframe segment 124 A, and transistor 122 B may be electrically connected to leadframe segment 124 B.
  • Capacitor 126 A may be electrically connected to leadframe segments 124 A, 124 B.
  • FIG. 9 is a top-view diagram of a device 120 including discrete capacitors 126 A- 126 E on a leadframe 128 , in accordance with some examples of this disclosure.
  • Device 120 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Capacitors 126 A- 126 E may operate in parallel in a similar manner to a single capacitor. Positioning capacitors 126 A- 126 E in parallel may increase the effective width and capacitance of an equivalent capacitor.
  • FIG. 10 is a block diagram of a device 130 including an integrated capacitor 136 , in accordance with some examples of this disclosure.
  • Device 130 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 132 A, 132 B may be electrically connected to conductive element 138 , which may act as a switch node.
  • Transistor 132 A may also be electrically connected to leadframe segment 134 A, and transistor 132 B may be electrically connected to leadframe segment 134 B.
  • Integrated capacitor 136 may be electrically connected to leadframe segments 134 A, 134 B.
  • Transistor 132 B and integrated capacitor 136 may comprise a single piece of semiconductor material, such as silicon, and be referred to as an IC. In some examples, integrated capacitor 136 may provide benefits such as smaller space, fewer components, and reduced parasitics.
  • FIG. 11 is a block diagram of a device 140 including an integrated capacitor 146 , in accordance with some examples of this disclosure.
  • Device 140 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1 .
  • Transistors 142 A, 142 B may be electrically connected to conductive element 148 , which may act as a switch node.
  • Transistor 142 A may also be electrically connected to leadframe segment 144 A, and transistor 142 B may be electrically connected to leadframe segment 144 B.
  • Integrated capacitor 146 may be electrically connected to leadframe segments 144 A, 144 B.
  • Transistor 142 A and integrated capacitor 146 may comprise a single piece of semiconductor material, such as silicon, and be referred to as an IC.
  • integrated capacitor 146 may provide benefits such as smaller space, fewer components, and reduced parasitics. Integrated capacitor 146 may operate in a different manner than integrated capacitor 136 based on whether the capacitor is integrated with a source-down transistor or a drain-down transistor. In some examples, integrated capacitor 146 may reduce the parasitics in device 140 more effectively than integrated capacitor 136 may reduce the parasitics in device 130 because integrated capacitor 146 is integrated with source-down transistor 142 A.
  • the transistor dies may include a thickness of approximately sixty micrometers. In some examples, the transistor dies may be thicker or thinner, depending on the application.
  • the capacitor may include a height or thickness of approximately one hundred micrometers or one hundred and fifty micrometers and a length of approximately three hundred micrometers.
  • Each leadframe segment may include a thickness of approximately two hundred micrometers or two hundred and fifty micrometers.
  • a thicker leadframe segment may allow more etching to form a position for the capacitor, but thicker leadframe segments may be more expensive. For example, half-etching may remove one hundred micrometers or one hundred and fifty micrometers of thickness from the leadframe segment.
  • the dimensions described herein may be exemplary and are not intended to limit this disclosure to any particular application or applications.
  • the transistors may include control terminals, such as gate terminals.
  • FIGS. 2-11 may have not depicted the control terminals for the transistors, but the control terminals may be electrical connected to internal devices or external devices.
  • the control terminals may be electrically connected to one or more driver circuits that produce signals to control the operation of the transistors.
  • the one or more driver circuits may be positioned in or outside of the devices of FIGS. 2-11 .
  • FIG. 12 is a flowchart depicting a process 170 of constructing a circuit, in accordance with some examples of this disclosure.
  • Process 170 is described with reference to device 50 in FIG. 2 , although other components, such as devices 60 , 70 , 80 , 90 , 100 , 120 , 130 , and 140 in FIGS. 2-11 , may exemplify similar techniques.
  • Process 170 includes electrically connecting first transistor 52 A to first leadframe segment 54 A ( 172 ).
  • First transistor 52 A may comprise a high-side vertical power FET with a high-side source terminal facing up and a high-side drain terminal facing down. The drain terminal of first transistor 52 A may electrically connect to first leadframe segment 54 A.
  • First leadframe segment 54 A may comprise an input-voltage node.
  • Process 170 further includes electrically connecting second transistor 52 B to first leadframe segment 54 B ( 174 ).
  • Second transistor 52 B may comprise a low-side vertical power FET with a low-side source terminal facing down and a low-side drain terminal facing up.
  • the source terminal of second transistor 52 B may electrically connect to second leadframe segment 54 B.
  • Second leadframe segment 54 B may comprise a reference-voltage node.
  • Process 170 further includes electrically connecting conductive element 58 to first transistor 52 A and second transistor 52 B ( 176 ).
  • the high-side source terminal of first transistor 52 A may electrically connect to conductive element 58 .
  • the low-side drain terminal of first transistor 52 A may electrically connect to conductive element 58 .
  • conductive element 58 may act as a switch node in a half-bridge circuit configuration.
  • Process 170 further includes electrically connecting a first end of capacitor 56 to first leadframe segment 54 A ( 178 ).
  • the first end of capacitor 56 may comprise a high side of capacitor 56 that is electrically connected to an input-voltage node.
  • First leadframe segment 54 A may be top-etched if etching, carving, or drilling removes more of the top portion of first leadframe segment 54 A than the top portion of first leadframe segment 54 A.
  • Process 170 further includes electrically connecting a second end of capacitor 56 to second leadframe segment 54 B ( 180 ).
  • the second end of capacitor 56 may comprise a low side of capacitor 56 that is electrically connected to a reference-voltage node.
  • Second leadframe segment 54 B may be top-etched if etching, carving, or drilling removes more of the top portion of second leadframe segment 54 B than the top portion of second leadframe segment 54 B.
  • Loop 57 may comprise capacitor 56 , leadframe segments 54 A, 54 B, transistors 52 A, 52 B, and conductive element 58 .
  • the parasitics of loop 57 may be based at least in part on the length of the circumference of loop 57 . Shortening the circumference of loop 57 may reduce the effect of parasitics on the operation of device 50 .
  • a distance between the high-side drain terminal of transistor 52 A and the high side of capacitor 56 may be less than approximately four hundred micrometers.
  • a distance between the low-side source terminal of transistor 52 B and the low side of capacitor 56 may be less than approximately four hundred micrometers.
  • transistors 10 A, 10 B may be designed with lower breakdown voltages.
  • Transistors 10 A, 10 B may have lower drain-to-source resistance when each transistor is on due to the lower breakdown voltages.
  • the lower drain-to-source resistances may improve the performance of transistors 10 A, 10 B, allowing transistors 10 A, 10 B to conduct more current at the same voltages.
  • the lower drain-to-source resistances may also reduce the power consumption of transistors 10 A, 10 B.
  • FIG. 13 is a conceptual block diagram of other device 244 including two drain-down transistors 230 , 232 , in accordance with some examples of this disclosure.
  • Transistors 230 , 232 may each have a control terminal, such as gate terminals 230 G, 232 G, which may be connected to driver signals 234 A, 234 B from a driver circuit (not shown in FIG. 2 ).
  • Each of transistors 230 , 232 may comprise two load terminals, such as source terminals 230 S, 232 S and drain terminals 230 D, 232 D.
  • High-side transistor 230 may function in a manner similar to transistor 10 A in FIG. 1
  • low-side transistor 232 may function in a manner similar to transistor 10 B in FIG. 1 .
  • a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment.
  • the device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment.
  • the device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor.
  • the device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.
  • a source terminal of the first transistor is electrically connected to the conductive element
  • a drain terminal of the second transistor is electrically connected to the conductive element
  • a source terminal of the second transistor is electrically connected to the second leadframe segment
  • the conductive element comprises a clip or a wire.
  • the capacitor comprises at least one discrete capacitor, a first end of each capacitor of the at least one discrete capacitor is electrically connected to the first leadframe segment, and a second end of each capacitor of the at least one discrete capacitor is electrically connected to the second leadframe segment.
  • the first leadframe segment is configured to attach to a PCB
  • the second leadframe segment is configured to attach to the PCB
  • the capacitor is configured to attach to the PCB.
  • the device of any combination of examples 1-5 further comprising an electrical loop comprising the first transistor, the first leadframe segment, the capacitor, and the second leadframe segment, the second transistor, and the conductive element, wherein an inductance of the electrical loop is less than approximately three hundred nanofarads.
  • a distance from the first transistor to the first end of the capacitor is less than approximately four hundred micrometers, and a distance from the second transistor to the second end of the capacitor is less than approximately four hundred micrometers.
  • a method comprises electrically connecting a first transistor to a first leadframe segment, and electrically connecting a second transistor to a second leadframe segment.
  • the method further comprises electrically connecting a conductive element to the first transistor and the second transistor.
  • the method further comprises electrically connecting a first end of a capacitor to the first leadframe segment, and electrically connecting a second end of the capacitor to the second leadframe segment.
  • electrically connecting the first end of the capacitor to the first leadframe segment comprises etching a portion of the first leadframe segment opposite the first transistor; and electrically connecting the second end of the capacitor to the second leadframe segment comprises etching a portion of the second leadframe segment opposite the second transistor.
  • any combination of examples 9-11 forming a first conductive path through the first leadframe segment; and forming a second conductive path through the second leadframe segment, wherein electrically connecting the first end of the capacitor to the first leadframe segment further comprises electrically connecting the first end of the capacitor to the first conductive path, and electrically connecting the second end of the capacitor to the second leadframe segment further comprises electrically connecting the second end of the capacitor to the second conductive path.
  • electrically connecting the first transistor to the first leadframe segment comprises soldering the first transistor to the first leadframe segment
  • electrically connecting the second transistor to the second leadframe segment comprises soldering the second transistor to the second leadframe segment.
  • Electrically connecting the conductive element to the first transistor and the second transistor comprises soldering the conductive element to the first transistor and the second transistor
  • electrically connecting the first end of the capacitor to the first leadframe segment comprises soldering the first end of the capacitor to the first leadframe segment.
  • Electrically connecting a second end of the capacitor to the second leadframe segment comprises soldering the second end of the capacitor to the second leadframe segment.
  • a power converter device comprising an input-voltage leadframe segment, a reference-voltage leadframe segment, and a high-side transistor, wherein a high-side drain terminal of the high-side transistor is electrically connected to the input-voltage leadframe segment.
  • the power converter device further comprises a low-side transistor, wherein a low-side source terminal of the low-side transistor is electrically connected to the reference-voltage leadframe segment.
  • the power converter device further comprises a conductive element, wherein the conductive element is electrically connected to a high-side source terminal of the high-side transistor and a low-side drain terminal of the low-side transistor.
  • the power converter device further comprises a capacitor, wherein a high side of the capacitor is electrically connected to the input-voltage leadframe segment, a low side of the capacitor is electrically connected to the reference-voltage leadframe segment, a first distance between the high-side drain terminal and the high side of the capacitor is less than approximately four hundred micrometers, and.
  • the power converter device further comprises a second distance between the low-side source terminal and the low side of the capacitor is less than approximately four hundred micrometers.
  • the power converter device of example 19 further comprising an integrated circuit comprising the capacitor and the low-side transistor, wherein a third distance between the high-side transistor and the integrated circuit is less than two hundred micrometers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)

Abstract

In some examples, a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment. The device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment. The device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor. The device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.

Description

    TECHNICAL FIELD
  • This disclosure relates to semiconductor packaging, and more specifically, to semiconductor packages for power electronics.
  • BACKGROUND
  • A half-bridge circuit may include two analog devices or switches. Half-bridge circuits may be used in power supplies for motors, in rectifiers, and for power conversion. Each half-bridge circuit package has several contacts and may include several conductive paths to connect the contacts to each other and to external components.
  • A half-bridge circuit may experience ringing if the circuit is underdamped. The ringing may occur approximately when one device of the half-bridge circuit closes and the other device opens. One method for minimizing the impact of ringing is to reduce the turn-on times of the devices. Another method to minimize the ringing is to reduce the size of a package for the half-bridge circuit and implement a decoupling capacitor attached to the printed-circuit-board voltage input.
  • SUMMARY
  • This disclosure describes techniques for a device comprising a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment. The device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment. The device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor. The device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.
  • In some examples, a method comprises electrically connecting a first transistor to a first leadframe segment, and electrically connecting a second transistor to a second leadframe segment. The method further comprises electrically connecting a conductive element to the first transistor and the second transistor. The method further comprises electrically connecting a first end of a capacitor to the first leadframe segment, and electrically connecting a second end of the capacitor to the second leadframe segment.
  • In some examples, a power converter device comprises an input-voltage leadframe segment, a reference-voltage leadframe segment, and a high-side transistor, wherein a high-side drain terminal of the high-side transistor is electrically connected to the input-voltage leadframe segment. The power converter device further comprises a low-side transistor, wherein a low-side source terminal of the low-side transistor is electrically connected to the reference-voltage leadframe segment. The power converter device further comprises a conductive element, wherein the conductive element is electrically connected to a high-side source terminal of the high-side transistor and a low-side drain terminal of the low-side transistor. The power converter device further comprises a capacitor, wherein a high side of the capacitor is electrically connected to the input-voltage leadframe segment, a low side of the capacitor is electrically connected to the reference-voltage leadframe segment, a first distance between the high-side drain terminal and the high side of the capacitor is less than approximately four hundred micrometers, and a second distance between the low-side source terminal and the low side of the capacitor is less than approximately four hundred micrometers.
  • The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a circuit diagram of a half-bridge circuit including a capacitor between an input node and a reference node, in accordance with some examples of this disclosure.
  • FIG. 2 is a block diagram of a device including a capacitor on a top-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 3 is a block diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 4 is a diagram of a device including a capacitor on a top-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 5 is a diagram of a device including a capacitor on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 6 is a diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 7 is a diagram of a device including a capacitor on a bottom-etched leadframe, in accordance with some examples of this disclosure.
  • FIG. 8 is a side-view diagram of a device including a discrete capacitor on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 9 is a top-view diagram of a device including discrete capacitors on a leadframe, in accordance with some examples of this disclosure.
  • FIG. 10 is a block diagram of a device including an integrated capacitor, in accordance with some examples of this disclosure.
  • FIG. 11 is a block diagram of a device including an integrated capacitor, in accordance with some examples of this disclosure.
  • FIG. 12 is a flowchart depicting a process of constructing a circuit, in accordance with some examples of this disclosure.
  • FIG. 13 is a conceptual block diagram of device circuit including two drain-down transistors, in accordance with some examples of this disclosure.
  • DETAILED DESCRIPTION
  • A half-bridge circuit may include parasitic capacitances and parasitic inductances defined by the components and connections of the half-bridge circuit. A capacitor connected between the input-voltage node and the reference-voltage node may reduce the effect of parasitics on the half-bridge circuit. In some examples, the distance between each transistor of the half-bridge circuit and the capacitor may influence the effectiveness of the capacitor. In some examples, connecting the capacitor directly to the transistor leadframe segments may substantially improve the operation of the half-bridge circuit at high frequencies by reducing the ringing and resonant peaks that may occur when switching between transistors. By reducing the effect of parasitics in the half-bridge circuit, the circuit may be designed to include transistors with lower breakdown voltages, lower resistances, and lower power consumption, while maintaining or improving performance.
  • FIG. 1 is a circuit diagram of a half-bridge circuit including a capacitor 6 between an input node 8 and a reference node 16, in accordance with some examples of this disclosure. In some examples, power converter 2 may comprise a half-bridge direct-current-to-direct-current (DC-to-DC) buck converter for converting an input DC signal to an output DC signal with a lower voltage. As a DC-to-DC buck converter, power converter 2 may operate as a voltage regulator in a variety of applications. As a DC-to-DC buck converter, a voltage amplitude of an input DC signal may be higher than a voltage amplitude of an output DC signal. However, the techniques of this disclosure may apply to other circuits and configurations, such as other power converters, including multi-phase power converters.
  • Power converter 2 may include device 4, which may include an integrated circuit (IC) or discrete components. Power converter 2 may include transistors 10A, 10B, inductor 18, capacitor 22, and pulse-width modulation (PWM) control and driver 12. In some examples, power converter 2 may contain more or fewer components than the components depicted in FIG. 1. Power converter 2 may include input node 8, reference node 16, and output node 20, as well as other nodes not shown in FIG. 1. Nodes 8, 16, 20 may be configured to connect to external components. For example, input node 8 may connect to an input voltage such as a power supply, output node 20 may connect to an electronic device, reference node 16 may connect to a reference voltage, such as reference ground. In some examples, PWM control and driver 12 may connect to an external circuit to a node (not shown in FIG. 1).
  • Although, a MOSFET symbol is shown in FIG. 1 as transistors 10A, 10B, it is contemplated that any electrical device that is controlled by a voltage may be used in place of the MOSFET as shown. For example, transistors 10A, 10B may include, but not limited to, any type of field-effect transistor (FET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a high-electron-mobility transistor (HEMT), a gallium-nitride (GaN) based transistor, or another element that uses voltage for its control.
  • Transistors 10A, 10B may comprise n-type transistors or p-type transistors, and transistors 10A, 10B may comprise vertical power transistors. For a vertical power transistor, the source terminal and the drain terminal may be on opposite sides or opposite surfaces of the transistor. Current in a vertical power transistor may flow through the transistor from top to bottom or from bottom to top. In some examples, transistors 10A, 10B may comprise other analog devices such as diodes. Transistors 10A, 10B may also include freewheeling diodes connected in parallel with transistors to prevent reverse breakdown of transistors 10A, 10B. In some examples, transistors 10A, 10B may operate as switches or as analog devices. In still other examples, transistors 10 may include more than two transistors, such as in multi-phase power converters or other more complex power circuits. For example, in a multi-phase power converter, power converter 2 may have one high-side transistor and one low-side transistor for each phase. Therefore, a multi-phase power converter may include one or more replications of power converter 2 as depicted in FIG. 1.
  • FIG. 1 depicts transistors 10A, 10B with three terminals: drain (D), source (S), and gate (G). Current may flow between the drain and source of transistors 10A, 10B, based on the voltage at the gate. Current may flow from input node 8 to switch node 14, through the drain and source of transistor 10A, based on the voltage at the gate of transistor 10A. Current may flow from switch node 14 to reference node 16, through the drain and source of transistor 10B, based on the voltage at the gate of transistor 10B. Transistor 10A may comprise a high-side transistor, and transistor 10B may comprise a low-side transistor because transistor 10B is connected to reference node 16.
  • Transistors 10A, 10B may comprise various material compounds, such as silicon (Si), silicon carbide (SiC), Gallium Nitride (GaN), or any other combination of one or more semiconductor materials. To take advantage of higher power density requirements in some circuits, power converters may operate at higher frequencies. Improvements in magnetics and faster switching, such as Gallium Nitride (GaN) switches, may support higher frequency converters. These higher frequency circuits may require control signals to be sent with more precise timing than for lower frequency circuits.
  • PWM control and driver 12 may deliver signals and/or voltages to the control terminals of transistors 10A, 10B. FIG. 1 depicts PWM control and driver 12 as one component, but the PWM control circuit and the driver circuit may be separate components. In some examples, PWM control and driver 12, only the PWM control circuit, or only the driver circuit may be located outside of power converter 2 or outside of device 4.
  • Inductor 18 may comprise an optional coil inductor that is outside of device 4. Inductor 18 may connect to switch node 14 and output node 20. Inductor 18 may impede the flow of alternating-current (AC) electricity, while allowing DC electricity to flow between switch node 14 and output node 20.
  • Capacitors 6, 22 may comprise discrete capacitors, integrated silicon capacitors, film capacitors, electrolytic capacitors, ceramic capacitors, or any other suitable type of capacitors. Capacitor 6 may be inside of device 4, and capacitor 22 may be an optional component in power converter 2 outside of device 4. A first end of capacitor 6 may electrically connect to input node 8, and a second end of capacitor 6 may electrically connect to reference node 16, and capacitor 22 may connect to output node 20 and reference node 16. Capacitors 6, 22 may impede the flow of DC electricity, while allowing AC electricity to flow between nodes. Capacitor 22 may act as a smoothing capacitor for the voltage at output node 20 to moderate fluctuations in the voltage at output node 20.
  • In accordance with the techniques of this disclosure, capacitor 6 may reduce the ringing in loop 24 comprising input node 8, transistors 10A, 10B, switch node 14, and reference node 16. The ringing may be based on parasitic capacitances and parasitic inductances throughout device 4, such as at switch node 14 between transistors 10A, 10B. To remove the parasitic inductances at switch node 14, capacitor 6 may be electrically connected to the drain terminal of transistor 10A and the source terminal of transistor 10B. In some examples, the effectiveness of capacitor 6 in cancelling the parasitics may be based on the distance between the drain terminal of transistor 10A through capacitor 6 to the source terminal of transistor 10B. By reducing the circumference of loop 24, capacitor 6 may reduce or eliminate the ringing at switch node 14, thereby allowing faster switching speeds and lower power consumption for device 4 and power converter 2 in some examples.
  • By reducing the parasitics in device 4, transistors 10A, 10B may be designed with lower breakdown voltages because the resonant voltage peaks at switching may be reduced or eliminated. With lower breakdown voltages, transistors 10A, 10B may have lower drain-to-source resistance when each transistor is closed or conducting current. The lower drain-to-source resistances may improve the performance of transistors 10A, 10B, allowing transistors 10A, 10B to conduct more current at the same voltages. The lower drain-to-source resistances may also reduce the power consumption of transistors 10A, 10B.
  • FIG. 2 is a block diagram of a device 50 including a capacitor 56 on a top-etched leadframe 54A, 54B, in accordance with some examples of this disclosure. Device 50 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 52A, 52B may comprise discrete vertical transistors such as vertical power FETs. Current may travel from one side of each of transistors 52A, 52B to an opposite side of transistors 52A, 52B.
  • Transistors 52A, 52B may each have a control terminal and two load terminals. Each of the load terminals of transistors 52A, 52B may comprise a pad or area at the surface of transistors 52A, 52B to form external electrical connections. Transistor 52A may function as a high-side transistor in a manner similar to transistor 10A in FIG. 1, and transistor 52B may function as a low-side transistor in a manner similar to transistor 10B in FIG. 1. In some examples, transistors 52A, 52B may be MOSFETs, BJTs, IGBTs, and/or any suitable type of transistor. If transistors 52A, 52B are bipolar transistors, each control terminal may be a base and the load terminals may be emitters and collectors.
  • Transistors 52A, 52B may be electrically connected to conductive element 58, which may act as a switch node. Conductive element 58 may comprise a metallization layer, a clip, a ribbon, a die paddle, a wire bond, a copper pillar, a through-silicon via, and/or any other suitable conductive material. Transistor 52A may also be electrically connected to leadframe segment 54A, and transistor 52B may be electrically connected to leadframe segment 54B. Capacitor 56 may also be electrically connected to leadframe segments 54A and/or 54B. Conductive element 58 may be electrically connected to leadframe segment 54C. Leadframe segments 54A, 54B, 54C may comprise die paddles, metallization layers, and/or any other suitable conductive material. In some examples, device 50 may include embedded metal layers in addition to or instead of leadframe segments, such as in a high frequency fusion device. The embedded layers may include copper and/or any other suitable conductive material.
  • In some examples, the electrical connections between transistors 52A, 52B and conductive element 58 and between transistors 52A, 52B and leadframe segments 54A, 54B may be formed by soldering. The electrical connections between capacitor 56 and leadframe segments 54A, 54B may also be formed by soldering. Soldering components to form electrical connections may include placing solder between the components, applying heat to melt the solder, and allowing the solder to cool to form the electrical connection. The components of device 50 may also be glued or adhered together with conductive paste, conductive tape, conductive epoxy, and/or metal sintering. The connections between transistors 52A, 52B, leadframe segments 54A, 54B, conductive element 58 (depicted as shaded layers in FIG. 2) may include metalized plated laser vias, solder, and/or high-pressure/high-frequency metalized bonding such as diffusion bonding. Diffusion bonding may include direct bonding between transistors 52A, 52B, each of which may be a semiconductor die, and leadframe segments 54A, 54B and conductive element 58.
  • In some examples, device 50 may be fully or partially encapsulated in a molding compound and/or any other suitable insulating material. Transistors 52A, 52B, leadframe segments 54A, 54B, 54C, and capacitor 56 may be fully encapsulated, while conductive element 58 may be partially encapsulated to allow for thermal dissipation and/or electrical connection between conductive element 58 and an external device. In some examples, capacitor 56 may be partially encapsulated to allow external electrical connections and/or thermal dissipation. The devices depicted in any of FIGS. 2-11 may implement soldering, adhering, and/or encapsulation as described herein.
  • Capacitor 56 may be electrically connected to leadframe segments 54A, 54B. Capacitor 56 may comprise one or more capacitors connected in parallel to function similar to a single capacitor. A first end of each capacitor of capacitor 56 may be electrically connected to leadframe segment 54B, and a second end of each capacitor of capacitor 56 may be electrically connected to leadframe segment 54A.
  • Each of leadframe segments 54A, 54B may be etched, carved, and/or drilled to remove a space for capacitor 56 to be positioned on top of each of leadframe segments 54A, 54B. Leadframe segments 54A, 54B, as depicted in FIG. 2, may be referred to as “top-etched” because the etching, carving, or drilling may remove more of the top portions of leadframe segments 54A, 54B than the bottom portions of leadframe segments 54A, 54B. Leadframe segments 54A, 54B, as depicted in FIG. 2, may also be referred to as “adjacent-etched” because the top portion of leadframe segments 54A, 54B is adjacent to transistors 52A, 52B and the bottom portion of leadframe segments 54A, 54B is opposite of transistors 52A, 52B. Capacitor 56 may be positioned partially between transistors 52A, 52B, such that a portion of capacitor 56 may extend into the space between transistors 52A, 52B.
  • Capacitor 56 may reduce the ringing at conductive element 58 during transitions when one transistor of transistors 52A, 52B opens and the other transistor of transistors 52A, 52B closes. The effectiveness of capacitor 56 between leadframe segments 54A, 54B may be based on the circumference of loop 57 including capacitor 56, leadframe segments 54A, 54B, transistors 52A, 52B, and conductive element 58. By positioning capacitor 56 between transistors 52A, 52B, device 50 may reduce distance 55 and the circumference of loop 57. In some examples, loop 57 may include a distance from transistor 52A through leadframe segment 54A, capacitor 56, and leadframe segment 54B to transistor 52B that is less than or equal to approximately one millimeter. A distance in loop 57 may be measured by tracing an electrical path through each of the components in loop 57.
  • FIG. 3 is a block diagram of a device 60 including a capacitor 66 on a bottom-etched leadframe 64, in accordance with some examples of this disclosure. Device 60 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 62A, 62B may be electrically connected to conductive element 68, which may act as a switch node. Transistor 62A may also be electrically connected to leadframe segment 64A, and transistor 62B may be electrically connected to leadframe segment 64B.
  • Capacitor 66 may be electrically connected to leadframe segments 64A, 64B. Each of leadframe segments 64A, 64B may be etched, carved, and/or drilled to remove a space for capacitor 66 to be positioned on the bottom of each of leadframe segments 64A, 64B. Leadframe segments 64A, 64B, as depicted in FIG. 3, may be referred to as “bottom-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 64A, 64B than the top portions of leadframe segments 64A, 64B. Leadframe segments 64A, 64B, as depicted in FIG. 3, may also be referred to as “opposite-etched” because the top portion of leadframe segments 64A, 64B is adjacent to transistors 62A, 62B and the bottom portion of leadframe segments 64A, 64B is opposite of transistors 62A, 62B. For devices including bottom-etched leadframe segments 64A, 64B and possibly other devices, soldering may include double-sided reflow to form the electrical connections for capacitor 66.
  • In some examples, each of leadframe segments 64A, 64B may have a thickness greater than one hundred micrometers and less than approximately three hundred micrometers. The thickness of capacitor 66 may be greater than one hundred micrometers and less than approximately two hundred micrometers. The thickness of a component may be measured in a vertical direction as depicted in FIG. 3. In some examples, a distance from transistor 62A to the end of capacitor 66 that is electrically connected to leadframe segment 64A may be less than approximately four hundred micrometers. A distance from transistor 62B to the end of capacitor 66 that is electrically connected to leadframe segment 64B may be less than approximately four hundred micrometers. In some examples, the distance may be as small as one hundred micrometers for two-hundred-micrometer half-etched leadframes. The distance from one of transistors 62A, 62B to an end of capacitor 66 may be measured by tracing an electrical path through loop 67 that may include one of leadframe segments 64A, 64B. A short distance from each of transistors 62A, 62B to the ends of capacitor 66 may reduce the effect of parasitics in loop 67. The distances described herein may apply to the devices in any of FIGS. 2-11. As used herein, “approximately” may indicate a tolerance of ten percent for distances and dimensions.
  • In some examples, each of leadframe segments 64A, 64B may be configured to attach to an optional printed circuit board (PCB) or an optional printed wiring board (PWB) (not shown in FIG. 3). Capacitor 66 may be configured to attach to the PCB or the PWB. Leadframe segments 64A, 64B and capacitor 66 may be electrically connected to traces in the PCB or the PWB.
  • Capacitor 66 may reduce the ringing at conductive element 68 during transitions when one transistor of transistors 62A, 62B opens and the other transistor of transistors 62A, 62B closes. The effectiveness of capacitor 66 between leadframe segments 64A, 64B may be based on the circumference of loop 67 including capacitor 66, leadframe segments 64A, 64B, transistors 62A, 62B, and conductive element 68. By positioning capacitor 66 between transistors 62A, 62B, device 60 may reduce distance 65 and the circumference of loop 67. In some examples, distance 65 may be shorter than distance 55 depicted in FIG. 2, and the circumference of loop 67 may be shorter than the circumference of loop 57 depicted in FIG. 3. Loop 67 may include an inductance of less than approximately three hundred nanofarads.
  • In some examples, loop 67 may include a distance from transistor 62A through leadframe segment 64A, capacitor 66, and leadframe segment 64B to transistor 62B that is less than or equal to approximately one millimeter. A distance in loop 67 may be measured by tracing an electrical path through each of the components in loop 67. The distances described herein may apply to the devices in any of FIGS. 2-11.
  • FIG. 4 is a diagram of a device 70 including a capacitor 76 on a top-etched leadframe 74, in accordance with some examples of this disclosure. Device 70 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 72A, 72B may be electrically connected to conductive element 78, which may act as a switch node. Transistor 72A may also be electrically connected to leadframe segment 74A, and transistor 72B may be electrically connected to leadframe segment 74B.
  • Capacitor 76 may be electrically connected to leadframe segments 74A, 74B. Electrically connecting an end of capacitor 76 to one of leadframe segments 74A, 74B may include etching a portion of one or both of leadframe segments 74A, 74B. Leadframe segments 74A, 74B, as depicted in FIG. 4, may be referred to as “top-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 74A, 74B than the top portions of leadframe segments 74A, 74B. Leadframe segments 74A, 74B, as depicted in FIG. 4, may also be referred to as “adjacent-etched” because the top portion of leadframe segments 74A, 74B is adjacent to transistors 72A, 72B and the bottom portion of leadframe segments 74A, 74B is opposite of transistors 72A, 72B. Capacitor 76 may be positioned partially between transistors 72A, 72B, such that a portion of capacitor 76 may extend into the space between transistors 72A, 72B.
  • FIG. 5 is a diagram of a device 80 including a capacitor 86 on a leadframe 84, in accordance with some examples of this disclosure. Device 80 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 82A, 82B may be electrically connected to conductive element 88, which may act as a switch node. Transistor 82A may also be electrically connected to leadframe segment 84A, and transistor 82B may be electrically connected to leadframe segment 84B. Capacitor 86 may be electrically connected to leadframe segments 84A, 84B, 84D, 84E. Leadframe segments 84A, 84B, as depicted in FIG. 5, may be referred to as “top-etched” and/or “bottom-etched” because the etching, carving, or drilling may remove bottom portions and top portions of leadframe segments 84A, 84B. As depicted in FIG. 5, a distance between one of transistors 82A, 82B and an end of capacitor 86 may include an electrical path that does not necessarily include one of leadframe segments 84A, 84B.
  • FIG. 6 is a diagram of a device including a capacitor 96 on a bottom-etched leadframe 94, in accordance with some examples of this disclosure. Device 90 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 92A, 92B may be electrically connected to conductive element 98, which may act as a switch node. Transistor 92A may also be electrically connected to leadframe segment 94A, and transistor 92B may be electrically connected to leadframe segment 94B. Capacitor 96 may be electrically connected to transistors 92A, 92B and leadframe segments 94A, 94B. Leadframe segments 94A, 94B, as depicted in FIG. 6, may be referred to as “bottom-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 94A, 94B than the top portions of leadframe segments 94A, 94B. Leadframe segments 94A, 94B, as depicted in FIG. 6, may also be referred to as “opposite-etched.”
  • FIG. 7 is a diagram of a device including a capacitor 106 on a bottom-etched leadframe 104, in accordance with some examples of this disclosure. Device 100 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 102A, 102B may be electrically connected to conductive element 108, which may act as a switch node. Transistor 102A may also be electrically connected to leadframe segment 104A, and transistor 102B may be electrically connected to leadframe segment 104B. Capacitor 106 may be electrically connected to leadframe segments 104A, 104B. Leadframe segments 104A, 104B, as depicted in FIG. 7, may be referred to as “bottom-etched” because the etching, carving, or drilling may remove more of the bottom portions of leadframe segments 104A, 104B than the top portions of leadframe segments 104A, 104B. Leadframe segments 104A, 104B, as depicted in FIG. 7, may also be referred to as “opposite-etched.”
  • Capacitor 106 may be electrically connected to transistors 102A, 102B through conductive paths 110A, 110B. In some examples, conductive paths 110A, 110B may be pre-formed through leadframe segments 104A, 104B by first creating a hole in each of leadframe segments 104A, 104B and then placing or forming conductive paths 110A, 110B in the respective holes of leadframe segments 104A, 104B. Conductive paths 110A, 110B may be formed through leadframe segments 104A, 104B by drilling, etching, or carving a hole or path through leadframe segments 104A, 104B and filling the hole or path with conductive material, such as copper or solder. Conductive paths 110A, 110B may comprise the same conductive materials as the respective source terminal or drain terminal of transistors 102A, 102B and/or any other suitable conductive material. By using the same conductive material as the respective terminals of transistors 102A, 102B, the connection between conductive paths 110A, 110B and transistors 102A, 102B and capacitor 106 may not need soldering.
  • FIG. 8 is a side-view diagram of a device 120 including a discrete capacitor 126A on a leadframe 128, in accordance with some examples of this disclosure. Device 120 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 122A, 122B may be electrically connected to conductive element 128, which may act as a switch node. Transistor 122A may also be electrically connected to leadframe segment 124A, and transistor 122B may be electrically connected to leadframe segment 124B. Capacitor 126A may be electrically connected to leadframe segments 124A, 124B.
  • FIG. 9 is a top-view diagram of a device 120 including discrete capacitors 126A-126E on a leadframe 128, in accordance with some examples of this disclosure. Device 120 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Capacitors 126A-126E may operate in parallel in a similar manner to a single capacitor. Positioning capacitors 126A-126E in parallel may increase the effective width and capacitance of an equivalent capacitor.
  • FIG. 10 is a block diagram of a device 130 including an integrated capacitor 136, in accordance with some examples of this disclosure. Device 130 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 132A, 132B may be electrically connected to conductive element 138, which may act as a switch node. Transistor 132A may also be electrically connected to leadframe segment 134A, and transistor 132B may be electrically connected to leadframe segment 134B. Integrated capacitor 136 may be electrically connected to leadframe segments 134A, 134B. Transistor 132B and integrated capacitor 136 may comprise a single piece of semiconductor material, such as silicon, and be referred to as an IC. In some examples, integrated capacitor 136 may provide benefits such as smaller space, fewer components, and reduced parasitics.
  • FIG. 11 is a block diagram of a device 140 including an integrated capacitor 146, in accordance with some examples of this disclosure. Device 140 may operate as a half-bridge circuit in a manner similar to device 4 depicted in FIG. 1. Transistors 142A, 142B may be electrically connected to conductive element 148, which may act as a switch node. Transistor 142A may also be electrically connected to leadframe segment 144A, and transistor 142B may be electrically connected to leadframe segment 144B. Integrated capacitor 146 may be electrically connected to leadframe segments 144A, 144B. Transistor 142A and integrated capacitor 146 may comprise a single piece of semiconductor material, such as silicon, and be referred to as an IC. In some examples, integrated capacitor 146 may provide benefits such as smaller space, fewer components, and reduced parasitics. Integrated capacitor 146 may operate in a different manner than integrated capacitor 136 based on whether the capacitor is integrated with a source-down transistor or a drain-down transistor. In some examples, integrated capacitor 146 may reduce the parasitics in device 140 more effectively than integrated capacitor 136 may reduce the parasitics in device 130 because integrated capacitor 146 is integrated with source-down transistor 142A.
  • For the devices in any of FIGS. 2-11, the transistor dies may include a thickness of approximately sixty micrometers. In some examples, the transistor dies may be thicker or thinner, depending on the application. The capacitor may include a height or thickness of approximately one hundred micrometers or one hundred and fifty micrometers and a length of approximately three hundred micrometers. Each leadframe segment may include a thickness of approximately two hundred micrometers or two hundred and fifty micrometers. A thicker leadframe segment may allow more etching to form a position for the capacitor, but thicker leadframe segments may be more expensive. For example, half-etching may remove one hundred micrometers or one hundred and fifty micrometers of thickness from the leadframe segment. The dimensions described herein may be exemplary and are not intended to limit this disclosure to any particular application or applications.
  • For the devices in any of FIGS. 2-11, the transistors may include control terminals, such as gate terminals. FIGS. 2-11 may have not depicted the control terminals for the transistors, but the control terminals may be electrical connected to internal devices or external devices. The control terminals may be electrically connected to one or more driver circuits that produce signals to control the operation of the transistors. The one or more driver circuits may be positioned in or outside of the devices of FIGS. 2-11.
  • FIG. 12 is a flowchart depicting a process 170 of constructing a circuit, in accordance with some examples of this disclosure. Process 170 is described with reference to device 50 in FIG. 2, although other components, such as devices 60, 70, 80, 90, 100, 120, 130, and 140 in FIGS. 2-11, may exemplify similar techniques.
  • Process 170 includes electrically connecting first transistor 52A to first leadframe segment 54A (172). First transistor 52A may comprise a high-side vertical power FET with a high-side source terminal facing up and a high-side drain terminal facing down. The drain terminal of first transistor 52A may electrically connect to first leadframe segment 54A. First leadframe segment 54A may comprise an input-voltage node.
  • Process 170 further includes electrically connecting second transistor 52B to first leadframe segment 54B (174). Second transistor 52B may comprise a low-side vertical power FET with a low-side source terminal facing down and a low-side drain terminal facing up. The source terminal of second transistor 52B may electrically connect to second leadframe segment 54B. Second leadframe segment 54B may comprise a reference-voltage node.
  • Process 170 further includes electrically connecting conductive element 58 to first transistor 52A and second transistor 52B (176). The high-side source terminal of first transistor 52A may electrically connect to conductive element 58. The low-side drain terminal of first transistor 52A may electrically connect to conductive element 58. In some examples, conductive element 58 may act as a switch node in a half-bridge circuit configuration.
  • Process 170 further includes electrically connecting a first end of capacitor 56 to first leadframe segment 54A (178). The first end of capacitor 56 may comprise a high side of capacitor 56 that is electrically connected to an input-voltage node. First leadframe segment 54A may be top-etched if etching, carving, or drilling removes more of the top portion of first leadframe segment 54A than the top portion of first leadframe segment 54A.
  • Process 170 further includes electrically connecting a second end of capacitor 56 to second leadframe segment 54B (180). The second end of capacitor 56 may comprise a low side of capacitor 56 that is electrically connected to a reference-voltage node. Second leadframe segment 54B may be top-etched if etching, carving, or drilling removes more of the top portion of second leadframe segment 54B than the top portion of second leadframe segment 54B.
  • Loop 57 may comprise capacitor 56, leadframe segments 54A, 54B, transistors 52A, 52B, and conductive element 58. The parasitics of loop 57 may be based at least in part on the length of the circumference of loop 57. Shortening the circumference of loop 57 may reduce the effect of parasitics on the operation of device 50. In some examples, a distance between the high-side drain terminal of transistor 52A and the high side of capacitor 56 may be less than approximately four hundred micrometers. In some examples, a distance between the low-side source terminal of transistor 52B and the low side of capacitor 56 may be less than approximately four hundred micrometers.
  • With reduced parasitics in device 4, transistors 10A, 10B may be designed with lower breakdown voltages. Transistors 10A, 10B may have lower drain-to-source resistance when each transistor is on due to the lower breakdown voltages. The lower drain-to-source resistances may improve the performance of transistors 10A, 10B, allowing transistors 10A, 10B to conduct more current at the same voltages. The lower drain-to-source resistances may also reduce the power consumption of transistors 10A, 10B.
  • FIG. 13 is a conceptual block diagram of other device 244 including two drain-down transistors 230, 232, in accordance with some examples of this disclosure. Transistors 230, 232 may each have a control terminal, such as gate terminals 230G, 232G, which may be connected to driver signals 234A, 234B from a driver circuit (not shown in FIG. 2). Each of transistors 230, 232 may comprise two load terminals, such as source terminals 230S, 232S and drain terminals 230D, 232D. High-side transistor 230 may function in a manner similar to transistor 10A in FIG. 1, and low-side transistor 232 may function in a manner similar to transistor 10B in FIG. 1. In some examples, transistors 230, 232 may be MOSFETs, BJTs, IGBTs, and/or any suitable type of transistor. Transistors 230, 232 may be configured such that source terminal 230S is electrically connected to drain terminal 232D by switch node 238.
  • Capacitor 242 may reduce the ringing at switch node 238 during transitions when one transistor of transistors 230, 232 opens and the other transistor closes. The effectiveness of capacitor 242 between input node 236 and reference node 240 may be based on the circumference of loop 246 including capacitor 242, input node 236, high-side transistor 230, switch node 238, low-side transistor 232, and reference node 240. By implementing two drain-down transistors 230, 232, loop 246 may have a longer circumference and may experience more ringing than the loops in the devices depicted in FIGS. 2-11. Therefore, capacitor 242 and device 244 may be less effective at reducing the ringing at switch node 238 than the devices depicted in FIGS. 2-11.
  • The following numbered examples demonstrate one or more aspects of the disclosure.
  • Example 1
  • A device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is electrically connected to the first leadframe segment. The device further comprises a second transistor, wherein the second transistor is electrically connected to the second leadframe segment. The device further comprises a conductive element, wherein the conductive element is electrically connected to the first transistor and the second transistor. The device further comprises a capacitor, wherein a first end of the capacitor is electrically connected to the first leadframe segment and a second end of the capacitor is electrically connected to the second leadframe segment.
  • Example 2
  • The device of example 1, further comprising an integrated circuit comprising the capacitor and the first transistor, wherein a drain terminal of the first transistor is electrically connected to the first leadframe segment. A source terminal of the first transistor is electrically connected to the conductive element, a drain terminal of the second transistor is electrically connected to the conductive element, a source terminal of the second transistor is electrically connected to the second leadframe segment, the conductive element comprises a clip or a wire.
  • Example 3
  • The device of any combination of examples 1-2, wherein the capacitor comprises at least one discrete capacitor, a first end of each capacitor of the at least one discrete capacitor is electrically connected to the first leadframe segment, and a second end of each capacitor of the at least one discrete capacitor is electrically connected to the second leadframe segment.
  • Example 4
  • The device of any combination of examples 1-3, wherein the first leadframe segment is configured to attach to a PCB, the second leadframe segment is configured to attach to the PCB, and the capacitor is configured to attach to the PCB.
  • Example 5
  • The device of any combination of examples 1-4, wherein a distance from the first transistor to the second transistor through the first leadframe segment, the capacitor, and the second leadframe segment is less than or equal to approximately one millimeter.
  • Example 6
  • The device of any combination of examples 1-5, further comprising an electrical loop comprising the first transistor, the first leadframe segment, the capacitor, and the second leadframe segment, the second transistor, and the conductive element, wherein an inductance of the electrical loop is less than approximately three hundred nanofarads.
  • Example 7
  • The device of any combination of examples 1-6, wherein a thickness of the first leadframe segment is greater than one hundred micrometers and less than approximately three hundred micrometers, a thickness of the second leadframe segment is greater than one hundred micrometers and less than approximately three hundred micrometers, and a thickness of the capacitor is greater than one hundred micrometers and less than approximately two hundred micrometers.
  • Example 8
  • The device of any combination of examples 1-7, wherein a distance from the first transistor to the first end of the capacitor is less than approximately four hundred micrometers, and a distance from the second transistor to the second end of the capacitor is less than approximately four hundred micrometers.
  • Example 9
  • A method comprises electrically connecting a first transistor to a first leadframe segment, and electrically connecting a second transistor to a second leadframe segment. The method further comprises electrically connecting a conductive element to the first transistor and the second transistor. The method further comprises electrically connecting a first end of a capacitor to the first leadframe segment, and electrically connecting a second end of the capacitor to the second leadframe segment.
  • Example 10
  • The method of example 9, wherein electrically connecting the first end of the capacitor to the first leadframe segment comprises etching a portion of the first leadframe segment adjacent to the first transistor; and electrically connecting the second end of the capacitor to the second leadframe segment comprises etching a portion of the second leadframe segment adjacent to the second transistor.
  • Example 11
  • The method of any combination of examples 9 and 10, electrically connecting the first end of the capacitor to the first leadframe segment comprises etching a portion of the first leadframe segment opposite the first transistor; and electrically connecting the second end of the capacitor to the second leadframe segment comprises etching a portion of the second leadframe segment opposite the second transistor.
  • Example 12
  • The method of any combination of examples 9-11, forming a first conductive path through the first leadframe segment; and forming a second conductive path through the second leadframe segment, wherein electrically connecting the first end of the capacitor to the first leadframe segment further comprises electrically connecting the first end of the capacitor to the first conductive path, and electrically connecting the second end of the capacitor to the second leadframe segment further comprises electrically connecting the second end of the capacitor to the second conductive path.
  • Example 13
  • The method of any combination of examples 9-12, wherein the first conductive path comprises solder, and the second conductive path comprises solder.
  • Example 14
  • The method of any combination of examples 9-13, encapsulating the first transistor, the second transistor, the first leadframe segment, the second leadframe segment, and the conductive element in a molding compound, and partially encapsulating the capacitor in the molding compound.
  • Example 15
  • The method of any combination of examples 9-14, further comprising attaching the first leadframe segment to a printed circuit board (PCB), and attaching the second leadframe segment to the PCB; and attaching the capacitor to the PCB.
  • Example 16
  • The method of any combination of examples 9-15, wherein electrically connecting the first transistor to the first leadframe segment comprises soldering the first transistor to the first leadframe segment, and electrically connecting the second transistor to the second leadframe segment comprises soldering the second transistor to the second leadframe segment. Electrically connecting the conductive element to the first transistor and the second transistor comprises soldering the conductive element to the first transistor and the second transistor, and electrically connecting the first end of the capacitor to the first leadframe segment comprises soldering the first end of the capacitor to the first leadframe segment. Electrically connecting a second end of the capacitor to the second leadframe segment comprises soldering the second end of the capacitor to the second leadframe segment.
  • Example 17
  • The method of any combination of examples 9-16, wherein a first distance between the first transistor and the first end of the capacitor is less than approximately four hundred micrometers; and a second distance between the second transistor and the second end of the capacitor is less than approximately four hundred micrometers.
  • Example 18
  • The method of any combination of examples 9-17, wherein a distance from the first transistor through the first leadframe segment, the capacitor, and the second leadframe segment to the second transistor is less than or equal to approximately one millimeter.
  • Example 19
  • A power converter device comprising an input-voltage leadframe segment, a reference-voltage leadframe segment, and a high-side transistor, wherein a high-side drain terminal of the high-side transistor is electrically connected to the input-voltage leadframe segment. The power converter device further comprises a low-side transistor, wherein a low-side source terminal of the low-side transistor is electrically connected to the reference-voltage leadframe segment. The power converter device further comprises a conductive element, wherein the conductive element is electrically connected to a high-side source terminal of the high-side transistor and a low-side drain terminal of the low-side transistor. The power converter device further comprises a capacitor, wherein a high side of the capacitor is electrically connected to the input-voltage leadframe segment, a low side of the capacitor is electrically connected to the reference-voltage leadframe segment, a first distance between the high-side drain terminal and the high side of the capacitor is less than approximately four hundred micrometers, and. The power converter device further comprises a second distance between the low-side source terminal and the low side of the capacitor is less than approximately four hundred micrometers.
  • Example 20
  • The power converter device of example 19, further comprising an integrated circuit comprising the capacitor and the low-side transistor, wherein a third distance between the high-side transistor and the integrated circuit is less than two hundred micrometers.
  • Various examples of the disclosure have been described. Any combination of the described systems, operations, or functions is contemplated. These and other examples are within the scope of the following claims.

Claims (20)

1: A device comprising:
a first transistor;
a second transistor;
a first leadframe segment positioned on a first side of the first transistor and electrically connected to the first transistor;
a second leadframe segment positioned on a first side of the second transistor and electrically connected to the second transistor, wherein the first side of the first transistor and the first side of the second transistor are a same side;
a conductive element positioned on a second side of the first transistor and positioned on a second side of the second transistor, wherein the second side of the first transistor and the second side of the second transistor are a same side, and wherein the conductive element is electrically connected to the first transistor and the second transistor; and
a capacitor, wherein:
a first end of the capacitor is electrically connected to the first leadframe segment, and
a second end of the capacitor is electrically connected to the second leadframe segment.
2: The device of claim 1, further comprising an integrated circuit comprising the capacitor and the first transistor, wherein:
a drain terminal on the first side of the first transistor is electrically connected to the first leadframe segment;
a source terminal on the second side of the first transistor is electrically connected to the conductive element;
a drain terminal on the second side of the second transistor is electrically connected to the conductive element;
a source terminal on the first side of the second transistor is electrically connected to the second leadframe segment; and
the conductive element comprises a clip or a wire.
3: The device of claim 1, wherein:
the capacitor comprises at least one discrete capacitor;
a first end of each capacitor of the at least one discrete capacitor is electrically connected to the first leadframe segment; and
a second end of each capacitor of the at least one discrete capacitor is electrically connected to the second leadframe segment.
4: The device of claim 3, wherein:
the first leadframe segment is configured to attach to a printed circuit board (PCB);
the second leadframe segment is configured to attach to the PCB; and
the capacitor is configured to attach to the PCB.
5: The device of claim 1, wherein a distance from the first transistor to the second transistor through the first leadframe segment, the capacitor, and the second leadframe segment is less than or equal to approximately one millimeter.
6: The device of claim 1, further comprising an electrical loop comprising the first transistor, the first leadframe segment, the capacitor, and the second leadframe segment, the second transistor, and the conductive element, wherein an inductance of the electrical loop is less than approximately three hundred nanofarads.
7: The device of claim 1, wherein:
a thickness of the first leadframe segment is greater than one hundred micrometers and less than approximately three hundred micrometers;
a thickness of the second leadframe segment is greater than one hundred micrometers and less than approximately three hundred micrometers; and
a thickness of the capacitor is greater than one hundred micrometers and less than approximately two hundred micrometers.
8: The device of claim 1, wherein:
a distance from the first transistor to the first end of the capacitor is less than approximately four hundred micrometers; and
a distance from the second transistor to the second end of the capacitor is less than approximately four hundred micrometers.
9: A method comprising:
electrically connecting a first transistor to a first leadframe segment positioned on a first side of the first transistor;
electrically connecting a second transistor to a second leadframe segment positioned on a first side of the second transistor, wherein the first side of the first transistor and the first side of the second transistor are a same side;
electrically connecting a conductive element to the first transistor and the second transistor, wherein the conductive element is positioned on a second side of the first transistor and positioned on a second side of the second transistor, wherein the second side of the first transistor and the second side of the second transistor are a same side;
electrically connecting a first end of a capacitor to the first leadframe segment; and
electrically connecting a second end of the capacitor to the second leadframe segment.
10: The method of claim 9, wherein:
electrically connecting the first end of the capacitor to the first leadframe segment comprises etching a portion of the first leadframe segment adjacent to the first transistor; and
electrically connecting the second end of the capacitor to the second leadframe segment comprises etching a portion of the second leadframe segment adjacent to the second transistor.
11: The method of claim 9, wherein:
electrically connecting the first end of the capacitor to the first leadframe segment comprises etching a portion of the first leadframe segment opposite the first transistor; and
electrically connecting the second end of the capacitor to the second leadframe segment comprises etching a portion of the second leadframe segment opposite the second transistor.
12: The method of claim 11, further comprising:
forming a first conductive path through the first leadframe segment; and
forming a second conductive path through the second leadframe segment, wherein:
electrically connecting the first end of the capacitor to the first leadframe segment further comprises electrically connecting the first end of the capacitor to the first conductive path, and
electrically connecting the second end of the capacitor to the second leadframe segment further comprises electrically connecting the second end of the capacitor to the second conductive path.
13: The method of claim 12, wherein:
the first conductive path comprises solder; and
the second conductive path comprises solder.
14: The method of claim 11, further comprising:
encapsulating the first transistor, the second transistor, the first leadframe segment, the second leadframe segment, and the conductive element in a molding compound; and
partially encapsulating the capacitor in the molding compound.
15: The method of claim 14, further comprising:
attaching the first leadframe segment to a printed circuit board (PCB);
attaching the second leadframe segment to the PCB; and
attaching the capacitor to the PCB.
16: The method of claim 9, wherein:
electrically connecting the first transistor to the first leadframe segment comprises soldering the first side of the first transistor to the first leadframe segment;
electrically connecting the second transistor to the second leadframe segment comprises soldering the first side of the second transistor to the second leadframe segment;
electrically connecting the conductive element to the first transistor and the second transistor comprises soldering the conductive element to the second side of the first transistor and the second side of the second transistor;
electrically connecting the first end of the capacitor to the first leadframe segment comprises soldering the first end of the capacitor to the first leadframe segment; and
electrically connecting a second end of the capacitor to the second leadframe segment comprises soldering the second end of the capacitor to the second leadframe segment.
17: The method of claim 9, wherein:
a first distance between the first transistor and the first end of the capacitor is less than approximately four hundred micrometers; and
a second distance between the second transistor and the second end of the capacitor is less than approximately four hundred micrometers.
18: The method of claim 9, wherein a distance from the first transistor through the first leadframe segment, the capacitor, and the second leadframe segment to the second transistor is less than or equal to approximately one millimeter.
19: A power converter device comprising:
a high-side transistor;
an input-voltage leadframe segment positioned on a first side of the high-side transistor, wherein a high-side drain terminal on the first side of the high-side transistor is electrically connected to the input-voltage leadframe segment;
a low-side transistor;
a reference-voltage leadframe segment positioned on a first side of the low-side transistor, wherein a low-side source terminal on the first side of the low-side transistor is electrically connected to the reference-voltage leadframe segment, and wherein the first side of the high-side transistor and the first side of the low-side transistor are a same side;
a conductive element positioned on a second side of the high-side transistor and positioned on a second side of the low-side transistor, wherein the second side of the high-side transistor and the second side of the low-side transistor are a same side, and wherein the conductive element is electrically connected to a high-side source terminal on the second side of the high-side transistor and a low-side drain terminal on the second side of the low-side transistor; and
a capacitor, wherein:
a high side of the capacitor is electrically connected to the input-voltage leadframe segment,
a low side of the capacitor is electrically connected to the reference-voltage leadframe segment,
a first distance between the high-side drain terminal and the high side of the capacitor is less than approximately four hundred micrometers, and
a second distance between the low-side source terminal and the low side of the capacitor is less than approximately four hundred micrometers.
20: The system of claim 19, further comprising an integrated circuit comprising the capacitor and the low-side transistor, wherein a third distance between the high-side transistor and the integrated circuit is less than two hundred micrometers.
US15/258,819 2016-09-07 2016-09-07 Package for die-bridge capacitor Active US9922912B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/258,819 US9922912B1 (en) 2016-09-07 2016-09-07 Package for die-bridge capacitor
DE102017215480.2A DE102017215480A1 (en) 2016-09-07 2017-09-04 Package for the bridge-capacitor
CN201710795026.3A CN107799511A (en) 2016-09-07 2017-09-06 Packaging body for chip bridge capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/258,819 US9922912B1 (en) 2016-09-07 2016-09-07 Package for die-bridge capacitor

Publications (2)

Publication Number Publication Date
US20180068934A1 true US20180068934A1 (en) 2018-03-08
US9922912B1 US9922912B1 (en) 2018-03-20

Family

ID=61198275

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/258,819 Active US9922912B1 (en) 2016-09-07 2016-09-07 Package for die-bridge capacitor

Country Status (3)

Country Link
US (1) US9922912B1 (en)
CN (1) CN107799511A (en)
DE (1) DE102017215480A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190287884A1 (en) * 2018-03-13 2019-09-19 Semiconductor Components Industries, Llc Multi-chip packages with stabilized die pads
US10892209B2 (en) * 2019-03-25 2021-01-12 Texas Instruments Incorporated Semiconductor device with metal die attach to substrate with multi-size cavity
US20220093573A1 (en) * 2020-09-24 2022-03-24 Infineon Technologies Austria Ag Semiconductor module

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190287881A1 (en) 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
US10593612B2 (en) * 2018-03-19 2020-03-17 Stmicroelectronics S.R.L. SMDs integration on QFN by 3D stacked solution
DE102018107094B4 (en) 2018-03-26 2021-04-15 Infineon Technologies Austria Ag Multi-package top cooling and process for its manufacture
CN113098234B (en) 2020-01-08 2022-11-01 台达电子企业管理(上海)有限公司 Power supply system
DE102020119611A1 (en) 2020-07-24 2022-01-27 Infineon Technologies Ag CIRCUIT ARRANGEMENT AND METHOD OF FORMING CIRCUIT ARRANGEMENT

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124616A (en) 2000-10-13 2002-04-26 Aisan Ind Co Ltd Chip-component mounting structure on lead frame
JP2004296624A (en) 2003-03-26 2004-10-21 Sanken Electric Co Ltd Semiconductor device
US7005325B2 (en) 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration
US20080013298A1 (en) 2006-07-14 2008-01-17 Nirmal Sharma Methods and apparatus for passive attachment of components for integrated circuits
JP2009182022A (en) 2008-01-29 2009-08-13 Renesas Technology Corp Semiconductor device
CN103646942B (en) * 2010-02-25 2016-01-13 万国半导体有限公司 Semiconductor packaging structure applied to power switcher circuit
CN102064161B (en) * 2010-11-12 2013-09-04 嘉兴斯达微电子有限公司 Optimized power package structure of intelligent power module
US8269330B1 (en) * 2011-04-22 2012-09-18 Cyntec Co., Ltd. MOSFET pair with stack capacitor and manufacturing method thereof
US9397212B2 (en) * 2012-10-18 2016-07-19 Infineon Technologies Americas Corp. Power converter package including top-drain configured power FET
US8916474B2 (en) * 2013-02-18 2014-12-23 Infineon Technologies Ag Semiconductor modules and methods of formation thereof
US9780018B2 (en) * 2014-12-16 2017-10-03 Infineon Technologies Americas Corp. Power semiconductor package having reduced form factor and increased current carrying capability
CN106340513B (en) * 2015-07-09 2019-03-15 台达电子工业股份有限公司 A kind of power module of integral control circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190287884A1 (en) * 2018-03-13 2019-09-19 Semiconductor Components Industries, Llc Multi-chip packages with stabilized die pads
US10438877B1 (en) * 2018-03-13 2019-10-08 Semiconductor Components Industries, Llc Multi-chip packages with stabilized die pads
US10892209B2 (en) * 2019-03-25 2021-01-12 Texas Instruments Incorporated Semiconductor device with metal die attach to substrate with multi-size cavity
US11908776B2 (en) 2019-03-25 2024-02-20 Texas Instruments Incorporated Semiconductor device with metal die attach to substrate with multi-size cavity
US20220093573A1 (en) * 2020-09-24 2022-03-24 Infineon Technologies Austria Ag Semiconductor module
US11817430B2 (en) * 2020-09-24 2023-11-14 Infineon Technologies Austria Ag Semiconductor module
US12087740B2 (en) 2020-09-24 2024-09-10 Infineon Technologies Austria Ag Method of forming a semiconductor module

Also Published As

Publication number Publication date
US9922912B1 (en) 2018-03-20
CN107799511A (en) 2018-03-13
DE102017215480A1 (en) 2018-03-08

Similar Documents

Publication Publication Date Title
US9922912B1 (en) Package for die-bridge capacitor
US10784213B2 (en) Power device package
CN107769520B (en) Electric device and method for manufacturing the same
US10204847B2 (en) Multi-phase common contact package
CN107768342B (en) Power switch package with pre-formed electrical connections for connecting an inductor to one or more transistors
US20170221798A1 (en) Compact multi-die power semiconductor package
US9299690B2 (en) Method for fabricating a power semiconductor package including vertically stacked driver IC
US10147703B2 (en) Semiconductor package for multiphase circuitry device
US10490505B2 (en) Single-sided power device package
CN107769555B (en) Power converter with at least five electrical connections on one side
US8582317B2 (en) Method for manufacturing a semiconductor component and structure therefor
US10573631B2 (en) Multi-phase power converter with common connections
US11990455B2 (en) Semiconductor device
US9754862B2 (en) Compound semiconductor device including a multilevel carrier
US10128173B2 (en) Common contact leadframe for multiphase applications
US11387179B2 (en) IC package with half-bridge power module
US9866213B1 (en) High voltage switch module
CN108323211B (en) Power device package

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHO, EUNG SAN;CLAVETTE, DANNY;GALIPEAU, DARRYL;SIGNING DATES FROM 20160906 TO 20160907;REEL/FRAME:039663/0301

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4