US20180068845A1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
US20180068845A1
US20180068845A1 US15/811,282 US201715811282A US2018068845A1 US 20180068845 A1 US20180068845 A1 US 20180068845A1 US 201715811282 A US201715811282 A US 201715811282A US 2018068845 A1 US2018068845 A1 US 2018068845A1
Authority
US
United States
Prior art keywords
exposure
resist layer
wafer edge
wafer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/811,282
Inventor
Takuya Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US15/811,282 priority Critical patent/US20180068845A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAGIWARA, TAKUYA
Publication of US20180068845A1 publication Critical patent/US20180068845A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70341—Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
    • G03F7/0392—Macromolecular compounds which are photodegradable, e.g. positive electron resists the macromolecular compound being present in a chemically amplified positive photoresist composition
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/2026—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction
    • G03F7/2028—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction of an edge bead on wafers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2041—Exposure; Apparatus therefor in the presence of a fluid, e.g. immersion; using fluid cooling means
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2041—Exposure; Apparatus therefor in the presence of a fluid, e.g. immersion; using fluid cooling means
    • G03F7/2043—Exposure; Apparatus therefor in the presence of a fluid, e.g. immersion; using fluid cooling means with the production of a chemical active agent from a fluid, e.g. an etching agent; with meterial deposition from the fluid phase, e.g. contamination resists
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/32—Liquid compositions therefor, e.g. developers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/32—Liquid compositions therefor, e.g. developers
    • G03F7/325—Non-aqueous compositions
    • G03F7/327—Non-aqueous alkaline compositions, e.g. anhydrous quaternary ammonium salts
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors

Definitions

  • the present invention relates to a manufacturing method of a semiconductor device, and in particular, to a technique effective when applied to a manufacturing method of a semiconductor device using liquid immersion exposure.
  • the liquid immersion exposure is an exposure system in which in a minute gap between a lens and a semiconductor wafer, a water film (meniscus) is formed with the use of the surface tension of water, whereby the minute gap between the lens and a surface to be irradiated (semiconductor wafer) is caused to have a high refractive index, which makes it possible to increase the effective numerical aperture (NA) of the lens to a higher level than normal dry exposure. Because a finer pattern can be resolved by increasing the NA of a lens, the liquid immersion exposure is being put to industrially practical use.
  • Patent Document 1 describes a technique in which, in order to make the surface layer of a resist film hydrophilic, an oxide layer is formed over the surface layer of the resist film by irradiating the resist film with vacuum ultraviolet light while a silicon substrate is being exposed to an active oxygen atmosphere.
  • Patent Document 2 describes a technique in which, in liquid immersion lithography, exposure processing can be performed while a liquid is being prevented from flowing outside a wafer even when an area near to the outer periphery of the wafer is exposed. Specifically, a liquid repellent agent layer is provided over the outer peripheral end surface of the wafer and the peripheral portion of the end surface.
  • Patent Document 3 describes a technique in which a substrate is wetted in advance by supplying a pre-wetting liquid before liquid immersion exposure, so that an immersion liquid is supplied between the wetted substrate and a projection system.
  • Patent Document 4 Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-528835 (Patent Document 4) describes a technique with respect to an immersion scanner provided with a means for preventing a gas bubble from appearing in an immersion liquid and for removing a gas bubble.
  • Patent Document 5 describes a technique with respect to a lithography apparatus in which an influence of a bubble in an immersion liquid, which may affect the imaging quality of immersion lithography, is reduced.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2006-108564
  • Patent Document 2 Japanese Unexamined Patent Application Publication No. 2008-235542
  • Patent Document 3 Japanese Unexamined Patent Application Publication No. 2009-117873
  • Patent Document 4 Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-528835
  • Patent Document 5 Japanese Unexamined Patent Application Publication No. 2009-88552
  • a top-coatless resist having a high water-repellent property is used to reduce the processing time of one semiconductor wafer; however, it has been found that, because of the high water-repellent property, a pattern defect is caused in the peripheral portion of the semiconductor wafer, thereby decreasing the reliability of a semiconductor device formed over the semiconductor wafer. Accordingly, in a manufacturing method of a semiconductor device using liquid immersion exposure, there is a need for a technique for improving the reliability of a semiconductor device.
  • a film to be processed is formed over a circular semiconductor substrate, so that a resist layer whose surface is water repellent is formed over the film to be processed. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the circular semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.
  • the reliability of a semiconductor device can be improved.
  • FIG. 1 is a view for explaining liquid immersion exposure
  • FIG. 2 is a view for explaining engulfment of a bubble in liquid immersion exposure
  • FIG. 3 is a process flow view illustrating part of a process flow of a semiconductor device
  • FIG. 4 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device
  • FIG. 5 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 4 ;
  • FIG. 6 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 5 ;
  • FIG. 7 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 6 ;
  • FIG. 8 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 7 ;
  • FIG. 9 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 8 ;
  • FIG. 10 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 9 ;
  • FIG. 11 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 10 ;
  • FIG. 12 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 11 ;
  • FIG. 13 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 12 ;
  • FIG. 14 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 13 ;
  • FIG. 15 is a plan view of a semiconductor wafer, illustrating an exposure region.
  • hatching may be omitted even in sectional views in order to make them easier to see.
  • hatching may be added even in plan views in order to make them easier to see.
  • FIG. 1 is a view for explaining liquid immersion exposure.
  • An apparatus having a structure as illustrated, for example, in FIG. 1 is used in the liquid immersion exposure.
  • a light source LTS and a photomask (reticle) MK 1 are arranged above a lens (projection lens) LS, and a semiconductor wafer SW is arranged under the lens LS so as to be arranged (vacuum-adsorbed) and held over a wafer stage ST.
  • deionized water enters an inlet port NZa of a nozzle NZ and is discharged from a suction port NZb such that a gap between the lens LS and the surface to be irradiated (surface to be exposed) of the semiconductor wafer SW is filled with deionized water.
  • a meniscus (water film) is formed in the minute gap between the lens LS and the surface to be irradiated of the semiconductor wafer SW.
  • the meniscus functions as an immersion liquid MS, but it is said that the surface to be irradiated of the semiconductor wafer SW should be water repellent because of the meniscus formation.
  • a resist layer (a resist film, a photoresist layer, or a photosensitive resist layer) PR for microfabrication is formed as a single-layer resist film or a multi-layer resist film over the surface to be irradiated of the semiconductor wafer SW.
  • the semiconductor wafer SW has a semiconductor substrate SUB and the resist layer PR.
  • the light source LTS is, for example, an ArF excimer laser having a wavelength of 193 nm.
  • the photomask MK 1 is a mask for printing a desired pattern over the resist layer PR, and is formed of glass or quartz.
  • a reduced projection pattern which is almost the same as the pattern the photomask MK 1 has, is printed over the resist layer PR with the light emitted from the light source LTS reaching the semiconductor wafer SW via the photomask MK 1 , the lens LS, and the immersion liquid MS.
  • the semiconductor wafer SW in other words, the resist layer PR
  • exposure light ArF excimer laser light
  • the resist layer PR is required to be highly water repellent in order to make it possible that the immersion liquid moves at high speed, smoothly, and without leaving a drop of water.
  • the water-repellent property of the resist layer PR is low, there is the concern that a drop of water of the immersion liquid MS (immersion water) may be left when the semiconductor wafer SW is scanned. If a drop of water is left, it eliminates heat of vaporization from the semiconductor wafer SW when it is dried, and accordingly the semiconductor wafer SW contracts, thereby causing misalignment in superposition between the photomask MK 1 and the semiconductor wafer SW.
  • a top-coatless resist is used as the resist layer PR having a high water-repellent property.
  • a high water-repellent property can be achieved when the top-coatless resist is coated once, because a trace amount of a polymer having low surface free energy (fluorine-containing polymer) is mixed as a water repellent into a resist liquid and the water repellents are concentrated only in the surface, when a coated film is formed, by using the surface segregation effect of the water repellent.
  • FIG. 2 is a view for explaining engulfment of a bubble in the liquid immersion exposure.
  • a wafer stage guide WSG is arranged around the semiconductor wafer SW so as to surround the entire circumference of the semiconductor wafer SW.
  • the wafer stage guide WSG has a height almost equal to that of the main surface of the semiconductor wafer SW over which the resist layer PR has been formed, and there is a gap GP having a width of approximately several millimeters between the semiconductor wafer SW and the wafer stage guide WSG. Further, a mechanism is adopted, in which the wafer stage guide WSG moves integrally with the wafer stage ST when the semiconductor wafer SW is scanned.
  • the wafer stage guide WSG is provided in order to prevent the immersion liquid MS from spilling and falling from the surface of the semiconductor wafer SW, and the surface thereof is coated, for example, with a fluorine-based resin, or the like, in order to provide a water-repellent property. Because each of the resist layer PR formed over the surface of the semiconductor wafer SW and the wafer stage guide WSG has a high water-repellent property, the immersion liquid MS never spills and falls in the gap GP even when the immersion liquid MS lies across the surface of the semiconductor wafer SW, the gap GP, and the wafer stage guide WSG. In other words, the resist layer PR is required to be water repellent also in order to hold the immersion liquid MS over the surface of the semiconductor wafer SW.
  • the bubble VD having a diameter of approximately several millimeters is caused in the outer periphery of the main surface of the semiconductor wafer SW, and in the area where the bubble VD has been caused, a pattern is not resolved, thereby causing a pattern defect. It has been found that, that is, a pattern defect is caused because the pattern is defocused when the light path of the exposure light is disturbed by the bubble VD. It has also been known that, as the water-repellent property of the resist layer PR is higher, the bubble VD is more likely to be caused.
  • a semiconductor device has a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
  • the semiconductor device is formed in a chip region of a rectangular shape, and a plurality of the chip regions are arranged in a matrix pattern in a semiconductor wafer.
  • a plurality of the semiconductor devices are formed over one semiconductor wafer.
  • FIG. 3 is a process flow view illustrating part of a process flow of the semiconductor device
  • FIGS. 4 to 14 are essential-part sectional views each illustrating a manufacturing step of a semiconductor device
  • FIG. 15 is a plan view of the semiconductor wafer, illustrating an exposure region.
  • a semiconductor substrate SUB including, for example, silicon is first provided (Step S 1 in FIG. 3 .)
  • the semiconductor substrate SUB is the semiconductor wafer SW whose planar shape is circular (approximately circular).
  • FIG. 4 illustrates part of each of a peripheral portion PC and a central portion CP of the semiconductor wafer SW.
  • the peripheral portion PC includes at least the later-described first wafer edge exposure region WEE 1 and second wafer edge exposure region WEE 2 .
  • the central portion CP means a central portion (inner portion) of the semiconductor wafer SW, the central portion being located inside the peripheral portion PC.
  • the sectional shape of the outer periphery of the semiconductor wafer SW is briefly illustrated as a rectangular shape, but actually the corners on the main surface side and the rear surface side of the semiconductor wafer SW are chamfered in the thickness direction, as illustrated in FIG. 2 .
  • a film to be processed (layer to be processed) 2 is formed over the semiconductor substrate SUB via an insulating film 1 including, for example, a silicon oxide film (Step S 2 in FIG. 3 .)
  • the film to be processed 2 includes, for example, a silicon nitride film.
  • an antireflection film is formed over the film to be processed 2 .
  • a EARL (Bottom Antireflective Layer) using an inorganic film or a BARC (Bottom Antireflective Coating) using an organic film is used as the antireflection film.
  • the BARC is formed by using coating and thermal curing.
  • a tri-layer resist process may be adopted, in which a Bottom layer 3 and a middle layer 4 are used as the antireflection film.
  • the middle layer 4 functions as a mask for processing the bottom layer 3 while the bottom layer 3 as a mask for processing the film to be processed 2 in terms of processing.
  • the tri-layer resist process is adopted for the antireflection film.
  • the bottom layer 3 was formed as follows: for example, a chemical solution HM8005 (made by JSR Corp.) was coated by a spin coating method so as to have a thickness of 200 nm; and then a polymer was crosslinked by a heat treatment.
  • the middle layer (middle layer film) 4 containing carbon (C) and silicon (Si) as main components, was formed over the bottom layer 3 .
  • the middle layer 4 was formed by using SHB-A759 (made by Shin-Etsu Chemical Co., Ltd.) as a base material (base resin). After the material was coated by a spin coating method so as to have a thickness of 80 nm, the base polymer was crosslinked by a heat treatment at 180° C. for 90 seconds, thereby allowing the middle layer 4 to be formed.
  • the resist layer (photosensitive resist layer, top-coatless resist layer, resist film) PR is formed by spin coating a top-coatless resist (Step S 3 in FIG. 3 .) The coating was followed by thermal curing.
  • the resist layer PR is formed by using a chemically amplified positive resist.
  • the material of the resist layer PR is made by dissolving these materials (the aforementioned base polymer, PAG, quencher, and water-repellent additive) in PGMEA (propylene glycol monomethyl ether
  • the resist layer PR was coated by a spin coating method so as to have a thickness of 100 nm followed by a heat treatment at 100° C. for 60 seconds.
  • the water-repellent additive added to the resist layer PR was surface-segregated during the spin coating, and as a result, the resist layer PR exhibited a high water-repellent property in which the receding contact angle of the resist layer PR was 75.0.
  • first wafer edge exposure is performed in a region (outer peripheral region) near to the outer periphery WF of the semiconductor wafer SW, as illustrated in FIG. 5 (Step S 4 in FIG. 3 .)
  • a region having a first width (e.g., 1 mm) from the outer periphery WF of the semiconductor wafer SW is selectively irradiated with exposure light by using a photomask MK 2 , as illustrated in FIGS. 5 and 15 .
  • the region irradiated with exposure light is the first wafer edge exposure region WEE 1 .
  • FIG. 1 As illustrated in FIG.
  • the first wafer edge exposure region WEE 1 is a region between the outer periphery WF and a first wafer edge exposure region inner periphery W 1 .
  • DUV Deep Ultraviolet
  • the resist layer PR when the resist layer PR was irradiated, for example, at a light exposure of 100 mJ/cm 2 , with exposure light having a wavelength of 200 nm emitted from a mercury xenon lamp, an acid was generated from a photo-acid generating agent in the chemically amplified positive resist, and the generated acid caused the deprotection reaction of the base resin of the resist to partially progress, so that a polar group appeared in the base resin.
  • the receding contact angle of the surface of the resist layer PR in the first wafer edge exposure region WEE 1 was lowered to 72.0. That is, the water-repellent property of the resist layer PR in the first wafer edge exposure region WEE 1 was lowered by the first wafer edge exposure.
  • liquid immersion exposure is performed, as illustrated in FIGS. 6 and 15 (Step S 5 in FIG. 3 .)
  • Liquid immersion exposure is performed on the resist layer PR formed over the main surface of the semiconductor wafer SW, as described with reference to FIGS. 1 and 2 .
  • the pattern formed in the photomask (reticle) MK 1 is imaged over the resist layer PR by reduced projection exposure, and the light exposure of exposure light having a wavelength of 193 nm was set to 20 mJ/cm 2 .
  • the liquid immersion exposure is scanning exposure in which chip regions CH are sequentially formed over the main surface of the semiconductor wafer SW by scanning the semiconductor wafer SW with respect to the lens LS.
  • the chip regions CH are arranged over the main surface of the semiconductor wafer SW and in a matrix pattern in the vertical and horizontal directions, and they are also formed across the entire circumference of the outer periphery WF of the semiconductor wafer SW. That is, the outer periphery WF of the semiconductor wafer SW is located inside the chip regions CH arranged in a matrix pattern (in other words, inside a liquid immersion exposure region IL.) Because the liquid immersion exposure is performed on the outer periphery WF of the semiconductor wafer SW, the aforementioned problems regarding the bubble VD are caused.
  • the reason why the chip regions CH are formed also across the outer periphery WF of the semiconductor wafer SW is that processing accuracy and yield are improved by matching the environments of processing, such as exposure, etching, or the like, for both the chip regions CH located in the central portion CP of the semiconductor wafer SW and those located in the peripheral portion PC. Also, it is because the number of the chip regions CH over the semiconductor wafer SW is increased.
  • FIG. 6 illustrates an example in which only a partial portion of the central portion CP of the semiconductor wafer SW is irradiated with the exposure light in the liquid immersion exposure.
  • second wafer edge exposure is performed in the outer periphery of the semiconductor wafer SW, as illustrated in FIG. 7 (Step S 6 in FIG. 3 .)
  • a region having a second width (e.g., 1.5 mm) from the outer periphery WF of the semiconductor wafer SW is selectively irradiated with exposure light by using a photomask MK 3 , as illustrated in FIGS. 7 and 15 .
  • the region irradiated with exposure light is the second wafer edge exposure region WEE 2 .
  • the second wafer edge exposure region WEE 2 is a region between the outer periphery WF and a second wafer edge exposure region inner periphery W 2 .
  • the second wafer edge exposure is performed in order to remove, in the later-described developing step, the resist layer PR in an area near to the outer periphery WF of the semiconductor wafer SW.
  • the thickness of the resist layer PR in the area near to the outer periphery WF of the semiconductor wafer SW is more likely to vary in comparison with the central portion CP. This is because the circumference of the semiconductor wafer SW is chamfered in the thickness direction, or because the resist layer PR is coated by a spin coating method, or the like.
  • the variation in the film thickness causes a pattern defect of the film to be processed 2 in the area near to the outer periphery WF of the semiconductor wafer SW.
  • the second wafer edge exposure is performed in order to remove the resist layer PR in a region where a variation in the thickness of the resist layer PR is to be caused.
  • the second wafer edge exposure region inner periphery W 2 is located more inside the main surface of the semiconductor wafer SW (located nearer to the center) than the first wafer edge exposure region inner periphery W 1 . That is, an influence of the exposure light in the first wafer edge exposure, which may be affected on the chip regions CH formed inside the second wafer edge exposure region inner periphery W 2 (formed near to the center), can be prevented (reduced) by separating the second wafer edge exposure region inner periphery W 2 from the first wafer edge exposure region inner periphery W 1 .
  • the second wafer edge exposure region inner periphery W 2 may be set at a distance of 2 mm from the outer periphery WF.
  • the resist layer PR is irradiated, for example, at a light exposure of 60 mJ/cm 2 , with exposure light emitted from a mercury xenon lamp,
  • PEB Post Exposure Bake
  • an acid is generated from the acid generating agent contained in the resist layer PR in the region irradiated with the exposure light (ultraviolet light). Further, a deprotection reaction is caused to progress in the resist layer PR in the irradiated region by performing the PEE.
  • the acid generated in the irradiated region acts on an alkali dissolution inhibiting group of the base resin, the alkali dissolution inhibiting group being acid-dissociable, so that the base resin is decomposed, which changes the resist layer PR so as to have a molecular structure dissoluble in an alkali developer.
  • Step S 7 in FIG. 3 An alkaline tetramethylammonium hydroxide liquid (hereinafter, referred to as a TMAH liquid), or the like, is used as a developer, and the development is performed for 30 seconds.
  • the resist layer PR in the region irradiated with exposure light is dissolved by the development, so that a resist pattern PRa is completed and the middle layer 4 is exposed from an opening that is a dissolved area of the resist layer PR.
  • the resist layer PR in each of the region irradiated with ArF excimer laser exposure light and the second wafer edge exposure region WEE 2 is removed.
  • the middle layer 4 and the bottom layer 3 are etched, as illustrated in FIG. 9 (Step S 8 in FIG. 3 .)
  • the middle layer 4 was dry etched by using mixed gas of CHF 3 , CF 4 , and O 2 with the use of the resist pattern PRa as a mask, thereby allowing the pattern of the resist pattern PRa to be transferred to the middle layer 4 .
  • the bottom layer 3 is dry etched by using mixed gas of O 2 , N 2 , and HBr with the use of the pattern formed by the resist pattern PRa and the middle layer 4 as a mask, thereby allowing a bottom layer pattern 3 a , to which the pattern of the resist pattern PRa has been transferred, to be completed.
  • the resist pattern PRa and the middle layer 4 are removed and disappear.
  • the film to be processed 2 is etched by using the bottom layer pattern 3 a as a mask and a trench GV is formed, as illustrated in FIG. 10 (Step S 9 in FIG. 3 .)
  • the silicon nitride film that is the film to be processed 2 , the insulating film 1 , and the semiconductor substrate (silicon substrate) SUB are sequentially dry etched by using mixed gas of Cl, HBr, SF 6 , and O 2 . Because the resist pattern PRa of the resist layer PR is transferred to the film to be processed 2 and the trench GV is formed in the semiconductor substrate SUB by using the film to be processed 2 as a mask, the trench GV is formed at a position corresponding to the opening of the resist pattern PRa.
  • an element isolation insulating film 5 including, for example, a silicon oxide film is deposited over the semiconductor substrate SUB by a CVD (Chemical Vapor Deposition) method, so that the trench GV is filled with the element isolation insulating film 5 , as illustrated in FIG. 11 .
  • CVD Chemical Vapor Deposition
  • the element isolation insulating film 5 is selectively left only in the trench GV by performing CMP (Chemical Mechanical Polishing) processing on the element isolation insulating film 5 , thereby allowing an element isolation region STI to be formed, as illustrated in FIG. 12 (Step S 10 in FIG. 3 .)
  • CMP Chemical Mechanical Polishing
  • a gate insulating film GI and a gate electrode GE are formed over the main surface of the semiconductor substrate SUB, as illustrated in FIG. 13 .
  • an active region surrounded, in plan view, by the element isolation region STI is formed over the main surface of the semiconductor substrate SUB.
  • an insulating film to become the gate insulating film GI and a conductor film to become the gate electrode GE are formed over the main surface of the semiconductor substrate SUB.
  • the gate electrode GE and the gate insulating film GI are formed by etching the conductor film and the insulating film.
  • the gate electrode GE can be formed by performing Step S 3 to Step S 9 in FIG. 3 with the use of the conductor film as the aforementioned film to be processed.
  • the gate insulating film GI can be formed by a silicon oxide film, a silicon oxynitride film, or the like.
  • the gate electrode GE can be formed by a polycrystalline silicon film, a metal film, or the like.
  • the conductor film may be caused to correspond to the semiconductor substrate SUB.
  • the etching step of forming the trench GV in the semiconductor substrate SUB corresponds to the step of etching the conductor film in order to form the gate electrode GE.
  • a low-concentration semiconductor region NM is sequentially formed, as illustrated in FIG. 14 .
  • the low-concentration semiconductor region NM is first formed over the surface of the semiconductor substrate SUB at both the ends of the gate electrode GE.
  • the low-concentration semiconductor region NM is, for example, an n-type semiconductor region, and is formed by ion-implanting impurities, such as phosphorus (P), arsenic (As), or the like, in a self-aligned manner to the gate electrode GE.
  • the sidewall insulating film SP can be selectively formed over the sidewall of the gate electrode GE by depositing an insulating film so as to cover the upper surface and the side surface of the gate electrode GE and then by performing anisotropic dry etching on the insulating film.
  • the sidewall insulating film SP may include a silicon oxide film, a silicon nitride film, or a laminated structure of the two.
  • the high-concentration semiconductor region NH is formed over the surface of the semiconductor substrate SUB at both the ends of the gate electrode GE.
  • the high-concentration semiconductor region NH is, for example, an n-type semiconductor region, and is formed by ion-implanting impurities, such as phosphorus (P), arsenic (As), or the like, in a self-aligned manner with respect to the gate electrode GE and the sidewall insulating film SP.
  • the MISFET is formed by the gate electrode GE, the gate insulating film GI, the low-concentration semiconductor region NM, and the high-concentration semiconductor region NH.
  • the source and drain of the MISFET are formed by the low-concentration semiconductor region NM and the high-concentration semiconductor region NH.
  • the water-repellent property of the resist layer PR to be used in liquid immersion exposure is lowered by performing first wafer edge exposure on the resist layer PR before the liquid immersion exposure, thereby allowing the engulfment of the bubble VD to be prevented and a pattern defect of the resist pattern PRa to be prevented in the liquid immersion exposure.
  • a pattern defect of each of a silicon nitride film, which is the film to be processed 2 to which the pattern of the resist pattern PRa has been transferred, and the element isolation region STI can be prevented, thereby allowing a semiconductor device with high reliability to be provided. Furthermore, the manufacturing yield of a semiconductor device can be improved.
  • the engulfment of the bubble VD is noticeable, the light exposure in the first wafer edge exposure is increased. Thereby, the hydrophilic property of the first wafer edge exposure region WEE 1 can be increased to a higher level, so that the engulfment of the bubble VD can be suppressed. If water leak is caused in the gap GP by performing the first wafer edge exposure, the light exposure in the first wafer edge exposure is reduced. Thereby, the excessive hydrophilic property of the resist surface, which may be caused by performing the first wafer edge exposure, can be improved.
  • the light exposure in the first wafer edge exposure can be easily changed by performing the first wafer edge exposure and the second wafer edge exposure in different steps, thereby allowing the engulfment of the bubble VD, which may be caused during liquid immersion exposure, to be prevented.
  • the exposure light, with which the first wafer edge exposure region WEE 1 is irradiated never adversely affects the chip region CH formed inside the second wafer edge exposure region WEE 2 (formed inside (near to the center of) the second wafer edge exposure region inner periphery W 2 ), even when the light exposure in the first wafer edge exposure is changed. Accordingly, the light exposure in the first wafer edge exposure can be increased sufficiently, and hence the water-repellent property of the resist layer PR can be lowered sufficiently.
  • an exposure apparatus using, for example, DUV light can be adopted for the first wafer edge exposure, and hence both the processing time of the first wafer edge exposure and manufacturing cost can be reduced. Because an exposure apparatus using DUV light can also be adopted for the second wafer edge exposure, similar effects can be obtained.
  • the surface of the semiconductor wafer SW (resist layer PR) is subjected to a washing treatment by deionized water immediately after the first wafer edge exposure of Step S 4 in FIG. 3 .
  • the deprotection reaction of the base resin that forms the resist layer PR partially progresses immediately after the first wafer edge exposure, so that a polar group appears. Because the polar group has a high affinity with water, the orientation thereof is changed in a direction toward the surface of the resist layer PR when water is supplied to the surface thereof, thereby allowing the hydrophilic property of the resist layer PR to be improved.
  • the aforementioned washing treatment is effective particularly when the water-repellent property of the resist layer PR cannot be sufficiently lowered in the first wafer edge exposure, and the like.
  • a heat treatment is performed on the semiconductor wafer SW immediately after the first wafer edge exposure of Step S 4 in FIG. 3 . It is preferable that the heat treatment is performed under the conditions at 70° C. for approximately 10 seconds, the temperature and time being set to be lower and shorter than the conditions of the PEB.
  • the deprotection reaction of the resist layer PR in the first wafer edge exposure region WEE 1 can be caused to progress to a further level, so that the water-repellent property is greatly lowered.
  • the heat treatment is effective particularly when the water-repellent property of the resist layer PR cannot be sufficiently lowered in the first wafer edge exposure, and the like.
  • the second wafer edge exposure is performed before the liquid immersion exposure in the process flow in FIG. 3 .
  • Either the first wafer edge exposure or the second wafer edge exposure may be performed first as long as they are performed before the liquid immersion exposure, but it is important to perform both of them.
  • Exposure conditions are the same as those in the aforementioned embodiment, and the first wafer edge exposure and the second wafer edge exposure are performed on different regions and under different conditions, respectively. That is, it is important to make the width of the second wafer edge exposure region WEE 2 larger than that of the first wafer edge exposure region WEE 1 for controlling the water-repellent property.
  • the chip region CH formed inside the second wafer edge exposure region WEE 2 (formed inside (near to the center of) the second wafer edge exposure region inner periphery W 2 ) cannot be adversely affected by the exposure light in the first wafer edge exposure.
  • the first wafer edge exposure can be omitted; however, the chip region inside the second wafer edge exposure region inner periphery W 2 in FIG. 15 is affected, and hence it is preferable to perform the first wafer edge exposure and the second wafer edge exposure together.
  • the first wafer edge exposure and the second wafer edge exposure can be performed in a single exposure apparatus unit, and hence the processing time of the exposure steps can be reduced.
  • it is common that the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure are performed in exposure apparatus units different from each other.
  • the first wafer edge exposure and the second wafer edge exposure can be performed in a single exposure apparatus unit, and hence both the time for transfers among units and throughput can be reduced.
  • a semiconductor device according to the present embodiment can be thus manufactured.
  • the present invention has been described by using an example in which, for example, the resist layer PR is formed over the film to be processed 2 via the bottom layer 3 and the middle layer 4 , but the middle layer 4 , the bottom layer 3 , or both of the two may be omitted.

Abstract

The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 15/451,525 filed on Mar. 7, 2017, which is a continuation of U.S. patent application Ser. No. 15/137,964 filed on Apr. 25, 2016, now U.S. Pat. No. 9,627,203 issued on Apr. 18, 2017, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-099065 filed on May 14, 2015 including the specification, drawings and abstract are incorporated herein by reference in their entirety.
    • BACKGROUND
  • The present invention relates to a manufacturing method of a semiconductor device, and in particular, to a technique effective when applied to a manufacturing method of a semiconductor device using liquid immersion exposure.
  • The liquid immersion exposure is an exposure system in which in a minute gap between a lens and a semiconductor wafer, a water film (meniscus) is formed with the use of the surface tension of water, whereby the minute gap between the lens and a surface to be irradiated (semiconductor wafer) is caused to have a high refractive index, which makes it possible to increase the effective numerical aperture (NA) of the lens to a higher level than normal dry exposure. Because a finer pattern can be resolved by increasing the NA of a lens, the liquid immersion exposure is being put to industrially practical use.
  • Japanese Unexamined Patent Application Publication No. 2006-108564 (Patent Document 1) describes a technique in which, in order to make the surface layer of a resist film hydrophilic, an oxide layer is formed over the surface layer of the resist film by irradiating the resist film with vacuum ultraviolet light while a silicon substrate is being exposed to an active oxygen atmosphere.
  • Japanese Unexamined Patent Application Publication No. 2008-235542 (Patent Document 2) describes a technique in which, in liquid immersion lithography, exposure processing can be performed while a liquid is being prevented from flowing outside a wafer even when an area near to the outer periphery of the wafer is exposed. Specifically, a liquid repellent agent layer is provided over the outer peripheral end surface of the wafer and the peripheral portion of the end surface.
  • Japanese Unexamined Patent Application Publication No. 2009-117873 (Patent Document 3) describes a technique in which a substrate is wetted in advance by supplying a pre-wetting liquid before liquid immersion exposure, so that an immersion liquid is supplied between the wetted substrate and a projection system.
  • Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-528835 (Patent Document 4) describes a technique with respect to an immersion scanner provided with a means for preventing a gas bubble from appearing in an immersion liquid and for removing a gas bubble.
  • Japanese Unexamined Patent Application Publication No. 2009-88552 (Patent Document 5) describes a technique with respect to a lithography apparatus in which an influence of a bubble in an immersion liquid, which may affect the imaging quality of immersion lithography, is reduced.
    • RELATED ART DOCUMENT Patent Document
  • [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-108564
  • [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2008-235542
  • [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2009-117873
  • [Patent Document 4] Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-528835
  • [Patent Document 5] Japanese Unexamined Patent Application Publication No. 2009-88552
    • SUMMARY
  • According to the study by the present inventors, the following fact has been known.
  • In liquid immersion exposure, a top-coatless resist having a high water-repellent property is used to reduce the processing time of one semiconductor wafer; however, it has been found that, because of the high water-repellent property, a pattern defect is caused in the peripheral portion of the semiconductor wafer, thereby decreasing the reliability of a semiconductor device formed over the semiconductor wafer. Accordingly, in a manufacturing method of a semiconductor device using liquid immersion exposure, there is a need for a technique for improving the reliability of a semiconductor device.
  • Other problems and new characteristics will become clear from the description and accompanying drawings of the present specification.
  • According to one embodiment, a film to be processed is formed over a circular semiconductor substrate, so that a resist layer whose surface is water repellent is formed over the film to be processed. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the circular semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.
  • According to the one embodiment, the reliability of a semiconductor device can be improved.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a view for explaining liquid immersion exposure;
  • FIG. 2 is a view for explaining engulfment of a bubble in liquid immersion exposure;
  • FIG. 3 is a process flow view illustrating part of a process flow of a semiconductor device;
  • FIG. 4 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device;
  • FIG. 5 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 4;
  • FIG. 6 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 5;
  • FIG. 7 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 6;
  • FIG. 8 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 7;
  • FIG. 9 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 8;
  • FIG. 10 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 9;
  • FIG. 11 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 10;
  • FIG. 12 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 11;
  • FIG. 13 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 12;
  • FIG. 14 is an essential-part sectional view illustrating a manufacturing step of a semiconductor device, following FIG. 13; and
  • FIG. 15 is a plan view of a semiconductor wafer, illustrating an exposure region.
    •  DETAILED DESCRIPTION
  • When necessary for convenience in the following embodiment, description is given by dividing the embodiment into a plurality of sections or embodiments; however, unless otherwise indicated, they are not independent of one another, but one is related with the other part or the whole as a modification, a detail, supplementary description, etc. In addition, in the following embodiments, when referred to the number of elements, etc. (number of units, numerical value, quantity, range, etc., are included), unless stated explicitly or except when the number is obviously limited to specific numbers in principle, the number is not limited to the specific ones but may be more or less than the specific numbers. Further, in the following embodiments, it is needless to say that components (also including constituent steps, etc.) are not necessarily requisite unless stated explicitly or except when they are obviously requisite in principle. Similarly, when the shapes and positional relations, etc., of the constituents, etc., are referred to in the following embodiments, those substantially the same or similar to the shapes, etc., should also be included, unless otherwise indicated or except when considered to be clearly otherwise in principle. This also applies to the aforementioned numerical values and ranges.
  • Hereinafter, preferred embodiments of the present invention will be described in detail based on the accompanying drawings. In each view for explaining the embodiments, components having the same function will be denoted with the same reference numerals, and duplicative description thereof will be omitted. In the following embodiments, description of the same or similar parts will not be repeated in principle, unless particularly necessary.
  • In the views used in the embodiments, hatching may be omitted even in sectional views in order to make them easier to see. Alternatively, hatching may be added even in plan views in order to make them easier to see.
  • It will first be described how the study by the present inventors has reached the present invention.
  • FIG. 1 is a view for explaining liquid immersion exposure.
  • An apparatus having a structure as illustrated, for example, in FIG. 1 is used in the liquid immersion exposure. In the immersion scanner of FIG. 1, a light source LTS and a photomask (reticle) MK1 are arranged above a lens (projection lens) LS, and a semiconductor wafer SW is arranged under the lens LS so as to be arranged (vacuum-adsorbed) and held over a wafer stage ST. Then, deionized water enters an inlet port NZa of a nozzle NZ and is discharged from a suction port NZb such that a gap between the lens LS and the surface to be irradiated (surface to be exposed) of the semiconductor wafer SW is filled with deionized water. With the deionized water, a meniscus (water film) is formed in the minute gap between the lens LS and the surface to be irradiated of the semiconductor wafer SW. The meniscus functions as an immersion liquid MS, but it is said that the surface to be irradiated of the semiconductor wafer SW should be water repellent because of the meniscus formation. A resist layer (a resist film, a photoresist layer, or a photosensitive resist layer) PR for microfabrication is formed as a single-layer resist film or a multi-layer resist film over the surface to be irradiated of the semiconductor wafer SW. The semiconductor wafer SW has a semiconductor substrate SUB and the resist layer PR. The light source LTS is, for example, an ArF excimer laser having a wavelength of 193 nm. The photomask MK1 is a mask for printing a desired pattern over the resist layer PR, and is formed of glass or quartz.
  • A reduced projection pattern, which is almost the same as the pattern the photomask MK1 has, is printed over the resist layer PR with the light emitted from the light source LTS reaching the semiconductor wafer SW via the photomask MK1, the lens LS, and the immersion liquid MS.
  • In the liquid immersion exposure (liquid immersion lithography), scanning exposure is performed, in which the semiconductor wafer SW (in other words, the resist layer PR) is irradiated with exposure light (ArF excimer laser light) by scanning the semiconductor wafer SW with respect to the lens LS. In this case, the resist layer PR is required to be highly water repellent in order to make it possible that the immersion liquid moves at high speed, smoothly, and without leaving a drop of water. If the water-repellent property of the resist layer PR is low, there is the concern that a drop of water of the immersion liquid MS (immersion water) may be left when the semiconductor wafer SW is scanned. If a drop of water is left, it eliminates heat of vaporization from the semiconductor wafer SW when it is dried, and accordingly the semiconductor wafer SW contracts, thereby causing misalignment in superposition between the photomask MK1 and the semiconductor wafer SW.
  • A top-coatless resist is used as the resist layer PR having a high water-repellent property. A high water-repellent property can be achieved when the top-coatless resist is coated once, because a trace amount of a polymer having low surface free energy (fluorine-containing polymer) is mixed as a water repellent into a resist liquid and the water repellents are concentrated only in the surface, when a coated film is formed, by using the surface segregation effect of the water repellent.
  • In this case, however, it has been found from the study by the present inventors that there are the following problems.
  • FIG. 2 is a view for explaining engulfment of a bubble in the liquid immersion exposure.
  • In the immersion scanner, a wafer stage guide WSG is arranged around the semiconductor wafer SW so as to surround the entire circumference of the semiconductor wafer SW. The wafer stage guide WSG has a height almost equal to that of the main surface of the semiconductor wafer SW over which the resist layer PR has been formed, and there is a gap GP having a width of approximately several millimeters between the semiconductor wafer SW and the wafer stage guide WSG. Further, a mechanism is adopted, in which the wafer stage guide WSG moves integrally with the wafer stage ST when the semiconductor wafer SW is scanned.
  • The wafer stage guide WSG is provided in order to prevent the immersion liquid MS from spilling and falling from the surface of the semiconductor wafer SW, and the surface thereof is coated, for example, with a fluorine-based resin, or the like, in order to provide a water-repellent property. Because each of the resist layer PR formed over the surface of the semiconductor wafer SW and the wafer stage guide WSG has a high water-repellent property, the immersion liquid MS never spills and falls in the gap GP even when the immersion liquid MS lies across the surface of the semiconductor wafer SW, the gap GP, and the wafer stage guide WSG. In other words, the resist layer PR is required to be water repellent also in order to hold the immersion liquid MS over the surface of the semiconductor wafer SW.
  • According to the study by the present inventors, however, it has been known that a defect is caused when a top-coatless resist having a high water-repellent property is used as the resist layer PR due to high-speed processing in the liquid immersion exposure. When the semiconductor wafer SW moves from a state, in which the immersion liquid MS lies across the surface of the semiconductor wafer SW, the gap GP, and the wafer stage guide WSG, to the outside direction of the semiconductor wafer SW with respect to the lens LS, the air present in the gap GP is engulfed into the immersion liquid MS, thereby causing a bubble VD in the immersion liquid MS, as illustrated in FIG. 2. The bubble VD having a diameter of approximately several millimeters is caused in the outer periphery of the main surface of the semiconductor wafer SW, and in the area where the bubble VD has been caused, a pattern is not resolved, thereby causing a pattern defect. It has been found that, that is, a pattern defect is caused because the pattern is defocused when the light path of the exposure light is disturbed by the bubble VD. It has also been known that, as the water-repellent property of the resist layer PR is higher, the bubble VD is more likely to be caused.
  • It has been known that, when a semiconductor device is thus manufactured by the liquid immersion exposure using a top-coatless resist, there are problems in which the reliability of the semiconductor device may be decreased, the manufacturing yield thereof may be decreased, and the like. In the following embodiment, innovations for overcoming these problems are made, the innovations being characterized by the fact that the water-repellent property of a resist film is controlled in the peripheral region of a semiconductor wafer before liquid immersion exposure.
    • Embodiment
  • A semiconductor device according to the present embodiment has a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors). The semiconductor device is formed in a chip region of a rectangular shape, and a plurality of the chip regions are arranged in a matrix pattern in a semiconductor wafer. A plurality of the semiconductor devices are formed over one semiconductor wafer.
  • FIG. 3 is a process flow view illustrating part of a process flow of the semiconductor device, and FIGS. 4 to 14 are essential-part sectional views each illustrating a manufacturing step of a semiconductor device. FIG. 15 is a plan view of the semiconductor wafer, illustrating an exposure region.
  • As illustrated in FIG. 4, a semiconductor substrate SUB including, for example, silicon is first provided (Step S1 in FIG. 3.) The semiconductor substrate SUB is the semiconductor wafer SW whose planar shape is circular (approximately circular). FIG. 4 illustrates part of each of a peripheral portion PC and a central portion CP of the semiconductor wafer SW. The peripheral portion PC includes at least the later-described first wafer edge exposure region WEE1 and second wafer edge exposure region WEE2. The central portion CP means a central portion (inner portion) of the semiconductor wafer SW, the central portion being located inside the peripheral portion PC. The sectional shape of the outer periphery of the semiconductor wafer SW is briefly illustrated as a rectangular shape, but actually the corners on the main surface side and the rear surface side of the semiconductor wafer SW are chamfered in the thickness direction, as illustrated in FIG. 2.
  • Subsequently, a film to be processed (layer to be processed) 2 is formed over the semiconductor substrate SUB via an insulating film 1 including, for example, a silicon oxide film (Step S2 in FIG. 3.) The film to be processed 2 includes, for example, a silicon nitride film. Subsequently, an antireflection film is formed over the film to be processed 2. A EARL (Bottom Antireflective Layer) using an inorganic film or a BARC (Bottom Antireflective Coating) using an organic film is used as the antireflection film. The BARC is formed by using coating and thermal curing. When light is imaged by using light having a large incident angle, a tri-layer resist process may be adopted, in which a Bottom layer 3 and a middle layer 4 are used as the antireflection film. In the tri-layer resist process, the middle layer 4 functions as a mask for processing the bottom layer 3 while the bottom layer 3 as a mask for processing the film to be processed 2 in terms of processing. Hereinafter, an example is described, in which the tri-layer resist process is adopted for the antireflection film. The bottom layer 3 was formed as follows: for example, a chemical solution HM8005 (made by JSR Corp.) was coated by a spin coating method so as to have a thickness of 200 nm; and then a polymer was crosslinked by a heat treatment.
  • Subsequently, the middle layer (middle layer film) 4, containing carbon (C) and silicon (Si) as main components, was formed over the bottom layer 3. The middle layer 4 was formed by using SHB-A759 (made by Shin-Etsu Chemical Co., Ltd.) as a base material (base resin). After the material was coated by a spin coating method so as to have a thickness of 80 nm, the base polymer was crosslinked by a heat treatment at 180° C. for 90 seconds, thereby allowing the middle layer 4 to be formed.
  • Subsequently, the resist layer (photosensitive resist layer, top-coatless resist layer, resist film) PR is formed by spin coating a top-coatless resist (Step S3 in FIG. 3.) The coating was followed by thermal curing. The resist layer PR is formed by using a chemically amplified positive resist. A methacrylate resin, to which a 2-methyl adamantyl group was bonded, the 2-methyl adamantyl group being detached when sympathizing with an acid, was used as a base polymer of the resist layer PR (addition amount: 7.0 mass % based on the total mass); and triphenylsulfonium nonaflate was used as PAG (addition amount: 5.0 mass % based on the total mass of the base polymer.) Triethanolamine was used as a quencher (addition amount: 5.0 mass % based on the mass of the base polymer); and a fluorine compound insoluble in an alkali developer was used as a water-repellent additive (addition amount: 4.0 mass based on the mass of the base polymer.) The material of the resist layer PR is made by dissolving these materials (the aforementioned base polymer, PAG, quencher, and water-repellent additive) in PGMEA (propylene glycol monomethyl ether acetate) that was used as a solvent. The resist layer PR was coated by a spin coating method so as to have a thickness of 100 nm followed by a heat treatment at 100° C. for 60 seconds. The water-repellent additive added to the resist layer PR was surface-segregated during the spin coating, and as a result, the resist layer PR exhibited a high water-repellent property in which the receding contact angle of the resist layer PR was 75.0.
  • Subsequently, in order to lower the water-repellent property of the resist layer PR, first wafer edge exposure is performed in a region (outer peripheral region) near to the outer periphery WF of the semiconductor wafer SW, as illustrated in FIG. 5 (Step S4 in FIG. 3.) In the first wafer edge exposure, a region having a first width (e.g., 1 mm) from the outer periphery WF of the semiconductor wafer SW is selectively irradiated with exposure light by using a photomask MK2, as illustrated in FIGS. 5 and 15. The region irradiated with exposure light is the first wafer edge exposure region WEE1. As illustrated in FIG. 15, the first wafer edge exposure region WEE1 is a region between the outer periphery WF and a first wafer edge exposure region inner periphery W1. In the first wafer edge exposure, it is preferable to employ dry exposure using DUV (Deep Ultraviolet) light having a wavelength longer than that of the light used in the liquid immersion exposure in order to reduce processing time and cost.
  • In the first wafer edge exposure, when the resist layer PR was irradiated, for example, at a light exposure of 100 mJ/cm2, with exposure light having a wavelength of 200 nm emitted from a mercury xenon lamp, an acid was generated from a photo-acid generating agent in the chemically amplified positive resist, and the generated acid caused the deprotection reaction of the base resin of the resist to partially progress, so that a polar group appeared in the base resin. As a result, the receding contact angle of the surface of the resist layer PR in the first wafer edge exposure region WEE1 was lowered to 72.0. That is, the water-repellent property of the resist layer PR in the first wafer edge exposure region WEE1 was lowered by the first wafer edge exposure.
  • Subsequently, liquid immersion exposure is performed, as illustrated in FIGS. 6 and 15 (Step S5 in FIG. 3.) Liquid immersion exposure is performed on the resist layer PR formed over the main surface of the semiconductor wafer SW, as described with reference to FIGS. 1 and 2. In the liquid immersion exposure, the pattern formed in the photomask (reticle) MK1 is imaged over the resist layer PR by reduced projection exposure, and the light exposure of exposure light having a wavelength of 193 nm was set to 20 mJ/cm2. The liquid immersion exposure is scanning exposure in which chip regions CH are sequentially formed over the main surface of the semiconductor wafer SW by scanning the semiconductor wafer SW with respect to the lens LS. The chip regions CH are arranged over the main surface of the semiconductor wafer SW and in a matrix pattern in the vertical and horizontal directions, and they are also formed across the entire circumference of the outer periphery WF of the semiconductor wafer SW. That is, the outer periphery WF of the semiconductor wafer SW is located inside the chip regions CH arranged in a matrix pattern (in other words, inside a liquid immersion exposure region IL.) Because the liquid immersion exposure is performed on the outer periphery WF of the semiconductor wafer SW, the aforementioned problems regarding the bubble VD are caused. Incidentally, the reason why the chip regions CH are formed also across the outer periphery WF of the semiconductor wafer SW is that processing accuracy and yield are improved by matching the environments of processing, such as exposure, etching, or the like, for both the chip regions CH located in the central portion CP of the semiconductor wafer SW and those located in the peripheral portion PC. Also, it is because the number of the chip regions CH over the semiconductor wafer SW is increased.
  • FIG. 6 illustrates an example in which only a partial portion of the central portion CP of the semiconductor wafer SW is irradiated with the exposure light in the liquid immersion exposure.
  • Subsequently, second wafer edge exposure is performed in the outer periphery of the semiconductor wafer SW, as illustrated in FIG. 7 (Step S6 in FIG. 3.) In the second wafer edge exposure, a region having a second width (e.g., 1.5 mm) from the outer periphery WF of the semiconductor wafer SW is selectively irradiated with exposure light by using a photomask MK3, as illustrated in FIGS. 7 and 15. The region irradiated with exposure light is the second wafer edge exposure region WEE2. As illustrated in FIG. 15, the second wafer edge exposure region WEE2 is a region between the outer periphery WF and a second wafer edge exposure region inner periphery W2. In the second wafer edge exposure, it is preferable to employ dry exposure using DUV light having a wavelength longer than that of the light used in the liquid immersion exposure in order to reduce processing time and cost.
  • The second wafer edge exposure is performed in order to remove, in the later-described developing step, the resist layer PR in an area near to the outer periphery WF of the semiconductor wafer SW. The thickness of the resist layer PR in the area near to the outer periphery WF of the semiconductor wafer SW is more likely to vary in comparison with the central portion CP. This is because the circumference of the semiconductor wafer SW is chamfered in the thickness direction, or because the resist layer PR is coated by a spin coating method, or the like. The variation in the film thickness causes a pattern defect of the film to be processed 2 in the area near to the outer periphery WF of the semiconductor wafer SW. The second wafer edge exposure is performed in order to remove the resist layer PR in a region where a variation in the thickness of the resist layer PR is to be caused.
  • It is important that the second wafer edge exposure region inner periphery W2 is located more inside the main surface of the semiconductor wafer SW (located nearer to the center) than the first wafer edge exposure region inner periphery W1. That is, an influence of the exposure light in the first wafer edge exposure, which may be affected on the chip regions CH formed inside the second wafer edge exposure region inner periphery W2 (formed near to the center), can be prevented (reduced) by separating the second wafer edge exposure region inner periphery W2 from the first wafer edge exposure region inner periphery W1. The second wafer edge exposure region inner periphery W2 may be set at a distance of 2 mm from the outer periphery WF. In the second wafer edge exposure, the resist layer PR is irradiated, for example, at a light exposure of 60 mJ/cm2, with exposure light emitted from a mercury xenon lamp,
  • Subsequently, PEB (Post Exposure Bake) is performed on the resist layer PR under conditions, for example, at 100° C. for 60 seconds. Because of the aforementioned first wafer edge exposure, liquid immersion exposure, and second wafer edge exposure, an acid is generated from the acid generating agent contained in the resist layer PR in the region irradiated with the exposure light (ultraviolet light). Further, a deprotection reaction is caused to progress in the resist layer PR in the irradiated region by performing the PEE. That is, the acid generated in the irradiated region acts on an alkali dissolution inhibiting group of the base resin, the alkali dissolution inhibiting group being acid-dissociable, so that the base resin is decomposed, which changes the resist layer PR so as to have a molecular structure dissoluble in an alkali developer.
  • Subsequently, development is performed on the semiconductor wafer SW, as illustrated in FIG. 8 (Step S7 in FIG. 3.) An alkaline tetramethylammonium hydroxide liquid (hereinafter, referred to as a TMAH liquid), or the like, is used as a developer, and the development is performed for 30 seconds. The resist layer PR in the region irradiated with exposure light is dissolved by the development, so that a resist pattern PRa is completed and the middle layer 4 is exposed from an opening that is a dissolved area of the resist layer PR. In the liquid immersion exposure, the resist layer PR in each of the region irradiated with ArF excimer laser exposure light and the second wafer edge exposure region WEE2 is removed.
  • As a result of the inspection of the resist pattern PRa obtained when the development is completed, it has been found that pattern defects are reduced in comparison with the state before the first wafer edge exposure is performed. That is, by performing the first wafer edge exposure on the resist layer PR of the semiconductor wafer SW before the liquid immersion exposure, the water-repellent property of the resist layer PR in the first wafer edge exposure region WEE1 can be lowered and the engulfment of a bubble can be prevented during the liquid immersion exposure, thereby allowing a pattern defect of the resist pattern PRa to be prevented.
  • Subsequently, the middle layer 4 and the bottom layer 3 are etched, as illustrated in FIG. 9 (Step S8 in FIG. 3.) The middle layer 4 was dry etched by using mixed gas of CHF3, CF4, and O2 with the use of the resist pattern PRa as a mask, thereby allowing the pattern of the resist pattern PRa to be transferred to the middle layer 4. Further, the bottom layer 3 is dry etched by using mixed gas of O2, N2, and HBr with the use of the pattern formed by the resist pattern PRa and the middle layer 4 as a mask, thereby allowing a bottom layer pattern 3 a, to which the pattern of the resist pattern PRa has been transferred, to be completed. During the etching of the bottom layer 3, the resist pattern PRa and the middle layer 4 are removed and disappear.
  • Subsequently, the film to be processed 2 is etched by using the bottom layer pattern 3 a as a mask and a trench GV is formed, as illustrated in FIG. 10 (Step S9 in FIG. 3.) In this step, the silicon nitride film that is the film to be processed 2, the insulating film 1, and the semiconductor substrate (silicon substrate) SUB are sequentially dry etched by using mixed gas of Cl, HBr, SF6, and O2. Because the resist pattern PRa of the resist layer PR is transferred to the film to be processed 2 and the trench GV is formed in the semiconductor substrate SUB by using the film to be processed 2 as a mask, the trench GV is formed at a position corresponding to the opening of the resist pattern PRa.
  • Subsequently, an element isolation insulating film 5 including, for example, a silicon oxide film is deposited over the semiconductor substrate SUB by a CVD (Chemical Vapor Deposition) method, so that the trench GV is filled with the element isolation insulating film 5, as illustrated in FIG. 11.
  • Subsequently, the element isolation insulating film 5 is selectively left only in the trench GV by performing CMP (Chemical Mechanical Polishing) processing on the element isolation insulating film 5, thereby allowing an element isolation region STI to be formed, as illustrated in FIG. 12 (Step S10 in FIG. 3.)
  • Subsequently, the film to be processed 2 and the insulating film 1 are removed, and then a gate insulating film GI and a gate electrode GE are formed over the main surface of the semiconductor substrate SUB, as illustrated in FIG. 13.
  • When the film to be processed 2 and the insulating film 1 are removed after the element isolation region STI is formed, an active region surrounded, in plan view, by the element isolation region STI is formed over the main surface of the semiconductor substrate SUB. Subsequently, an insulating film to become the gate insulating film GI and a conductor film to become the gate electrode GE are formed over the main surface of the semiconductor substrate SUB. Then, the gate electrode GE and the gate insulating film GI are formed by etching the conductor film and the insulating film. The gate electrode GE can be formed by performing Step S3 to Step S9 in FIG. 3 with the use of the conductor film as the aforementioned film to be processed. The gate insulating film GI can be formed by a silicon oxide film, a silicon oxynitride film, or the like. On the other hand, the gate electrode GE can be formed by a polycrystalline silicon film, a metal film, or the like.
  • Alternatively, the conductor film may be caused to correspond to the semiconductor substrate SUB. In that case, the etching step of forming the trench GV in the semiconductor substrate SUB corresponds to the step of etching the conductor film in order to form the gate electrode GE.
  • Subsequently, a low-concentration semiconductor region NM, a sidewall insulating film SP, and a high-concentration semiconductor region NH are sequentially formed, as illustrated in FIG. 14. The low-concentration semiconductor region NM is first formed over the surface of the semiconductor substrate SUB at both the ends of the gate electrode GE. The low-concentration semiconductor region NM is, for example, an n-type semiconductor region, and is formed by ion-implanting impurities, such as phosphorus (P), arsenic (As), or the like, in a self-aligned manner to the gate electrode GE.
  • Subsequently, the sidewall insulating film SP can be selectively formed over the sidewall of the gate electrode GE by depositing an insulating film so as to cover the upper surface and the side surface of the gate electrode GE and then by performing anisotropic dry etching on the insulating film. The sidewall insulating film SP may include a silicon oxide film, a silicon nitride film, or a laminated structure of the two.
  • Subsequently, the high-concentration semiconductor region NH is formed over the surface of the semiconductor substrate SUB at both the ends of the gate electrode GE. The high-concentration semiconductor region NH is, for example, an n-type semiconductor region, and is formed by ion-implanting impurities, such as phosphorus (P), arsenic (As), or the like, in a self-aligned manner with respect to the gate electrode GE and the sidewall insulating film SP.
  • The MISFET is formed by the gate electrode GE, the gate insulating film GI, the low-concentration semiconductor region NM, and the high-concentration semiconductor region NH. The source and drain of the MISFET are formed by the low-concentration semiconductor region NM and the high-concentration semiconductor region NH.
  • According to the present embodiment, the water-repellent property of the resist layer PR to be used in liquid immersion exposure, the resist layer PR being present in the first wafer edge exposure region WEE1 located in the periphery of the semiconductor wafer SW, is lowered by performing first wafer edge exposure on the resist layer PR before the liquid immersion exposure, thereby allowing the engulfment of the bubble VD to be prevented and a pattern defect of the resist pattern PRa to be prevented in the liquid immersion exposure.
  • Further, a pattern defect of each of a silicon nitride film, which is the film to be processed 2 to which the pattern of the resist pattern PRa has been transferred, and the element isolation region STI can be prevented, thereby allowing a semiconductor device with high reliability to be provided. Furthermore, the manufacturing yield of a semiconductor device can be improved.
  • If the engulfment of the bubble VD is noticeable, the light exposure in the first wafer edge exposure is increased. Thereby, the hydrophilic property of the first wafer edge exposure region WEE1 can be increased to a higher level, so that the engulfment of the bubble VD can be suppressed. If water leak is caused in the gap GP by performing the first wafer edge exposure, the light exposure in the first wafer edge exposure is reduced. Thereby, the excessive hydrophilic property of the resist surface, which may be caused by performing the first wafer edge exposure, can be improved. As described above, the light exposure in the first wafer edge exposure can be easily changed by performing the first wafer edge exposure and the second wafer edge exposure in different steps, thereby allowing the engulfment of the bubble VD, which may be caused during liquid immersion exposure, to be prevented.
  • By making the width of the second wafer edge exposure region WEE2 larger than that of the first wafer edge exposure region WEE1, the exposure light, with which the first wafer edge exposure region WEE1 is irradiated, never adversely affects the chip region CH formed inside the second wafer edge exposure region WEE2 (formed inside (near to the center of) the second wafer edge exposure region inner periphery W2), even when the light exposure in the first wafer edge exposure is changed. Accordingly, the light exposure in the first wafer edge exposure can be increased sufficiently, and hence the water-repellent property of the resist layer PR can be lowered sufficiently.
  • By making the wavelength of the exposure light in the first wafer edge exposure longer than that of the exposure light in liquid immersion exposure, an exposure apparatus using, for example, DUV light can be adopted for the first wafer edge exposure, and hence both the processing time of the first wafer edge exposure and manufacturing cost can be reduced. Because an exposure apparatus using DUV light can also be adopted for the second wafer edge exposure, similar effects can be obtained.
  • Further, a pattern defect in the gate electrode GE, to which a similar manufacturing method has been applied, can be prevented.
    • <First Variation>
  • In First Variation, the surface of the semiconductor wafer SW (resist layer PR) is subjected to a washing treatment by deionized water immediately after the first wafer edge exposure of Step S4 in FIG. 3.
  • In the resist layer PR in the first wafer edge exposure region WEE1, the deprotection reaction of the base resin that forms the resist layer PR partially progresses immediately after the first wafer edge exposure, so that a polar group appears. Because the polar group has a high affinity with water, the orientation thereof is changed in a direction toward the surface of the resist layer PR when water is supplied to the surface thereof, thereby allowing the hydrophilic property of the resist layer PR to be improved.
  • The aforementioned washing treatment is effective particularly when the water-repellent property of the resist layer PR cannot be sufficiently lowered in the first wafer edge exposure, and the like.
    • <Second Variation>
  • In Second Variation, a heat treatment is performed on the semiconductor wafer SW immediately after the first wafer edge exposure of Step S4 in FIG. 3. It is preferable that the heat treatment is performed under the conditions at 70° C. for approximately 10 seconds, the temperature and time being set to be lower and shorter than the conditions of the PEB.
  • By performing the heat treatment immediately after the first wafer edge exposure, the deprotection reaction of the resist layer PR in the first wafer edge exposure region WEE1 can be caused to progress to a further level, so that the water-repellent property is greatly lowered. Similarly to the case of First Variation, the heat treatment is effective particularly when the water-repellent property of the resist layer PR cannot be sufficiently lowered in the first wafer edge exposure, and the like.
    • <Third Variation>
  • In Third Variation, the second wafer edge exposure is performed before the liquid immersion exposure in the process flow in FIG. 3. Either the first wafer edge exposure or the second wafer edge exposure may be performed first as long as they are performed before the liquid immersion exposure, but it is important to perform both of them. Exposure conditions are the same as those in the aforementioned embodiment, and the first wafer edge exposure and the second wafer edge exposure are performed on different regions and under different conditions, respectively. That is, it is important to make the width of the second wafer edge exposure region WEE2 larger than that of the first wafer edge exposure region WEE1 for controlling the water-repellent property. By maintaining this relationship, the chip region CH formed inside the second wafer edge exposure region WEE2 (formed inside (near to the center of) the second wafer edge exposure region inner periphery W2) cannot be adversely affected by the exposure light in the first wafer edge exposure. For example, when the light exposure of the exposure light in the second wafer edge exposure is increased, the first wafer edge exposure can be omitted; however, the chip region inside the second wafer edge exposure region inner periphery W2 in FIG. 15 is affected, and hence it is preferable to perform the first wafer edge exposure and the second wafer edge exposure together.
  • In Third Variation, the first wafer edge exposure and the second wafer edge exposure can be performed in a single exposure apparatus unit, and hence the processing time of the exposure steps can be reduced. In the aforementioned embodiment, it is common that the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure are performed in exposure apparatus units different from each other. In Third Variation, the first wafer edge exposure and the second wafer edge exposure can be performed in a single exposure apparatus unit, and hence both the time for transfers among units and throughput can be reduced.
  • A semiconductor device according to the present embodiment can be thus manufactured.
  • The invention made by the present inventors has been specifically described above based on its preferred embodiments, but it is needless to say that the invention should not be limited to the embodiments and may be modified variously within a range not departing from the gist thereof.
  • The present invention has been described by using an example in which, for example, the resist layer PR is formed over the film to be processed 2 via the bottom layer 3 and the middle layer 4, but the middle layer 4, the bottom layer 3, or both of the two may be omitted.

Claims (1)

What is claimed is:
1. A manufacturing method of a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate whose outer periphery is approximately circular;
(b) forming a first insulating film over the semiconductor substrate;
(c) forming a resist layer over the first insulating film;
(d) irradiating first exposure light to a part of the resist layer which is located in a region having a first width from the outer periphery of the semiconductor substrate;
(e) irradiating third exposure light to a part of the resist layer which is located in a region having a second width being larger than the first width from the outer periphery of the semiconductor substrate;
(f) after the steps (d) and (e), performing liquid immersion exposure in which the resist layer is irradiated with second exposure light;
(g) after the step (f), forming a resist pattern including a first pattern by removing the resist layer located in a region irradiated with the second exposure light and the third exposure light;
(h) after the step (g), etching the first insulating film such that the first insulating film has the first pattern;
(i) after the step (h), forming a trench in the semiconductor substrate by using the first pattern as a mask;
(j) after the step (i), forming a second insulating film over the semiconductor substrate including inside of the trench; and
(k) after the step (j), polishing the second insulating film by CMP method, thereby the second insulating film being outside of the trench is removed and the second insulating film being inside of the trench is kept.
US15/811,282 2015-05-14 2017-11-13 Manufacturing method of semiconductor device Abandoned US20180068845A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/811,282 US20180068845A1 (en) 2015-05-14 2017-11-13 Manufacturing method of semiconductor device

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2015-099065 2015-05-14
JP2015099065A JP6456238B2 (en) 2015-05-14 2015-05-14 Manufacturing method of semiconductor device
US15/137,964 US9627203B2 (en) 2015-05-14 2016-04-25 Manufacturing method of semiconductor device
US15/451,525 US9847226B2 (en) 2015-05-14 2017-03-07 Manufacturing method of semiconductor device
US15/811,282 US20180068845A1 (en) 2015-05-14 2017-11-13 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/451,525 Continuation US9847226B2 (en) 2015-05-14 2017-03-07 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
US20180068845A1 true US20180068845A1 (en) 2018-03-08

Family

ID=55806193

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/137,964 Active US9627203B2 (en) 2015-05-14 2016-04-25 Manufacturing method of semiconductor device
US15/451,525 Active US9847226B2 (en) 2015-05-14 2017-03-07 Manufacturing method of semiconductor device
US15/811,282 Abandoned US20180068845A1 (en) 2015-05-14 2017-11-13 Manufacturing method of semiconductor device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US15/137,964 Active US9627203B2 (en) 2015-05-14 2016-04-25 Manufacturing method of semiconductor device
US15/451,525 Active US9847226B2 (en) 2015-05-14 2017-03-07 Manufacturing method of semiconductor device

Country Status (6)

Country Link
US (3) US9627203B2 (en)
EP (1) EP3093712A1 (en)
JP (1) JP6456238B2 (en)
KR (1) KR20160134515A (en)
CN (1) CN106158598B (en)
TW (1) TWI699821B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102614850B1 (en) * 2016-10-05 2023-12-18 삼성전자주식회사 Method of manufacuturing semiconductor device
JP6732121B2 (en) * 2017-05-25 2020-07-29 東京エレクトロン株式会社 Substrate processing method, storage medium, and substrate processing system
JP6938260B2 (en) * 2017-07-20 2021-09-22 株式会社ディスコ Wafer grinding method
CN108319057A (en) * 2018-03-29 2018-07-24 武汉华星光电技术有限公司 Substrate edges processing method, mask plate
CN113506746B (en) * 2021-06-28 2024-03-19 华虹半导体(无锡)有限公司 Method for solving high step difference in marking area of super junction technology

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040152323A1 (en) * 2003-02-03 2004-08-05 Kabushiki Kaisha Toshiba Method for exposing a photosensitive resist layer with near-field light
US20050221234A1 (en) * 2004-03-24 2005-10-06 Shinichi Ito Resist pattern forming method, semiconductor apparatus using said method, and exposure apparatus thereof
US7050146B2 (en) * 2004-02-09 2006-05-23 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US20070134600A1 (en) * 2005-12-08 2007-06-14 Tokyo Electron Limited Coating and developing apparatus, coating and developing method and storage medium in which a computer-readable program is stored
US20080107999A1 (en) * 2004-11-11 2008-05-08 Nikon Corporation Exposure Method, Device Manufacturing Method, and Substrate
US20080135207A1 (en) * 2006-12-08 2008-06-12 Tokyo Electron Limited Heat treatment device
US20090053651A1 (en) * 2007-08-22 2009-02-26 Shin-Etsu Chemical Co., Ltd. Patterning process
US20090107519A1 (en) * 2007-10-30 2009-04-30 Sokudo Co., Ltd. Method and system for chemically enhanced laser trimming of substrate edges
US20100119960A1 (en) * 2008-09-19 2010-05-13 Tokyo Electron Limited Dual Tone Development Processes
US20100195066A1 (en) * 2009-01-30 2010-08-05 Semes Co., Ltd. System and method for treating substrate
US20100196828A1 (en) * 2009-02-03 2010-08-05 Daisuke Kawamura Method of manufacturing semiconductor device
US20100311244A1 (en) * 2009-06-09 2010-12-09 Shanghai Ic R&D Center Co., Ltd. Double-exposure method
US20110039061A1 (en) * 2009-02-19 2011-02-17 Massachusetts Institute Of Technology Directed material assembly
US20110294069A1 (en) * 2010-05-31 2011-12-01 Rohm And Haas Electronic Materials Llc Photoresist compositions and methods of forming photolithographic patterns
US20120045721A1 (en) * 2010-08-18 2012-02-23 Tokyo Electron Limited Method for forming a self-aligned double pattern
US20120088194A1 (en) * 2007-06-12 2012-04-12 Fujifilm Corporation Method of forming patterns
US8795556B2 (en) * 2010-08-05 2014-08-05 International Business Machines Corporation Self-aligned permanent on-chip interconnect structure formed by pitch splitting
US20150241776A1 (en) * 2014-02-21 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Lithography Patterning

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11162803A (en) * 1997-12-01 1999-06-18 Seiko Epson Corp Method for treating positive resist
US20040067654A1 (en) * 2002-10-07 2004-04-08 Promos Technologies, Inc. Method of reducing wafer etching defect
KR20050002359A (en) * 2003-06-30 2005-01-07 주식회사 하이닉스반도체 Method for Forming Pattern of Semiconductor Device
KR100724478B1 (en) * 2003-06-30 2007-06-04 엘지.필립스 엘시디 주식회사 Fabrication method for liquid crystal display device
JP2006528835A (en) 2003-07-24 2006-12-21 カール・ツアイス・エスエムテイ・アーゲー Microlithography projection exposure apparatus and method for introducing immersion liquid into immersion space
KR20050113457A (en) * 2004-05-29 2005-12-02 주식회사 하이닉스반도체 Method of manufacturing flash memory device
JP2006108564A (en) * 2004-10-08 2006-04-20 Renesas Technology Corp Electronic device manufacturing method and exposure system
US7196770B2 (en) 2004-12-07 2007-03-27 Asml Netherlands B.V. Prewetting of substrate before immersion exposure
JP4634822B2 (en) * 2005-02-24 2011-02-16 株式会社東芝 Resist pattern forming method and semiconductor device manufacturing method
JP4368365B2 (en) * 2006-08-02 2009-11-18 Ｔｄｋ株式会社 Immersion exposure substrate, manufacturing method thereof, and immersion exposure method
JP4357514B2 (en) * 2006-09-29 2009-11-04 株式会社東芝 Immersion exposure method
JP2008235542A (en) 2007-03-20 2008-10-02 Dainippon Printing Co Ltd Wafer for oil immersion lithography and its manufacturing method
US7824846B2 (en) * 2007-09-19 2010-11-02 International Business Machines Corporation Tapered edge bead removal process for immersion lithography
JP2009295716A (en) * 2008-06-04 2009-12-17 Toshiba Corp Method for manufacturing semiconductor device and substrate processing apparatus
JP4853536B2 (en) * 2009-03-13 2012-01-11 東京エレクトロン株式会社 Coating, developing device, coating, developing method and storage medium
US7845868B1 (en) * 2009-09-09 2010-12-07 Nanya Technology Corporation Apparatus for semiconductor manufacturing process
JP5816488B2 (en) * 2011-08-26 2015-11-18 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9372406B2 (en) * 2012-04-13 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Film portion at wafer edge

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040152323A1 (en) * 2003-02-03 2004-08-05 Kabushiki Kaisha Toshiba Method for exposing a photosensitive resist layer with near-field light
US7050146B2 (en) * 2004-02-09 2006-05-23 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US20050221234A1 (en) * 2004-03-24 2005-10-06 Shinichi Ito Resist pattern forming method, semiconductor apparatus using said method, and exposure apparatus thereof
US20080107999A1 (en) * 2004-11-11 2008-05-08 Nikon Corporation Exposure Method, Device Manufacturing Method, and Substrate
US20070134600A1 (en) * 2005-12-08 2007-06-14 Tokyo Electron Limited Coating and developing apparatus, coating and developing method and storage medium in which a computer-readable program is stored
US20080135207A1 (en) * 2006-12-08 2008-06-12 Tokyo Electron Limited Heat treatment device
US20120088194A1 (en) * 2007-06-12 2012-04-12 Fujifilm Corporation Method of forming patterns
US20090053651A1 (en) * 2007-08-22 2009-02-26 Shin-Etsu Chemical Co., Ltd. Patterning process
US20090107519A1 (en) * 2007-10-30 2009-04-30 Sokudo Co., Ltd. Method and system for chemically enhanced laser trimming of substrate edges
US20100119960A1 (en) * 2008-09-19 2010-05-13 Tokyo Electron Limited Dual Tone Development Processes
US20100195066A1 (en) * 2009-01-30 2010-08-05 Semes Co., Ltd. System and method for treating substrate
US20100196828A1 (en) * 2009-02-03 2010-08-05 Daisuke Kawamura Method of manufacturing semiconductor device
US20110039061A1 (en) * 2009-02-19 2011-02-17 Massachusetts Institute Of Technology Directed material assembly
US20100311244A1 (en) * 2009-06-09 2010-12-09 Shanghai Ic R&D Center Co., Ltd. Double-exposure method
US20110294069A1 (en) * 2010-05-31 2011-12-01 Rohm And Haas Electronic Materials Llc Photoresist compositions and methods of forming photolithographic patterns
US8795556B2 (en) * 2010-08-05 2014-08-05 International Business Machines Corporation Self-aligned permanent on-chip interconnect structure formed by pitch splitting
US20120045721A1 (en) * 2010-08-18 2012-02-23 Tokyo Electron Limited Method for forming a self-aligned double pattern
US20150241776A1 (en) * 2014-02-21 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Lithography Patterning

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Utilizing Topcoat-Less Resists" by Hamid Khorram, January 2010 *

Also Published As

Publication number Publication date
CN106158598B (en) 2021-11-02
EP3093712A1 (en) 2016-11-16
US20170178897A1 (en) 2017-06-22
US9847226B2 (en) 2017-12-19
JP6456238B2 (en) 2019-01-23
JP2016218099A (en) 2016-12-22
US20160336173A1 (en) 2016-11-17
TWI699821B (en) 2020-07-21
TW201709275A (en) 2017-03-01
US9627203B2 (en) 2017-04-18
CN106158598A (en) 2016-11-23
KR20160134515A (en) 2016-11-23

Similar Documents

Publication Publication Date Title
US9847226B2 (en) Manufacturing method of semiconductor device
US10281819B2 (en) Silicon-containing photoresist for lithography
US8460856B2 (en) Material and method for photolithography
CN109427553B (en) Semiconductor method for protecting wafer from bevel contamination
TWI584083B (en) A method for lithography patterning
US11387104B2 (en) Grafting design for pattern post-treatment in semiconductor manufacturing
US11143963B2 (en) Negative tone developer for extreme ultraviolet lithography
US7662542B2 (en) Pattern forming method and semiconductor device manufacturing method
US10520821B2 (en) Lithography process with enhanced etch selectivity
TWI401542B (en) Immersion lithography defect reduction with top coater removal
US20080156346A1 (en) Method and apparatus for cleaning a substrate
US20220057715A1 (en) Substrate treating composition and method for fabricating a semiconductor device using the same
US8084192B2 (en) Method for forming resist pattern
US20230062148A1 (en) Method and system for manufacturing a semiconductor device
CN116053116B (en) Method for patterning semiconductor device
US20230369060A1 (en) Method and system for manufacturing a semiconductor device
US20170227852A1 (en) Photoresist with Polar-Acid-Labile-Group
TWI830691B (en) Method for lithography patterning
KR100960483B1 (en) Method for Manufacturing of Semiconductor Device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAGIWARA, TAKUYA;REEL/FRAME:044123/0621

Effective date: 20160309

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION