US20170373140A1 - Semiconductor Device with Field Dielectric in an Edge Area - Google Patents

Semiconductor Device with Field Dielectric in an Edge Area Download PDF

Info

Publication number
US20170373140A1
US20170373140A1 US15/681,454 US201715681454A US2017373140A1 US 20170373140 A1 US20170373140 A1 US 20170373140A1 US 201715681454 A US201715681454 A US 201715681454A US 2017373140 A1 US2017373140 A1 US 2017373140A1
Authority
US
United States
Prior art keywords
zones
semiconductor device
extension zone
depletable
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/681,454
Inventor
Franz Hirler
Stefan Gamerith
Joachim Weyers
Wolfgang Jantscher
Waqas Mumtaz Syed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Priority to US15/681,454 priority Critical patent/US20170373140A1/en
Assigned to INFINEON TECHNOLOGIES AUSTRIA AG reassignment INFINEON TECHNOLOGIES AUSTRIA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SYED, WAQAS MUMTAZ, JANTSCHER, WOLFGANG, GAMERITH, STEFAN, HIRLER, FRANZ, WEYERS, JOACHIM
Publication of US20170373140A1 publication Critical patent/US20170373140A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • a semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body.
  • a field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body.
  • the field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.
  • a semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body.
  • An interlayer dielectric structure adjoins a first surface of the semiconductor body. In the edge area the interlayer dielectric structure separates a gate construction from the semiconductor body.
  • a non-depletable extension zone In the vertical projection of at least a portion of the gate construction in the semiconductor body is a non-depletable extension zone of a conductivity type of body/anode zones of the transistor cells. The non-depletable extension zone is electrically connected to at least one of the body/anode zones.
  • a half-bridge circuit includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body.
  • a field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure from the semiconductor body.
  • the field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.
  • FIG. 1A is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment related to planar gate electrodes and a stepless transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1B is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment related to planar gate electrodes and a stepped transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1C is a schematic cross-sectional view of a portion of a superjunction IGFET according to an embodiment related to planar gate electrodes and a stepless transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1D is a schematic cross-sectional view of a portion of a superjunction IGFET according to an embodiment related to a buried depletable extension zone and a stepless transition of a field dielectric between a conductive structure and a semiconductor body.
  • FIG. 1E is a schematic cross-sectional view of a portion of a superjunction IGFET in accordance with an embodiment related to buried gate electrodes.
  • FIG. 1F is a schematic cross-sectional view of a portion of an MCD (MOS-controlled diode) according to another embodiment.
  • FIG. 2A is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone surrounding an active area along a circumferential line at a constant dopant concentration.
  • FIG. 2B is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment providing a non-depletable extension zone that surrounds an active area and that includes sections of enhanced dopant concentration.
  • FIG. 2C is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with an enlarged portion of a non-depletable extension zone formed in the vertical projection of a gate construction.
  • FIG. 2D is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone exclusively formed in the vertical projection of a gate construction.
  • FIG. 2E is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone including a section of enhanced dopant concentration in the vertical projection of a gate construction.
  • FIG. 2F is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment providing a segmented non-depletable extension zone.
  • FIG. 2G is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a portion of a non-depletable extension zone formed in the vertical projection of a portion of a gate construction.
  • FIG. 3 is a schematic cross-sectional view of a portion of a semiconductor device in accordance with another embodiment with a non-depletable extension zone in the vertical projection of a portion of a gate construction.
  • FIG. 4 is a schematic diagram comparing switching-off losses for illustrating effects of the embodiments.
  • FIG. 5A is a schematic circuit diagram of a half-bridge circuit according to an embodiment with two n-type IGFETs.
  • FIG. 5B is a schematic circuit diagram of a half-bridge circuit according to an embodiment with a p-type and an n-type IGFET.
  • FIG. 5C is a schematic circuit diagram of a half-bridge circuit according to an embodiment with IGBTs.
  • FIG. 5D is a schematic circuit diagram of a full-bridge circuit according to a further embodiment.
  • electrically connected describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor.
  • electrically coupled includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.
  • n ⁇ means a doping concentration which is lower than the doping concentration of an “n”-doping region while an “n+”-doping region has a higher doping concentration than an “n”-doping region.
  • Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”-doping regions may have the same or different absolute doping concentrations.
  • FIGS. 1A to 1E refer to controllable semiconductor devices 500 including active transistor cells and/or controllable desaturation or injection cells, for example controllable semiconductor diodes such as MCDs, IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor FETs) in the usual meaning including FETs with metal gates as well as FETs with non-metal gates, JFETs (junction field effect transistors), IGBTs (insulated gate bipolar transistors), and thyristors, by way of example.
  • controllable semiconductor diodes such as MCDs, IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor FETs) in the usual meaning including FETs with metal gates as well as FETs with non-metal gates, JFETs (junction field effect transistors), IGBTs (insulated gate bipolar transistors), and thyristors, by way of example.
  • Each of the semiconductor devices 500 is based on a semiconductor body 100 from a single-crystalline semiconductor material such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any other A III Bv semiconductor.
  • a single-crystalline semiconductor material such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any other A III Bv semiconductor.
  • the semiconductor body 100 has a first surface 101 which may be approximately planar or which may be given by a plane spanned by coplanar surface sections as well as a mainly planar second surface 102 parallel to the first surface 101 .
  • a minimum distance between the first and second surfaces 101 , 102 is selected to achieve a specified voltage blocking capability of the semiconductor device 500 .
  • a side surface 103 connects the first and second surfaces 101 , 102 .
  • the semiconductor body 100 may have a rectangular shape with an edge length in the range of several millimeters or may be disc-shaped with a diameter of several centimeters.
  • a normal to the first surface 101 defines a vertical direction and directions orthogonal to the vertical direction are lateral directions.
  • the semiconductor body 100 includes a drift zone 120 of a first conductivity type as well as a pedestal layer 130 between the drift zone 120 and the second surface 102 .
  • a dopant concentration in the drift zone 120 may gradually or in steps increase or decrease with increasing distance to the first surface 101 at least in portions of its vertical extension. According to other embodiments the dopant concentration in the drift zone 120 may be approximately uniform. A mean dopant concentration in the drift zone 120 may be between 5E12 cm ⁇ 3 and 1E16 cm ⁇ 3 , for example in a range from 5E13 cm ⁇ 3 to 5E15 cm ⁇ 3 .
  • the drift zone 120 may include further dopant zones, e.g. a superjunction structure.
  • the pedestal layer 130 may have the first conductivity type in case the semiconductor device 500 is a semiconductor diode, an IGFET or a JFET, may have a second conductivity type, which is complementary to the first conductivity type, in case the semiconductor device 500 is an IGBT or a thyristor or may contain zones of both conductivity types extending between the drift zone 120 and the second surface 102 in case the semiconductor device 500 is an MCD or an RC-IGBT (reverse conducting IGBT).
  • the dopant concentration in the pedestal layer 130 is sufficiently high to form an ohmic contact with a metal directly adjoining the second surface 102 .
  • a mean dopant concentration for a p-type pedestal layer 130 or p-type zones of the pedestal layer 130 may be at least 1E16 cm ⁇ 3 , for example at least 5E17 cm ⁇ 3 .
  • the semiconductor devices 500 further includes active, functional transistor cells TC in an active area 610 , whereas an edge area 690 between the side surface 103 and the active area 610 is devoid of any functional transistor cells of the type present in the active area 610 .
  • Each active transistor cell TC includes body/anode zones 115 of the second conductivity type forming first pn junctions pn 1 with the drift zone 120 as well as source zones 110 forming second pn junctions with the body/anode zones 115 .
  • the source zones 110 may be wells extending from the first surface 101 into the semiconductor body 100 , for example into the body/anode zones 115 .
  • a gate structure 150 includes a conductive gate electrode 155 which may include or consist of a heavily doped polycrystalline silicon layer or a metal-containing layer as well as a gate dielectric 151 separating the gate electrode 155 from the semiconductor body 100 .
  • the gate dielectric 151 capacitively couples the gate electrode 155 to channel portions of the body/anode zones 115 .
  • the first conductivity type is the n-type and the second conductivity type is the p-type. Similar considerations as outlined below apply to embodiments with the first conductivity being the p-type and the second conductivity type being the n-type.
  • the gate structure 150 includes an idle portion 150 a including an idle gate electrode 155 a in the edge area 690 .
  • the idle gate electrode 155 a and the gate electrode 155 are electrically and structurally connected to each other and may be portions of the same layered structure.
  • a gate construction 330 may be connected to the gate electrode 155 via the idle gate electrode 155 a.
  • the gate construction 330 may include at least one of a gate pad, a gate finger, and a gate runner electrically connected to the gate electrode 155 , respectively.
  • a gate pad may be a metal pad suitable as a landing pad for a bond wire or another chip-to-leadframe or chip-to-chip connection like a soldered clip.
  • the gate pad may be arranged between a first load electrode 310 and the side surface 103 or in a center portion of the semiconductor body 100 .
  • a gate runner may be a metal line surrounding the active area 610 .
  • a gate finger may be a metal line separating the active areas 610 in separated cell fields.
  • An interlayer dielectric 210 separates the gate construction 330 from the semiconductor body 100 and may insulate the gate electrode 155 from the first load electrode 310 .
  • a conductive structure 157 structurally and electrically connects the idle gate electrode 155 a with the gate construction 330 or with a gate contact structure 315 g extending from the gate construction 330 into the interlayer dielectric 210 .
  • the conductive structure 157 can be a part of an integrated gate resistor or polycrystalline silicon diode or can be omitted below the gate construction 330 .
  • a portion of the interlayer dielectric 210 between the conductive structure 157 and the semiconductor body 100 forms a field dielectric 211 .
  • the field dielectric 211 has a transition Tr between a first vertical extension close to the gate dielectric thickness in a portion directly adjoining the idle gate electrode 155 a and a second vertical extension, which is greater than the first vertical extension, in a section directly adjoining the gate construction 330 or the gate contact structure 315 g .
  • the transition Tr may be continuous or may include one or more steps.
  • the gate electrode 155 , the idle gate electrode 155 a and the conductive structure 157 may be homogeneous structures or may have a layered structure including one or more metal containing layers. According to an embodiment the gate electrode 155 , the idle gate electrode 155 a and the conductive structure 157 may include or consist of a heavily doped polycrystalline silicon layer.
  • the gate dielectric 151 may include or consist of a semiconductor oxide, for example thermally grown or deposited silicon oxide, semiconductor nitride, for example deposited or thermally grown silicon nitride or a semiconductor oxynitride, for example silicon oxynitride.
  • the first load electrode 310 may be, e.g., an anode electrode of an MCD, a source electrode of an IGFET or an emitter electrode of an IGBT.
  • Contact structures 315 electrically connect the first load electrode 310 with the body/anode zones 115 and the source zones 110 .
  • the first load electrode 310 may be or may be electrically coupled or connected to a first load terminal L 1 , for example the anode terminal of an MCD, the emitter terminal of an IGBT or the source terminal of an IGFET.
  • a second load electrode 320 which directly adjoins the second surface 102 and the pedestal layer 130 , may form or may be electrically connected to a second load terminal L 2 , which may be the cathode terminal of an MCD, the collector terminal of an IGBT or the drain terminal of an IGFET.
  • Each of the first and second load electrodes 310 , 320 may consist of or contain, as main constituent(s), aluminum (Al), copper (Cu), or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, at least one of the first and second load electrodes 310 , 320 may contain, as main constituent(s), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), vanadium (V), silver (Ag), gold (Au), platinum (Pt), and/or palladium (Pd).
  • At least one of the first and second load electrodes 310 , 320 may include two or more sub-layers, wherein each sub-layer contains one or more of Ni, Ti, V, Ag, Au, Pt, W, and Pd as main constituent(s), e.g., a silicide, a nitride and/or an alloy.
  • the interlayer dielectric 210 may include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicon glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass), by way of example.
  • BSG boron silicate glass
  • PSG phosphorus silicate glass
  • BPSG boron phosphorus silicate glass
  • the semiconductor body 100 includes a non-depletable extension zone 170 of the second conductivity type.
  • the non-depletable extension zone 170 is electrically connected to at least one of the body/anode zones 115 and may directly adjoin or overlap with an outermost of the body/anode zones 115 , by way of example.
  • a net dopant concentration in the non-depletable extension zone 170 is sufficiently high such that the non-depletable extension zone 170 is not completely depleted when the respective semiconductor device 500 is operated within its maximum blocking ratings.
  • the net dopant concentration of the non-depletable extension zone 170 is such that when a maximum voltage is applied between the first and second load electrodes 310 , 320 the non-depletable extension zone 170 is not depleted regardless of a gate voltage applied to the gate construction 330 provided that the applied gate voltage is within the maximum ratings of the semiconductor device 500 for the gate voltage.
  • the semiconductor device 500 When the semiconductor device 500 is operated with the forward-biased first pn junction pn 1 between the body/anode zones 115 and the drift zone 120 , the body/anode zones 115 inject holes and the pedestal layer 130 injects electrons into the drift zone 120 .
  • the injected charge carriers form a charge carrier plasma in both the active area 610 and the edge area 690 .
  • the semiconductor device 500 commutates after reverse-biasing the first pn junction pn 1 the second load electrode 320 drains off electrons and the first electrode 310 drains off holes.
  • Holes flowing from the edge area 690 to the first load electrode 310 travel to the outermost contact structure 315 that electrically connects the first load electrode 310 with the outermost source and body/anode zones 110 , 115 of the active area 610 .
  • the hole current flow results in high hole concentrations and high hole current densities in a portion of the edge area 690 in the vertical projection of the conductive structure 157 .
  • the electric surface field strength is high resulting in increased charge carrier multiplication.
  • the dynamic breakdown voltage is locally reduced and the field dielectric 211 can be irreversibly damaged.
  • the non-depletable extension zone 170 effects that a surface electric field is only formed beyond a minimum hole current density which compensates for the charge of the stationary p-type dopants in the non-depletable extension zone 170 .
  • Increasing the p-type dopant concentration reduces the surface electric field strength such that the dynamic breakdown voltage may be locally increased.
  • the field dielectric 211 is more reliable and in a half-bridge circuit the semiconductor device 500 can sustain steeper and faster gate signals of the commutating switch of the half-bridge circuit.
  • the effective dose of p-type dopants in the non-depletable extension zone is greater than 2.5E12 cm ⁇ 2 , for example at least 1E13 cm ⁇ 2 .
  • the p-type dopant dose in the non-depletable extension zone 170 is greater than 2E13 cm ⁇ 2 .
  • the non-depletable extension zone 170 directly adjoins or overlaps or is electrically connected with the p-type body/anode zone 115 of the outermost transistor cell TC of the active area 610 with reference to the edge area 690 .
  • the impurity concentration is constant or decreases by not more than 50% between a starting point of the transition Tr, where a vertical extension of the transition Tr starts to increase from the first vertical extension, and a reference point at a distance of at least 1 ⁇ m to the starting point.
  • the impurity concentration is constant or deviates by not more than 50% over a distance of at least 3 ⁇ m, for example at least 8 ⁇ m, to the starting point in the direction along which the transition Tr increases.
  • a vertical extension of the non-depletable extension zone 170 perpendicular to the first surface 101 may exceed a vertical extension of the body/anode zones 115 of the transistor cells TC.
  • the semiconductor device 500 of FIG. 1B differs from the semiconductor device 500 of FIG. 1A in that a dedicated contact structure 315 a electrically connects the first load electrode 310 directly with the non-depletable extension zone 170 in the edge area 690 .
  • the dedicated contact structure 315 a is spatially separated from any source zone 110 .
  • the transition Tr of the field dielectric 211 includes a step that corresponds to a vertical step in the conductive structure 157 .
  • the semiconductor device 500 of FIG. 1C is a superjunction IGFET based on the semiconductor device 500 of FIG. 1A .
  • the first load electrode 310 is effective as source electrode electrically connected to a source terminal S.
  • the second load terminal 320 is effective as drain electrode D.
  • An edge termination construction 195 formed in a portion of the edge area 690 directly adjoining the side surface 103 may include a drain electrode construction 325 on a front side of the semiconductor body 100 opposite to the second load electrode 320 .
  • the drift zone 120 may include a superjunction structure 180 including first zones 181 of the first conductivity type and second zones 182 of the second conductivity type. At least the second zones 182 or at least the first zones 181 may be columnar structures formed by implantation e.g. in successive epitaxy and implantation steps. According to other embodiments the second zones 182 are formed by depositing material containing p-type dopants into trenches temporally formed between the first zones 181 or by introducing dopants through sidewalls of trenches temporally extending from the first surface 101 into the drift zone 120 .
  • the lateral cross-sectional areas of the second zones 182 may be circles, ovals, ellipses or rectangles with or without rounded corners and the first zones 181 may form a grid with the second zones 182 arranged in the meshes.
  • lateral cross-sectional areas of the first zones 181 are circles, ellipses, ovals or rectangles with or without rounded corners and the second zones 182 form a grid with the first zones 181 arranged in the meshes.
  • the first and second zones 181 , 182 form a regular stripe pattern, wherein the stripes may extend through a significant portion of the active area 610 or may cross the active area 610 .
  • the dopant concentrations in the first and second zones 181 , 182 may be adjusted to each other such that the portion of the drift zone 120 including the superjunction structure 180 can be completely depleted in a reverse blocking mode of the semiconductor device 500 .
  • the first and second zones 181 , 182 may be formed exclusively within the active area 610 , whereas the edge area 690 or a gate area in the vertical projection of gate constructions such as gate pads, gate fingers and/or gate runners are devoid of any superjunction structure, for example devoid of any first and second zones 181 , 182 .
  • the semiconductor device 500 may include a superjunction structure with first and second zones 181 , 182 in the active area 610 and only intrinsic or weakly doped regions of the first conductivity type having a lower net impurity concentration than the first zones 181 in the edge area 610 and in the vertical projection of gate areas.
  • first zones 181 and second zones 182 may overlap in the edge area 610 and/or in the vertical projection of gate areas to form regions of a low net dopant concentration in the concerned areas.
  • a superjunction structure with first and second zones 181 , 182 is formed in both the active area 610 and the edge area 690 .
  • a depletable extension zone 175 may directly adjoin to or overlap with the non-depletable extension zone 170 and one, some or all of the second zones 182 in the edge area 690 along the illustrated cross-sectional line.
  • the p-type dopant dose in the depletable extension zone 175 is sufficiently low such that the depletable extension zone 175 is completely depleted in the blocking mode of the semiconductor device 500 .
  • the implanted p-type dopant dose in the depletable extension zone 175 may result from an implant dose of at most 3.5E12 cm ⁇ 2 resulting, when considering segregation effects, in a remnant effective p-type dopant dose of at most 2E12 cm ⁇ 2 in silicon.
  • a vertical extension of the non-depletable extension zone 170 perpendicular to the first surface 101 may exceed a vertical extension of the body/anode zones 115 of the transistor cells TC.
  • an edge of a depletion zone in the semiconductor body 100 oriented to the first surface 101 may have a greater distance to the first surface 101 in the non-depletable extension zone 170 than in p-type structures including the body/anode zones 115 and the second zones 182 .
  • the effect may be even more pronounced since in the active area 610 the second zones 182 accelerate the hole discharge and, when finally the hole current in the active area 610 pinches off, the edge area 690 still discharges holes and due to leakage inductance carries further increased hole current densities.
  • the depletable extension zone 175 reduces the resistance effective for the total hole current flow from at least one or some of the second zones 182 of the edge area 690 to a contact structure 315 electrically connecting the first load electrode 310 with the extension zones 170 , 175 and may reduce the switching losses.
  • the comparatively high hole current density significantly reduces the dynamic breakdown voltage of the field dielectric 211 .
  • the non-depletable extension zone 170 locally decreases the surface electric field strength without significantly adversely affecting the lateral voltage blocking capability despite that the hole current densities are increased by approximately one order of magnitude.
  • the semiconductor device 500 of FIG. 1D differs from the superjunction IGFET of FIG. 1C in that the depletable extension zone 175 is connected to all second zones 182 in the edge area 690 between the non-depletable extension zone 170 and the side surface 103 and in that a spacer zone 173 of the first conductivity type separates the depletable extension zone 175 from the first surface 101 .
  • the spacer zone 173 reduces the effect of holes flowing into direction of the active area 610 during commutation on the field dielectric 211 .
  • the surface electric field is more homogenous, the integrated ionization charge along the hole current flow is reduced and the dynamic breakdown voltage is further increased.
  • the semiconductor device 500 of FIG. 1E is an IGFET based on the semiconductor device 500 of FIG. 1A .
  • a field stop layer 128 having a dopant concentration at least twice as high as in the drift zone 120 separates the drift zone 120 from the pedestal layer 130 .
  • a buffer layer with a dopant concentration that is lower than in the first zones 181 is formed between the pedestal layer 130 and the second zones 182 .
  • the transistor cells TC are vertical transistor cells TC with the gate structures 150 including buried gate electrodes 155 extending from the first surface 101 into the semiconductor body 100 .
  • a dielectric structure 205 may separate the first load electrode 310 from the buried gate electrodes 155 .
  • IGBTs on the basis of the IGFETs of FIGS. 1C to 1E with the pedestal layer 130 having the p-type or including p-type zones.
  • the first load electrode 310 is effective as an emitter electrode forming or electrically connected or coupled to an emitter terminal.
  • the second load electrode 320 is effective as collector electrode and forms or is electrically connected to a collector terminal.
  • the semiconductor device 500 of FIG. 1F is an MCD that may include a barrier layer 121 between the body/anode zones 115 and the drift zone 120 .
  • the pedestal layer 130 may include first zones 131 of the first conductivity type and second zones 132 of the second conductivity type extending between the drift zone 120 and the second surface 102 , respectively.
  • the transistor cells TC are switched off in the normal forward-biased state of the MCD. Before commutation, a potential applied to the gate electrode 155 generates inversion layers from the source zones 110 to the drift zone 120 through the body/anode zones 115 .
  • the inversion layers short-circuit the first pn junction pn 1 between the body/anode zones 115 and the drift zone 120 and reduce or suppress hole injection from the body/anode zones 115 into the drift zone 120 .
  • the carrier plasma in the drift zone 120 is reduced and the recovery charge can be decreased.
  • the barrier layer 121 reduces the lateral voltage drop along the first pn junction pn 1 to avoid injection between the gate structures 150 in a distance to the inversion layers.
  • the semiconductor device 500 may include IGFET cells and MGD cells with gate electrodes electrically connected to the first load electrode 310 .
  • the current flow between the first and second load electrodes 310 , 320 results in that the body/anode zones 115 are negatively biased with respect to the first load electrode 310 and the gate electrodes of the MGDs and an inversion layer may be formed in the body/anode zones 115 .
  • the total current through the semiconductor device 500 is above an average current flow density threshold, it is typically dominated by a unipolar current flow reducing the electric losses compared to the case of a total current flow across the first pn junctions pn 1 .
  • FIGS. 2A to 2G refer to lateral cross-sections of semiconductor devices 500 for illustrating embodiments of the lateral extension of the non-depletable extension zones 170 of any of the semiconductor devices 500 of FIGS. 1A to 1E .
  • An edge area 690 devoid of functional transistor cells separates an active area 610 , which includes the functional transistor cells, from the side surface 103 of a semiconductor body 100 .
  • the edge area 690 includes gate area 695 in the vertical projection of a gate construction 330 .
  • the gate area 695 is assigned to a gate construction 330 including a single gate pad.
  • the gate construction 330 may include more than one gate pad, a gate runner, and/or one or more gate fingers and the gate area 695 may include further portions in the vertical projection of gate fingers and/or gate runners that form sections of electric connections between gate electrodes and a gate pad in a metallization plane.
  • Gate pad and gate area 695 may be arranged in a corner or along one of the lateral sides of the semiconductor body 100 .
  • a gate runner may surround the active area 610 .
  • a gate finger may separate the active areas 610 in separate cell fields.
  • FIG. 2A shows a non-depletable extension zone 170 completely surrounding the active area 610 along a circumferential line CL sparing the gate area 695 .
  • a net dopant concentration of the non-depletable extension zone 170 is constant.
  • a depletable extension zone 175 may directly adjoin or overlap with the non-depletable extension zone 170 in the edge area 690 at a side oriented to the side surface 103 .
  • FIG. 2B refers to an embodiment with a first, along the circumferential line CL approximately constant net dopant concentration p 1 + in first sections 170 a of the non-depletable extension zone and an enhanced second net dopant concentration p 2 + , which is higher, e.g. at least twice as high as the first net dopant concentration p 1 + , in second sections 170 b .
  • the second sections 170 b may be laterally curved sections close to the corners of the semiconductor body 100 and/or sections between the active area 610 and the gate area 695 .
  • the first sections 170 a may be straight sections connecting the second sections 170 b.
  • the second sections 170 b may be formed by implanting the concerned dopants at a locally increased implant dose or by performing a first implant with uniform implant dose along the circumferential line CL and a second implant which is selectively effective in the second sections.
  • the higher dopant concentration in the second sections 170 b may compensate for an increased hole current close to the corners and to the gate area 695 and resulting from increased hole current density in wider portions of the semiconductor body 100 without source and body contacts, e.g. in the gate area 695 and close to the corners, where more holes are allocated per length unit of the extension zones 170 , 175 along the circumferential line CL.
  • the dopant concentration profiles of the non-depletable extension zones 170 along the circumferential line CL may include further sections with a dopant concentration between the first and the second dopant concentrations.
  • the first sections 170 a of the non-depletable extension zone may contain a dopant dose of at least 2.5E12 cm ⁇ 2 , for example at least 1E13 cm ⁇ 2 or greater than 2E13 cm ⁇ 2 .
  • the second sections 170 b may contain a dopant dose which is at least twice as high as the first dopant dose, for example at least four times as high as the first dopant dose.
  • the non-depletable extension zone 170 includes an enlarged portion 170 x formed in the vertical projection of a gate pad in the gate area 695 .
  • the enlarged portion 170 x may extend over the complete gate area 695 and may overlap the complete vertical projection of a gate construction including at least a gate pad.
  • a further portion of the non-depletable extension zone 170 surrounds the active area 610 as described with reference to FIG. 2A .
  • the non-depletable extension zone 170 is exclusively formed in the vertical projection of a gate pad in the gate area 695 .
  • the non-depletable extension zone 170 may include further sections in further sections of the gate area 695 assigned to gate fingers and/or gate runners.
  • the semiconductor device 500 of FIG. 2E differs from the one in FIG. 2B in that the non-depletable extension zone 170 includes a section of enhanced dopant concentration 170 b that extends over the complete or at least a main portion of the gate area 695 and overlaps with at least a main portion of the vertical projection of a gate pad.
  • the non-depletable extension zone 170 may include further sections in further sections of the gate area 695 assigned to gate fingers and/or gate runners.
  • FIG. 2F refers to an embodiment with the non-depletable extension zone 170 including isolated segments arranged along the circumferential line CL.
  • the segments may be curved sections in the corners of the semiconductor body 100 and/or sections between the active area 610 and the gate area 695 .
  • FIG. 2G refers to a layout with the gate area 695 arranged along one of the lateral sides and symmetric with respect to a lateral center axis of the semiconductor body 100 . Sections of the depletable and not-depletable extension zones 175 , 170 may completely span the gate area 695 . In a further embodiment, the gate pad may be located in the middle of the active area 610 .
  • FIG. 3 refers to semiconductor devices 500 with a non-depletable extension zone 170 formed at least in a portion of the vertical projection of a gate construction 330 .
  • the non-depletable extension zone 170 may extend over at least 40% of the vertical projection of the gate construction 330 , for example over at least 80%. According to an embodiment the non-depletable extension zone 170 extends over the whole vertical projection of the gate construction 330 .
  • the configuration of the gate construction 330 , the conductive structure 157 electrically connecting the gate construction 330 with idle gate electrodes 155 a as well as the non-depletable extension zone 170 as shown in FIG. 3 can be combined with any of the semiconductor devices 500 described with reference to FIGS. 1A to 1F .
  • An interlayer dielectric structure 200 adjoins a first surface 101 of the semiconductor body 100 . In the edge area 690 the interlayer dielectric structure 200 separates a gate construction 330 from the semiconductor body 100 .
  • the interlayer dielectric structure 200 may include a conductive structure 157 , wherein a field dielectric 211 separates the conductive structure 157 from the semiconductor body 100 and a capping dielectric 212 separates the conductive structure 157 from the gate construction 330 .
  • the gate construction 330 may be a gate pad suitable as a landing pad for a bond wire or another chip-to-leadframe or chip-to-chip connection like a soldered clip.
  • the gate pad can be in direct connection with the conductive structure 157 .
  • the conductive structure 157 can be a part of an integrated gate resistor or polycrystalline silicon diode or can be omitted below the gate pad. For further details reference is made to the description of FIGS. 1A to 2G .
  • the non-depletable extension zones 170 reduce a resistance effective for a hole current flow between the edge area 690 and the outermost contact of the first load electrode 310 oriented to the edge area 690 .
  • the non-depletable extension zone 170 is not fully depleted and, consequently, improves the depletion process of holes and reduces dynamic switching losses.
  • the non-depletable extension zone 170 shields the gate construction 330 such that the gate-to-drain capacity C gd is not increased or is increased to a lower degree resulting in reduced switching losses.
  • FIG. 4 schematically shows the switching losses Eoff as a function of the load current Isat. Comparative examples 791 without non-depletable extension zones show higher switching losses as comparable devices 792 including non-depletable extension zones. The non-depletable extension zones reduce the commutation losses. Since in resonant applications energy capacitively stored in the semiconductor device 500 is recovered, losses resulting from a gate construction 330 may contribute to a third of the overall commutation losses.
  • FIGS. 5A to 5D refer to electronic circuits 700 including one or more half-bridge circuits 710 based on two semiconductor switching devices 711 , 712 with load current paths connected in series between Vdd and Gnd.
  • the semiconductor switching devices 711 , 712 may be IGFETs or IGBTs. At least one of the semiconductor switching devices 711 , 712 may be or may include one of the semiconductor devices 500 of the previous figures.
  • the half-bridge circuit 710 or the complete electronic circuit 700 may be integrated in a power module.
  • the electronic circuit 700 may include a gate driver circuit 720 generating and driving a first gate signal at a first driver terminal Gout 1 and a second gate signal at a second driver terminal Gout 2 .
  • the first and second driver terminals Gout 1 , Gout 2 are electrically coupled or connected to gate terminals G of the semiconductor switching devices 711 , 712 .
  • the gate driver circuit 720 controls the gate signals such that during regular switching cycles the first and second switching devices 711 , 712 are alternatingly in the on state. During desaturation cycles, the gate driver circuit 720 may apply desaturation pulses before switching one of the switching devices 711 , 712 into the on state.
  • the switching devices 711 , 712 are n-IGFETs with a source terminal S of the first switching device 711 and a drain terminal D of the second switching device 712 electrically connected to a switching terminal Sw.
  • the first switching device 711 , 712 is a p-IGFET and the second switching device 712 is an n-IGFET.
  • the switching devices 711 , 712 are n-channel IGBTs with an emitter terminal E of the first switching device 711 and a collector terminal C of the second switching device 712 electrically connected to a switching terminal Sw.
  • FIG. 5D shows an electronic circuit 700 with two half-bridges 710 whose load paths are connected in parallel and operated in a full-bridge configuration.
  • a load 900 e.g. an inductive load, may be connected to the switching terminals Sw of the two half-bridges 710 .
  • the load 900 may be a motor winding, an inductive cooking plate or a transformer winding in a switched-mode power supply, by way of example.
  • the electronic circuit 700 may include three half-bridges 710 for driving a motor with three windings wherein each winding is connected between a star node of the motor windings and one of the switching terminals Sw of the half bridges 710 .

Abstract

A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.

Description

    BACKGROUND
  • Applications like half bridge circuits use a body diode between a body and a drift zone in a semiconductor body of a semiconductor switching device as a freewheeling diode in the reverse mode of the switching device. In the forward-biased mode of the body diode holes and electrons injected into the drift zone form a high density charge carrier plasma that results in a low forward voltage drop of the body diode. A significant portion of the charge carrier floods an edge area separating an active area including transistor cells from a side surface of the semiconductor body. When the switching device changes from reverse-biased to forward-biased, the body diode changes from forward-biased to reverse-biased and mobile charge carriers are removed from the drift zone.
  • It is desirable to provide more reliable semiconductor devices.
    • SUMMARY
  • According to an embodiment a semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.
  • According to another embodiment a semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body. An interlayer dielectric structure adjoins a first surface of the semiconductor body. In the edge area the interlayer dielectric structure separates a gate construction from the semiconductor body. In the vertical projection of at least a portion of the gate construction in the semiconductor body is a non-depletable extension zone of a conductivity type of body/anode zones of the transistor cells. The non-depletable extension zone is electrically connected to at least one of the body/anode zones.
  • According to a further embodiment a half-bridge circuit includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.
  • Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the invention and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description.
  • FIG. 1A is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment related to planar gate electrodes and a stepless transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1B is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment related to planar gate electrodes and a stepped transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1C is a schematic cross-sectional view of a portion of a superjunction IGFET according to an embodiment related to planar gate electrodes and a stepless transition of a field dielectric between a semiconductor body and a conductive structure.
  • FIG. 1D is a schematic cross-sectional view of a portion of a superjunction IGFET according to an embodiment related to a buried depletable extension zone and a stepless transition of a field dielectric between a conductive structure and a semiconductor body.
  • FIG. 1E is a schematic cross-sectional view of a portion of a superjunction IGFET in accordance with an embodiment related to buried gate electrodes.
  • FIG. 1F is a schematic cross-sectional view of a portion of an MCD (MOS-controlled diode) according to another embodiment.
  • FIG. 2A is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone surrounding an active area along a circumferential line at a constant dopant concentration.
  • FIG. 2B is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment providing a non-depletable extension zone that surrounds an active area and that includes sections of enhanced dopant concentration.
  • FIG. 2C is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with an enlarged portion of a non-depletable extension zone formed in the vertical projection of a gate construction.
  • FIG. 2D is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone exclusively formed in the vertical projection of a gate construction.
  • FIG. 2E is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a non-depletable extension zone including a section of enhanced dopant concentration in the vertical projection of a gate construction.
  • FIG. 2F is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment providing a segmented non-depletable extension zone.
  • FIG. 2G is a schematic lateral cross-sectional view of a semiconductor device in accordance with an embodiment with a portion of a non-depletable extension zone formed in the vertical projection of a portion of a gate construction.
  • FIG. 3 is a schematic cross-sectional view of a portion of a semiconductor device in accordance with another embodiment with a non-depletable extension zone in the vertical projection of a portion of a gate construction.
  • FIG. 4 is a schematic diagram comparing switching-off losses for illustrating effects of the embodiments.
  • FIG. 5A is a schematic circuit diagram of a half-bridge circuit according to an embodiment with two n-type IGFETs.
  • FIG. 5B is a schematic circuit diagram of a half-bridge circuit according to an embodiment with a p-type and an n-type IGFET.
  • FIG. 5C is a schematic circuit diagram of a half-bridge circuit according to an embodiment with IGBTs.
  • FIG. 5D is a schematic circuit diagram of a full-bridge circuit according to a further embodiment.
    •  DETAILED DESCRIPTION
  • In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements have been designated by corresponding references in the different drawings if not stated otherwise.
  • The terms “having”, “containing”, “including”, “comprising” and the like are open, and the terms indicate the presence of stated structures, elements or features but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
  • The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.
  • The Figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n−” means a doping concentration which is lower than the doping concentration of an “n”-doping region while an “n+”-doping region has a higher doping concentration than an “n”-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”-doping regions may have the same or different absolute doping concentrations.
  • FIGS. 1A to 1E refer to controllable semiconductor devices 500 including active transistor cells and/or controllable desaturation or injection cells, for example controllable semiconductor diodes such as MCDs, IGFETs (insulated gate field effect transistors) including MOSFETs (metal oxide semiconductor FETs) in the usual meaning including FETs with metal gates as well as FETs with non-metal gates, JFETs (junction field effect transistors), IGBTs (insulated gate bipolar transistors), and thyristors, by way of example.
  • Each of the semiconductor devices 500 is based on a semiconductor body 100 from a single-crystalline semiconductor material such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any other AIIIBv semiconductor.
  • The semiconductor body 100 has a first surface 101 which may be approximately planar or which may be given by a plane spanned by coplanar surface sections as well as a mainly planar second surface 102 parallel to the first surface 101. A minimum distance between the first and second surfaces 101, 102 is selected to achieve a specified voltage blocking capability of the semiconductor device 500. A side surface 103 connects the first and second surfaces 101, 102.
  • In a plane perpendicular to the cross-sectional plane the semiconductor body 100 may have a rectangular shape with an edge length in the range of several millimeters or may be disc-shaped with a diameter of several centimeters. A normal to the first surface 101 defines a vertical direction and directions orthogonal to the vertical direction are lateral directions.
  • The semiconductor body 100 includes a drift zone 120 of a first conductivity type as well as a pedestal layer 130 between the drift zone 120 and the second surface 102.
  • A dopant concentration in the drift zone 120 may gradually or in steps increase or decrease with increasing distance to the first surface 101 at least in portions of its vertical extension. According to other embodiments the dopant concentration in the drift zone 120 may be approximately uniform. A mean dopant concentration in the drift zone 120 may be between 5E12 cm−3 and 1E16 cm−3, for example in a range from 5E13 cm−3 to 5E15 cm−3. The drift zone 120 may include further dopant zones, e.g. a superjunction structure.
  • The pedestal layer 130 may have the first conductivity type in case the semiconductor device 500 is a semiconductor diode, an IGFET or a JFET, may have a second conductivity type, which is complementary to the first conductivity type, in case the semiconductor device 500 is an IGBT or a thyristor or may contain zones of both conductivity types extending between the drift zone 120 and the second surface 102 in case the semiconductor device 500 is an MCD or an RC-IGBT (reverse conducting IGBT). The dopant concentration in the pedestal layer 130 is sufficiently high to form an ohmic contact with a metal directly adjoining the second surface 102. In case the semiconductor body 100 is based on silicon Si, a mean dopant concentration for a p-type pedestal layer 130 or p-type zones of the pedestal layer 130 may be at least 1E16 cm−3, for example at least 5E17 cm−3.
  • The semiconductor devices 500 further includes active, functional transistor cells TC in an active area 610, whereas an edge area 690 between the side surface 103 and the active area 610 is devoid of any functional transistor cells of the type present in the active area 610. Each active transistor cell TC includes body/anode zones 115 of the second conductivity type forming first pn junctions pn1 with the drift zone 120 as well as source zones 110 forming second pn junctions with the body/anode zones 115. The source zones 110 may be wells extending from the first surface 101 into the semiconductor body 100, for example into the body/anode zones 115.
  • A gate structure 150 includes a conductive gate electrode 155 which may include or consist of a heavily doped polycrystalline silicon layer or a metal-containing layer as well as a gate dielectric 151 separating the gate electrode 155 from the semiconductor body 100. The gate dielectric 151 capacitively couples the gate electrode 155 to channel portions of the body/anode zones 115.
  • In the illustrated embodiments and for the following description, the first conductivity type is the n-type and the second conductivity type is the p-type. Similar considerations as outlined below apply to embodiments with the first conductivity being the p-type and the second conductivity type being the n-type.
  • When a voltage applied to the gate electrode 150 exceeds a preset threshold voltage, electrons accumulate in the channel portions of the body/anode zones 115 directly adjoining the gate dielectric 151 and form inversion channels short-circuiting the first pn junctions pn1.
  • The gate structure 150 includes an idle portion 150 a including an idle gate electrode 155 a in the edge area 690. The idle gate electrode 155 a and the gate electrode 155 are electrically and structurally connected to each other and may be portions of the same layered structure. A gate construction 330 may be connected to the gate electrode 155 via the idle gate electrode 155 a.
  • The gate construction 330 may include at least one of a gate pad, a gate finger, and a gate runner electrically connected to the gate electrode 155, respectively. A gate pad may be a metal pad suitable as a landing pad for a bond wire or another chip-to-leadframe or chip-to-chip connection like a soldered clip. The gate pad may be arranged between a first load electrode 310 and the side surface 103 or in a center portion of the semiconductor body 100. A gate runner may be a metal line surrounding the active area 610. A gate finger may be a metal line separating the active areas 610 in separated cell fields. An interlayer dielectric 210 separates the gate construction 330 from the semiconductor body 100 and may insulate the gate electrode 155 from the first load electrode 310.
  • A conductive structure 157 structurally and electrically connects the idle gate electrode 155 a with the gate construction 330 or with a gate contact structure 315 g extending from the gate construction 330 into the interlayer dielectric 210. The conductive structure 157 can be a part of an integrated gate resistor or polycrystalline silicon diode or can be omitted below the gate construction 330. A portion of the interlayer dielectric 210 between the conductive structure 157 and the semiconductor body 100 forms a field dielectric 211. The field dielectric 211 has a transition Tr between a first vertical extension close to the gate dielectric thickness in a portion directly adjoining the idle gate electrode 155 a and a second vertical extension, which is greater than the first vertical extension, in a section directly adjoining the gate construction 330 or the gate contact structure 315 g. The transition Tr may be continuous or may include one or more steps.
  • The gate electrode 155, the idle gate electrode 155 a and the conductive structure 157 may be homogeneous structures or may have a layered structure including one or more metal containing layers. According to an embodiment the gate electrode 155, the idle gate electrode 155 a and the conductive structure 157 may include or consist of a heavily doped polycrystalline silicon layer.
  • The gate dielectric 151 may include or consist of a semiconductor oxide, for example thermally grown or deposited silicon oxide, semiconductor nitride, for example deposited or thermally grown silicon nitride or a semiconductor oxynitride, for example silicon oxynitride.
  • The first load electrode 310 may be, e.g., an anode electrode of an MCD, a source electrode of an IGFET or an emitter electrode of an IGBT. Contact structures 315 electrically connect the first load electrode 310 with the body/anode zones 115 and the source zones 110. The first load electrode 310 may be or may be electrically coupled or connected to a first load terminal L1, for example the anode terminal of an MCD, the emitter terminal of an IGBT or the source terminal of an IGFET.
  • A second load electrode 320, which directly adjoins the second surface 102 and the pedestal layer 130, may form or may be electrically connected to a second load terminal L2, which may be the cathode terminal of an MCD, the collector terminal of an IGBT or the drain terminal of an IGFET.
  • Each of the first and second load electrodes 310, 320 may consist of or contain, as main constituent(s), aluminum (Al), copper (Cu), or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, at least one of the first and second load electrodes 310, 320 may contain, as main constituent(s), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), vanadium (V), silver (Ag), gold (Au), platinum (Pt), and/or palladium (Pd). For example, at least one of the first and second load electrodes 310, 320 may include two or more sub-layers, wherein each sub-layer contains one or more of Ni, Ti, V, Ag, Au, Pt, W, and Pd as main constituent(s), e.g., a silicide, a nitride and/or an alloy.
  • The interlayer dielectric 210 may include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicon glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass), by way of example.
  • In the vertical projection of the transition Tr in the field dielectric 211, the semiconductor body 100 includes a non-depletable extension zone 170 of the second conductivity type. The non-depletable extension zone 170 is electrically connected to at least one of the body/anode zones 115 and may directly adjoin or overlap with an outermost of the body/anode zones 115, by way of example. A net dopant concentration in the non-depletable extension zone 170 is sufficiently high such that the non-depletable extension zone 170 is not completely depleted when the respective semiconductor device 500 is operated within its maximum blocking ratings.
  • According to an embodiment the net dopant concentration of the non-depletable extension zone 170 is such that when a maximum voltage is applied between the first and second load electrodes 310, 320 the non-depletable extension zone 170 is not depleted regardless of a gate voltage applied to the gate construction 330 provided that the applied gate voltage is within the maximum ratings of the semiconductor device 500 for the gate voltage.
  • When the semiconductor device 500 is operated with the forward-biased first pn junction pn1 between the body/anode zones 115 and the drift zone 120, the body/anode zones 115 inject holes and the pedestal layer 130 injects electrons into the drift zone 120. The injected charge carriers form a charge carrier plasma in both the active area 610 and the edge area 690. When the semiconductor device 500 commutates after reverse-biasing the first pn junction pn1 the second load electrode 320 drains off electrons and the first electrode 310 drains off holes. Holes flowing from the edge area 690 to the first load electrode 310 travel to the outermost contact structure 315 that electrically connects the first load electrode 310 with the outermost source and body/ anode zones 110, 115 of the active area 610. The hole current flow results in high hole concentrations and high hole current densities in a portion of the edge area 690 in the vertical projection of the conductive structure 157.
  • On the other hand in areas of the semiconductor body 100 below the transition Tr the electric surface field strength is high resulting in increased charge carrier multiplication. As a result of the surface field strength and the hole current flow, the dynamic breakdown voltage is locally reduced and the field dielectric 211 can be irreversibly damaged.
  • The non-depletable extension zone 170 effects that a surface electric field is only formed beyond a minimum hole current density which compensates for the charge of the stationary p-type dopants in the non-depletable extension zone 170. Increasing the p-type dopant concentration reduces the surface electric field strength such that the dynamic breakdown voltage may be locally increased. The field dielectric 211 is more reliable and in a half-bridge circuit the semiconductor device 500 can sustain steeper and faster gate signals of the commutating switch of the half-bridge circuit.
  • In case of a silicon semiconductor body 100, the effective dose of p-type dopants in the non-depletable extension zone is greater than 2.5E12 cm−2, for example at least 1E13 cm−2. According to an embodiment the p-type dopant dose in the non-depletable extension zone 170 is greater than 2E13 cm−2. The non-depletable extension zone 170 directly adjoins or overlaps or is electrically connected with the p-type body/anode zone 115 of the outermost transistor cell TC of the active area 610 with reference to the edge area 690.
  • Within the non-depletable extension zone 170 the impurity concentration is constant or decreases by not more than 50% between a starting point of the transition Tr, where a vertical extension of the transition Tr starts to increase from the first vertical extension, and a reference point at a distance of at least 1 μm to the starting point. According to an embodiment, the impurity concentration is constant or deviates by not more than 50% over a distance of at least 3 μm, for example at least 8 μm, to the starting point in the direction along which the transition Tr increases.
  • A vertical extension of the non-depletable extension zone 170 perpendicular to the first surface 101 may exceed a vertical extension of the body/anode zones 115 of the transistor cells TC.
  • The semiconductor device 500 of FIG. 1B differs from the semiconductor device 500 of FIG. 1A in that a dedicated contact structure 315 a electrically connects the first load electrode 310 directly with the non-depletable extension zone 170 in the edge area 690. The dedicated contact structure 315 a is spatially separated from any source zone 110. The transition Tr of the field dielectric 211 includes a step that corresponds to a vertical step in the conductive structure 157.
  • The semiconductor device 500 of FIG. 1C is a superjunction IGFET based on the semiconductor device 500 of FIG. 1A. The first load electrode 310 is effective as source electrode electrically connected to a source terminal S. The second load terminal 320 is effective as drain electrode D. An edge termination construction 195 formed in a portion of the edge area 690 directly adjoining the side surface 103 may include a drain electrode construction 325 on a front side of the semiconductor body 100 opposite to the second load electrode 320.
  • The drift zone 120 may include a superjunction structure 180 including first zones 181 of the first conductivity type and second zones 182 of the second conductivity type. At least the second zones 182 or at least the first zones 181 may be columnar structures formed by implantation e.g. in successive epitaxy and implantation steps. According to other embodiments the second zones 182 are formed by depositing material containing p-type dopants into trenches temporally formed between the first zones 181 or by introducing dopants through sidewalls of trenches temporally extending from the first surface 101 into the drift zone 120.
  • The lateral cross-sectional areas of the second zones 182 may be circles, ovals, ellipses or rectangles with or without rounded corners and the first zones 181 may form a grid with the second zones 182 arranged in the meshes. According to another embodiment lateral cross-sectional areas of the first zones 181 are circles, ellipses, ovals or rectangles with or without rounded corners and the second zones 182 form a grid with the first zones 181 arranged in the meshes. In accordance with a further embodiment the first and second zones 181, 182 form a regular stripe pattern, wherein the stripes may extend through a significant portion of the active area 610 or may cross the active area 610.
  • The dopant concentrations in the first and second zones 181, 182 may be adjusted to each other such that the portion of the drift zone 120 including the superjunction structure 180 can be completely depleted in a reverse blocking mode of the semiconductor device 500.
  • According to an embodiment, the first and second zones 181, 182 may be formed exclusively within the active area 610, whereas the edge area 690 or a gate area in the vertical projection of gate constructions such as gate pads, gate fingers and/or gate runners are devoid of any superjunction structure, for example devoid of any first and second zones 181, 182. For example, the semiconductor device 500 may include a superjunction structure with first and second zones 181, 182 in the active area 610 and only intrinsic or weakly doped regions of the first conductivity type having a lower net impurity concentration than the first zones 181 in the edge area 610 and in the vertical projection of gate areas. Alternatively first zones 181 and second zones 182 may overlap in the edge area 610 and/or in the vertical projection of gate areas to form regions of a low net dopant concentration in the concerned areas.
  • According to the illustrated embodiment, a superjunction structure with first and second zones 181, 182 is formed in both the active area 610 and the edge area 690. A depletable extension zone 175 may directly adjoin to or overlap with the non-depletable extension zone 170 and one, some or all of the second zones 182 in the edge area 690 along the illustrated cross-sectional line.
  • The p-type dopant dose in the depletable extension zone 175 is sufficiently low such that the depletable extension zone 175 is completely depleted in the blocking mode of the semiconductor device 500. For example, the implanted p-type dopant dose in the depletable extension zone 175 may result from an implant dose of at most 3.5E12 cm−2 resulting, when considering segregation effects, in a remnant effective p-type dopant dose of at most 2E12 cm−2 in silicon.
  • A vertical extension of the non-depletable extension zone 170 perpendicular to the first surface 101 may exceed a vertical extension of the body/anode zones 115 of the transistor cells TC. For example, in the reverse biased mode an edge of a depletion zone in the semiconductor body 100 oriented to the first surface 101 may have a greater distance to the first surface 101 in the non-depletable extension zone 170 than in p-type structures including the body/anode zones 115 and the second zones 182.
  • When the semiconductor device 500 commutates the first and second zones 181, 182 are depleted, wherein in the second zones 182 holes travel along the vertical direction and reach the first surface 101. In the edge area 690, a resulting hole current at the first surface 101 into the direction of the next contact structure 315 adds to a hole current resulting from the holes injected into the drift zone 120 in the forward-biased mode of the body pn junction pn1. As a result, in superjunction devices the effect discussed above is more significant since a greater portion of the holes is first guided to the first surface 101 and then guided along the first surface into the direction of the first contact 315. The effect may be even more pronounced since in the active area 610 the second zones 182 accelerate the hole discharge and, when finally the hole current in the active area 610 pinches off, the edge area 690 still discharges holes and due to leakage inductance carries further increased hole current densities.
  • The depletable extension zone 175 reduces the resistance effective for the total hole current flow from at least one or some of the second zones 182 of the edge area 690 to a contact structure 315 electrically connecting the first load electrode 310 with the extension zones 170, 175 and may reduce the switching losses.
  • In addition, the comparatively high hole current density significantly reduces the dynamic breakdown voltage of the field dielectric 211. Instead, the non-depletable extension zone 170 locally decreases the surface electric field strength without significantly adversely affecting the lateral voltage blocking capability despite that the hole current densities are increased by approximately one order of magnitude.
  • The semiconductor device 500 of FIG. 1D differs from the superjunction IGFET of FIG. 1C in that the depletable extension zone 175 is connected to all second zones 182 in the edge area 690 between the non-depletable extension zone 170 and the side surface 103 and in that a spacer zone 173 of the first conductivity type separates the depletable extension zone 175 from the first surface 101. The spacer zone 173 reduces the effect of holes flowing into direction of the active area 610 during commutation on the field dielectric 211. The surface electric field is more homogenous, the integrated ionization charge along the hole current flow is reduced and the dynamic breakdown voltage is further increased.
  • The semiconductor device 500 of FIG. 1E is an IGFET based on the semiconductor device 500 of FIG. 1A. A field stop layer 128 having a dopant concentration at least twice as high as in the drift zone 120 separates the drift zone 120 from the pedestal layer 130. In another embodiment a buffer layer with a dopant concentration that is lower than in the first zones 181 is formed between the pedestal layer 130 and the second zones 182.
  • The transistor cells TC are vertical transistor cells TC with the gate structures 150 including buried gate electrodes 155 extending from the first surface 101 into the semiconductor body 100. A dielectric structure 205 may separate the first load electrode 310 from the buried gate electrodes 155.
  • Other embodiments may refer to IGBTs on the basis of the IGFETs of FIGS. 1C to 1E with the pedestal layer 130 having the p-type or including p-type zones. For IGBTs, the first load electrode 310 is effective as an emitter electrode forming or electrically connected or coupled to an emitter terminal. The second load electrode 320 is effective as collector electrode and forms or is electrically connected to a collector terminal.
  • The semiconductor device 500 of FIG. 1F is an MCD that may include a barrier layer 121 between the body/anode zones 115 and the drift zone 120. The pedestal layer 130 may include first zones 131 of the first conductivity type and second zones 132 of the second conductivity type extending between the drift zone 120 and the second surface 102, respectively. The transistor cells TC are switched off in the normal forward-biased state of the MCD. Before commutation, a potential applied to the gate electrode 155 generates inversion layers from the source zones 110 to the drift zone 120 through the body/anode zones 115. The inversion layers short-circuit the first pn junction pn1 between the body/anode zones 115 and the drift zone 120 and reduce or suppress hole injection from the body/anode zones 115 into the drift zone 120. The carrier plasma in the drift zone 120 is reduced and the recovery charge can be decreased. The barrier layer 121 reduces the lateral voltage drop along the first pn junction pn1 to avoid injection between the gate structures 150 in a distance to the inversion layers.
  • According to an embodiment referring to IGFETs including MGD (MOS gated diode) cells the semiconductor device 500 may include IGFET cells and MGD cells with gate electrodes electrically connected to the first load electrode 310. In the reverse conducting mode of the semiconductor device 500 the current flow between the first and second load electrodes 310, 320 results in that the body/anode zones 115 are negatively biased with respect to the first load electrode 310 and the gate electrodes of the MGDs and an inversion layer may be formed in the body/anode zones 115. If in the reverse mode the total current through the semiconductor device 500 is above an average current flow density threshold, it is typically dominated by a unipolar current flow reducing the electric losses compared to the case of a total current flow across the first pn junctions pn1.
  • FIGS. 2A to 2G refer to lateral cross-sections of semiconductor devices 500 for illustrating embodiments of the lateral extension of the non-depletable extension zones 170 of any of the semiconductor devices 500 of FIGS. 1A to 1E.
  • An edge area 690 devoid of functional transistor cells separates an active area 610, which includes the functional transistor cells, from the side surface 103 of a semiconductor body 100. The edge area 690 includes gate area 695 in the vertical projection of a gate construction 330. In the illustrated embodiment the gate area 695 is assigned to a gate construction 330 including a single gate pad. According to other embodiments, the gate construction 330 may include more than one gate pad, a gate runner, and/or one or more gate fingers and the gate area 695 may include further portions in the vertical projection of gate fingers and/or gate runners that form sections of electric connections between gate electrodes and a gate pad in a metallization plane. Gate pad and gate area 695 may be arranged in a corner or along one of the lateral sides of the semiconductor body 100. A gate runner may surround the active area 610. A gate finger may separate the active areas 610 in separate cell fields.
  • FIG. 2A shows a non-depletable extension zone 170 completely surrounding the active area 610 along a circumferential line CL sparing the gate area 695. Along the circumferential line CL, a net dopant concentration of the non-depletable extension zone 170 is constant. A depletable extension zone 175 may directly adjoin or overlap with the non-depletable extension zone 170 in the edge area 690 at a side oriented to the side surface 103.
  • FIG. 2B refers to an embodiment with a first, along the circumferential line CL approximately constant net dopant concentration p1 + in first sections 170 a of the non-depletable extension zone and an enhanced second net dopant concentration p2 +, which is higher, e.g. at least twice as high as the first net dopant concentration p1 +, in second sections 170 b. The second sections 170 b may be laterally curved sections close to the corners of the semiconductor body 100 and/or sections between the active area 610 and the gate area 695. The first sections 170 a may be straight sections connecting the second sections 170 b.
  • The second sections 170 b may be formed by implanting the concerned dopants at a locally increased implant dose or by performing a first implant with uniform implant dose along the circumferential line CL and a second implant which is selectively effective in the second sections.
  • The higher dopant concentration in the second sections 170 b may compensate for an increased hole current close to the corners and to the gate area 695 and resulting from increased hole current density in wider portions of the semiconductor body 100 without source and body contacts, e.g. in the gate area 695 and close to the corners, where more holes are allocated per length unit of the extension zones 170, 175 along the circumferential line CL.
  • The dopant concentration profiles of the non-depletable extension zones 170 along the circumferential line CL may include further sections with a dopant concentration between the first and the second dopant concentrations. The first sections 170 a of the non-depletable extension zone may contain a dopant dose of at least 2.5E12 cm−2, for example at least 1E13 cm−2 or greater than 2E13 cm−2. The second sections 170 b may contain a dopant dose which is at least twice as high as the first dopant dose, for example at least four times as high as the first dopant dose.
  • In the semiconductor device 500 in FIG. 2C the non-depletable extension zone 170 includes an enlarged portion 170 x formed in the vertical projection of a gate pad in the gate area 695. The enlarged portion 170 x may extend over the complete gate area 695 and may overlap the complete vertical projection of a gate construction including at least a gate pad. A further portion of the non-depletable extension zone 170 surrounds the active area 610 as described with reference to FIG. 2A.
  • In FIG. 2D the non-depletable extension zone 170 is exclusively formed in the vertical projection of a gate pad in the gate area 695. The non-depletable extension zone 170 may include further sections in further sections of the gate area 695 assigned to gate fingers and/or gate runners.
  • The semiconductor device 500 of FIG. 2E differs from the one in FIG. 2B in that the non-depletable extension zone 170 includes a section of enhanced dopant concentration 170 b that extends over the complete or at least a main portion of the gate area 695 and overlaps with at least a main portion of the vertical projection of a gate pad. The non-depletable extension zone 170 may include further sections in further sections of the gate area 695 assigned to gate fingers and/or gate runners.
  • FIG. 2F refers to an embodiment with the non-depletable extension zone 170 including isolated segments arranged along the circumferential line CL. The segments may be curved sections in the corners of the semiconductor body 100 and/or sections between the active area 610 and the gate area 695.
  • FIG. 2G refers to a layout with the gate area 695 arranged along one of the lateral sides and symmetric with respect to a lateral center axis of the semiconductor body 100. Sections of the depletable and not- depletable extension zones 175, 170 may completely span the gate area 695. In a further embodiment, the gate pad may be located in the middle of the active area 610.
  • FIG. 3 refers to semiconductor devices 500 with a non-depletable extension zone 170 formed at least in a portion of the vertical projection of a gate construction 330. The non-depletable extension zone 170 may extend over at least 40% of the vertical projection of the gate construction 330, for example over at least 80%. According to an embodiment the non-depletable extension zone 170 extends over the whole vertical projection of the gate construction 330. The configuration of the gate construction 330, the conductive structure 157 electrically connecting the gate construction 330 with idle gate electrodes 155 a as well as the non-depletable extension zone 170 as shown in FIG. 3 can be combined with any of the semiconductor devices 500 described with reference to FIGS. 1A to 1F. An interlayer dielectric structure 200 adjoins a first surface 101 of the semiconductor body 100. In the edge area 690 the interlayer dielectric structure 200 separates a gate construction 330 from the semiconductor body 100. The interlayer dielectric structure 200 may include a conductive structure 157, wherein a field dielectric 211 separates the conductive structure 157 from the semiconductor body 100 and a capping dielectric 212 separates the conductive structure 157 from the gate construction 330.
  • In the vertical projection of at least a portion of the gate construction 330 in the semiconductor body 100 is a non-depletable extension zone 170 of a conductivity type of body/anode zones 115 of the transistor cells TC. The gate construction 330 may be a gate pad suitable as a landing pad for a bond wire or another chip-to-leadframe or chip-to-chip connection like a soldered clip. The gate pad can be in direct connection with the conductive structure 157. The conductive structure 157 can be a part of an integrated gate resistor or polycrystalline silicon diode or can be omitted below the gate pad. For further details reference is made to the description of FIGS. 1A to 2G.
  • During commutation, the non-depletable extension zones 170 reduce a resistance effective for a hole current flow between the edge area 690 and the outermost contact of the first load electrode 310 oriented to the edge area 690. Compared to depletable extension zones, which are fully depleted in case of the hole current flow and, consequently, have a comparatively high ohmic resistance, the non-depletable extension zone 170 is not fully depleted and, consequently, improves the depletion process of holes and reduces dynamic switching losses. While without non-depletable extension zones 170 a capacity of the gate construction 330 adds to the gate-to-drain capacity Cgd after depletion of the second zones 182, the non-depletable extension zone 170 shields the gate construction 330 such that the gate-to-drain capacity Cgd is not increased or is increased to a lower degree resulting in reduced switching losses.
  • The diagram of FIG. 4 schematically shows the switching losses Eoff as a function of the load current Isat. Comparative examples 791 without non-depletable extension zones show higher switching losses as comparable devices 792 including non-depletable extension zones. The non-depletable extension zones reduce the commutation losses. Since in resonant applications energy capacitively stored in the semiconductor device 500 is recovered, losses resulting from a gate construction 330 may contribute to a third of the overall commutation losses.
  • FIGS. 5A to 5D refer to electronic circuits 700 including one or more half-bridge circuits 710 based on two semiconductor switching devices 711, 712 with load current paths connected in series between Vdd and Gnd. The semiconductor switching devices 711, 712 may be IGFETs or IGBTs. At least one of the semiconductor switching devices 711, 712 may be or may include one of the semiconductor devices 500 of the previous figures. The half-bridge circuit 710 or the complete electronic circuit 700 may be integrated in a power module.
  • The electronic circuit 700 may include a gate driver circuit 720 generating and driving a first gate signal at a first driver terminal Gout1 and a second gate signal at a second driver terminal Gout2. The first and second driver terminals Gout1, Gout2 are electrically coupled or connected to gate terminals G of the semiconductor switching devices 711, 712. The gate driver circuit 720 controls the gate signals such that during regular switching cycles the first and second switching devices 711, 712 are alternatingly in the on state. During desaturation cycles, the gate driver circuit 720 may apply desaturation pulses before switching one of the switching devices 711, 712 into the on state.
  • In FIG. 5A the switching devices 711, 712 are n-IGFETs with a source terminal S of the first switching device 711 and a drain terminal D of the second switching device 712 electrically connected to a switching terminal Sw.
  • In FIG. 5B the first switching device 711, 712 is a p-IGFET and the second switching device 712 is an n-IGFET.
  • In FIG. 5C the switching devices 711, 712 are n-channel IGBTs with an emitter terminal E of the first switching device 711 and a collector terminal C of the second switching device 712 electrically connected to a switching terminal Sw.
  • FIG. 5D shows an electronic circuit 700 with two half-bridges 710 whose load paths are connected in parallel and operated in a full-bridge configuration. A load 900, e.g. an inductive load, may be connected to the switching terminals Sw of the two half-bridges 710. The load 900 may be a motor winding, an inductive cooking plate or a transformer winding in a switched-mode power supply, by way of example. According to another embodiment the electronic circuit 700 may include three half-bridges 710 for driving a motor with three windings wherein each winding is connected between a star node of the motor windings and one of the switching terminals Sw of the half bridges 710.
  • Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (20)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor body comprising transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body;
a field dielectric adjoining a first surface of the semiconductor body and separating, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body, the field dielectric comprising a transition from a first to a second, greater vertical extension; and
a non-depletable extension zone of a conductivity type of body/anode zones of the transistor cells and electrically connected to at least one of the body/anode zones, wherein the transition is in the vertical projection of the non-depletable extension zone,
wherein the non-depletable extension zone surrounds the active area at uniform width.
2. The semiconductor device of claim 1, wherein the non-depletable extension zone is electrically connected to a metallic load electrode.
3. The semiconductor device of claim 1, wherein the non-depletable extension zone has an effective dopant dose greater than 2.5E12 cm−2.
4. The semiconductor device of claim 1, further comprising:
a depletable extension zone of the conductivity type of the body/anode zones, directly adjoining the non-depletable extension zone, and arranged between the non-depletable extension zone and the side surface.
5. The semiconductor device of claim 4, wherein the depletable extension zone has an effective dopant dose of at most 2.0E12 cm−2.
6. The semiconductor device of claim 4, further comprising:
a spacer zone between the first surface and the depletable extension zone and forming a pn junction with the depletable extension zone.
7. The semiconductor device of claim 1, wherein the conductive structure is a section of an electric connection between a gate construction and gate electrodes of the transistor cells.
8. The semiconductor device of claim 1, wherein the non-depletable extension zone directly adjoins a body/anode zone of at least one of the transistor cells.
9. The semiconductor device of claim 1, wherein a vertical extension of the non-depletable extension zone perpendicular to the first surface exceeds a vertical extension of the body/anode zones of the transistor cells.
10. The semiconductor device of claim 1, further comprising:
first zones of a first conductivity type opposite to a second conductivity type given by the conductivity type of the body/anode zones; and
second zones of the second conductivity type, the first and the second zones alternately arranged in the semiconductor body in the active area,
wherein in the active area, the second zones directly adjoin the body/anode zones and the first zones form pn junctions with the body/anode zones.
11. The semiconductor device of claim 1, wherein an impurity concentration in the non-depletable extension zone does not decrease by more than 50% between a starting point of the transition, where a vertical extension of the transition starts to increase from the first vertical extension, and a reference point at a distance of at least 3 μm to the starting point.
12. The semiconductor device of claim 1, further comprising:
a metal gate pad in a vertical projection of a gate area of the edge area,
wherein the gate area is in a corner or along one lateral side of the semiconductor body,
wherein a portion of the non-depletable extension zone is formed along a line separating the active area and the gate area.
13. The semiconductor device of claim 1, wherein along a circumferential line around the active area a net dopant concentration of the non-depletable extension zone is constant.
14. The semiconductor device of claim 1, further comprising:
first zones of a first conductivity type opposite to a second conductivity type given by the conductivity type of the body/anode zones; and
second zones of the second conductivity type, the first and the second zones alternately arranged in the semiconductor body in the active area and the edge area,
wherein in the active area, the second zones directly adjoin to the body/anode zones and the first zones form pn junctions with the body/anode zones.
15. The semiconductor device of claim 14, wherein the non-depletable extension zone overlaps with the second zones, and wherein along a circumferential line around the active area, a net dopant dose of the non-depletable extension zone is constant.
16. The semiconductor device of claim 14, further comprising:
a depletable extension zone of the conductivity type of the body/anode zones,
wherein the depletable extension zone directly adjoins the non-depletable extension zone and at least one of the second zones in the edge area.
17. The semiconductor device of claim 16, further comprising:
a spacer zone between the first surface and the depletable extension zone and forming a pn junction with the depletable extension zone.
18. The semiconductor device of claim 1, wherein the non-depletable extension zone has an effective dopant dose greater than 2E13 cm−2.
19. The semiconductor device of claim 1, wherein the non-depletable extension comprises straight first sections with a constant first net dopant concentration and laterally curved second sections, wherein the first sections connect the second sections and a second net dopant concentration of the second sections is at least twice as high as the first net dopant concentration.
20. A half-bridge circuit, comprising:
a semiconductor body comprising transistor cells arranged in an active area and absent in an edge area between the active area and a side surface of the semiconductor body;
a field dielectric adjoining a first surface of the semiconductor body and separating, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body, the field dielectric comprising a transition from a first to a second, greater vertical extension; and
a non-depletable extension zone of a conductivity type of body/anode zones of the transistor cells and electrically connected to at least one of the body/anode zones,
wherein the transition is in the vertical projection of the non-depletable extension zone,
wherein the non-depletable extension zone surrounds the active area at uniform width.
US15/681,454 2014-05-14 2017-08-21 Semiconductor Device with Field Dielectric in an Edge Area Abandoned US20170373140A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/681,454 US20170373140A1 (en) 2014-05-14 2017-08-21 Semiconductor Device with Field Dielectric in an Edge Area

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/277,169 US9773863B2 (en) 2014-05-14 2014-05-14 VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body
US15/681,454 US20170373140A1 (en) 2014-05-14 2017-08-21 Semiconductor Device with Field Dielectric in an Edge Area

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/277,169 Continuation US9773863B2 (en) 2014-05-14 2014-05-14 VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body

Publications (1)

Publication Number Publication Date
US20170373140A1 true US20170373140A1 (en) 2017-12-28

Family

ID=54361825

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/277,169 Active 2034-07-13 US9773863B2 (en) 2014-05-14 2014-05-14 VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body
US15/681,454 Abandoned US20170373140A1 (en) 2014-05-14 2017-08-21 Semiconductor Device with Field Dielectric in an Edge Area

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/277,169 Active 2034-07-13 US9773863B2 (en) 2014-05-14 2014-05-14 VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body

Country Status (4)

Country Link
US (2) US9773863B2 (en)
KR (1) KR101721313B1 (en)
CN (2) CN110085659A (en)
DE (1) DE102015107456B4 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU184252U1 (en) * 2018-01-09 2018-10-19 Открытое акционерное общество "ОКБ-Планета" ОАО "ОКБ-Планета" CONSTRUCTION OF INTEGRAL RESISTORS IN MICROSHEMES ON EPITAXIAL STRUCTURES OF GALLIUM ARSENIDE
US20180342576A1 (en) * 2015-03-27 2018-11-29 Fairchild Semiconductor Corporation Avalanche-rugged silicon carbide (sic) power device
EP3716340A1 (en) * 2019-03-25 2020-09-30 Infineon Technologies Austria AG Transistor device
EP4254511A1 (en) 2022-04-01 2023-10-04 STMicroelectronics S.r.l. Electronic device with reduced switching oscillations

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10468479B2 (en) * 2014-05-14 2019-11-05 Infineon Technologies Austria Ag VDMOS having a drift zone with a compensation structure
US9318587B2 (en) * 2014-05-30 2016-04-19 Alpha And Omega Semiconductor Incorporated Injection control in semiconductor power devices
US10361266B2 (en) * 2014-06-09 2019-07-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US9871126B2 (en) * 2014-06-16 2018-01-16 Infineon Technologies Ag Discrete semiconductor transistor
CN105529262A (en) * 2014-09-29 2016-04-27 无锡华润华晶微电子有限公司 Vertical double diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
DE102014116773A1 (en) * 2014-11-17 2016-05-19 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell
DE102015110484B4 (en) 2015-06-30 2023-09-28 Infineon Technologies Austria Ag Semiconductor components and method for forming a semiconductor component
DE112016005768B4 (en) 2015-12-18 2023-03-16 Rohm Co., Ltd. semiconductor device
DE102016100519B4 (en) * 2016-01-13 2023-05-17 Infineon Technologies Austria Ag Semiconductor devices comprising an edge construction with straight sections and corner sections
JP6855700B2 (en) * 2016-08-05 2021-04-07 富士電機株式会社 Semiconductor devices and their manufacturing methods
JP6832094B2 (en) * 2016-08-05 2021-02-24 ローム株式会社 Power module and motor drive circuit
DE102016118499B4 (en) 2016-09-29 2023-03-30 Infineon Technologies Dresden Gmbh Semiconductor devices and method of forming a semiconductor device
DE102016120772B4 (en) * 2016-10-31 2020-06-10 Infineon Technologies Dresden Gmbh Semiconductor device with gate pad, gate electrode and integration layer
US10312710B1 (en) * 2017-01-31 2019-06-04 The United States Of America, As Represented By The Secretary Of The Navy Energy recovery pulse forming network
DE102017105548A1 (en) * 2017-03-15 2018-09-20 Infineon Technologies Dresden Gmbh SEMICONDUCTOR DEVICE CONTAINING A GATE CONTACT STRUCTURE
CN107591451A (en) * 2017-08-31 2018-01-16 上海华虹宏力半导体制造有限公司 Superjunction devices
CN111883585B (en) * 2020-08-21 2024-02-06 上海华虹宏力半导体制造有限公司 Superjunction device
JP2023137644A (en) * 2022-03-18 2023-09-29 株式会社東芝 Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
US6498368B2 (en) * 1999-12-09 2002-12-24 Hitachi, Ltd. Power semiconductor device
US20050029584A1 (en) * 2003-08-04 2005-02-10 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US20080001221A1 (en) * 2006-06-30 2008-01-03 Sanyo Electric Co., Ltd. Insulated gate semiconductor device
US20090045481A1 (en) * 2007-07-12 2009-02-19 Fuji Electric Device Technology Co., Ltd. Semiconductor device having breakdown voltage maintaining structure and its manufacturing method
US7737469B2 (en) * 2006-05-16 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device having superjunction structure formed of p-type and n-type pillar regions

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973368A (en) 1996-06-05 1999-10-26 Pearce; Lawrence G. Monolithic class D amplifier
DE19840032C1 (en) * 1998-09-02 1999-11-18 Siemens Ag Semiconductor device for compensation element
US7098506B2 (en) * 2000-06-28 2006-08-29 Renesas Technology Corp. Semiconductor device and method for fabricating the same
DE19947020B4 (en) 1999-09-30 2006-02-23 Infineon Technologies Ag Compensation component with variable charge balance and its manufacturing process
JP4765012B2 (en) 2000-02-09 2011-09-07 富士電機株式会社 Semiconductor device and manufacturing method thereof
DE10066053B4 (en) 2000-12-08 2006-03-30 Infineon Technologies Ag Semiconductor device with increased breakdown voltage
US6612214B2 (en) * 2001-10-05 2003-09-02 Robud Die cutter blanket-anvil locking arrangement
JP2006005275A (en) 2004-06-21 2006-01-05 Toshiba Corp Semiconductor device for electric power
JP4825424B2 (en) * 2005-01-18 2011-11-30 株式会社東芝 Power semiconductor device
DE102005023026B4 (en) 2005-05-13 2016-06-16 Infineon Technologies Ag Power semiconductor device with plate capacitor structure
DE102005038260B3 (en) 2005-08-12 2007-03-22 Infineon Technologies Ag Semiconductor component and production process for high current or voltage devices has front and rear contacts and divided edge zone around cell field region
DE102006047489B9 (en) * 2006-10-05 2013-01-17 Infineon Technologies Austria Ag Semiconductor device
JP5196766B2 (en) 2006-11-20 2013-05-15 株式会社東芝 Semiconductor device
JP2008251923A (en) * 2007-03-30 2008-10-16 Sanyo Electric Co Ltd Semiconductor device
JP4621708B2 (en) 2007-05-24 2011-01-26 株式会社東芝 Semiconductor device and manufacturing method thereof
DE102007030755B3 (en) 2007-07-02 2009-02-19 Infineon Technologies Austria Ag Semiconductor device having a trench edge having edge and method for producing a border termination
JP2009087998A (en) * 2007-09-27 2009-04-23 Sanyo Electric Co Ltd Semiconductor device
CN100565879C (en) * 2008-01-08 2009-12-02 苏州硅能半导体科技股份有限公司 A kind of deep groove large power MOS device and manufacture method thereof
CN101853854B (en) * 2010-03-12 2012-11-21 无锡新洁能功率半导体有限公司 Groove power MOS component with improved type terminal structure and manufacturing method thereof
CN101814528B (en) * 2010-05-04 2011-06-22 无锡新洁能功率半导体有限公司 Semiconductor element with improved terminal and manufacturing method thereof
JP5633992B2 (en) * 2010-06-11 2014-12-03 トヨタ自動車株式会社 Semiconductor device and manufacturing method of semiconductor device
WO2012056536A1 (en) * 2010-10-27 2012-05-03 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
TWI407568B (en) * 2010-11-22 2013-09-01 Sinopower Semiconductor Inc Semiconductor device
JP5569600B2 (en) * 2011-01-17 2014-08-13 富士電機株式会社 Semiconductor device and manufacturing method thereof
US8941188B2 (en) 2012-03-26 2015-01-27 Infineon Technologies Austria Ag Semiconductor arrangement with a superjunction transistor and a further device integrated in a common semiconductor body
CN104838500B (en) * 2012-12-04 2017-08-15 株式会社电装 Semiconductor device and its manufacture method
US20140231928A1 (en) 2013-02-18 2014-08-21 Infineon Technologies Austria Ag Super Junction Semiconductor Device with an Edge Area Having a Reverse Blocking Capability
CN104282732B (en) * 2013-07-01 2017-06-27 株式会社东芝 Semiconductor device
US8958189B1 (en) 2013-08-09 2015-02-17 Infineon Technologies Austria Ag High-voltage semiconductor switch and method for switching high voltages
US10468479B2 (en) * 2014-05-14 2019-11-05 Infineon Technologies Austria Ag VDMOS having a drift zone with a compensation structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
US6498368B2 (en) * 1999-12-09 2002-12-24 Hitachi, Ltd. Power semiconductor device
US20050029584A1 (en) * 2003-08-04 2005-02-10 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US7737469B2 (en) * 2006-05-16 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device having superjunction structure formed of p-type and n-type pillar regions
US20080001221A1 (en) * 2006-06-30 2008-01-03 Sanyo Electric Co., Ltd. Insulated gate semiconductor device
US20090045481A1 (en) * 2007-07-12 2009-02-19 Fuji Electric Device Technology Co., Ltd. Semiconductor device having breakdown voltage maintaining structure and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180342576A1 (en) * 2015-03-27 2018-11-29 Fairchild Semiconductor Corporation Avalanche-rugged silicon carbide (sic) power device
US10504989B2 (en) * 2015-03-27 2019-12-10 Fairchild Semiconductor Corporation Avalanche-rugged silicon carbide (SiC) power device
RU184252U1 (en) * 2018-01-09 2018-10-19 Открытое акционерное общество "ОКБ-Планета" ОАО "ОКБ-Планета" CONSTRUCTION OF INTEGRAL RESISTORS IN MICROSHEMES ON EPITAXIAL STRUCTURES OF GALLIUM ARSENIDE
EP3716340A1 (en) * 2019-03-25 2020-09-30 Infineon Technologies Austria AG Transistor device
US11374125B2 (en) 2019-03-25 2022-06-28 Infineon Technologies Austria Ag Vertical transistor device having a discharge region comprising at least one lower dose section and located at least partially below a gate electrode pad
EP4254511A1 (en) 2022-04-01 2023-10-04 STMicroelectronics S.r.l. Electronic device with reduced switching oscillations

Also Published As

Publication number Publication date
CN110085659A (en) 2019-08-02
DE102015107456A1 (en) 2015-11-19
US20150333168A1 (en) 2015-11-19
CN105185821B (en) 2019-04-23
DE102015107456B4 (en) 2021-09-23
KR101721313B1 (en) 2017-03-29
US9773863B2 (en) 2017-09-26
KR20150130934A (en) 2015-11-24
CN105185821A (en) 2015-12-23

Similar Documents

Publication Publication Date Title
US9773863B2 (en) VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body
US9209109B2 (en) IGBT with emitter electrode electrically connected with an impurity zone
US9960243B2 (en) Semiconductor device with stripe-shaped trench gate structures and gate connector structure
US9799729B2 (en) Method of manufacturing a semiconductor device with field electrode structures, gate structures and auxiliary diode structures
US9954056B2 (en) Semiconductor device with superjunction structure and transistor cells in a transition region along a transistor cell region
US8482031B2 (en) Lateral insulated gate bipolar transistors (LIGBTS)
US11462620B2 (en) Semiconductor device having a transistor cell region and a termination region with needle-shaped field plate structures
JP3964819B2 (en) Insulated gate semiconductor device
US9337827B2 (en) Electronic circuit with a reverse-conducting IGBT and gate driver circuit
US9553179B2 (en) Semiconductor device and insulated gate bipolar transistor with barrier structure
KR100895057B1 (en) Semiconductor Device
US9159819B2 (en) Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode
US10249746B2 (en) Bipolar transistor with superjunction structure
US9666665B2 (en) Semiconductor device with semiconductor mesa including a constriction
US9899478B2 (en) Desaturable semiconductor device with transistor cells and auxiliary cells
US20200006544A1 (en) Semiconductor device including silicon carbide body and transistor cells
US11588048B2 (en) Semiconductor device with insulated gate transistor cell and rectifying junction
JPH09107097A (en) Rectifier device and its drive method

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AUSTRIA AG, AUSTRIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HIRLER, FRANZ;GAMERITH, STEFAN;WEYERS, JOACHIM;AND OTHERS;SIGNING DATES FROM 20140602 TO 20140702;REEL/FRAME:043340/0766

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION