US20170330933A1 - Air gaps formed by porous silicon removal - Google Patents
Air gaps formed by porous silicon removal Download PDFInfo
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- US20170330933A1 US20170330933A1 US15/622,549 US201715622549A US2017330933A1 US 20170330933 A1 US20170330933 A1 US 20170330933A1 US 201715622549 A US201715622549 A US 201715622549A US 2017330933 A1 US2017330933 A1 US 2017330933A1
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- semiconductor layer
- porous semiconductor
- active device
- device region
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- 229910021426 porous silicon Inorganic materials 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 238000002955 isolation Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 2
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- 239000000463 material Substances 0.000 description 16
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- 230000008569 process Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002048 anodisation reaction Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
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- 230000006872 improvement Effects 0.000 description 2
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- 239000002253 acid Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
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- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
Definitions
- the invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to semiconductor structures for an active device region and methods of forming such semiconductor structures.
- SOI semiconductor-on-insulator
- an SOI wafer includes a thin device layer of semiconductor material, a handle substrate, and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the device layer from the handle substrate.
- Integrated circuits are fabricated using the semiconductor material of the device layer. A primary source of the improved performance is due to the presence of the BOX layer.
- a method for forming a semiconductor structure using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer.
- One or more trench isolation regions are formed in the device layer that surround an active device region.
- An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer.
- a removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region such that the active device layer is supported.
- a device structure is formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer.
- the semiconductor structure includes one or more trench isolation regions in the device layer and an air gap in the porous semiconductor layer.
- the one or more trench isolation regions surround an active device region.
- the air gap is vertically located beneath the active device region and laterally located between a first section of the porous semiconductor layer and a second section of the porous semiconductor layer.
- the first section of the porous semiconductor layer and the second section of the porous semiconductor layer are located beneath the active device region such that the active device layer is supported.
- FIGS. 1-4 are cross-sectional views of a portion of a substrate at successive stages of a processing method for fabricating a structure for a device region in accordance with an embodiment of the invention.
- FIG. 5 is a top view of the structure of FIG. 4 in which the device structures and protective layer are omitted for purposes of clarity of description.
- a substrate 10 comprises a single-crystal semiconductor material, such as silicon, usable to form the devices of an integrated circuit.
- Substrate 10 may be, for example, a bulk silicon wafer or an active silicon SOI layer of a silicon-on-insulator wafer.
- the substrate 10 may include a device layer 12 , which may contain an amount of an electrically-active dopant that enhances its electrical properties relative to the remainder of the substrate 10 .
- the substrate 10 further includes a porous semiconductor layer 14 that is located beneath the device layer 12 at the top surface of the substrate 10 and a handle wafer 11 .
- the porous semiconductor layer 14 may be formed by converting the semiconductor material (e.g. silicon) of a seed wafer to a porous semiconductor material (e.g., porous silicon) using an anodization process performed using an aqueous electrolyte or anodization solution containing hydrofluoric acid (HF), such as a solution of hydrofluoric acid and a monohydric alcohol like ethanol.
- HF hydrofluoric acid
- the seed wafer is contacted with a biased electrode and immersed, along with a separate oppositely-biased electrode, into a bath of the anodization solution.
- An electrical current is passed through the electrodes and the seed wafer for an anodization time sufficient to convert the heavily doped silicon to porous silicon and complete the process forming the porous semiconductor layer 14 .
- the anodization process creates pores across the depth of the porous semiconductor layer 14 in which the resulting porosity may be proportional to factors such as current density.
- the porous semiconductor layer 14 may include sub-layers of differing porosity may be formed by changing the current density during anodization to two different values.
- the surface of the porous semiconductor layer 14 may be smoothed and the pores at its surface sealed by, for example, a combination of a wet etch using a solution containing hydrofluoric acid and hydrogen peroxide (H 2 O 2 ) and a subsequent thermal anneal in a hydrogen-rich atmosphere.
- the device layer 12 may then be formed on the sealed and smoothed surface by, for example, an epitaxial deposition process involving chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- the device layer 12 and porous semiconductor layer 14 may then be transferred to the substrate 10 by a transfer process.
- Trench isolation regions 16 are located in the semiconductor material of the substrate 10 .
- An active device region 18 used in fabricating a device structure is bounded by the trench isolation regions 16 .
- the active device region 18 is comprised of a portion of the semiconductor material of the device layer 12 , and has an outer boundary 17 established in part by location of the trench isolation regions 16 .
- the trench isolation regions 16 extend from the top surface of the device layer 12 to a shallow depth beneath the top surface.
- the trench isolation regions 16 may be formed by forming an etch mask using photolithography and etching to define trenches, followed by filling the trenches with a dielectric material, such as silicon dioxide (SiO 2 ) deposited by chemical vapor phase deposition and subsequently planarized.
- a dielectric material such as silicon dioxide (SiO 2 ) deposited by chemical vapor phase deposition and subsequently planarized.
- the trench isolation regions 16 are etched and partially removed in the presence of a mask to form an openings 19 that extend completely through the trench isolation regions 16 to the underlying porous semiconductor layer 14 .
- the etchant used to remove the portions of the trench isolation regions 16 to form the openings 19 may be a buffered hydrofluoric acid (BHF) solution, which removes silicon dioxide selective to (i.e., at a higher etch rate than) silicon.
- BHF buffered hydrofluoric acid
- Other portions of the trench isolation regions 16 located laterally between the openings 19 and the active device region 18 are protected and preserved due to the presence of the mask.
- Oxidized regions 20 are formed in the semiconductor material of the porous semiconductor layer 14 .
- the oxidized regions 20 may be formed using a wet or dry thermal oxidation process and with the same mask used to form the openings 19 present.
- the oxidation agent used to form the oxidized regions 20 is directed through the openings 19 to the porous semiconductor layer 14 . Due to its porosity, the porous semiconductor layer 14 may more readily oxidize than the semiconductor material of the substrate 10 underlying the oxidized regions 20 , which may serve to confine the depth of oxidation to the thickness of the porous semiconductor layer 14 .
- the oxidation may proceed laterally beneath the trench isolation regions 16 such that portions of the oxidized regions 20 are located beneath the trench isolation regions 16 .
- the oxidized regions 20 laterally bound a section 15 of the porous semiconductor layer 14 .
- a layer 22 is deposited and patterned.
- the layer 22 is comprised of a material that etches selective to (i.e., at a higher etch rate than) the materials of the trench isolation regions 16 and the active device region 18 .
- the layer 22 covers the oxidized regions 20 and overlaps with a portion of the trench isolation regions 16 adjacent to the oxidized regions 20 .
- a mask present during deposition defines the locations at which the layer 22 is present and absent.
- the mask may be the same mask used during the prior etching process partially removing the trench isolation regions 16 .
- the layer 22 may be comprised of a dielectric layer, such as silicon nitride (Si 3 N 4 ), deposited by chemical vapor deposition and etched by an etching process, such as reactive ion etching.
- the trench isolation regions 16 are etched and partially removed over areas not covered by the layer 22 .
- the etchant which removes the material of the trench isolation regions 16 selective to the material of the active device region 18 , may be a buffered hydrofluoric acid (BHF) solution. Portions of the trench isolation regions 16 adjacent to and bordering the active device region 18 are removed by the etch to trenches defining openings 24 extending through the trench isolation regions 16 to the section 15 of the porous semiconductor layer 14 . Other portions of the trench isolation regions 16 laterally separated from the active device region 18 by the openings 24 are protected and preserved due to the presence of the layer 22 .
- BHF buffered hydrofluoric acid
- the oxidized regions 20 are protected during etching and preserved due to the presence of the layer 22 , and the semiconductor material of the active device region 18 is unaffected by the etching process.
- the outer boundary 17 of the active device region 18 is located adjacent to the openings 24 following the partial removal of the trench isolation regions 16 .
- the openings 24 are located laterally between the residual portions of the trench isolation regions 16 and the active device region 18 .
- one or more device structures 40 are formed using the active device region 18 during front-end-of-line (FEOL) processing.
- the device structure(s) 40 and active device region 18 are covered by a protective barrier layer 41 , such as by a layer of silicon nitride deposited by chemical vapor deposition, to prevent modification of the device structure(s) 40 and active device region 18 when subsequently forming the air gap 26 .
- the section 15 of the porous semiconductor layer 14 is removed to form an air gap 26 .
- the section 15 of the porous semiconductor layer 14 functions as a temporary, sacrificial material that occupies the space opened at this juncture of the processing method to define the air gap 26 .
- the air gap 26 may have nominally the same volume as the section 15 of the porous semiconductor layer 14 that is removed.
- the oxidized regions 20 limit the space over which the section 15 of the porous semiconductor layer 14 is removed, and laterally bound the air gap 26 after the section 15 is removed.
- the section 15 of the porous semiconductor layer 14 may be removed using a removal agent, such as etchant solution (e.g., dilute potassium hydroxide (1% KOH in water)), that is directed through the openings 24 .
- etchant solution e.g., dilute potassium hydroxide (1% KOH in water)
- the removal agent interacts with the section 15 of the porous semiconductor layer 14 and causes its removal outward through the openings 24 .
- the etchant solution may be heated and/or supplied under high pressure, such as being forced through the openings 24 under a pressure of 2 to 3 atmospheres.
- the process removing the section 15 of the porous semiconductor layer 14 does not rely on an acid as an etchant.
- the oxidized regions 20 are unaffected by the process removing the section 15 of the porous semiconductor layer 14 , and are intact following its removal.
- the air gap 26 is vertically located beneath the active device region 18 between the handle wafer 11 and the active device region 18 . More specifically, the air gap 26 is vertically located beneath a beam or bridge 28 of the active device region 18 , as diagrammatically illustrated by the dashed lines in FIG. 5 .
- the openings 24 are laterally located between the side edges 29 , 31 of the bridge 28 and respective trench isolation regions 16 such that the bridge 28 is not connected or supported at its side edges 29 , 31 .
- the porous semiconductor layer 14 is not removed from underneath sections 30 , 32 of the active device region 18 .
- the bridge 28 extends laterally from one end integrally attached to the section 30 of the active device region 18 to an opposite end integrally attached to the section 32 of the active device region 18 .
- the sections 30 , 32 of the active device region 18 directly support the bridge 28 .
- the porous semiconductor material in the sections 34 , 36 of the porous semiconductor layer 14 is neither oxidized nor removed, and these sections 34 , 36 are respectively located beneath the sections 30 , 32 of the active device region 18 .
- the bridge 28 is also laterally located between these sections 34 , 36 of the porous semiconductor layer 14 .
- the removal process is controlled (e.g., timed) such that these sections 34 , 36 of the porous semiconductor layer 14 are not removed when the sacrificial section 15 is removed.
- These sections 34 , 36 of the porous semiconductor layer 14 directly support the sections 30 , 32 of the active device region 18 and thereby indirectly support the bridge 28 .
- the air gap 26 may be characterized by an effective permittivity or dielectric constant of near unity (vacuum permittivity), or may be filled by air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum).
- the “silicon on nothing” architecture provides efficient electrical isolation for the one or more device structures 40 .
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined.
- the term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
- a feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Abstract
Description
- The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to semiconductor structures for an active device region and methods of forming such semiconductor structures.
- Devices fabricated using semiconductor-on-insulator (SOI) technologies may exhibit certain performance improvements in comparison with comparable devices built directly in a bulk silicon substrate. Generally, an SOI wafer includes a thin device layer of semiconductor material, a handle substrate, and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the device layer from the handle substrate. Integrated circuits are fabricated using the semiconductor material of the device layer. A primary source of the improved performance is due to the presence of the BOX layer.
- Improved semiconductor structures for an active device region and methods of forming such semiconductor structures are needed.
- In an embodiment of the invention, a method is provided for forming a semiconductor structure using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region such that the active device layer is supported.
- In an embodiment of the invention, a device structure is formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. The semiconductor structure includes one or more trench isolation regions in the device layer and an air gap in the porous semiconductor layer. The one or more trench isolation regions surround an active device region. The air gap is vertically located beneath the active device region and laterally located between a first section of the porous semiconductor layer and a second section of the porous semiconductor layer. The first section of the porous semiconductor layer and the second section of the porous semiconductor layer are located beneath the active device region such that the active device layer is supported.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIGS. 1-4 are cross-sectional views of a portion of a substrate at successive stages of a processing method for fabricating a structure for a device region in accordance with an embodiment of the invention. -
FIG. 5 is a top view of the structure ofFIG. 4 in which the device structures and protective layer are omitted for purposes of clarity of description. - With reference to
FIG. 1 and in accordance with an embodiment of the invention, asubstrate 10 comprises a single-crystal semiconductor material, such as silicon, usable to form the devices of an integrated circuit.Substrate 10 may be, for example, a bulk silicon wafer or an active silicon SOI layer of a silicon-on-insulator wafer. At its top surface, thesubstrate 10 may include adevice layer 12, which may contain an amount of an electrically-active dopant that enhances its electrical properties relative to the remainder of thesubstrate 10. - The
substrate 10 further includes aporous semiconductor layer 14 that is located beneath thedevice layer 12 at the top surface of thesubstrate 10 and ahandle wafer 11. In an embodiment of the invention, theporous semiconductor layer 14 may be formed by converting the semiconductor material (e.g. silicon) of a seed wafer to a porous semiconductor material (e.g., porous silicon) using an anodization process performed using an aqueous electrolyte or anodization solution containing hydrofluoric acid (HF), such as a solution of hydrofluoric acid and a monohydric alcohol like ethanol. The seed wafer is contacted with a biased electrode and immersed, along with a separate oppositely-biased electrode, into a bath of the anodization solution. An electrical current is passed through the electrodes and the seed wafer for an anodization time sufficient to convert the heavily doped silicon to porous silicon and complete the process forming theporous semiconductor layer 14. The anodization process creates pores across the depth of theporous semiconductor layer 14 in which the resulting porosity may be proportional to factors such as current density. For example, theporous semiconductor layer 14 may include sub-layers of differing porosity may be formed by changing the current density during anodization to two different values. The surface of theporous semiconductor layer 14 may be smoothed and the pores at its surface sealed by, for example, a combination of a wet etch using a solution containing hydrofluoric acid and hydrogen peroxide (H2O2) and a subsequent thermal anneal in a hydrogen-rich atmosphere. Thedevice layer 12 may then be formed on the sealed and smoothed surface by, for example, an epitaxial deposition process involving chemical vapor deposition (CVD). Thedevice layer 12 andporous semiconductor layer 14 may then be transferred to thesubstrate 10 by a transfer process. -
Trench isolation regions 16 are located in the semiconductor material of thesubstrate 10. Anactive device region 18 used in fabricating a device structure is bounded by thetrench isolation regions 16. Theactive device region 18 is comprised of a portion of the semiconductor material of thedevice layer 12, and has anouter boundary 17 established in part by location of thetrench isolation regions 16. Thetrench isolation regions 16 extend from the top surface of thedevice layer 12 to a shallow depth beneath the top surface. Thetrench isolation regions 16 may be formed by forming an etch mask using photolithography and etching to define trenches, followed by filling the trenches with a dielectric material, such as silicon dioxide (SiO2) deposited by chemical vapor phase deposition and subsequently planarized. - With reference to
FIG. 2 in which like reference numerals refer to like features inFIG. 1 and at a subsequent fabrication stage of the processing method, thetrench isolation regions 16 are etched and partially removed in the presence of a mask to form anopenings 19 that extend completely through thetrench isolation regions 16 to the underlyingporous semiconductor layer 14. The etchant used to remove the portions of thetrench isolation regions 16 to form theopenings 19 may be a buffered hydrofluoric acid (BHF) solution, which removes silicon dioxide selective to (i.e., at a higher etch rate than) silicon. Other portions of thetrench isolation regions 16 located laterally between theopenings 19 and theactive device region 18 are protected and preserved due to the presence of the mask. - Oxidized
regions 20 are formed in the semiconductor material of theporous semiconductor layer 14. The oxidizedregions 20 may be formed using a wet or dry thermal oxidation process and with the same mask used to form theopenings 19 present. The oxidation agent used to form the oxidizedregions 20 is directed through theopenings 19 to theporous semiconductor layer 14. Due to its porosity, theporous semiconductor layer 14 may more readily oxidize than the semiconductor material of thesubstrate 10 underlying the oxidizedregions 20, which may serve to confine the depth of oxidation to the thickness of theporous semiconductor layer 14. The oxidation may proceed laterally beneath thetrench isolation regions 16 such that portions of the oxidizedregions 20 are located beneath thetrench isolation regions 16. The oxidizedregions 20 laterally bound a section 15 of theporous semiconductor layer 14. - With reference to
FIG. 3 in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of the processing method, alayer 22 is deposited and patterned. Thelayer 22 is comprised of a material that etches selective to (i.e., at a higher etch rate than) the materials of thetrench isolation regions 16 and theactive device region 18. Thelayer 22 covers the oxidizedregions 20 and overlaps with a portion of thetrench isolation regions 16 adjacent to the oxidizedregions 20. A mask present during deposition defines the locations at which thelayer 22 is present and absent. The mask may be the same mask used during the prior etching process partially removing thetrench isolation regions 16. Thelayer 22 may be comprised of a dielectric layer, such as silicon nitride (Si3N4), deposited by chemical vapor deposition and etched by an etching process, such as reactive ion etching. - The
trench isolation regions 16 are etched and partially removed over areas not covered by thelayer 22. The etchant, which removes the material of thetrench isolation regions 16 selective to the material of theactive device region 18, may be a buffered hydrofluoric acid (BHF) solution. Portions of thetrench isolation regions 16 adjacent to and bordering theactive device region 18 are removed by the etch totrenches defining openings 24 extending through thetrench isolation regions 16 to the section 15 of theporous semiconductor layer 14. Other portions of thetrench isolation regions 16 laterally separated from theactive device region 18 by theopenings 24 are protected and preserved due to the presence of thelayer 22. - The oxidized
regions 20 are protected during etching and preserved due to the presence of thelayer 22, and the semiconductor material of theactive device region 18 is unaffected by the etching process. Theouter boundary 17 of theactive device region 18 is located adjacent to theopenings 24 following the partial removal of thetrench isolation regions 16. Theopenings 24 are located laterally between the residual portions of thetrench isolation regions 16 and theactive device region 18. - With reference to
FIGS. 4, 5 in which like reference numerals refer to like features inFIG. 3 and at a subsequent fabrication stage of the processing method, one ormore device structures 40, such as one or more field effect transistors, are formed using theactive device region 18 during front-end-of-line (FEOL) processing. The device structure(s) 40 andactive device region 18 are covered by aprotective barrier layer 41, such as by a layer of silicon nitride deposited by chemical vapor deposition, to prevent modification of the device structure(s) 40 andactive device region 18 when subsequently forming theair gap 26. - The section 15 of the
porous semiconductor layer 14 is removed to form anair gap 26. The section 15 of theporous semiconductor layer 14 functions as a temporary, sacrificial material that occupies the space opened at this juncture of the processing method to define theair gap 26. Theair gap 26 may have nominally the same volume as the section 15 of theporous semiconductor layer 14 that is removed. Theoxidized regions 20 limit the space over which the section 15 of theporous semiconductor layer 14 is removed, and laterally bound theair gap 26 after the section 15 is removed. - The section 15 of the
porous semiconductor layer 14 may be removed using a removal agent, such as etchant solution (e.g., dilute potassium hydroxide (1% KOH in water)), that is directed through theopenings 24. The removal agent interacts with the section 15 of theporous semiconductor layer 14 and causes its removal outward through theopenings 24. In the representative embodiments, the etchant solution may be heated and/or supplied under high pressure, such as being forced through theopenings 24 under a pressure of 2 to 3 atmospheres. In an embodiment, The process removing the section 15 of theporous semiconductor layer 14 does not rely on an acid as an etchant. Theoxidized regions 20 are unaffected by the process removing the section 15 of theporous semiconductor layer 14, and are intact following its removal. - The
air gap 26 is vertically located beneath theactive device region 18 between thehandle wafer 11 and theactive device region 18. More specifically, theair gap 26 is vertically located beneath a beam or bridge 28 of theactive device region 18, as diagrammatically illustrated by the dashed lines inFIG. 5 . Theopenings 24 are laterally located between the side edges 29, 31 of the bridge 28 and respectivetrench isolation regions 16 such that the bridge 28 is not connected or supported at its side edges 29, 31. Theporous semiconductor layer 14 is not removed from underneathsections active device region 18. The bridge 28 extends laterally from one end integrally attached to thesection 30 of theactive device region 18 to an opposite end integrally attached to thesection 32 of theactive device region 18. Thesections active device region 18 directly support the bridge 28. - The porous semiconductor material in the sections 34, 36 of the
porous semiconductor layer 14 is neither oxidized nor removed, and these sections 34, 36 are respectively located beneath thesections active device region 18. The bridge 28 is also laterally located between these sections 34, 36 of theporous semiconductor layer 14. The removal process is controlled (e.g., timed) such that these sections 34, 36 of theporous semiconductor layer 14 are not removed when the sacrificial section 15 is removed. These sections 34, 36 of theporous semiconductor layer 14 directly support thesections active device region 18 and thereby indirectly support the bridge 28. - The
air gap 26 may be characterized by an effective permittivity or dielectric constant of near unity (vacuum permittivity), or may be filled by air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum). The “silicon on nothing” architecture provides efficient electrical isolation for the one ormore device structures 40. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
- A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (7)
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WO2019139573A1 (en) * | 2018-01-10 | 2019-07-18 | Intel Corporation | Techniques to reduce substrate coupling for monolithically integrated rf circuits |
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FR3085536A1 (en) * | 2018-09-03 | 2020-03-06 | Soitec | CFET DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE |
US11016055B2 (en) | 2019-07-09 | 2021-05-25 | Globalfoundries Singapore Pte. Ltd. | Sensors with a front-end-of-line solution-receiving cavity |
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