WO2019139573A1

WO2019139573A1 - Techniques to reduce substrate coupling for monolithically integrated rf circuits

Info

Publication number: WO2019139573A1
Application number: PCT/US2018/013151
Authority: WO
Inventors: Paul B. FISCHER; Han Wui Then; Sansaptak DASGUPTA; Marko Radosavljevic; Kevin Lin
Original assignee: Intel Corporation
Priority date: 2018-01-10
Filing date: 2018-01-10
Publication date: 2019-07-18

Abstract

Techniques are disclosed for fabricating airgaps to explicitly suppress parasitic electrical pathways between devices through the use of selectively etchable materials or layers. Using such features, relatively high device densities can be achieved while still suppressing crosstalk between devices. In particular, selective etchable layers are incorporated into a fabrication process. Lithographically defined access holes or trenches are introduced to facilitate the selection of etchable regions.

Description

TECHNIQUES TO REDUCE SUBSTRATE COUPLING

FOR MONOLITHICALLY INTEGRATED RF CIRCUITS

BACKGROUND

[0001] Manufacturers and consumers of radio frequency (“RF”) electronics are motivated to increase integrated component density to reduce manufacturing costs and purchase price. However, there are a number of non-trivial issues associated with such increased component density.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 shows examples of parasitic capacitance and resistive pathways between two transistors in an integrated circuit structure.

[0003] FIG. 2a depicts a standard method referred to as shallow trench isolation (“STI”) for mitigating capacitive coupling. FIG. 2b depicts a standard method that employs separate dies to mitigate capacitive coupling.

[0004] FIG. 3 depicts a cross-section view of an integrated circuit structure including airgaps for reducing capacitive coupling, according to one embodiment of the present disclosure.

[0005] FIG. 4 shows a cross-section view of an integrated circuit structure including one or more airgaps for reducing capacitive coupling, according to another embodiment of the present disclosure.

[0006] FIG. 5 shows a top down view of an example access trench, according to one embodiment of the present disclosure.

[0007] FIG. 6a shows a cross-section view of an integrated circuit that includes a gallium nitride (GaN) device layer epitaxially grown on silicon (Si) by way of two sacrificial buffer layers, prior to removal of those sacrificial buffer layers to form an airgap, according to one embodiment of the present disclosure. [0008] FIG. 6b shows a cross-section view of the integrated circuit structure of FIG. 6a after the sacrificial buffer layers have been removed to form the airgap, according to one embodiment of the present disclosure.

[0009] FIG. 6c shows a cross-section view of the integrated circuit structure after an etching process and sealant has been applied according to one embodiment of the present disclosure.

[0010] FIG. 7 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

[0011] The present disclosure relates to techniques for forming structures that explicitly suppress parasitic electrical pathways between transistor devices through the use of selectively etchable layers. The techniques are particularly useful in integrated circuit structures for radio frequency (“RF”) applications, but any number of other applications may benefit as well. In any case, the selectively etchable layers are etched to create regions effectively underlying the device layer. The resultant regions are airgaps, i.e., regions of air or vacuum. Because air or vacuum has a very low relative dielectric constant and very high resistivity, such airgap structures create low capacitive and resistive linkages. Utilizing airgaps to reduce capacitive coupling facilitates achieving high device densities while still suppressing crosstalk between devices. In particular, according to one embodiment of the present disclosure, selective etchable layers herein referred to as sacrificial layers, which may also serve as buffers to accommodate lattice matching differentials in addition to providing etch selectivity, are incorporated into a fabrication process. Lithographically defined access holes or trenches are introduced to facilitate the access and selection of etchable regions and the resulting fabrication of airgaps with particular geometric structure, according to some embodiments. In some such cases, the particular geometric structure of the airgaps may be achieved via a combination of the geometry of the access trenches as well as the diffusion time of an etchant introduced via the access holes to remove portions of the etchable regions of sacrificial layers.

General Overview

[0012] As previously explained, there are a number of non-trivial issues associated with increased component density in the context of integrated circuits. In particular, crosstalk between devices effectively places a practical limit to how closely discrete devices can be spaced due to the decreased electrical isolation. This is particularly true for RF transistors because, at elevated frequencies, even subtle capacitive coupling paths can become unintended low impedance paths and lead to signal crosstalk. Signals from one circuit bleed into neighboring circuits creating distortion and noise or otherwise degrade device performance. FIG. 1 shows examples of parasitic capacitance and resistive pathways between transistors of an integrated circuit structure. Transistor devices 102(a)- 102(b) are fabricated on active device layer 104, which is in turn fabricated on silicon substrate 106. Active device layer 104 may be a semiconductor material such as gallium nitride (“GaN”). As can be seen, parasitic capacitance 108(a) exists in active device layer 104 between neighboring transistor devices 102(a)- 102(b). In addition, parasitic capacitances 108(b)- 108(c) may exist between active device layer 104 and substrate 106. One possible technique for reducing capacitive coupling is shallow trench isolation (“STI”), as depicted in FIG. 2a. As can be seen, trenches 204(a)- 204(b) are etched to isolate transistors 102(a) and 102(b), which are respectively fabricated on active device layers 104(a)- 104(b). The trenches 204(a)-204(b) are filled with an insulator material such as silicon dioxide. The substrate 220 provides for a high resistance conductive path. While STI can be effective in some applications, it is less effective at high frequencies. Another possible technique is to use separate dies, such as shown in FIG. 2b where devices 102(c) and 102(d) are respectively fabricated on separate dies 206(a)-206(b) eliminating capacitive coupling between devices 102(c) and 102(d). However, this technique suffers from reduced performance because of area and cost penalties associated with integration of separate dies.

[0013] Thus, there exists a need for techniques to reduce capacitive coupling for monolithic integrated circuits, particularly for RF applications.

Architecture and Methodology

[0014] FIG. 3 depicts a cross-section view of an integrated circuit structure including airgaps for reducing capacitive coupling, according to one embodiment of the present disclosure. Devices 102(1)- 102(4), which in some embodiments may be metal oxide semiconductor field effect transistors (MOSFETs) but other transistor types may be used as well (e.g., thin film transistors), are fabricated on active device layer 104 (104(1)-104(4)). As will be appreciated, some parts of transistors 102 may include material that is compositionally different from the device layer 104 material, according to some embodiments. For example, device layer 104 may be gallium nitride and the source and drain regions of transistors 102 may be indium gallium nitride having an indium concentration between 5% and 20%, in an embodiment. In such cases, the material of the channel region between the source and drain regions can be the material of the device layer 104, but may also be another material, as will be appreciated. In other embodiments, the source and drain regions of transistors 102 are doped portions of the material making up device layer 104. In a more general sense, and as will be further appreciated in light of this disclosure, numerous transistor configurations can be used here, and this disclosure is not intended to be limited to any particular such configurations.

[0015] Active device layer 104 is formed on a sacrificial layer 302 (302(l)-302(4)). As further shown in FIG. 3, airgaps 304 (304(l)-304(3)) are introduced in the sacrificial layer 302 between active device layer 104 and substrate 106 in order to reduce capacitive coupling between active device layer 104 and substrate 106. Techniques for fabricating airgaps 304(1)- 304(3) are described below with respect to FIGs. 6a-6c. Further, although FIG. 3 only shows airgaps 304(l)-304(3), this is merely an example, and it will be understood that any number of airgaps 304 may be introduced in an arbitrary arrangement between active device layer 104 and substrate 106.

[0016] Also, as shown in FIG. 3, sealant 308 (308(a)-308(c)) may be introduced between adjacent active device layers (i.e., between 104(1)- 104(2), between 104(2)- 104(3), and between 104(3)-104(4)). As will be described below with respect to FIGs. 4, 5, and 6a-6c, fabrication of airgaps 304(l)-304(3) may be achieved via formation of an access trench 306 through which an etchant is introduced to remove portions of the sacrificial layer 302. The geometry of airgaps 304(l)-304(4) may be controlled by designing an appropriate access trench geometry (width and height) and utilizing the diffusion time properties of an etchant in a controlled manner. Upon formation of airgaps 304(l)-304(3), the access trenches 306 may then be sealed with sealant 308(a)-308(c). In the embodiment shown, the access trenches 306 shown are completely filled with sealant 308, but in other embodiments the access trenches 306 are pinched off or otherwise only partially filled, such that a bottom portion of the access trenches 306 in unfilled with sealant 308. In some such example cases, the sidewalls of the access trenches 306 may be conformally coated with sealant 308, such that an additional portion of the airgap 304 is between the conformally coated sidewalls of the access trenches 306. As the capacitance of air or vacuum is low, the introduction of airgaps 304(l)-304(3) greatly reduces the capacitive coupling between active device layer 104 and substrate 106.

[0017] In some example embodiments, the airgaps 304(l)-304(3) have a height that is about the same as the thickness of the sacrificial layer 302, particularly where the etchant used is selective to the materials used in the device layer 104 and substrate 106 (i.e., the etchant removes the material of the sacrificial layer at a rate that is at least 3x faster than the rate at which 104 and 106 materials are removed, or at least 5x faster, or at least lOx faster, or at least 15c faster, or at least 20x faster, etc). In still other embodiments, sacrificial layer 302 is a multilayer structure, and the airgaps 304(l)-304(3) have a height that is about the same as the thickness of one or more those layers making up the sacrificial structure. In such cases, the etchant used may be selective to the layers of the multilayer structure that don’t get etched (or are otherwise etched to a lesser degree), as will be appreciated. In one such example case, only one or more middle layers of the multilayer sacrificial structure 302 are removed to provide airgaps 304, and outer layers of the multilayer sacrificial structure 302 remain intact (except where the access trenches 306 pass through the upper outer layer to provide access to the one or more middle layers, so the airgaps can be formed using a selective etchant).

[0018] According to some embodiments, the width of the airgap effectively depends on the dwell time of the etch, wherein the longer the etchant is allowed to diffuse or otherwise dwell in the airgap being formed, the further laterally in the sacrificial layer the airgap progresses. In some embodiments, the airgap 304 extends laterally to at least under the adjacent source or drain region of the neighboring transistor. In other embodiments, the airgap 304 extends laterally to at least under the gate region of the neighboring transistor. In still other embodiments, the airgap 304 extends laterally to at least under both the source region and the drain region (as well as the channel region between the source and drain regions) of the neighboring transistor. In a more general sense, the airgap 304 extends laterally to a point sufficient to provide the electrical isolation desired for a given application.

[0019] Further note that the airgaps 304(l)-304(3) may all be etched simultaneously by a given etch process and therefore have similar geometries, as will be appreciated. However, in other embodiments, the airgaps 304(l)-304(3) may be formed separately from one another so as to allow for diverse geometries amongst the airgaps 304(l)-304(3). In such cases, for instance, a first set of airgaps 304 can be formed under a set of RF transistors forming an amplifier circuit, and a second set of airgaps 304 can be formed under a set of RF transistors forming a filter circuit. In such cases, the region where the second set of airgaps are formed can be masked off while the first set of airgaps are formed, and vice-versa. Note that airgaps 304 having diverse geometries may also all be etched simultaneously by a given etch process. For instance, in some such cases, the sacrificial layer 302 has multiple segments or portion, each configured with dissimilar materials to provide different etch rates, wherein the different etch rates allow for the simultaneous formation of the airgaps 304 having diverse geometries. So, for example, portions 302(1) and 302(2) of sacrificial layer 302 may have a first etch rate, and portions 302(3) and 302(4) of sacrificial layer 302 may have a second etch rate that is faster than the first etch rate, for a given etchant. In such a case, airgaps 304(1) and 304(3) can be formed simultaneously during the common etch process, but airgap 304(3) will be laterally longer (wider) than airgap 304(1). Any number of configurations can be used for sacrificial layer 302 to facilitate formation of such diverse airgaps 304. In any such cases, the geometry of the various airgaps 304, including width and/or height, can be to set provide the electrical isolation desired at a given location of an integrated circuit, or for a given application.

Airgap Fabrication

[0020] FIG. 4 shows a cross-section view of an integrated circuit structure including one or more airgaps for reducing capacitive coupling, according to another embodiment of the present disclosure. As can be seen, sacrificial layer 302 is introduced between active device layer 104 and substrate 106. As can be further seen, part of the sacrificial layer 302 under access trench 306 has been removed to provide airgap 304. According to one embodiment, sacrificial layer 302 comprises a selectively removable material. A selectively removable material is any material that may be selectively removed or eroded, for example, by application of a chemical compound such as an etchant, while material surrounding (above and below) that selectively removable material remains substantially intact. As previously explained, sacrificial layer 302 may comprise multiple material layers, with one or more those layers being selectively removable. For example, according to some such embodiments, sacrificial layer 302 may comprise a first material layer comprising aluminum nitride (“A1N”) and a second material layer comprising aluminum gallium nitride (“AlGaN”, such as Al_xGai_-xN where x=50% or more). Further recall that the sacrificial layer 302 may also having buffering qualities and have one or more of its components that are graded from a first concentration that provides compatibility to the material composition of substrate 106 to a second concentration that provides compatibility to the material composition of device layer 104. Such buffering can be used, for instance, to facilitate better lattice matching and a higher quality device layer 104.

[0021] Access trench 306 effectively provides a conduit for the introduction of an etchant that will operate to remove portions of sacrificial layer 302, with no or minimal impact on the device layer 104 and substrate 106. As can be seen, a central portion of sacrificial layer 302 under the access trench 306 has been removed. An etchant may be, for example, a wet etchant that may be associated with a diffusion time. Any number of anisotropic and/or isotropic etch schemes can be used, as will be appreciated. The shape of access trench 306 and the diffusion time of an etchant introduced via the access trench 306 allows for the formation of airgaps 304 between active device layer 104 and substrate 106 in any arbitrary geometry. The vertical height and lateral width of the airgaps 304 can be set as previously explained.

[0022] As can be further seen, the transistors 102 (102(a) and (102(b)) of the device layer each have a source region, a drain region, and a channel region therebetween. A gate structure is formed over the channel region, and generally includes a gate dielectric on the channel region and gate electrode on the gate dielectric. The gate structure may further include gate spacers and a hard mask on top of the gate electrode. Numerous transistor configurations can be used here, as will be appreciated.

[0023] The gate spacers (if included) may be, for example, silicon nitride or silicon dioxide. The gate dielectric may be, for example, any suitable gate dielectric material such as silicon dioxide or high-k gate dielectric materials. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used. Further, the gate electrode may comprise a wide range of suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, titanium nitride, or tantalum nitride, for example. In some embodiments, the gate dielectric and/or gate electrode may include a multilayer structure of two or more material layers or components. For instance, in one such embodiment, the gate dielectric is a bi-layer structure having a first dielectric material (e.g., silicon dioxide) in contact with the channel region and a second dielectric material (e.g., hafnium oxide) in contact with the first dielectric material, the first dielectric material having a dielectric constant that is lower than the dielectric constant of the second dielectric material. Likewise, the gate electrode structure may include a central metal plug portion (e.g., tungsten) with one or more outer work function layers and/or barrier layers (e.g., tantalum, tantalum nitride), and/or a resistance reducing cap layer (e.g., copper, gold). In some embodiments, the gate dielectric and/or gate electrode may include grading (increasing or decreasing, as the case may be) of the concentration of one or more materials therein. Numerous different gate structure configurations can be used, as will be apparent in light of this disclosure.

[0024] The source and drain regions can be, for example, epitaxial source and drain regions that are provisioned in respective source and drain trenches within the device layer 104. In some such cases, the source and drain regions are multilayer structures, such as a relatively thin liner layer and a relatively thicker cap layer. Component grading can be used in any one or all of the layers to facilitate desired component concentrations. For instance, in one example embodiment, a liner of indium gallium arsenide is provided having an indium concentration that is graded from less than 5% and transitions to an indium nitride cap. In other embodiments, the source and drain regions are doped portions of the device layer 104, such as doped gallium arsenide or indium phosphide. Numerous source and drain region configurations can be used, as will be appreciated in light of this disclosure.

[0025] FIG. 5 shows a top down view of an example access trench according to one embodiment of the present disclosure. As can be seen, transistor devices l02(a)-l02(b) are fabricated on active device layer 104. Access trench 306 exposes the underlying sacrificial layer 302. An etchant is introduced into access trench 306 to remove portions of sacrificial layer 302. According to one embodiment, a region of sacrificial layer 302 may be removed based upon the geometry/dimensions of access trench 306 and the diffusion time of the etchant. Parasitic path length 310 may be effectively enlarged by removing regions of sacrificial layer 302 thereby reducing the parasitic coupling with the substrate.

Example Structures

[0026] FIG. 6a shows a cross-section view of an integrated circuit that includes a gallium nitride (GaN) device layer epitaxially grown on silicon (Si) by way of two buffer layers, prior to removal of those buffer layers to form an airgap, according to one embodiment of the present disclosure. As can be seen, the two buffer layers (A1N 602 and Al_xGai_-xN 604) are fabricated over silicon substrate 608. As will be appreciated, both buffer layers A1N 602 and Al_xGai_-xN 604 effectively serve as sacrificial layer 302. As will be further appreciated, GaN 606 may operate as a device layer 104 upon which active devices such as MOSFETs and thin film transistors may be fabricated (e.g., RF front end devices, such as RF power transistors, RF filter transistors, and RF switching transistors).

[0027] Gallium nitride (GaN) is a desirable semiconductor for RF applications as it is ideal for many RF front end analog circuit functions: power amplifiers, voltage regulators, switches, filters, and low noise amplifiers. In GaN implementation schemes, GaN epitaxially grown on Si is attractive as it is a relatively low cost substrate. Creation of sufficiently high quality GaN can be achieved, for example, with the use of stress buffer layers to accommodate the large lattice mismatch between Si and GaN. In the case of Si, the lattice mismatch with respect to GaN is 17%. Example buffer layers include A1N and AlGaN, such as shown in FIG. 6a. For illustration purposed only two such buffer layers are shown, but any number of buffer configurations can be used, including one or more layers. In still other embodiments, the GaN device layer 606 can be provided via an epitaxial lateral overgrowth process, which can also be used to provide a quality GaN layer. In some such cases, for instance, a layer of silicon dioxide can be formed on the silicon substrate 608. This oxide layer can act as the sacrificial layer 302. A trench is then etched down through the oxide layer to expose the silicon substrate 608. GaN is then grown up from the underlying silicon and out of the trench, and then proceeds to grow laterally across the top surface of the silicon dioxide layer 302. In any such cases, an access trench 306 can then be formed to expose the sacrificial layer or structure 302 for purpose of creating the airgaps 304. FIG. 6a also shows an example access trench 306 patterned or otherwise formed in the GaN device layer 606 through to the underlying buffer layer 604.

[0028] GaN is robust to many standard wet chemical etchants. On the other hand, A1N can be readily etched in basic solutions such as potassium hydroxide (“KOH”) and tetramethylammonium hydroxide (“TMAH”). Depending on its aluminum content, AlGaN is also etched by these same example etchants to a decreasing extent as aluminum content decreases. Although FIG. 6a shows only a single AlGaN layer 604, according to alternative embodiments A1N layer 602 and several layers of AlGaN 604 with varying Al content may be utilized. In a more general sense, again, any number of buffer layer configurations can be used, and the present disclosure is not intended to be limited to any particular ones.

[0029] The source and drain regions can be any suitable group III-V semiconductor material such as indium gallium arsenide (InGaAs), or indium arsenide (InAs), or some other group III- V compound. In still other embodiments, other semiconductor materials can be used for device layer 606 and the source and drain regions, such as group IV semiconductor materials such as germanium and silicon (e.g., Si, Ge, SiGe, or SiGe:C having carbon concentration in the range of 2 to 8 percent).

[0030] FIG. 6b shows a cross-section view of the integrated circuit structure of FIG. 6a after the sacrificial buffer layers have been removed to form the airgap, according to one embodiment of the present disclosure. In particular, as shown in FIG. 6b A1N layer 602 and AlGaN layer(s) 604 are at least partially removed upon exposure to etchants such as KOH and TMAH depending on the Al content of the film, thereby forming airgap 304, which operates to reduce capacitive coupling to silicon substrate 608. Note the etchants such as KOH and TMAH can etch the A1N layer 602 and AlGaN layer(s) 604 relatively faster than they etch the silicon substrate 608 and GaN layer 606. As will be appreciated, some of the substrate 608 may be removed as well during formation of the airgap 304, providing a degree of corresponding topography on the upper surface of substrate 608, which may accordingly further increase the height of the airgap 304, as will be appreciated.

[0031] FIG. 6c shows a cross-section view of the integrated circuit structure after an etching process and sealant has been applied according to one embodiment of the present disclosure. As can be seen, a sealant 308 may be applied to the structure thereby sealing access trench 306 and facilitating the fabrication of backend layers such as interconnect. According to one embodiment, sealant 308 may be an oxide, such as silicon dioxide. According to other embodiments, sealant may be silicon nitride or another dielectric material. The structure may be planarized and cleaned as needed to prepare for further processing such as source drain contact structure formation and backend processing where one or more interconnect layers are formed above the device layer to provide desired connections suitable for the given circuitry. Note that the sealant 308 in this example embodiment does not fill the entire access trench 306, but rather pinches off near the top of the trench 306. Further note the conical shape of the airgap, as defined in the sealant within the trench 306. Further note the dimple formed in the top surface of the sealant, which results from the underlying access trench. In some embodiments, the dimple is removed during planarization, will be appreciated. The planarization process can proceed, for instance, until the top of the gate structure is exposed.

[0032] The resulting structure shown in FIG. 6c can be further processed to complete the fabrication process. For instance, if a gate-last process is employed, the dummy gate structure can be removed and replaced with the final gate structure. Alternatively, if a gate-last process is used, then the final gate structure will already be installed. In any such cases, source and drain contact structures can also be formed, where contact trenches are patterned and etched into the sealant 308 (or insulator structure used in the planarization process) over the source and drain regions, followed by deposition of one or more contact materials to form the contact structure. Standard contact formation processes and materials can be used. Backend processing can proceed after contact structure formation.

[0033] FIG. 7 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. Computing system 1000 may employ a number integrated circuit structures as variously provided herein. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

[0034] Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

[0035] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. Communication chip 1006 may be an RF process utilizing a process as described herein to introduce airgaps 304 to operate to reduce capacitive coupling between an active device layer 104 and substrate 106. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0036] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices configured as variously described herein. The term“processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0037] The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices configured as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

[0038] In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

[0039] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0040] Example 1 includes an integrated circuit structure, comprising: a substrate; a first layer of a semiconductor material; a structure between said substrate and said first layer, the structure including a second layer of a first material having a different etch rate than that of the semiconductor material, wherein said second layer includes an airgap that laterally extends between said first layer and said substrate; a trench passing through said first layer to said airgap, such that a first portion of the airgap laterally extends from the trench in a first direction, and a second portion of the airgap laterally extends from the trench in a second direction that is opposite the first direction; and a second material filling at least a portion of said trench, thereby blocking off said airgap.

[0041] Example 2 includes the subj ect matter of Example 1 , wherein said structure comprises one or more other layers in addition to said second layer, and said trench passes through at least one of said other layers to said airgap of said second layer.

[0042] Example 3 includes the subject matter of Example 2, wherein said first material of said second layer comprises aluminum and nitrogen, and an additional layer included in said other layers comprises aluminum, gallium, and nitrogen, said additional layer being between said first layer and said second layer.

[0043] Example 4 includes the subject matter of Example 3, wherein said semiconductor material of said first layer comprises gallium and nitrogen.

[0044] Example 5 includes the subject matter of Example 3 or 4, wherein said semiconductor material of said first layer is gallium nitride, said first material of said second layer is aluminum nitride, and said additional layer is a layer of aluminum gallium nitride.

[0045] Example 6 includes the subject matter of any of Examples 3 through 5, wherein said first semiconductor material of said first layer is a first group III-V semiconductor material, and said first material of said second layer is a second group III-V semiconductor material that is compositionally different from said first group III-V semiconductor material, and said additional layer is a layer of a third group III-V semiconductor material that is compositionally different from said first and second group III-V semiconductor materials.

[0046] Example 7 includes the subject matter of any of Examples 1 through 6, wherein said semiconductor material of said first layer comprises gallium and nitrogen, and said first material of second layer comprises aluminum and nitrogen.

[0047] Example 8 includes the subject matter of any of Examples 1 through 7, wherein said semiconductor material of said first layer is a first group III-V semiconductor material, and said first material of said second layer is a second group III-V semiconductor material that is compositionally different from said first group III-V semiconductor material. [0048] Example 9 includes the subject matter of any of Examples 1 through 8, wherein said first material of said second layer has an aluminum concentration of at least 50%.

[0049] Example 10 includes the subject matter of any of Examples 1 through 9, wherein said substrate is a bulk silicon substrate.

[0050] Example 11 includes the subject matter of any of Examples 1 through 10, wherein said second material is an insulator (e.g., oxide, nitride, or other insulator material).

[0051] Example 12 includes the subject matter of any of Examples 1 through 11, wherein said first layer includes a first transistor and a second transistor, and the airgap extends laterally in a first direction so as to be between at least a portion of the first transistor and the substrate, and the airgap extends laterally in a second direction so as to be between at least a portion of the second transistor and the substrate.

[0052] Example 13 includes the subject matter of any of Examples 1 through 12, wherein said semiconductor material of said first layer has a first etch rate for a given etchant, and said first material of said second layer has a second etch rate for said given etchant that is at least 3x faster than the first etch rate.

[0053] Example 14 includes the subject matter of any of Examples 1 through 13, wherein said integrated circuit structure is part of a radio frequency (RF) circuit.

[0054] Example 15 includes the subject matter of Example 14, wherein said RF circuit is an amplifier.

[0055] Example 16 includes the subject matter of Example 14, wherein said RF circuit is a filter.

[0056] Example 17 includes the subject matter of Example 14, wherein said RF circuit is a switching circuit.

[0057] Example 18 is a mobile communication device comprising said integrated circuit structure according to any of Examples 1 through 17.

[0058] Example 19 is an integrated solid-state RF (“Radio Frequency”) circuit comprising: an active device layer; at least one transistor on said active device layer, wherein said at least one transistor processes RF signals; a structure located beneath said active device layer and above a substrate, wherein said structure includes an airgap between said active device layer and said substrate; a trench penetrating said active device layer to said structure; and a material filling at least a portion of said trench so as to block off said airgap. [0059] Example 20 includes the subject matter of Example 19, wherein said structure comprises a first material layer comprising aluminum nitride and a second material layer comprising aluminum gallium nitride.

[0060] Example 21 includes the subject matter of Example 20, wherein said second material layer comprises a selectable ratio of aluminum to gallium according to Al_xGai_-xN, wherein x>50%.

[0061] Example 22 includes the subject matter of Example 19 or 20, wherein said substrate is comprised of silicon.

[0062] Example 23 includes the subject matter of any of Examples 19 through 22, wherein said at least one transistor is a metal oxide semiconductor field effect transistor (MOSFET).

[0063] Example 24 includes the subject matter of any of Examples 19 through 23, wherein said material filling at least a portion of said trench is an insulator.

[0064] Example 25 includes the subject matter of any of Examples 19 through 24, wherein at least one layer of said structure is susceptible to a faster etch rate than the active device layer, with respect to a given etch scheme. As will be appreciated, a portion of said structure where said airgap is located can be removed by said given etch scheme, according to some such example embodiments.

[0065] Example 26 is a computing system further comprising: a memory; a processor; a communication chip, wherein said communication chip includes a structure located beneath an active device layer and above a substrate, wherein said structure includes an airgap between said active device layer and said substrate; a trench passing through said active device layer to said structure; and a material filling at least a portion of said trench thereby blocking off said airgap.

[0066] Example 27 includes the subject matter of Example 26, wherein said active device layer is a GaN layer.

[0067] Example 28 includes the subject matter of Example 26 or 27, wherein said structure includes one or both of a sacrificial layer and a buffer layer.

[0068] Example 29 includes the subject matter of Example 28, wherein said structure further comprises AlGaN and A1N.

[0069] Example 30 includes the subject matter of Example 29, wherein said AlGaN comprises a selectable ratio of Al to Ga according to AlxGal-xN, wherein x>50%. [0070] Example 31 includes the subject matter of any of Examples 26 through 30, wherein said material filling at least a portion of said trench is an insulator.

[0071] The foregoing description of example embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.

Claims

CLAIMS What is claimed is:

1. An integrated circuit structure, comprising:

a substrate;

a first layer of a semiconductor material;

a structure between said substrate and said first layer, the structure including a second layer of a first material having a different etch rate than that of the semiconductor material, wherein said second layer includes an airgap that laterally extends between said first layer and said substrate; a trench passing through said first layer to said airgap, such that a first portion of the airgap laterally extends from the trench in a first direction, and a second portion of the airgap laterally extends from the trench in a second direction that is opposite the first direction; and

a second material filling at least a portion of said trench, thereby blocking off said airgap.

2. The integrated circuit structure according to claim 1, wherein said structure comprises one or more other layers in addition to said second layer, and said trench passes through at least one of said other layers to said airgap of said second layer.

3. The integrated circuit structure according to claim 2, wherein said first material of said second layer comprises aluminum and nitrogen, and an additional layer included in said other layers comprises aluminum, gallium, and nitrogen, said additional layer being between said first layer and said second layer.

4. The integrated circuit structure according to claim 3, wherein said semiconductor material of said first layer comprises gallium and nitrogen.

5. The integrated circuit structure according to claim 3, wherein said semiconductor material of said first layer is gallium nitride, said first material of said second layer is aluminum nitride, and said additional layer is a layer of aluminum gallium nitride.

6. The integrated circuit structure according to claim 3, wherein said first semiconductor material of said first layer is a first group III-V semiconductor material, and said first material of said second layer is a second group III-V semiconductor material that is compositionally different from said first group III-V semiconductor material, and said additional layer is a layer of a third group III-V semiconductor material that is compositionally different from said first and second group III-V semiconductor materials.

7. The integrated circuit structure according to claim 1, wherein said semiconductor material of said first layer comprises gallium and nitrogen, and said first material of second layer comprises aluminum and nitrogen.

8. The integrated circuit structure according to claim 1, wherein said semiconductor material of said first layer is a first group III-V semiconductor material, and said first material of said second layer is a second group III-V semiconductor material that is compositionally different from said first group III-V semiconductor material.

9. The integrated circuit structure according to claim 1, wherein said first material of said second layer has an aluminum concentration of at least 50%.

10. The integrated circuit structure according to claim 1, wherein said substrate is a bulk silicon substrate.

11. The integrated circuit structure according to claim 1, wherein said second material is an insulator.

12. The integrated circuit structure according to any of claims 1 through 11, wherein said first layer includes a first transistor and a second transistor, and the airgap extends laterally in a first direction so as to be between at least a portion of the first transistor and the substrate, and the airgap extends laterally in a second direction so as to be between at least a portion of the second transistor and the substrate.

13. The integrated circuit structure according to any of claims 1 through 11, wherein said semiconductor material of said first layer has a first etch rate for a given etchant, and said first material of said second layer has a second etch rate for said given etchant that is at least 3x faster than the first etch rate.

14. The integrated circuit structure according to any of claims 1 through 11, wherein said integrated circuit structure is part of a radio frequency (RF) circuit.

15. The integrated circuit structure according to claim 14, wherein said RF circuit is an amplifier.

16. The integrated circuit structure according to claim 14, wherein said RF circuit is a filter.

17. The integrated circuit structure according to claim 14, wherein said RF circuit is a switching circuit.

18. A mobile communication device comprising said integrated circuit structure according to any of claims 1 through 11.

19. An integrated solid-state RF (“Radio Frequency”) circuit comprising:

an active device layer;

at least one transistor on said active device layer, wherein said at least one transistor processes RF signals;

a structure located beneath said active device layer and above a substrate, wherein said structure includes an airgap between said active device layer and said substrate;

a trench penetrating said active device layer to said structure; and

a material filling at least a portion of said trench so as to block off said airgap.

20. The integrated solid-state RF circuit according to claim 19, wherein said structure comprises a first material layer comprising aluminum nitride and a second material layer comprising aluminum gallium nitride.

21. The integrated solid-state RF circuit according to claim 20, wherein said second material layer comprises a selectable ratio of aluminum to gallium according to Al_xGai-_xN, wherein x>50%.

22. The integrated solid-state RF circuit according to claim 19, wherein said substrate is comprised of silicon.

23. The integrated solid-state RF circuit according to claim 19, wherein said at least one transistor is a metal oxide semiconductor field effect transistor (MOSFET).

24. The integrated solid-state RF circuit according to claim 19, wherein said material filling at least a portion of said trench is an insulator.

25. The integrated solid-state RF circuit according to any of claims 19 through 24, wherein at least one layer of said structure is susceptible to a faster etch rate than the active device layer, with respect to a given etch scheme.