US20170192446A1 - Serial bus apparatus with controller circuit and related uses - Google Patents

Serial bus apparatus with controller circuit and related uses Download PDF

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Publication number
US20170192446A1
US20170192446A1 US14/989,378 US201614989378A US2017192446A1 US 20170192446 A1 US20170192446 A1 US 20170192446A1 US 201614989378 A US201614989378 A US 201614989378A US 2017192446 A1 US2017192446 A1 US 2017192446A1
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United States
Prior art keywords
voltage
trimmable
circuit
reached
current source
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Abandoned
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US14/989,378
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English (en)
Inventor
Chiahung Su
Madan Mohan Reddy Vemula
Abhijeet Chandrakant Kulkarni
Kenneth Jaramillo
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NXP BV
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NXP BV
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Priority to US14/989,378 priority Critical patent/US20170192446A1/en
Assigned to NXP B.V. reassignment NXP B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JARAMILLO, KENNETH, KULKARNI, Abhijeet Chandrakant, SU, CHIAHUNG, VEMULA, MADAN MOHAN REDDY
Priority to EP16200149.9A priority patent/EP3208685B1/en
Priority to CN201611125891.9A priority patent/CN106951052B/zh
Publication of US20170192446A1 publication Critical patent/US20170192446A1/en
Priority to US15/821,817 priority patent/US10209730B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J4/00—Circuit arrangements for mains or distribution networks not specified as ac or dc
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/16—Threshold monitoring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Definitions

  • aspects of various embodiments are directed to solutions in a serial bus system, and more particular aspects relate to low power solutions with trimmable components.
  • Bus interface protocols can be used to allow communication between a variety of different electronic devices and systems.
  • the protocols can define the connectors in terms of their physical sizes, dimensions, and electrical connection characteristics.
  • the protocols can also define how communications are carried out between connected devices. In some instances, the protocols define how devices negotiate with one another for purposes such as establishing communication speeds and power delivery options.
  • USB Universal Serial Bus
  • USB can be used to attach external peripherals to a Personal Computer, it can also be used for interfacings between peripherals, charging thereof and a host of other applications and uses, such as automotive, cameras, smart phones, televisions, and set-top boxes. USB can also be used as a source of power in various mobile device charging solutions. USB provides various different data transfer speeds.
  • the USB Power Delivery (PD) protocol supports a power negotiation and delivery solution that supports up to 100 W (20V ⁇ 5 A).
  • the apparatus can include a logic controller circuit that is configured to provide control over power delivery over the serial bus system.
  • the logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components.
  • Digital circuitry of the logic controller circuit can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode.
  • a voltage regulator circuit of the logic controller circuit can be configured to generate a regulated voltage from a supply voltage.
  • the logic controller circuit can also include a reset generation circuit that is configured to determine that the supply voltage has reached a first threshold voltage level; enable, in response to determining that the supply voltage has reached the first threshold voltage, the voltage regulator circuit; determine that the regulated voltage has reached a second threshold voltage level; determine that the supply voltage has reached a third threshold voltage level; and switch, in response to determining that the regulated voltage has reached the second threshold voltage level and that the supply voltage has reached the third threshold voltage level, the digital circuitry from the hibernation mode to the active mode.
  • a reset generation circuit that is configured to determine that the supply voltage has reached a first threshold voltage level; enable, in response to determining that the supply voltage has reached the first threshold voltage, the voltage regulator circuit; determine that the regulated voltage has reached a second threshold voltage level; determine that the supply voltage has reached a third threshold voltage level; and switch, in response to determining that the regulated voltage has reached the second threshold voltage level and that the supply voltage has reached the third threshold voltage level, the digital circuitry from the hibernation mode to the
  • Various embodiments of the present disclosure are directed toward a method for use with a low power logic controller circuit with trimmable analog components and that is configured to provide control over power delivery over a serial bus.
  • the method can include determining that a supply voltage has reached a first threshold voltage level; enabling, in response to determining that the supply voltage has reached the first threshold voltage, a voltage regulator circuit that is configured to generate a regulated voltage from the supply voltage; determining that the regulated voltage has reached a second threshold voltage level; determining that the supply voltage has reached a third threshold voltage level; and switching, in response to determining that the regulated voltage has reached the second threshold voltage level and that the supply voltage has reached the third threshold voltage level, a digital circuitry from a hibernation mode to an active mode, wherein the hibernation mode consumes less current than the active mode.
  • FIG. 1A depicts a block diagram for a system that is designed to use a serial bus interface to provide communication and power between devices, consistent with embodiments of the present disclosure
  • FIG. 1B shows a block diagram for a controller circuit, consistent with embodiments of the present disclosure
  • FIG. 2 depicts a state diagram for the behavior of a reset control circuit, consistent with embodiments of the present disclosure
  • FIG. 3 depicts a circuit diagram for a trimmable reference voltage circuit, consistent with embodiments of the present disclosure
  • FIG. 4 depicts a circuit diagram for a trimmable current source circuit, consistent with embodiments of the present disclosure
  • FIG. 5 shows a circuit diagram for a trimmable resistor circuit, consistent with embodiments of the present disclosure.
  • FIG. 6 shows a circuit diagram for a trimmable oscillator circuit, consistent with embodiments of the present disclosure.
  • aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving a controller circuit designed for use with a serial bus.
  • aspects of the present disclosure have been shown to be beneficial when used in the context of low power solutions with high accuracy.
  • the controller circuit can be constrained relative to cost and physical space, among other constraints.
  • a controller circuit includes analog circuitry that has been configured for providing accurate analog values and signals by providing a complex mix of different trimmable functional circuits.
  • Various embodiments are directed toward multiple trimmable functional circuits that are designed for use with an external test fixture that provides accurate reference points for the different functions.
  • one or more of the different functional circuits can be configured for low power consumption while providing high accuracy due in part to trimmable capabilities of the circuit(s).
  • USB protocol for type-C connectors specifies how different devices in a system negotiate (among other things) power providing capabilities.
  • This can include the use of a Configuration Channel (CC), with corresponding connection wires and pins.
  • CC controller circuit can be configured to detect and communicate signals using CC pins in order to detect port attachment and detachment events and to determine power providing capabilities, cable orientation, device roles, and port control for current mode.
  • embodiments and features are sometimes discussed with particular reference to USB and to type-C connectors. It is understood that various embodiments and features discussed herein can be used with a variety of additional and different protocols and applications, as well as to future versions of USB protocols and type-C connectors.
  • Certain embodiments are directed toward an apparatus for providing reduced power solutions in a serial bus system.
  • the apparatus includes a controller circuit that is configured to provide control over power delivery within the serial bus system.
  • the logic controller circuit can include analog circuitry with a plurality of analog components.
  • Trimming circuitry can be configured to allow for the fine tuning of values and settings for various analog components.
  • the trimming circuitry can be configured for use during manufacturing and testing of the device as part of a calibration process. For example, external reference voltages and resistive values can be provided by a test fixture. These voltages and values can be used by the trimming circuitry to compensate for process, voltage and temperature (PVT) variation effects.
  • PVT voltage and temperature
  • the controller circuit can include digital circuitry that provides a number of different control and detection functions related to the serial bus.
  • the digital circuit can be configured to switch between an active mode and a hibernation mode.
  • the hibernation mode can involve the placement of various components into a suspended state so that less current (and power) is consumed than in the active mode.
  • a reset generator circuit can be configured to control the hibernation and active states based upon status of various power supplies and an enable signal.
  • the controller circuit can include a voltage regulator circuit that is configured to generate a regulated voltage from a supply voltage.
  • the reset generation/control circuit can be configured to determine when the supply voltage has reached a first threshold voltage level. In response to this determination, the reset generation circuit can enable the voltage regulator circuit.
  • the reset generation circuit can also be configured to determine when the regulated voltage has reached a second threshold voltage level and when the supply voltage has reached a third threshold voltage level. In response to these two determinations, the reset generation circuit can switch the digital circuitry from the hibernation mode to the active mode.
  • USB Type-C CC control logic detection circuitry can benefit from an accurate voltage, current, resistor and clock frequency, which together support the ability to detect different events, such as attached or detached events.
  • FIG. 1A depicts a block diagram for a system that is designed to use a serial bus interface to provide communication and power between devices, consistent with embodiments of the present disclosure.
  • the system includes an application processor 102 , a bus interface logic 104 , signal driver circuit 106 , and physical connectors 108 .
  • Application processor 102 can include one or more computer processor circuits that are configured to provide and control aspects of the system that can include the operating system, applications running on the operating system, input and output (e.g. audio and video), and other functions.
  • Application processor designs can include multiple central processing units, memory interfaces, and graphic engines and can be configured to support various interfaces to other devices.
  • Bus interface logic 104 can be configured to carry out various functions defined in the relevant protocol. For example, various USB protocols specify that a compliant device should be capable of detecting the presence of other devices when they are connected to the physical connector 108 . USB functions can also include, but are not limited to, detecting the orientation of an attached cable, negotiating which device will provide power, and determining power providing capabilities of a connected device. Signal drivers and protection circuits 106 can include driver circuits that produce signals that are compliant with the particular protocol. Protection circuitry can provide protection from, as but a few examples, short circuit conditions between connections, over voltage conditions, and over current conditions.
  • Controller circuit 110 can be configured to manage power delivery functions at the physical (PHY) layer of the Open Systems Interconnection model (OSI model).
  • the controller circuit 110 can be implemented as part of a single integrated circuit (IC) chip.
  • the controller circuit 110 can be an IC chip that functions as a USB Type-C Configuration channel interface and USB PD Physical and Protocol layer functions.
  • the controller circuit 110 can be useful for a wide range of applications and platforms. Non-limiting examples of applications include notebook computers, desktop computers, tablets, smart phones and accessories. In some of the applications, power consumption can be of particular importance, such as applications involving various mobile devices.
  • Various embodiments are directed toward low power consumption of the IC chip, both during low power modes and active modes.
  • the controller circuit 110 can include analog circuitry 114 , which can include a plurality of analog components and trimming circuitry for configuring the analog components.
  • the controller circuit 110 can also include digital circuitry 116 that is configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less power and current than the active mode.
  • the digital circuitry can be designed using CMOS technology, which can include MOS transistors that exhibit particularly low power conditions when they are not being actively switched.
  • the trimming circuitry can be configured to use external pins to provide accurate reference points for trimming of the various analog components.
  • the trimming circuitry can be configured to use high-precision resistors, accurate voltage sources, accurate current sources, and combinations thereof. These accurate external reference points can then be used to adjust (or trim) the values for the analog components, which can help compensate for PVT variations.
  • FIG. 1B shows a block diagram for a controller circuit, consistent with embodiments of the present disclosure.
  • the controller circuit depicted in FIG. 1B can be used, for example, in the system depicted in FIG. 1A .
  • the controller circuit shown in FIG. 1B can be used in systems with various different configurations.
  • the reset generation/control circuit 156 can be configured to control the enabling, disabling, and power saving modes for various other circuits and components. This can include enabling each of the voltage regulator circuit 154 , digital circuitry 160 and analog circuitry 158 .
  • the reset control circuit 156 can be configured to detect when different voltage levels meet a particular threshold and use this information to control the enablement of the various circuits.
  • the voltage regulator circuit 154 can also be responsive to input control signals. For example, a hibernation signal can be used to determine whether the digital circuitry 160 is placed into an enabled/active mode or disabled/hibernation mode.
  • a trimmable voltage reference circuit 152 can be configured to provide an accurate reference voltage.
  • Various circuits such as the voltage regulator circuit 154 and circuits that generate on-chip biasing currents, can use the reference voltage and benefit from improved accuracy thereof.
  • the trimmable voltage reference circuit 152 can be configured to allow for adjustment (trimming) of the reference voltage value during calibration of the controller circuit. This trimming can be particularly useful for compensating for process, voltage, and temperature (PVT) variations between different devices. For instance, various implementations have sufficient resolution in the trimmable settings to allow for the total voltage variations between devices to be less than 2% over expected PVT for the devices.
  • the trimmable current sources and resistors 162 can be configured to provide accurate current and resistive values that can be used, for example, to generate output currents and resistances that comply with the serial bus protocol being used (e.g., according to the USB Type-C specification). For example, the current and resistor variations from USB Type-C spec is less than 8% and 10% over PVT, respectively.
  • the trimmable voltage reference circuit 152 can be configured to allow for adjustment (trimming) of the reference voltage value during calibration of the controller circuit. With sufficient resolution of trimmable settings in combination with accurate external references, the variations for the current and resistor values can be maintained within the USB Type-C specification over expected PVT.
  • the trimmable oscillator circuit 164 can be configured to generate a clock signal that has both low power consumption and low frequency variation over the expected PVT (due in part to trimming of the frequency).
  • the trimmable oscillator circuit 164 can be configured to generate a 45 Khz clock that is used by the digital circuitry 160 .
  • the frequency variation of this clock can be controlled to within about 5% over expected PVT variations.
  • FIG. 2 depicts a state diagram for the behavior of a reset control circuit, consistent with embodiments of the present disclosure.
  • the state diagram of FIG. 2 is consistent with a USB Type-C implementation; however, aspects depicted in the flow diagram can be applied to other protocols and corresponding implementations.
  • the reset controller can be configured to operate with a wide range of supply voltages (Vdd).
  • Vdd supply voltages
  • the reset control circuit can be designed to operate with a supply voltage that is between 2.7V and 5.5V.
  • the supply voltage can be provided by a source that is external to the controller circuit chip. The particular parameters of the supply voltage during ramp-up period would depend upon the external device.
  • Ramp up characteristics may vary considerably depending upon the attached device. Accordingly, various embodiments are directed toward a reset controller that is configured to provide a successful power up for a wide range of ramp up rates of supply voltages and to account for a non-monotonic supply voltage ramp up, or other variations.
  • the first state in the diagram begins when a Vdd powerup event occurs, per block 202 . This event represents the presence of a Vdd supply voltage.
  • the reset control circuit determines whether or not the supply voltage has reached a first threshold voltage, per block 204 .
  • analog components can be enabled, per block 206 .
  • the enabled analog components include a reference voltage generator circuit that can generate a reference voltage that is used by a voltage regulator. An optional delay can be implemented to allow time for the reference voltage to stabilize.
  • the particular value of this first threshold voltage can vary depending on the particular implementation.
  • the depicted first voltage is 1 . 47 volts, which represents a voltage at which the voltage regulator circuit can safely be enabled (block 208 ), for a particular implementation of a USB Type C compliant device.
  • the depicted 1.8V is provided as an example and is not necessarily limiting.
  • the reset control circuit can determine when the regulated output voltage (Va dd1.8 ) reaches a second threshold voltage level, per block 210 .
  • a second threshold voltage level For example, if the voltage regulator is designed to provide 1 . 8 V at steady state, the second threshold voltage could be set to around 1.09V.
  • the reset control circuit can be configured so that circuits that rely upon the regulated voltage are held in a reset state.
  • the reset control circuit can remove the reset for the components, per block 212 .
  • These circuits can include, but are not necessarily limited to, digital circuitry, oscillator(s), and reference current generators.
  • the removal of the reset state can allow the digital circuitry to enter an initial state where some elements have power but the entire circuitry is not yet be fully enabled.
  • the digital circuitry is in a hibernation state when the reset is removed, but an enable signal has not yet been provided. In the hibernation state, the power consumption of the digital components can be kept very low (e.g., by limiting switching of CMOS transistors).
  • the reset control circuit can also be configured to determine when the supply voltage reaches a third threshold level, per block 214 .
  • the depicted value is 2.6V, which corresponds to an acceptable tolerance relative to the above example in which the power supply voltage is expected to be between 2.7V and 5.5V.
  • the reset control circuit can generate an enable signal for the digital circuitry, per block 216 .
  • the reset control circuit can debounce this signal (e.g., for 12 ms) to avoid oscillating between enabled and disabled states.
  • This signal e.g., for 12 ms
  • An example of another solution for this concern is the use of a hysteresis for the enable versus disable voltage thresholds.
  • the reset control circuit can use analog comparator(s) to determine when the different voltages reach the corresponding threshold. This can include the use of a reference voltage to derive the threshold voltage, such as the (bandgap) reference voltage that is enabled in block 206 .
  • the controller circuit can include a processor circuit that is initialized from a set of instructions (image) stored in a memory circuit (or just a “memory”).
  • the reset control circuit can arrive at the state corresponding to block 216 after the image has already been retrieved (e.g., by entering and leaving hibernation mode).
  • the reset control circuit can be configured to determine whether or not the image was previously fetched, per block 218 .
  • the image fetch procedure can include a step in which a flag is set once the image retrieval has completed. The reset control circuit can check the value of this flag before proceeding to retrieve the image from memory, per block 220 . In either event, the controller circuit can then enter normal operation, per block 222 .
  • the reset control circuit can remove the enable signal so that the digital circuitry enters the hibernation mode, per block 228 .
  • the reset control circuit can keep the digital circuitry in the hibernation state until it detects that the supply voltage is above the third threshold and the hibernation mode signal is not present, per blocks 230 and 232 , respectively.
  • FIG. 3 depicts a circuit diagram for a trimmable reference voltage circuit, consistent with embodiments of the present disclosure.
  • Reference voltage circuit 302 can be configured to generate a reference voltage (V BG ) that is adjustable (trimmable) over a set of values.
  • V BG reference voltage
  • the reference voltage circuit 302 can be a bandgap reference circuit.
  • an external voltage (V EXT ) can be provided from automated test equipment. The automated test equipment does not have the size or cost constraints of the trimmable reference voltage circuit. Accordingly, it is possible to create a highly accurate reference voltage.
  • Comparator 304 can be configured to compare the reference voltage to the externally provided voltage and to produce an output (INTB) that is based upon the result of the comparison.
  • the resulting output can be used as part of a search algorithm and the testing process can be repeated for a different trim setting for the reference voltage circuit 302 .
  • the crossover point from negative to positive values for the output can be used to identify the desired setting for the trimmable reference voltage circuit.
  • Switches 306 can be used to connect and disconnect the comparator from the reference voltage and the external pin once the trimming process is completed.
  • comparator offset can lead to inaccurate measurement results from the comparator.
  • a low-offset comparator can be used.
  • the external reference voltage can be adjusted to compensate for an offset of the comparator.
  • FIG. 4 depicts a circuit diagram for a trimmable current source circuit, consistent with embodiments of the present disclosure.
  • Operational amplifier 402 is connected in a negative feedback configuration in order to maintain the current through transistor 404 at a desired current level.
  • the current through transistor 404 is provided to a trimmable resistor 410 and the resulting voltage (V trim ) is provided to the positive input terminal of the amplifier 402 to create the negative feedback.
  • a reference voltage (V BG ) is provided to the negative input terminal of the amplifier 402 .
  • the current at this point represents the steady state current level for the circuit.
  • Transistors 406 - 408 are configured as current mirrors to transistor 404 and thereby changes in the current through transistor 404 result in corresponding changes in the current through transistors 406 - 408 .
  • the internal reference current used by the controller circuit is produced by transistors 407 and 408 .
  • Transistor 406 operates to provide a measurement current (I mes ) that is the same as, or a known proportion of, the internal reference current.
  • the trimmable current source circuit includes a connection point (ID) that is designed for connection to automated test equipment that provides an external resistance (R EXT ).
  • the measurement current from transistor 406 creates a voltage (V mes ) due to a corresponding voltage drop across the external resistance (R EXT ). Accordingly, the voltage on the node (Vp) is representative of the current through transistor 406 .
  • the Vp node is also connected to the positive input terminal of comparator 412 in order to compare the voltage produced by the actual current with the expected voltage.
  • the measurement from comparator 412 is taken with switch 416 closed and switch 418 open.
  • the output used for the measurement will be based upon a comparison of V mes with V trim (where V trim is equal to V BG ).
  • the measurements can be repeated for different values of R trim and the output of comparator 412 can be stored to find the crossover point (e.g., where Vm>Vp transitions to Vp ⁇ Vm or vice versa). This information can then be used to select and set the appropriate value for R trim .
  • the trimmable current source circuit can include a connection point (PORT) that is designed for connection to automated test equipment in order to provide an external reference voltage (V EXT ).
  • V EXT external reference voltage
  • switch 418 can be closed and switch 416 can be open.
  • V m the voltage on the negative terminal
  • a comparator 412 can be designed to have low offset characteristics to improve the accuracy of the measurements.
  • the measurements can be carried out using a digital binary search algorithm, although other search algorithms are also possible.
  • FIG. 5 shows a circuit diagram for a trimmable resistor circuit, consistent with embodiments of the present disclosure.
  • the trimmable resistor circuit depicted in FIG. 5 is configured to set the resistive value for the trimmable resistor 502 .
  • the trimmable resistor circuit is configured to allow automated test equipment to connect to a connection point (ID).
  • the trimmable resistor circuit is configured to trim the resistance of the trimmable resistor 502 so that it matches an external resistance (R EXT ) provided by the automated test equipment. This is accomplished by comparing the trimming voltage (V trim ) to a reference voltage (V ref ).
  • a (binary) search algorithm can be used to find the desired setting and resistive value for the trimmable resistor 502 .
  • the reference voltage (V ref ) can be generated using a resistor divider circuit that uses two reference resistors (R ref ). Consistent with various embodiments, the resistors can be matched in terms of their ideal resistance, structure, and manufacturing process. In this manner, the PVT variations for the resistors will be closely matched and cancel one another out to provide V ref at very close to one half of V DD .
  • the external resistance (R EXT ) can then be set to the desired value of the trimmable resistor. The result is that V trim will match V ref when the trimmable resistor is at the desired value. For example, R EXT could be implemented using an external 5.1 K ⁇ resistor with a very high accuracy.
  • the resistance of the trimmable resistor (V trim ) can be trimmed to 5.1 K ⁇ 2% after completion of the (binary) search algorithm.
  • FIG. 6 shows a circuit diagram for a trimmable oscillator circuit, consistent with embodiments of the present disclosure.
  • the trimmable oscillator circuit depicted in FIG. 6 uses capacitive charging to determine the frequency of oscillation.
  • a trimmable current source 602 is configured to be used to control the charge rate and corresponding frequency of oscillation.
  • the frequency of oscillation can be calculated as:
  • Ton is the time between transitions
  • C is the capacitance of capacitor 604
  • I is the current provided by the trimmable current source 602
  • V ref is a reference voltage
  • t comp _ delay is the delay introduced by comparator 608 , SR (set reset) latch 610 , and any discharge time for capacitor 604 .
  • the circuit operates by charging capacitor 604 using the trimmable current source and comparing the resulting voltage (V p ) to the reference voltage (V ref ). Once the reference voltage has been exceeded by the charge on the capacitor, the output of the comparator 608 inverts causing latch 610 to enable transistor 606 , which then discharges the capacitor 604 . In response to the discharge, latch 610 is then reset. The resetting of latch 610 results in a positive edge on the inverted output (Qn) of latch 610 . The positive edge is provided to the clocking input of the flip flop 612 , which is configured to invert its output on each such edge.
  • the trimmable current source 602 can be a separate current source or it can be obtained from biasing circuitry, such as the trimmable circuitry discussed in connection with FIG. 4 .
  • the reference voltage (V ref ) can be obtained through a trimmable reference, such as the trimmable circuitry discussed in connection with FIG. 3 .
  • the capacitor 604 can be a trimmable for use in adjusting the clock frequency. The trimmable capacitor can be used in place or in combination with the trimmable current source.
  • trimmable oscillator can be provided that offers a clock frequency of 45 Khz with + ⁇ 5% over process, voltage and temperature.
  • an analog circuit architecture can provide high precision, multiple features and low power consumption. Particular results suggest that for a circuit with a trimmable voltage reference, an 1.8V on-chip regulator, trimmable current source(s), a trimmable oscillator and trimmable resistors, a nominal current consumption of about 4.4 uA can be achieved in a hibernation mode, and of about 13 uA in an active mode.
  • a “block” also sometimes “circuit”, “logic circuitry”, or “module” can be implemented using a circuit that carries out one or more of these or related operations/activities.
  • a hard-wired control block can be used to minimize the area for such an implementation in case limited flexibility is sufficient.
  • one or more modules are discreet logic circuits or programmable logic circuits configured and arranged for implementing these operations/activities.

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US14/989,378 2016-01-06 2016-01-06 Serial bus apparatus with controller circuit and related uses Abandoned US20170192446A1 (en)

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EP16200149.9A EP3208685B1 (en) 2016-01-06 2016-11-23 Serial bus apparatus with controller circuit and related uses
CN201611125891.9A CN106951052B (zh) 2016-01-06 2016-12-08 具有控制器电路的串行总线设备及相关使用
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US10209730B2 (en) 2019-02-19
CN106951052B (zh) 2021-11-09
EP3208685B1 (en) 2020-03-04

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