US20170160618A1 - Liquid crystal panel, liquid crystal display device, and manufacturing method thereof - Google Patents
Liquid crystal panel, liquid crystal display device, and manufacturing method thereof Download PDFInfo
- Publication number
- US20170160618A1 US20170160618A1 US15/439,434 US201715439434A US2017160618A1 US 20170160618 A1 US20170160618 A1 US 20170160618A1 US 201715439434 A US201715439434 A US 201715439434A US 2017160618 A1 US2017160618 A1 US 2017160618A1
- Authority
- US
- United States
- Prior art keywords
- line
- electrode
- liquid crystal
- film
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 95
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 72
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000010409 thin film Substances 0.000 claims description 21
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 122
- 239000010408 film Substances 0.000 description 259
- 230000001681 protective effect Effects 0.000 description 38
- 238000010586 diagram Methods 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- G02F2001/136231—
-
- G02F2001/13629—
-
- G02F2001/136295—
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
Definitions
- the present invention relates to a liquid crystal panel, and in particular, to a technique for reducing the number of times of application of exposure in a process of manufacturing the same.
- a pixel electrode and a common electrode are both formed on one substrate where a thin film transistor is formed.
- this kind of liquid crystal panel includes one of a type in which a common electrode is formed in the uppermost layer except an alignment layer film, and other conductor layers, such as a pixel electrode, a signal line, and so forth, are formed in layers lower than the common electrode.
- a common electrode is formed in the uppermost layer except an alignment layer film
- other conductor layers such as a pixel electrode, a signal line, and so forth
- an electric field generated by a voltage applied to a video signal line (drain line) can be shielded by using the common electrode. Consequently, a black matrix for hiding influence of an electric field on displayed image can be reduced in its width and thus an aperture ratio of a pixel can be improved.
- a substrate of a liquid crystal panel is generally manufactured using a photolithographic method.
- a photolithographic method a resist film is patterned on an insulating film and a conductor film at exposure processes, and the insulating film or the like is etched using the resist film as a mask.
- Exposure processes are desired fewer in the number of times of performing the process, because the exposure processes cost much due to using an expensive photo mask.
- An aspect of the present invention aims to reduce the number of times performing exposure processes in manufacturing of a liquid crystal panel and a liquid crystal display device having a pixel electrode and a common electrode formed on one substrate and a pixel electrode, a signal line, and so forth formed in a layer lower than the common electrode.
- Another aspect of the present invention aims to provide a manufacturing method thereof.
- a liquid crystal panel includes two substrates sandwiching liquid crystal; a thin film transistor formed on one substrate of the two substrates and having lines connected thereto; a pixel electrode formed on the one substrate and made of a transparent conductive material; and a common electrode formed on the one substrate and made of a transparent conductive material.
- the pixel electrode, the thin film transistor, and the lines are positioned in a layer lower than the common electrode.
- a gate line of the lines has a two-layered structure containing a lower line made of material identical to the pixel electrode and positioned in a layer same as the pixel electrode, and an upper line layered on the lower line and made of material having a higher electrical conductivity than the transparent conductive material.
- a liquid crystal display device including the above described liquid crystal panel.
- exposure using a multiple gradation mask can be carried out to a resist film at a process of forming a gate line and a pixel electrode. Consequently, the gate line and the pixel electrode can both be formed at a single exposure process, and therefore the number of exposure processes can be reduced.
- the thin film transistor may include an electrode formed above a first insulating film covering the gate line and the pixel electrode; the common electrode may be formed on a second insulating film over the first insulating film; and a connecting conductor maybe formed in a layer same as the common electrode and made of material identical to the common electrode, the connecting conductor being connected the electrode of the thin film transistor and the pixel electrode through a contact hole formed in the first insulating film and the second insulating film.
- the connection conductor can be formed without increasing the number of exposure processes.
- the electrode of the thin film transistor may include a part positioned above the pixel electrode; the part of the electrode and a part of the pixel electrode may be positioned inside the contact hole; and the connecting conductor may connect the part of the electrode and the part of the pixel electrode together inside the contact hole.
- an auxiliary common line maybe formed in a layer lower than the common electrode and connected to the common electrode through a contact hole; and the auxiliary common line may have a two-layered structure containing a lower auxiliary line positioned in a layer same as the pixel electrode and the lower line of the gate line and made of material identical to the pixel electrode, and an upper auxiliary line made of material identical to the upper line of the gate line and layered on the lower auxiliary line.
- the auxiliary common line may have a two-layered structure containing a lower auxiliary line positioned in a layer same as the pixel electrode and the lower line of the gate line and made of material identical to the pixel electrode, and an upper auxiliary line made of material identical to the upper line of the gate line and layered on the lower auxiliary line.
- the common electrode may have an auxiliary common line formed thereon and made of material having a higher electrical conductivity than the common electrode.
- the auxiliary common line it is possible to reduce the resistance of the common electrode by the auxiliary common line. Further, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- a drain line for receiving a video signal may be formed in a layer lower than the common electrode and connected to the thin film transistor, and an auxiliary common line, made of material having a higher electrical conductivity than the common electrode, may be formed in a layer same as the drain line and connected to the common electrode through a contact hole. In this embodiment, it is possible to reduce the resistance of the common electrode.
- the thin film transistor may include a channel formed of a semiconductor layer, and the drain line and the auxiliary common line may have a two-layered structure containing the semiconductor layer and a conductor layer on the semiconductor layer.
- exposure using a multiple gradation mask can be carried out to the resist film at a process forming the channel, the drain line, and the auxiliary common line. Consequently, it is possible to form the channel, the drain line, and the auxiliary common line at a single exposure process, and therefore, it is possible to reduce the number of exposure processes.
- the common electrode may be formed such that a part of the common electrode is positioned above a drain line connected to the thin film transistor and receiving a video signal. In this embodiment, an electric field generated by the drain line can be shielded by the common electrode.
- a second insulating film and an additional insulating portion may be formed between the part of the common electrode and the drain line, the additional insulating portion being made of material having a lower dielectric constant than the second insulating film.
- the additional insulating portion may be made of material for a resist film used in an etching process forming the second insulating film. As a result, the additional insulating portion can be formed without increasing the number of exposure processes.
- a method for manufacturing the liquid crystal panel comprising a process of layering a conductor film on a transparent conductive film for forming the pixel electrode, the conductor film having a higher electrical conductivity than the transparent conductive film; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a first resist film patterned corresponding to the pixel electrode and a second resist film thicker than the first resist film and patterned corresponding to a gate line of the lines, and a process of forming, using the first resist film and the second resist film, the pixel electrode from the transparent conductive film, and the gate line from the transparent conductive film and the conductor film.
- the gate line and the pixel electrode can both be made at a single exposure process, and therefore, it is possible to reduce the number of exposure processes.
- the method may further comprise a process of forming a first insulating film for covering the pixel electrode and the gate line; a process of forming an electrode constituting the thin film transistor above the first insulating film; a process of layering a second insulating film over the first insulating film such that the second insulating film covers the electrode of the thin film transistor; a process of forming a transparent conductive film on the second insulating film; and a process of forming, from the transparent conductive film, a connecting conductor and the common electrode, the connecting conductor being connected to the pixel electrode and the electrode of the thin film transistor through contact holes formed in the first insulating film and the second insulating film.
- the second resist film may be patterned corresponding to an auxiliary common line to be connected with the common electrode, in addition to the gate line. In this embodiment, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- the method may further comprise a process of layering on a transparent conductive film for forming the common electrode, a conductor film having a higher electrical conductivity than the transparent conductive film; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a third resist film patterned corresponding to the common electrode, and a fourth resist film thicker than the third resist film and patterned corresponding to an auxiliary common line to be formed on the common electrode; and a process of forming the common electrode from the transparent conductive film, and the auxiliary common line from the conductive film, using the third resist film and the fourth resist film.
- the method may further comprise a process of layering a conductor film on a semiconductor layer for forming a channel of the thin film transistor; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a fifth resist film patterned corresponding to the channel, and a sixth resist film thicker than the fifth resist film and patterned corresponding to a drain line connected to the thin film transistor and an auxiliary common line formed along the drain line; and a process of forming the channel from the semiconductor layer, and the drain line and the auxiliary common line from the semiconductor layer and the conductor layer, using the fifth resist film and the sixth resist film.
- a process of layering a conductor film on a semiconductor layer for forming a channel of the thin film transistor may further comprise a process of layering a conductor film on a semiconductor layer for forming a channel of the thin film transistor; a process of forming a resist film on the conductor film; a process of patterning the
- the method may further comprise a process of forming a first insulating film for covering the pixel electrode and the gate line to be connected to the thin film transistor; a process of forming a second insulating film over the first insulating film; a process of forming, on the second insulating film, a resist film having a lower dielectric constant than the second insulating film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a resist film having a part thicker than other part thereof on the drain line; a process of removing the resist film except the thicker part of the resist film; and a process of forming the common electrode on the thicker part of the resist film and the second insulating film.
- FIG. 1 is an exploded perspective view of a liquid crystal panel according to one embodiment of the present invention
- FIG. 2 is a plan view of a pixel formed on one transparent substrate (first substrate) constituting the liquid crystal panel;
- FIG. 3 is a cross sectional view of the liquid crystal panel with a cross section along the line III-III shown in FIG. 2 ;
- FIG. 4 is a cross sectional view of the liquid crystal panel with a cross section along the line IV-IV shown in FIG. 2 ;
- FIG. 5 is a diagram explaining a first exposure process in a manufacturing process of the first substrate
- FIG. 6 is a diagram explaining a second exposure process in a manufacturing process of the first substrate
- FIG. 7 is a diagram explaining a third exposure process in a manufacturing process of the first substrate
- FIG. 8 is a diagram explaining the third exposure process
- FIG. 9 is a diagram explaining the third exposure process
- FIG. 10 is a diagram explaining a fourth exposure process in a manufacturing process of the first substrate
- FIG. 11 is a diagram showing another example of a connection structure between a source electrode and a pixel electrode shown in FIG. 3 ;
- FIG. 12 is a plan view of a first substrate of a liquid crystal panel according to a second embodiment of the present invention.
- FIG. 13 is a cross sectional view of the first substrate shown in FIG. 12 , with a cross section along the line XIII-XIII shown in FIG. 12 ;
- FIG. 14 is a cross sectional view of the first substrate shown in FIG. 12 , with a cross section along the line XIV-XIV shown in FIG. 12 ;
- FIG. 15 is a plan view of a first substrate of a liquid crystal panel according to a third embodiment of the present invention.
- FIG. 16 is a cross sectional view of the first substrate shown in FIG. 15 , with a cross section along the line XVI-XVI shown in FIG. 15 ;
- FIG. 17 is a cross sectional view of the first substrate shown in FIG. 15 , with a cross section along the line XVII-XVII shown in FIG. 15 ;
- FIG. 18A is a diagram showing a manufacturing process of a first substrate according to the third embodiment.
- FIG. 18B is a diagram showing a manufacturing process of a first substrate according to the third embodiment.
- FIG. 18C is a diagram showing a manufacturing process of a first substrate according to the third embodiment.
- FIG. 18D is a diagram showing a manufacturing process of a first substrate according to the third embodiment.
- FIG. 19 is a plan view of a first substrate of a liquid crystal panel according to a fourth embodiment of the present invention.
- FIG. 20 is a cross sectional view of the first substrate shown in FIG. 19 , with a cross section along the line XX-XX shown in FIG. 19 ;
- FIG. 21 is a cross sectional view of the first substrate shown in FIG. 19 , with a cross section along the line XXI-XXI shown in FIG. 19 ;
- FIG. 22 is a cross sectional view of a liquid crystal panel according to a fifth embodiment of the present invention, with the cross section same as that along the line shown in FIG. 2 ;
- FIG. 23 is a cross sectional view of the liquid crystal panel according to the fifth embodiment of the present invention, with the cross section same as that along the line IV-IV shown in FIG. 2 ;
- FIG. 24 is a diagram showing a process forming an additional insulating portion in the fifth embodiment.
- FIG. 1 is an exploded perspective view of a liquid crystal display device according to an embodiment of the present invention.
- a liquid crystal display device includes a liquid crystal panel 10 .
- the liquid crystal display device further includes an upper frame 12 and a lower frame 14 that together sandwich the outer circumferential edge of the liquid crystal panel 10 .
- the liquid crystal panel 10 is held by these frames 12 , 14 .
- the liquid crystal display device includes a backlight unit (not shown). The backlight unit is placed on the rear side of the liquid crystal panel 10 , and irradiates light toward the rear surface of the liquid crystal panel 10 .
- FIG. 2 is a plan view of a pixel formed on one transparent substrate 16 constituting the liquid crystal panel 10 .
- FIGS. 3 and 4 are cross sectional views of the liquid crystal panel 10 .
- FIG. 3 is a cross sectional view with a cross section along the line III-III shown in FIG. 2
- FIG. 4 is a cross sectional view with a cross section along the line IV-IV shown in FIG. 2 .
- the liquid crystal panel 10 has a first substrate 16 and a second substrate 18 opposed to each other. These two substrates are transparent substrates (e.g., a glass substrate).
- the first substrate 16 and the second substrate 18 sandwich liquid crystal 20 .
- Polarizers 22 in a crossed-Nicols arrangement are respectively attached on the surface of the first substrate 16 opposite from the liquid crystal 20 and on the surface of the second substrate 18 opposite from the liquid crystal 20 .
- a black matrix 130 is formed on the surface of the second substrate 18 toward the liquid crystal 20 .
- the black matrix 130 is made of a highly light-shielding material such as resin that contains black pigment and carbon, metal chromium, and nickel.
- the black matrix 130 has a function of preventing light from being irradiated to a channel 53 of a thin film transistor 50 formed on the first substrate 16 . Further, in this example described here, as shown in FIG. 4 , the black matrix 130 is positioned on a drain line 56 to be described later formed on the first substrate 16 , being formed along the drain line 56 .
- color filters 100 are formed on the surface of the second substrate 18 toward the liquid crystal 20 .
- the color filters 100 are made of colored films in a plurality of colors (e.g., three colors including red, green, and blue).
- an overcoat film 120 is formed on the side of the second substrate 18 toward the liquid crystal 20 , covering the color filters 100 .
- the surface of the second substrate 18 toward the liquid crystal 20 is protected by the overcoat film 120 .
- the first substrate 16 will be described. In the description below, the direction in which the first substrate 16 faces the liquid crystal 20 is defined as an upper direction.
- a plurality of thin film transistors (hereinafter referred to as a TFT) 50 functioning as a switch for controlling the liquid crystal 20 are formed on the surface of the first substrate 16 toward the liquid crystal 20 (the upper surface).
- the TFT 50 includes a channel 53 formed of a semiconductor layer of amorphous silicon, microcrystal silicon, and so forth, a drain electrode 52 , and a source electrode 54 .
- the drain electrode 52 and the source electrode 54 are respectively positioned on the opposite sides to each other across the channel 53 .
- one electrode, of the two electrodes 52 , 54 , connected to a pixel electrode 70 is refereed as the source electrode 54
- the other electrode 52 is referred as a drain electrode.
- a plurality of gate lines 40 connected to the respective TFT's 50 are formed on the first substrate 16 .
- the drain lines 52 , the source electrodes 54 , and the channels 53 are positioned above the gate line 40 . Therefore, the gate line 40 includes parts functions as a gate electrode of the TFT 50 .
- a scan signal (a gate voltage) for turning on/off the TFT 50 is applied to the gate line 40 .
- a plurality of drain lines 56 connected to the drain electrodes 52 are formed on the first substrate 16 .
- a video signal (a voltage signal indicating a grayscale value of each pixel) is applied to the drain line 56 .
- the plurality of gate lines 40 and the plurality of drain lines 56 are arranged in matrix. That is, the plurality of gate lines 40 are formed substantially perpendicular to the respective drain lines 56 .
- An area surrounded by two adjacent gate lines 40 and two adjacent drain lines 56 constitutes a single pixel, and each pixel is provided with a TFT 50 .
- the liquid crystal panel 10 drives the liquid crystal 20 in an in-plane switching mode (that is, IPS mode), and thus the pixel electrode 70 and a common electrode 80 opposed to the pixel electrode 70 are both formed on the first substrate 16 .
- the pixel electrode and the common electrode 80 are both made of transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide).
- a video signal is applied via the drain line 56 and the TFT 50 to the pixel electrode 70 .
- the pixel electrode 70 has a substantially rectangular shape in a plan view, and a size corresponding to a single pixel.
- the common electrode 80 includes a common line 82 .
- the common line 82 is positioned above and formed along the drain line 56 .
- the common line 82 connects parts of the common electrode 80 that are opposed to the pixel electrode 70 together. With the above, the substantially same potential is resulted throughout the whole common electrode 80 .
- each slit is long in the direction along the drain line 56 . Further, each slit is bent midway thereof, and therefore a part thereof on one side (the upper side in FIG. 2 ) and a part of the other side (the lower side in FIG. 2 ) across the midway part are difference from each other in angle relative to a rubbing direction.
- the pixel electrode 70 , the TFT 50 , and lines connected to the TFT 50 are positioned in a lower layer (a layer closer to the first substrate 16 ) than the common electrode 80 .
- the common electrode 80 is formed in the uppermost layer (a layer closest to the liquid crystal 20 ) except an alignment film (not shown) for aligning liquid crystal 20 .
- the gate line 40 has a two-layered structure. That is, the gate line 40 has a lower gate line 40 a and an upper gate line 40 b.
- the lower gate line 40 a is made of transparent conductive material identical to the pixel electrode 70 , and positioned in the same layer as the pixel electrode 70 . That is, the pixel electrode 70 and the lower gate line 40 a are both positioned on the first substrate 16 .
- the upper gate line 40 b is layered on the lower gate line 40 a.
- the lower gate line 40 a is patterned into a shape corresponding to the upper gate line 40 b.
- the whole upper gate line 40 b is positioned on the lower gate line 40 a, being in contact with the lower gate line 40 a.
- Such a two-layered structure of the gate line 40 enables a manufacturing method to be described later.
- the upper gate line 40 b is made of material different from the lower gate line 40 a and the pixel electrode 70 .
- the upper gate line 40 b is made of metal having a higher electrical conductivity than the transparent conductive material of which the pixel electrode 70 or the like is made.
- the gate line 40 b is made of copper, molybdenum, aluminum, or the like. This enables a smaller resistance of the gate line 40 as a whole.
- a gate insulating film 42 is formed on and covering the upper side of the gate line 40 and the pixel electrode 70 .
- the gate insulating film 42 is made of inorganic material such as semiconductor oxide (oxide silicon (SiO 2 )), nitride semiconductor (silicon nitride (SiN x )) or the like.
- the channel 53 , the source electrode 54 , and the drain electrode 52 of the TFT 50 are formed above the gate insulating film 42 .
- the channel 53 or the like is formed on the gate insulating film 42 .
- the drain line 56 connected to the drain electrode 52 is formed above the gate insulating film 42 .
- the drain line 56 is positioned in the same layer as the electrodes 52 , 54 , being formed on the gate insulating film 42 .
- the source electrode 54 , the drain electrode 52 , and the drain line 56 have a two-layered structure including a semiconductor layer 60 for forming the channel 53 and a conductor layer layered on the semiconductor layer 60 (e.g., a metal layer such as copper, molybdenum, aluminum, and so forth). That is, the semiconductor layer 60 is patterned into a shape corresponding to the source electrode 54 , the drain electrode 52 , and the drain line 56 . Then, the whole conductor layer forming the source electrode 54 , the drain electrode 52 , and the drain line 56 is positioned on and in contact with the semiconductor layer 60 .
- a semiconductor layer 60 for forming the channel 53
- a conductor layer layered on the semiconductor layer 60 e.g., a metal layer such as copper, molybdenum, aluminum, and so forth. That is, the semiconductor layer 60 is patterned into a shape corresponding to the source electrode 54 , the drain electrode 52 , and the drain line 56 . Then, the whole conductor layer forming the source electrode
- a protective insulating film 44 is formed on and covering the upper side of the channel 53 , the source electrode 54 , the drain electrode 52 , and the drain line 56 .
- the protective insulating film 44 is made of inorganic material such as semiconductor oxide (oxide silicon (SiO 2 )), nitride semiconductor (silicon nitride (SiN x )), and so forth.
- the protective insulating film 44 prevents humidity contamination of the semiconductor layer 60 .
- the common electrode 80 is formed on the protective insulating film 44 .
- the common electrode 80 is formed such that apart thereof is positioned above the drain line 56 (that is, the part covers the drain line 56 ).
- the common electrode 80 includes the common line 82 .
- the common line 82 is positioned above the drain line 56 and thus overlaps the drain line 56 in a plan view.
- the common line 82 is wider than the drain line 56 .
- a video signal according to a grayscale value of each pixel is applied to the drain line 56 .
- the common line 82 has a function of shielding a noise of electric field due to change of the video signal. Consequently, it is possible to make smaller the width of the black matrix for preventing light transmission due to the noise of electric field.
- a connecting conductor 84 (a connecting line) for connecting the source electrode 54 and the pixel electrode 70 is formed in the same layer as the common electrode 80 .
- the connecting conductor 84 is formed on the protective insulating film 44 , and is connected to the pixel electrode 70 and the source electrode 54 through contact holes 94 , 92 , respectively.
- the contact hole 92 is formed above the source electrode 54 and penetrates the protective insulating film 44 .
- the contact hole 94 is formed above the pixel electrode 70 and penetrates the gate insulating film 42 and the protective insulating film 44 .
- the two contact holes 92 , 94 are positioned apart from each other.
- the connecting conductor 84 is bridged between the contact holes 92 , 94 , being connected to the pixel electrode 70 and the source electrode 54 through the contact holes 94 , 92 , respectively. Consequently, the source electrode 54 is electrically connected to the pixel electrode 70 .
- the connecting conductor 84 is made of transparent conductive material identical to the common electrode 80 .
- a connecting pad 32 is formed on the pixel electrode 70 .
- the connecting pad 32 is positioned at the lower end of the contact hole 94 , and in contact with the pixel electrode 70 .
- the connecting conductor 84 is connected to the pixel electrode 70 through the contact hole 94 and the connecting pad 32 .
- the connecting pad 32 is made of material having a higher electrical conductivity than the transparent conductive material of which the pixel electrode 70 and the lower gate line 40 a are made.
- the connecting pad 32 is made of material identical to the upper gate line 40 b (that is, metal such as copper or molybdenum).
- the connecting pad 32 is positioned in the same layer as the upper gate line 40 b. Therefore, the connecting pad 32 can be formed at the same process as the upper gate line 40 b, as to be described later. Incidentally, the connecting pad 32 is slightly larger in size than the contact hole 94 .
- FIGS. 5 to 10 are diagrams showing a manufacturing process of the first substrate 16 .
- the first substrate 16 is manufactured through four exposure processes.
- FIG. 5 is a diagram explaining a first exposure process
- FIG. 6 is a diagram explaining a second exposure process
- FIGS. 7 to 9 are diagrams explaining a third exposure process
- FIG. 10 is a diagram explaining a fourth exposure process.
- a transparent conductive film (e.g., a film such as indium tin oxide or indium zinc oxide) 79 for forming the pixel electrode 70 and a conductor film 49 for forming the upper gate line 40 b and the connecting pad 32 are layered on the first substrate 16 .
- the transparent conductive film 79 is formed on the first substrate 16 by means of spattering or vacuum evaporation, and the conductor film 49 (a metal film such as e.g., copper, molybdenum, aluminum, and so forth) having a higher electrical conductivity than the transparent conductive film 79 is formed on the transparent conductive film 79 .
- a resist film 99 is formed on the conductor film 49 .
- the resist film 99 is patterned through an exposure process using a photo mask and a development process, and thereby resist films 99 A, 99 B are formed on the conductor film 49 .
- a multiple gradation mask having three levels of light transmissivity such as a half-tone mask, a gray tone mask, is used as the photo mask, and thereby two resist films having different thickness are formed.
- a thin resist film 99 A having a pattern corresponding to the pixel electrode 70 and a thick resist film 99 B, thicker than the thin resist film 99 A, corresponding to the gate line 40 and the connecting pad 32 are formed.
- the pixel electrode 70 is formed using the thin resist film 99 A, and the gate line 40 and the connecting pad 32 are formed using the thick resist film 99 B.
- the conductor film 49 and the transparent conductive film 79 are etched using both of the thin resist film 99 A and the thick resist film 99 B as a mask. Consequently, as shown in 5 C in FIG. 5 , the conductor film 49 and the transparent conductive film 79 are removed in the absence area of the thin resist film 99 A and the thick resist film 99 B.
- the thin resist film 99 A is removed.
- the thick resist film 99 B being thicker than the thin resist film 99 A, is left having become thinner.
- the conductor film 49 is etched using the residual thick resist film 99 B as a mask, and the thick resist film 99 B is then completely removed. Consequently, as shown in 5 E in FIG. 5 , the above described gate line 40 , the connecting pad 32 , and the pixel electrode 70 are formed. That is, the pixel electrode 70 and the lower gate line 40 a are made from the transparent conductive film 79 , and the upper gate line 40 b and the connecting pad 32 are made from the conductor film 49 .
- the gate insulating film 42 is formed on and covering the gate line 40 , the pixel electrode 70 , and the connecting pad 32 .
- the gate insulating film 42 is formed using, e.g., plasma enhanced chemical vapor deposition.
- the channel 53 , the source electrode 54 , and the drain electrode 52 of the TFT 50 , and the drain line 56 are formed on the gate insulating film 42 .
- a multiple gradation mask is used so that those are formed in one exposure process.
- the semiconductor layer 60 , an Ohmic layer (not shown), and a conductor film for forming the source electrode 54 , and so forth, are layered on the gate insulating film 42 by means of plasma enhanced chemical vapor deposition or sputtering. Thereafter, a resist film is formed on the conductor film. Then, similar to the method shown in 5 C in FIG. 5 , the resist film is patterned utilizing a multiple gradation mask. That is, a thin resist film corresponding to a channel and a thick resist film corresponding to the source electrode 54 , the drain electrode 52 , and the drain line 56 are formed on the conductor film. Then, using the two resist patterns having different thickness, the channel 53 , the source electrode 54 , the drain electrode 52 , and the drain line 56 are formed.
- the protective insulating film 44 is formed on the gate insulating film 42 , covering the TFT 50 . Thereafter, a resist film 98 is layered on the protective insulating film 44 .
- plasma enhanced chemical vapor deposition can be employed, similar to forming the gate insulating film 42 .
- the contact hole 92 penetrating the protective insulating film 44 and the contact hole 94 penetrating the gate insulating film 42 and the protective insulating film 44 are formed.
- the resist film 98 is patterned through an exposure process and a development process. That is, a pattern (holes 98 a, 98 b ) corresponding to the contact holes 92 , 94 are formed on the resist film 98 (see 7 B).
- the protective insulating film 44 and the gate insulating film 42 are etched, and thereafter, the resist film 98 is removed.
- the contact holes 92 , 94 are resulted (see 7 C).
- a terminal of the gate line 40 and a terminal of the drain line 56 are positioned on the outer circumferential part of the first substrate 16 .
- an opening is formed on the gate insulating film 42 and the protective insulating film 44 , and the terminal of the gate line 40 is connected through the opening to a driving circuit for applying a scan signal to the gate line 40 .
- the terminal of the drain line 56 is connected through the opening to a driving circuit for applying a video signal to the drain line 56 .
- the opening for connection between the terminal of the gate line 40 and the driving circuit and the opening for connection between the terminal of the drain line 56 and the driving circuit are formed at the same time as the contact holes 92 , 94 shown in FIG. 7 .
- FIG. 8 is a cross sectional view of a terminal of the gate line 40 .
- the cross sections shown in 8 A, 8 B, and 8 C in FIG. 8 correspond to the respective processes shown in 7 A, 7 B, and C 7 in FIG. 7 .
- FIG. 9 is a cross sectional view of a terminal of the drain line 56 .
- the cross sections shown in 9 A, 9 B, and 9 C in FIG. 9 correspond to the respective processes shown in 7 A, 7 B, and 7 C in FIG. 7 .
- the gate insulating film 42 , the protective insulating film 44 , and the resist film 98 are layered on a terminal of the gate line 40 .
- the drain line 56 is formed on the gate insulating film 42 , and a terminal of the drain line 56 is covered by the protective insulating film 44 and the resist film 98 .
- the resist film 98 is patterned through the exposure process and the development process. That is, openings 98 c, 98 d of the resist film 98 are formed on the terminal of the gate line 40 and the terminal of the drain line 56 , respectively. Then, using the patterned resist film 98 as a mask, the protective insulating film 44 and the gate insulating film 42 are etched. Consequently, as shown in 8 C and 9 C, the openings 43 a, 43 b are formed on the respective terminals of the gate line 40 and of the drain line 56 . These terminals are connected to the respective driving circuits through the respective openings 43 a, 43 b.
- a transparent conductive film for forming the common electrode 80 is supplied also to the openings 43 a, 43 b at a process described later. Consequently, the terminals of the respective lines 40 , 56 are connected to the respective driving circuits via the transparent conductive film supplied to these respective openings 43 a, 43 b.
- the common electrode 80 and the connecting conductor 84 are formed on the protective insulating film 44 .
- a transparent conductive film 89 is formed on the protective insulating film 44 .
- the formation of the transparent conductive film 89 is carried out using, e.g., spattering.
- a resist film 97 is formed on the transparent conductive film 89 , and then patterned through an exposure process and a development process. That is, the resist film 97 is formed into a pattern corresponding to the common electrode 80 and the connecting conductor 84 .
- the transparent conductive film 89 is etched. Consequently, as shown in 10 B, the common electrode 80 and the connecting conductor 84 are formed on the protective insulating film 44 . Note that, in this process, a transparent conductive film is supplied also to the openings 43 a, 43 b described above, and after etching or the like, the transparent conductive film is left only in the openings 43 a, 43 b.
- the above described is an example of a manufacturing method of the first substrate 16 .
- the gate line 40 is made of material identical to the pixel electrode 70 and has a two-layered structure containing the lower gate line 40 a positioned in the same layer as the pixel electrode 70 , and the upper gate line 40 b layered on the lower gate line 40 a and made of material having a higher electrical conductivity than the transparent conductive material of which the pixel electrode 70 is made. Therefore, it is possible to form both of the gate line 40 and the pixel electrode 70 at one exposure process.
- the connecting conductor 84 connected to the source electrode 54 of the TFT 50 and the pixel electrode 70 through the contact holes 92 , 94 , respectively, is made of material identical to the common electrode 80 and formed in the same layer as the common electrode 80 .
- the connecting conductor 84 can be formed at the same process as the common electrode 80 . Consequently, it is possible to prevent increase of the number of manufacturing processes for the connecting conductor 84 .
- FIG. 11 is across sectional view showing another example of a structure for connection between the source electrode 54 and the pixel electrode 70 , showing the same cross section as that shown in FIG. 3 . Note that a member identical to that which is described above is given an identical reference numeral.
- the source electrode 54 extends toward the pixel electrode 70 , exceeding the edge of the gate line 40 .
- An end part 54 ′ of the source electrode 54 is positioned above the pixel electrode 70 (on the connecting pad 32 in this example), overlapping a part of the connecting pad 32 in a plan view.
- a contact hole 94 ′ is formed in and penetrating the protective insulating film 44 and the gate insulating film 42 .
- One contact hole 94 ′ is formed such that the end part 54 ′ of the source electrode 54 and a part of the connecting pad 32 are exposed. That is, the end part 54 ′ of the source electrode 54 and the part of the connecting pad 32 are positioned inside the contact hole 94 ′.
- a connecting conductor (connection electrode) 84 ′ connects the end part 54 ′ of the source electrode 54 and the pixel electrode 70 (the connecting pad 32 in this example) together inside the contact hole 94 ′.
- a connecting conductor 84 ′ is shorter, compared to the above described connecting conductor 84 , the aperture ratio of each pixel can be improved.
- the connecting conductor 84 ′ as well is made of material identical to the common electrode 80 , similar to the connecting conductor 84 .
- the connecting conductor 84 ′ can be formed at the same time as when the common electrode 80 is formed at the process shown in FIG. 10 .
- the source electrode 54 ′ can be formed at the same time as the source electrode 54 at the process described with reference to FIG. 6 .
- FIG. 12 is a plan view of a first substrate of a liquid crystal panel 110 according to a second embodiment of the present invention.
- FIGS. 13 and 14 are cross sectional views of the liquid crystal panel 110 in this embodiment, showing cross sections along the line XIII-XIII and the line XIV-XIV, respectively, in FIG. 12 . Note that a part identical to that which is described above is given an identical reference numeral in the respective diagrams.
- a common electrode 180 made of transparent conductive material is formed on the protective insulating film 44 .
- slits are formed on the common electrode 180 , but having a different shape from that of the common electrode 80 described above. That is, the slits on the common electrode 180 are formed diagonally extending from one common line 182 to another common line 182 .
- a plurality of slits are formed symmetrical to each other about the central line C of each pixel.
- the common line 182 in this example is formed along the drain line 56 , but not covering the drain line 56 .
- the capacitance between the drain line 56 and the common electrode 80 can be reduced. Consequently, it is possible to reduce delay in transmission of a video signal through the drain line 56 .
- an auxiliary common line 183 is formed in a layer lower than the common electrode 180 .
- the auxiliary common line 183 is formed in the same layer as the gate line 40 and the pixel electrode 70 . That is, the auxiliary common line 183 is formed on the first substrate 16 . Also, the auxiliary common line 183 is formed along the gate line 40 . In other words, the auxiliary common line 183 is formed parallel to the gate line 40 . Further, the auxiliary common line 183 is positioned closer to one of the two adjacent gate lines 40 .
- the auxiliary common line 183 has a two-layered structure. Specifically, the auxiliary common line 183 includes a lower auxiliary line 183 a made of transparent conductive material identical to the pixel electrode 70 and the lower gate line 40 a, and an upper auxiliary line 183 b layered on the lower auxiliary line 183 a and made of material identical to the upper gate line 40 b. That is, the upper auxiliary line 183 b is made of material having a higher electrical conductivity than the transparent conductive material.
- the auxiliary common line 183 is electrically connected to the common electrode 180 . This can reduce resistance of the common electrode 180 .
- a contact hole 195 is formed in the gate insulating film 42 and the protective insulating film 44 .
- the auxiliary common line 183 is electrically connected to the common electrode 180 through the contact hole 195 .
- Such an auxiliary common line 183 can be formed at the same process as the pixel electrode 70 and the gate line 40 , as shown in FIG. 5 . That is, after the transparent conductive film 79 , the conductor film 49 , and the resist film 99 are layered on the first substrate 16 ( 5 A in FIG. 5 ), the thin resist film 99 A having a pattern corresponding to the shape of the gate line 40 and the auxiliary common line 183 and the thick resist film 99 B having a pattern corresponding to the pixel electrode 70 are formed, using a multiple gradation mask. With the above, the auxiliary common line 183 can be formed without increasing the number of exposure processes.
- the contact hole 195 is formed at a process at which the contact holes 92 , 94 shown in FIG. 7 are formed. That is, a resist film having a pattern corresponding to the contact holes 92 , 94 , 195 is formed on the protective insulating film 44 (see 7 B in FIG. 7 ). Then, after the protective insulating film 44 and the gate insulating film 42 are etched, the resist film is removed. Through the above process, the contact holes 92 , 94 , 195 are formed. Other processes are similar to those in the first embodiment.
- FIG. 15 is a plan view of a first substrate of a liquid crystal panel 210 according to a third embodiment.
- FIGS. 16 and 17 are cross sectional views of the liquid crystal panel 210 in this embodiment, showing cross sections along the line XVI-XVI and the line XVII-XVII respectively in FIG. 15 . Note that a member identical to that which is described above is given an identical reference numeral in the respective diagrams.
- an auxiliary common line 283 is formed on the common electrode 80 .
- the auxiliary common line 283 is made of material having a higher electrical conductivity than the transparent conductive material of which the common electrode 80 is made.
- the auxiliary common line 283 is made of metal such as copper, molybdenum, aluminum. Therefore, the resistance of the common electrode 80 can be reduced.
- the auxiliary common line 283 is formed along the common line 82 , being layered on the common line 82 .
- the common line 82 is formed above the drain line 56 made of metal such as copper or the like.
- the auxiliary common line 283 can not invite drop of the aperture ratio of each pixel.
- the auxiliary connecting conductor 284 is layered on the connecting conductor 84 .
- the auxiliary connecting conductor 284 is made of material having a higher electrical conductivity than the transparent conductive material of which the common electrode 80 and the connecting conductor 84 are made.
- the auxiliary connecting conductor 284 is made of metal such as copper, molybdenum, aluminum, and so forth. The auxiliary connecting conductor 284 can reduce resistance of the connecting conductor 84 .
- FIGS. 18A to 18D are diagrams showing the fourth exposure process in manufacturing the first substrate according to the third embodiment.
- (a) is a cross sectional view showing a cross section along the line XVI-XVI shown in FIG. 15
- (b) is a cross sectional view showing a cross section along the line XVII-XVII shown in FIG. 15 .
- a multiple gradation mask is used in forming the common electrode 80 and the connecting conductor 84 as well. Therefore, the auxiliary connecting conductor 284 and the auxiliary common line 283 can be formed without increasing the number of exposure processes.
- the transparent conductive film 89 and a conductor film 289 for forming the auxiliary common line 283 and the auxiliary connecting conductor 284 are layered on the protective insulating film 44 , and the resist film 97 is further formed on the conductor film 289 .
- the resist film 97 is patterned through an exposure process using a multiple gradation mask and a development process, whereby resist films 97 A, 97 B having different thickness are formed on the conductor film 289 . That is, the thin resist film 97 A having a pattern corresponding to the shape of the common electrode 80 and the thick resist film 97 B having a pattern corresponding to the shape of the auxiliary common line 283 and the auxiliary connecting conductor 284 are formed. In the above, the thick resist film 97 B is thicker than the thin resist film 97 A.
- the conductor film 289 and the transparent conductive film 89 are etched using both of the thin resist film 97 A and the thick resist film 97 B as a mask.
- the thin resist film 97 A is removed.
- the thick resist film 97 B is left having become thinner.
- the conductor film 289 is etched using the residual thick resist film 97 B as a mask, and thereafter, the thick resist film 97 B is completely removed.
- the auxiliary common line 283 and the auxiliary connecting conductor 284 shown in FIGS. 15 and 16 are formed.
- Other processes are similar to those in the first embodiment.
- FIG. 19 is a plan view of a first substrate of a liquid crystal panel 310 according to a fourth embodiment of the present invention.
- FIGS. 20 and 21 are cross sectional views of the liquid crystal panel 310 in this embodiment, showing cross sections along the line XX-XX and the line XXI-XXI, respectively, in FIG. 19 .
- an auxiliary common line 383 is formed in the same layer as the drain line 56 .
- the auxiliary common line 383 is formed along the drain line 56 .
- the auxiliary common line 383 is formed parallel to the drain line 56 and closer to one of the two adjacent drain lines 56 .
- the common line 382 is positioned above and covering the auxiliary common line 383 and the drain line 56 . That is, the common line 382 is formed along the auxiliary common line 383 and the drain line 56 , overlapping these lines in a plan view.
- the auxiliary common line 383 is connected to the common electrode 380 through the contact hole 395 formed in the protective insulating film 44 .
- the auxiliary common line 383 includes a connection part 383 a, and the contact hole 395 is formed on the connection part 383 a.
- the connection part 383 a projects from the auxiliary common line 383 in the direction along the gate line 40 to be positioned on the gate line 40 . With this arrangement, drop of the aperture ratio of each pixel due to the connection part 383 a can be prevented. Note that such a connection part 383 a projecting from the auxiliary common line 383 may not be provided. That is, the contact hole 395 may be formed on the auxiliary common line 383 .
- the auxiliary common line 383 Similar to the drain line 56 , the auxiliary common line 383 as well has a two-layered structure containing the semiconductor layer 60 and a conductor layer layered on the semiconductor layer 60 . That is, in this embodiment, the semiconductor layer 60 is patterned into a shape corresponding to the source electrode 54 , the drain electrode 52 , the drain line 56 , and the auxiliary common line 383 .
- Such an auxiliary common line 383 can be formed at the process at which the drain line 56 is formed, without increasing the number of exposure processes. Specifically, at the process described with reference to FIG. 6 , the semiconductor layer 60 and a conductor film for forming the drain line 56 , the auxiliary common line 383 and so forth are layered on the gate insulating film 42 . Thereafter, a resist film is formed on the conductor film. Then, the resist film is patterned through an exposure process using a multiple gradation mask and a development process.
- a thin resist film having a pattern corresponding to the channel 53 and a thick resist film having a pattern corresponding to a part having a two-layered structure, such as the drain line 56 , the auxiliary common line 383 and so forth, are formed on the conductor film. Then, the channel 53 , the source electrode 54 , the drain electrode 52 , the drain line 56 , and the auxiliary common line 383 are formed using the thin resist film and the thick resist film.
- the contact hole 395 is formed at the process at which the contact holes 92 , 94 shown in FIG. 7 are formed. That is, a resist film having a pattern corresponding to the contact holes 92 , 94 , 395 is formed on the protective insulating film 44 (see 7 B in FIG. 7 ). Then, after the protective insulating film 44 and the gate insulating film 42 are etched, the patterned resist film is removed. With those processes, the contact holes 92 , 94 , 395 are formed. Other processes are similar to those in the first embodiment.
- FIGS. 22 and 23 are cross sectional views of a liquid crystal panel 410 according to a fifth embodiment of the present invention.
- the cross section shown in FIG. 22 is the same as the cross section along the line III-III shown in FIG. 2 .
- the cross section shown in FIG. 23 is the same as the cross section along the line IV-IV shown in FIG. 2 .
- the common electrode 80 is formed such that it is partially positioned above the drain line 56 .
- the common line 82 formed integral with the common electrode 80 is positioned above the drain line 56 .
- an additional insulating portion 445 is formed between the common line 82 and the drain line 56 .
- the additional insulating portion 445 is formed along the common line 82 and the drain line 56 , and on the protective insulating film 44 . That is, the additional insulating portion 445 is formed only between the common line 82 and the drain line 56 , but not in other parts. With this structure, drop of a light transmissivity due to the additional insulating portion 445 can be prevented.
- the additional insulating portion 445 is made of material having a lower dielectric constant than the protective insulating film 44 .
- material having a lower dielectric constant for example, in the case where SiO 2 or SiN x is used for the protective insulating film 44 , an organic material having a relative dielectric constant equal to 4 or smaller is used for the additional insulating portion 445 .
- the additional insulating portion 445 is made of material (e.g., photosensitivity acrylic resin) that can function as a resist film in an etching process for the protective insulating film 44 .
- material e.g., photosensitivity acrylic resin
- the additional insulating portion 445 can be formed on the protective insulating film 44 without increasing the number of exposure processes.
- FIG. 24 is a diagram showing a process of forming the additional insulating portion 445 . Note that the respective processes shown in 24 A, 24 B, and 24 C in FIG. 24 correspond to the respective processes shown in 7 A, 7 B, and 7 C in FIG. 7 . Below, a process different from the manufacturing process according to the first embodiment will be mainly described.
- the protective insulating film 44 and a resist film 449 for forming the additional insulating portion 445 are formed on the gate insulating film 42 so as to cover the TFT 50 .
- the resist film 449 is patterned through an exposure process and a development process. At the exposure process, two resist films having different thickness that are patterned using a multiple gradation mask are formed on the protective insulating film 44 . That is, a thin resist film 449 A having the contact holes 92 , 94 and the openings 43 a, 43 b (see FIGS.
- the thick resist film 449 B is positioned above and formed along the drain line 56 .
- the protective insulating film 44 and the gate insulating film 42 are etched to thereby form the contact holes 92 , 94 and the openings 43 a, 43 b on the terminals.
- the thin resist film 449 A is removed.
- the thick resist film 449 B becomes thinner as a result that the thick resist film 449 B is soaked in a remover solution used in this process.
- the residual thick resist film 449 B constitutes the additional insulating portion 445 .
- the common line 82 is formed on the additional insulating portion 445 through the process shown in FIG. 10 .
Abstract
A gate line (40) has a two-layered structure comprising a lower gate line (40 a) made of material identical to a pixel electrode (70), and positioned in the same layer as the pixel electrode (70), and an upper gate line (40 b) layered on the lower gate line (40 b), and made of material having a higher electrical conductivity than the transparent conductive material. According to this structure, it is possible to reduce the number of times performing exposure processes in manufacturing an in-plane switching type liquid crystal panel.
Description
- The present application claims priority from Japanese application JP2010-266443 filed on Nov. 30, 2010, the content of which is hereby incorporated by reference into this application.
- 1. Field of the Invention
- The present invention relates to a liquid crystal panel, and in particular, to a technique for reducing the number of times of application of exposure in a process of manufacturing the same.
- 2. Description of the Related Art
- In an in-plane switching liquid crystal panel, a pixel electrode and a common electrode (opposed electrode) are both formed on one substrate where a thin film transistor is formed. As described in International Publication No. WO2001/018597, this kind of liquid crystal panel includes one of a type in which a common electrode is formed in the uppermost layer except an alignment layer film, and other conductor layers, such as a pixel electrode, a signal line, and so forth, are formed in layers lower than the common electrode. In this type, an electric field generated by a voltage applied to a video signal line (drain line) can be shielded by using the common electrode. Consequently, a black matrix for hiding influence of an electric field on displayed image can be reduced in its width and thus an aperture ratio of a pixel can be improved.
- A substrate of a liquid crystal panel is generally manufactured using a photolithographic method. In the photolithographic method, a resist film is patterned on an insulating film and a conductor film at exposure processes, and the insulating film or the like is etched using the resist film as a mask.
- Exposure processes are desired fewer in the number of times of performing the process, because the exposure processes cost much due to using an expensive photo mask. An aspect of the present invention aims to reduce the number of times performing exposure processes in manufacturing of a liquid crystal panel and a liquid crystal display device having a pixel electrode and a common electrode formed on one substrate and a pixel electrode, a signal line, and so forth formed in a layer lower than the common electrode. Another aspect of the present invention aims to provide a manufacturing method thereof.
- According to an aspect of a liquid crystal panel includes two substrates sandwiching liquid crystal; a thin film transistor formed on one substrate of the two substrates and having lines connected thereto; a pixel electrode formed on the one substrate and made of a transparent conductive material; and a common electrode formed on the one substrate and made of a transparent conductive material. The pixel electrode, the thin film transistor, and the lines are positioned in a layer lower than the common electrode. A gate line of the lines has a two-layered structure containing a lower line made of material identical to the pixel electrode and positioned in a layer same as the pixel electrode, and an upper line layered on the lower line and made of material having a higher electrical conductivity than the transparent conductive material.
- According to another aspect of the present invention, there is provided a liquid crystal display device including the above described liquid crystal panel.
- According to the present invention, exposure using a multiple gradation mask can be carried out to a resist film at a process of forming a gate line and a pixel electrode. Consequently, the gate line and the pixel electrode can both be formed at a single exposure process, and therefore the number of exposure processes can be reduced.
- In an embodiment of the present invention, the thin film transistor may include an electrode formed above a first insulating film covering the gate line and the pixel electrode; the common electrode may be formed on a second insulating film over the first insulating film; and a connecting conductor maybe formed in a layer same as the common electrode and made of material identical to the common electrode, the connecting conductor being connected the electrode of the thin film transistor and the pixel electrode through a contact hole formed in the first insulating film and the second insulating film. According to this embodiment, the connection conductor can be formed without increasing the number of exposure processes. In this embodiment, the electrode of the thin film transistor may include a part positioned above the pixel electrode; the part of the electrode and a part of the pixel electrode may be positioned inside the contact hole; and the connecting conductor may connect the part of the electrode and the part of the pixel electrode together inside the contact hole. As a result, it is possible to make a smaller connecting conductor, and therefore the aperture ratio of a pixel can be improved.
- In another embodiment of the present invention, an auxiliary common line maybe formed in a layer lower than the common electrode and connected to the common electrode through a contact hole; and the auxiliary common line may have a two-layered structure containing a lower auxiliary line positioned in a layer same as the pixel electrode and the lower line of the gate line and made of material identical to the pixel electrode, and an upper auxiliary line made of material identical to the upper line of the gate line and layered on the lower auxiliary line. In this embodiment, it is possible to reduce the resistance of the common electrode by the auxiliary common line. Further, it is possible to form the auxiliary common line without increasing the number of exposure processes.
- In another embodiment of the present invention, the common electrode may have an auxiliary common line formed thereon and made of material having a higher electrical conductivity than the common electrode. In this embodiment, it is possible to reduce the resistance of the common electrode by the auxiliary common line. Further, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- In another embodiment of the present invention, a drain line for receiving a video signal may be formed in a layer lower than the common electrode and connected to the thin film transistor, and an auxiliary common line, made of material having a higher electrical conductivity than the common electrode, may be formed in a layer same as the drain line and connected to the common electrode through a contact hole. In this embodiment, it is possible to reduce the resistance of the common electrode.
- In this embodiment, the thin film transistor may include a channel formed of a semiconductor layer, and the drain line and the auxiliary common line may have a two-layered structure containing the semiconductor layer and a conductor layer on the semiconductor layer. As a result, exposure using a multiple gradation mask can be carried out to the resist film at a process forming the channel, the drain line, and the auxiliary common line. Consequently, it is possible to form the channel, the drain line, and the auxiliary common line at a single exposure process, and therefore, it is possible to reduce the number of exposure processes.
- In another embodiment of the present invention, the common electrode may be formed such that a part of the common electrode is positioned above a drain line connected to the thin film transistor and receiving a video signal. In this embodiment, an electric field generated by the drain line can be shielded by the common electrode.
- In this embodiment, a second insulating film and an additional insulating portion may be formed between the part of the common electrode and the drain line, the additional insulating portion being made of material having a lower dielectric constant than the second insulating film. As a result, it is possible to reduce the capacity between the drain line and the common electrode.
- In this embodiment, the additional insulating portion may be made of material for a resist film used in an etching process forming the second insulating film. As a result, the additional insulating portion can be formed without increasing the number of exposure processes.
- According to another aspect of the present invention, there is provided a method for manufacturing the liquid crystal panel, the method comprising a process of layering a conductor film on a transparent conductive film for forming the pixel electrode, the conductor film having a higher electrical conductivity than the transparent conductive film; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a first resist film patterned corresponding to the pixel electrode and a second resist film thicker than the first resist film and patterned corresponding to a gate line of the lines, and a process of forming, using the first resist film and the second resist film, the pixel electrode from the transparent conductive film, and the gate line from the transparent conductive film and the conductor film.
- According to the present invention, the gate line and the pixel electrode can both be made at a single exposure process, and therefore, it is possible to reduce the number of exposure processes.
- In one embodiment, the method may further comprise a process of forming a first insulating film for covering the pixel electrode and the gate line; a process of forming an electrode constituting the thin film transistor above the first insulating film; a process of layering a second insulating film over the first insulating film such that the second insulating film covers the electrode of the thin film transistor; a process of forming a transparent conductive film on the second insulating film; and a process of forming, from the transparent conductive film, a connecting conductor and the common electrode, the connecting conductor being connected to the pixel electrode and the electrode of the thin film transistor through contact holes formed in the first insulating film and the second insulating film. According to this embodiment, it is possible to form a connecting conductor without increasing the number of exposure processes.
- In one embodiment, the second resist film may be patterned corresponding to an auxiliary common line to be connected with the common electrode, in addition to the gate line. In this embodiment, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- In one embodiment, the method may further comprise a process of layering on a transparent conductive film for forming the common electrode, a conductor film having a higher electrical conductivity than the transparent conductive film; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a third resist film patterned corresponding to the common electrode, and a fourth resist film thicker than the third resist film and patterned corresponding to an auxiliary common line to be formed on the common electrode; and a process of forming the common electrode from the transparent conductive film, and the auxiliary common line from the conductive film, using the third resist film and the fourth resist film. In this embodiment, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- In one embodiment, the method may further comprise a process of layering a conductor film on a semiconductor layer for forming a channel of the thin film transistor; a process of forming a resist film on the conductor film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a fifth resist film patterned corresponding to the channel, and a sixth resist film thicker than the fifth resist film and patterned corresponding to a drain line connected to the thin film transistor and an auxiliary common line formed along the drain line; and a process of forming the channel from the semiconductor layer, and the drain line and the auxiliary common line from the semiconductor layer and the conductor layer, using the fifth resist film and the sixth resist film. As a result, it is possible to form an auxiliary common line without increasing the number of exposure processes.
- In one embodiment, the method may further comprise a process of forming a first insulating film for covering the pixel electrode and the gate line to be connected to the thin film transistor; a process of forming a second insulating film over the first insulating film; a process of forming, on the second insulating film, a resist film having a lower dielectric constant than the second insulating film; a process of patterning the resist film to form, through exposure using a multiple gradation mask, a resist film having a part thicker than other part thereof on the drain line; a process of removing the resist film except the thicker part of the resist film; and a process of forming the common electrode on the thicker part of the resist film and the second insulating film. In this embodiment, it is possible to form an insulating part having a low dielectric constant between the common electrode and the drain line without increasing the number of exposure processes.
-
FIG. 1 is an exploded perspective view of a liquid crystal panel according to one embodiment of the present invention; -
FIG. 2 is a plan view of a pixel formed on one transparent substrate (first substrate) constituting the liquid crystal panel; -
FIG. 3 is a cross sectional view of the liquid crystal panel with a cross section along the line III-III shown inFIG. 2 ; -
FIG. 4 is a cross sectional view of the liquid crystal panel with a cross section along the line IV-IV shown inFIG. 2 ; -
FIG. 5 is a diagram explaining a first exposure process in a manufacturing process of the first substrate; -
FIG. 6 is a diagram explaining a second exposure process in a manufacturing process of the first substrate; -
FIG. 7 is a diagram explaining a third exposure process in a manufacturing process of the first substrate; -
FIG. 8 is a diagram explaining the third exposure process; -
FIG. 9 is a diagram explaining the third exposure process; -
FIG. 10 is a diagram explaining a fourth exposure process in a manufacturing process of the first substrate; -
FIG. 11 is a diagram showing another example of a connection structure between a source electrode and a pixel electrode shown inFIG. 3 ; -
FIG. 12 is a plan view of a first substrate of a liquid crystal panel according to a second embodiment of the present invention; -
FIG. 13 is a cross sectional view of the first substrate shown inFIG. 12 , with a cross section along the line XIII-XIII shown inFIG. 12 ; -
FIG. 14 is a cross sectional view of the first substrate shown inFIG. 12 , with a cross section along the line XIV-XIV shown inFIG. 12 ; -
FIG. 15 is a plan view of a first substrate of a liquid crystal panel according to a third embodiment of the present invention; -
FIG. 16 is a cross sectional view of the first substrate shown inFIG. 15 , with a cross section along the line XVI-XVI shown inFIG. 15 ; -
FIG. 17 is a cross sectional view of the first substrate shown inFIG. 15 , with a cross section along the line XVII-XVII shown inFIG. 15 ; -
FIG. 18A is a diagram showing a manufacturing process of a first substrate according to the third embodiment; -
FIG. 18B is a diagram showing a manufacturing process of a first substrate according to the third embodiment; -
FIG. 18C is a diagram showing a manufacturing process of a first substrate according to the third embodiment; -
FIG. 18D is a diagram showing a manufacturing process of a first substrate according to the third embodiment; -
FIG. 19 is a plan view of a first substrate of a liquid crystal panel according to a fourth embodiment of the present invention; -
FIG. 20 is a cross sectional view of the first substrate shown inFIG. 19 , with a cross section along the line XX-XX shown inFIG. 19 ; -
FIG. 21 is a cross sectional view of the first substrate shown inFIG. 19 , with a cross section along the line XXI-XXI shown inFIG. 19 ; -
FIG. 22 is a cross sectional view of a liquid crystal panel according to a fifth embodiment of the present invention, with the cross section same as that along the line shown inFIG. 2 ; -
FIG. 23 is a cross sectional view of the liquid crystal panel according to the fifth embodiment of the present invention, with the cross section same as that along the line IV-IV shown inFIG. 2 ; and -
FIG. 24 is a diagram showing a process forming an additional insulating portion in the fifth embodiment. - In the following, one embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is an exploded perspective view of a liquid crystal display device according to an embodiment of the present invention. - As shown in
FIG. 1 , a liquid crystal display device includes aliquid crystal panel 10. The liquid crystal display device further includes anupper frame 12 and alower frame 14 that together sandwich the outer circumferential edge of theliquid crystal panel 10. Theliquid crystal panel 10 is held by theseframes liquid crystal panel 10, and irradiates light toward the rear surface of theliquid crystal panel 10. -
FIG. 2 is a plan view of a pixel formed on onetransparent substrate 16 constituting theliquid crystal panel 10.FIGS. 3 and 4 are cross sectional views of theliquid crystal panel 10. FIG. - 3 is a cross sectional view with a cross section along the line III-III shown in
FIG. 2 , andFIG. 4 is a cross sectional view with a cross section along the line IV-IV shown inFIG. 2 . - As shown in
FIGS. 3 and 4 , theliquid crystal panel 10 has afirst substrate 16 and asecond substrate 18 opposed to each other. These two substrates are transparent substrates (e.g., a glass substrate). Thefirst substrate 16 and thesecond substrate 18sandwich liquid crystal 20.Polarizers 22 in a crossed-Nicols arrangement are respectively attached on the surface of thefirst substrate 16 opposite from theliquid crystal 20 and on the surface of thesecond substrate 18 opposite from theliquid crystal 20. - A
black matrix 130 is formed on the surface of thesecond substrate 18 toward theliquid crystal 20. Theblack matrix 130 is made of a highly light-shielding material such as resin that contains black pigment and carbon, metal chromium, and nickel. Theblack matrix 130 has a function of preventing light from being irradiated to achannel 53 of athin film transistor 50 formed on thefirst substrate 16. Further, in this example described here, as shown inFIG. 4 , theblack matrix 130 is positioned on adrain line 56 to be described later formed on thefirst substrate 16, being formed along thedrain line 56. - Further,
color filters 100 are formed on the surface of thesecond substrate 18 toward theliquid crystal 20. The color filters 100 are made of colored films in a plurality of colors (e.g., three colors including red, green, and blue). - Further, an
overcoat film 120 is formed on the side of thesecond substrate 18 toward theliquid crystal 20, covering the color filters 100. The surface of thesecond substrate 18 toward theliquid crystal 20 is protected by theovercoat film 120. - The
first substrate 16 will be described. In the description below, the direction in which thefirst substrate 16 faces theliquid crystal 20 is defined as an upper direction. - As shown in
FIGS. 2 and 3 , a plurality of thin film transistors (hereinafter referred to as a TFT) 50 functioning as a switch for controlling theliquid crystal 20 are formed on the surface of thefirst substrate 16 toward the liquid crystal 20 (the upper surface). TheTFT 50 includes achannel 53 formed of a semiconductor layer of amorphous silicon, microcrystal silicon, and so forth, adrain electrode 52, and asource electrode 54. Thedrain electrode 52 and thesource electrode 54 are respectively positioned on the opposite sides to each other across thechannel 53. In this embodiment, one electrode, of the twoelectrodes pixel electrode 70 is refereed as thesource electrode 54, and theother electrode 52 is referred as a drain electrode. - As shown in
FIG. 2 , a plurality ofgate lines 40 connected to the respective TFT's 50 are formed on thefirst substrate 16. In this example, the drain lines 52, thesource electrodes 54, and thechannels 53 are positioned above thegate line 40. Therefore, thegate line 40 includes parts functions as a gate electrode of theTFT 50. A scan signal (a gate voltage) for turning on/off theTFT 50 is applied to thegate line 40. - As shown in
FIG. 4 , a plurality ofdrain lines 56 connected to thedrain electrodes 52 are formed on thefirst substrate 16. A video signal (a voltage signal indicating a grayscale value of each pixel) is applied to thedrain line 56. The plurality ofgate lines 40 and the plurality ofdrain lines 56 are arranged in matrix. That is, the plurality ofgate lines 40 are formed substantially perpendicular to the respective drain lines 56. An area surrounded by twoadjacent gate lines 40 and twoadjacent drain lines 56 constitutes a single pixel, and each pixel is provided with aTFT 50. - The
liquid crystal panel 10 drives theliquid crystal 20 in an in-plane switching mode (that is, IPS mode), and thus thepixel electrode 70 and acommon electrode 80 opposed to thepixel electrode 70 are both formed on thefirst substrate 16. The pixel electrode and thecommon electrode 80 are both made of transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide). - A video signal is applied via the
drain line 56 and theTFT 50 to thepixel electrode 70. Thepixel electrode 70 has a substantially rectangular shape in a plan view, and a size corresponding to a single pixel. - As shown in
FIG. 2 , thecommon electrode 80 includes acommon line 82. In the example described here, as shown inFIG. 4 , thecommon line 82 is positioned above and formed along thedrain line 56. Thecommon line 82 connects parts of thecommon electrode 80 that are opposed to thepixel electrode 70 together. With the above, the substantially same potential is resulted throughout the wholecommon electrode 80. - A plurality of slits are formed on a part of the
common electrode 80 that is opposed to thepixel electrode 70. Specifically, in the example shown inFIG. 2 , each slit is long in the direction along thedrain line 56. Further, each slit is bent midway thereof, and therefore a part thereof on one side (the upper side inFIG. 2 ) and a part of the other side (the lower side inFIG. 2 ) across the midway part are difference from each other in angle relative to a rubbing direction. - The
pixel electrode 70, theTFT 50, and lines connected to the TFT 50 (specifically, thegate line 40 and the drain line 56) are positioned in a lower layer (a layer closer to the first substrate 16) than thecommon electrode 80. In the example described here, as shown inFIG. 3 , thecommon electrode 80 is formed in the uppermost layer (a layer closest to the liquid crystal 20) except an alignment film (not shown) for aligningliquid crystal 20. - As shown in
FIG. 3 , thegate line 40 has a two-layered structure. That is, thegate line 40 has alower gate line 40 a and anupper gate line 40 b. Thelower gate line 40 a is made of transparent conductive material identical to thepixel electrode 70, and positioned in the same layer as thepixel electrode 70. That is, thepixel electrode 70 and thelower gate line 40 a are both positioned on thefirst substrate 16. Theupper gate line 40 b is layered on thelower gate line 40 a. Thelower gate line 40 a is patterned into a shape corresponding to theupper gate line 40 b. The wholeupper gate line 40 b is positioned on thelower gate line 40 a, being in contact with thelower gate line 40 a. Such a two-layered structure of thegate line 40 enables a manufacturing method to be described later. - The
upper gate line 40 b is made of material different from thelower gate line 40 a and thepixel electrode 70. Specifically, theupper gate line 40 b is made of metal having a higher electrical conductivity than the transparent conductive material of which thepixel electrode 70 or the like is made. For example, thegate line 40 b is made of copper, molybdenum, aluminum, or the like. This enables a smaller resistance of thegate line 40 as a whole. - As shown in
FIG. 3 , agate insulating film 42 is formed on and covering the upper side of thegate line 40 and thepixel electrode 70. Thegate insulating film 42 is made of inorganic material such as semiconductor oxide (oxide silicon (SiO2)), nitride semiconductor (silicon nitride (SiNx)) or the like. - As shown in
FIG. 3 , thechannel 53, thesource electrode 54, and thedrain electrode 52 of theTFT 50 are formed above thegate insulating film 42. In this example, thechannel 53 or the like is formed on thegate insulating film 42. - As shown in
FIG. 4 , thedrain line 56 connected to thedrain electrode 52 is formed above thegate insulating film 42. In the above, thedrain line 56 is positioned in the same layer as theelectrodes gate insulating film 42. - As shown in
FIGS. 3 and 4 , thesource electrode 54, thedrain electrode 52, and thedrain line 56 have a two-layered structure including asemiconductor layer 60 for forming thechannel 53 and a conductor layer layered on the semiconductor layer 60 (e.g., a metal layer such as copper, molybdenum, aluminum, and so forth). That is, thesemiconductor layer 60 is patterned into a shape corresponding to thesource electrode 54, thedrain electrode 52, and thedrain line 56. Then, the whole conductor layer forming thesource electrode 54, thedrain electrode 52, and thedrain line 56 is positioned on and in contact with thesemiconductor layer 60. - As shown in
FIGS. 3 and 4 , a protective insulatingfilm 44 is formed on and covering the upper side of thechannel 53, thesource electrode 54, thedrain electrode 52, and thedrain line 56. The protectiveinsulating film 44 is made of inorganic material such as semiconductor oxide (oxide silicon (SiO2)), nitride semiconductor (silicon nitride (SiNx)), and so forth. The protectiveinsulating film 44 prevents humidity contamination of thesemiconductor layer 60. - As shown in
FIG. 4 , thecommon electrode 80 is formed on the protective insulatingfilm 44. Thecommon electrode 80 is formed such that apart thereof is positioned above the drain line 56 (that is, the part covers the drain line 56). In this example, thecommon electrode 80 includes thecommon line 82. Thecommon line 82 is positioned above thedrain line 56 and thus overlaps thedrain line 56 in a plan view. Thecommon line 82 is wider than thedrain line 56. As described above, a video signal according to a grayscale value of each pixel is applied to thedrain line 56. Thecommon line 82 has a function of shielding a noise of electric field due to change of the video signal. Consequently, it is possible to make smaller the width of the black matrix for preventing light transmission due to the noise of electric field. - As shown in
FIG. 3 , a connecting conductor 84 (a connecting line) for connecting thesource electrode 54 and thepixel electrode 70 is formed in the same layer as thecommon electrode 80. In this example, the connectingconductor 84 is formed on the protective insulatingfilm 44, and is connected to thepixel electrode 70 and thesource electrode 54 through contact holes 94, 92, respectively. Thecontact hole 92 is formed above thesource electrode 54 and penetrates the protective insulatingfilm 44. Thecontact hole 94 is formed above thepixel electrode 70 and penetrates thegate insulating film 42 and the protective insulatingfilm 44. The twocontact holes conductor 84 is bridged between the contact holes 92, 94, being connected to thepixel electrode 70 and thesource electrode 54 through the contact holes 94, 92, respectively. Consequently, thesource electrode 54 is electrically connected to thepixel electrode 70. The connectingconductor 84 is made of transparent conductive material identical to thecommon electrode 80. - As shown in
FIG. 2 orFIG. 3 , a connectingpad 32 is formed on thepixel electrode 70. The connectingpad 32 is positioned at the lower end of thecontact hole 94, and in contact with thepixel electrode 70. Thus, the connectingconductor 84 is connected to thepixel electrode 70 through thecontact hole 94 and the connectingpad 32. The connectingpad 32 is made of material having a higher electrical conductivity than the transparent conductive material of which thepixel electrode 70 and thelower gate line 40 a are made. In this example, the connectingpad 32 is made of material identical to theupper gate line 40 b (that is, metal such as copper or molybdenum). With the above, electric connection between the lower end of thecontact hole 94 and thepixel electrode 70 becomes more stabilized. Further, the connectingpad 32 is positioned in the same layer as theupper gate line 40 b. Therefore, the connectingpad 32 can be formed at the same process as theupper gate line 40 b, as to be described later. Incidentally, the connectingpad 32 is slightly larger in size than thecontact hole 94. - A manufacturing method of the
first substrate 16 will be described.FIGS. 5 to 10 are diagrams showing a manufacturing process of thefirst substrate 16. In this embodiment, thefirst substrate 16 is manufactured through four exposure processes.FIG. 5 is a diagram explaining a first exposure process;FIG. 6 is a diagram explaining a second exposure process;FIGS. 7 to 9 are diagrams explaining a third exposure process; andFIG. 10 is a diagram explaining a fourth exposure process. - As shown in 5A in
FIG. 5 , initially, a transparent conductive film (e.g., a film such as indium tin oxide or indium zinc oxide) 79 for forming thepixel electrode 70 and aconductor film 49 for forming theupper gate line 40 b and the connectingpad 32 are layered on thefirst substrate 16. For example, the transparentconductive film 79 is formed on thefirst substrate 16 by means of spattering or vacuum evaporation, and the conductor film 49 (a metal film such as e.g., copper, molybdenum, aluminum, and so forth) having a higher electrical conductivity than the transparentconductive film 79 is formed on the transparentconductive film 79. Thereafter, a resistfilm 99 is formed on theconductor film 49. - Thereafter, as shown in 5B, the resist
film 99 is patterned through an exposure process using a photo mask and a development process, and thereby resistfilms conductor film 49. In the above exposure process, a multiple gradation mask having three levels of light transmissivity, such as a half-tone mask, a gray tone mask, is used as the photo mask, and thereby two resist films having different thickness are formed. Specifically, a thin resistfilm 99A having a pattern corresponding to thepixel electrode 70 and a thick resistfilm 99B, thicker than the thin resistfilm 99A, corresponding to thegate line 40 and the connectingpad 32 are formed. - Thereafter, the
pixel electrode 70 is formed using the thin resistfilm 99A, and thegate line 40 and the connectingpad 32 are formed using the thick resistfilm 99B. Specifically, initially, theconductor film 49 and the transparentconductive film 79 are etched using both of the thin resistfilm 99A and the thick resistfilm 99B as a mask. Consequently, as shown in 5C inFIG. 5 , theconductor film 49 and the transparentconductive film 79 are removed in the absence area of the thin resistfilm 99A and the thick resistfilm 99B. Thereafter, as shown in 5D, the thin resistfilm 99A is removed. At the time of removing the thin resistfilm 99A, the thick resistfilm 99B, being thicker than the thin resistfilm 99A, is left having become thinner. Thereafter, theconductor film 49 is etched using the residual thick resistfilm 99B as a mask, and the thick resistfilm 99B is then completely removed. Consequently, as shown in 5E inFIG. 5 , the above describedgate line 40, the connectingpad 32, and thepixel electrode 70 are formed. That is, thepixel electrode 70 and thelower gate line 40 a are made from the transparentconductive film 79, and theupper gate line 40 b and the connectingpad 32 are made from theconductor film 49. - Thereafter, as shown in
FIG. 6 , thegate insulating film 42 is formed on and covering thegate line 40, thepixel electrode 70, and the connectingpad 32. Thegate insulating film 42 is formed using, e.g., plasma enhanced chemical vapor deposition. - Thereafter, the
channel 53, thesource electrode 54, and thedrain electrode 52 of theTFT 50, and thedrain line 56 are formed on thegate insulating film 42. In this embodiment, a multiple gradation mask is used so that those are formed in one exposure process. - Specifically, the
semiconductor layer 60, an Ohmic layer (not shown), and a conductor film for forming thesource electrode 54, and so forth, are layered on thegate insulating film 42 by means of plasma enhanced chemical vapor deposition or sputtering. Thereafter, a resist film is formed on the conductor film. Then, similar to the method shown in 5C inFIG. 5 , the resist film is patterned utilizing a multiple gradation mask. That is, a thin resist film corresponding to a channel and a thick resist film corresponding to thesource electrode 54, thedrain electrode 52, and thedrain line 56 are formed on the conductor film. Then, using the two resist patterns having different thickness, thechannel 53, thesource electrode 54, thedrain electrode 52, and thedrain line 56 are formed. - Thereafter, as shown in 7A in
FIG. 7 , the protective insulatingfilm 44 is formed on thegate insulating film 42, covering theTFT 50. Thereafter, a resistfilm 98 is layered on the protective insulatingfilm 44. For forming the protective insulatingfilm 44, e.g., plasma enhanced chemical vapor deposition can be employed, similar to forming thegate insulating film 42. - Thereafter, as shown in 7B and 7C, the
contact hole 92 penetrating the protective insulatingfilm 44 and thecontact hole 94 penetrating thegate insulating film 42 and the protective insulatingfilm 44 are formed. Specifically, the resistfilm 98 is patterned through an exposure process and a development process. That is, a pattern (holes 98 a, 98 b) corresponding to the contact holes 92, 94 are formed on the resist film 98 (see 7B). Thereafter, using the thus pattered resistfilm 98 as a mask, the protective insulatingfilm 44 and thegate insulating film 42 are etched, and thereafter, the resistfilm 98 is removed. With the above, the contact holes 92, 94 are resulted (see 7C). - A terminal of the
gate line 40 and a terminal of thedrain line 56 are positioned on the outer circumferential part of thefirst substrate 16. On the outer circumferential part of thefirst substrate 16, an opening is formed on thegate insulating film 42 and the protective insulatingfilm 44, and the terminal of thegate line 40 is connected through the opening to a driving circuit for applying a scan signal to thegate line 40. Further, the terminal of thedrain line 56 is connected through the opening to a driving circuit for applying a video signal to thedrain line 56. The opening for connection between the terminal of thegate line 40 and the driving circuit and the opening for connection between the terminal of thedrain line 56 and the driving circuit are formed at the same time as the contact holes 92, 94 shown inFIG. 7 . -
FIG. 8 is a cross sectional view of a terminal of thegate line 40. The cross sections shown in 8A, 8B, and 8C inFIG. 8 correspond to the respective processes shown in 7A, 7B, and C7 inFIG. 7 .FIG. 9 is a cross sectional view of a terminal of thedrain line 56. The cross sections shown in 9A, 9B, and 9C inFIG. 9 correspond to the respective processes shown in 7A, 7B, and 7C inFIG. 7 . - As shown in 8A in
FIG. 8 , thegate insulating film 42, the protective insulatingfilm 44, and the resistfilm 98 are layered on a terminal of thegate line 40. As shown in 9A inFIG. 9 , thedrain line 56 is formed on thegate insulating film 42, and a terminal of thedrain line 56 is covered by the protective insulatingfilm 44 and the resistfilm 98. - Thereafter, as shown in 8B in
FIGS. 8 and 9B inFIG. 9 , the resistfilm 98 is patterned through the exposure process and the development process. That is,openings film 98 are formed on the terminal of thegate line 40 and the terminal of thedrain line 56, respectively. Then, using the patterned resistfilm 98 as a mask, the protective insulatingfilm 44 and thegate insulating film 42 are etched. Consequently, as shown in 8C and 9C, theopenings gate line 40 and of thedrain line 56. These terminals are connected to the respective driving circuits through therespective openings common electrode 80 is supplied also to theopenings respective lines respective openings - After the protective insulating
film 44 and thegate insulating film 42 are etched in the process shown inFIG. 7 ,FIG. 8 andFIG. 9 , thecommon electrode 80 and the connectingconductor 84 are formed on the protective insulatingfilm 44. Specifically, as shown in 10A inFIG. 10 , a transparentconductive film 89 is formed on the protective insulatingfilm 44. The formation of the transparentconductive film 89 is carried out using, e.g., spattering. Thereafter, a resistfilm 97 is formed on the transparentconductive film 89, and then patterned through an exposure process and a development process. That is, the resistfilm 97 is formed into a pattern corresponding to thecommon electrode 80 and the connectingconductor 84. Thereafter, using the patterned resistfilm 97 as a mask, the transparentconductive film 89 is etched. Consequently, as shown in 10B, thecommon electrode 80 and the connectingconductor 84 are formed on the protective insulatingfilm 44. Note that, in this process, a transparent conductive film is supplied also to theopenings openings first substrate 16. - In the above described
liquid crystal panel 10, thegate line 40 is made of material identical to thepixel electrode 70 and has a two-layered structure containing thelower gate line 40 a positioned in the same layer as thepixel electrode 70, and theupper gate line 40 b layered on thelower gate line 40 a and made of material having a higher electrical conductivity than the transparent conductive material of which thepixel electrode 70 is made. Therefore, it is possible to form both of thegate line 40 and thepixel electrode 70 at one exposure process. - In the
liquid crystal panel 10, in particular, the connectingconductor 84 connected to thesource electrode 54 of theTFT 50 and thepixel electrode 70 through the contact holes 92, 94, respectively, is made of material identical to thecommon electrode 80 and formed in the same layer as thecommon electrode 80. With the above, the connectingconductor 84 can be formed at the same process as thecommon electrode 80. Consequently, it is possible to prevent increase of the number of manufacturing processes for the connectingconductor 84. - Note that in the above-described example, the connecting
conductor 84 is connected to thesource electrode 54 and thepixel electrode 70 through the twocontact holes conductor 84 may be connected to thesource electrode 54 and thepixel electrode 70 via a single contact hole.FIG. 11 is across sectional view showing another example of a structure for connection between thesource electrode 54 and thepixel electrode 70, showing the same cross section as that shown inFIG. 3 . Note that a member identical to that which is described above is given an identical reference numeral. - In this example, the
source electrode 54 extends toward thepixel electrode 70, exceeding the edge of thegate line 40. Anend part 54′ of thesource electrode 54 is positioned above the pixel electrode 70 (on the connectingpad 32 in this example), overlapping a part of the connectingpad 32 in a plan view. Acontact hole 94′ is formed in and penetrating the protective insulatingfilm 44 and thegate insulating film 42. Onecontact hole 94′ is formed such that theend part 54′ of thesource electrode 54 and a part of the connectingpad 32 are exposed. That is, theend part 54′ of thesource electrode 54 and the part of the connectingpad 32 are positioned inside thecontact hole 94′. A connecting conductor (connection electrode) 84′ connects theend part 54′ of thesource electrode 54 and the pixel electrode 70 (the connectingpad 32 in this example) together inside thecontact hole 94′. As such a connectingconductor 84′ is shorter, compared to the above described connectingconductor 84, the aperture ratio of each pixel can be improved. Note that the connectingconductor 84′ as well is made of material identical to thecommon electrode 80, similar to the connectingconductor 84. The connectingconductor 84′ can be formed at the same time as when thecommon electrode 80 is formed at the process shown inFIG. 10 . Further, thesource electrode 54′ can be formed at the same time as thesource electrode 54 at the process described with reference toFIG. 6 . -
FIG. 12 is a plan view of a first substrate of aliquid crystal panel 110 according to a second embodiment of the present invention.FIGS. 13 and 14 are cross sectional views of theliquid crystal panel 110 in this embodiment, showing cross sections along the line XIII-XIII and the line XIV-XIV, respectively, inFIG. 12 . Note that a part identical to that which is described above is given an identical reference numeral in the respective diagrams. - In this embodiment, a
common electrode 180 made of transparent conductive material is formed on the protective insulatingfilm 44. In this example as well, slits are formed on thecommon electrode 180, but having a different shape from that of thecommon electrode 80 described above. That is, the slits on thecommon electrode 180 are formed diagonally extending from onecommon line 182 to anothercommon line 182. A plurality of slits are formed symmetrical to each other about the central line C of each pixel. - Further, as shown in
FIG. 13 , thecommon line 182 in this example is formed along thedrain line 56, but not covering thedrain line 56. With the above, the capacitance between thedrain line 56 and thecommon electrode 80 can be reduced. Consequently, it is possible to reduce delay in transmission of a video signal through thedrain line 56. - As shown in
FIG. 14 , an auxiliarycommon line 183 is formed in a layer lower than thecommon electrode 180. The auxiliarycommon line 183 is formed in the same layer as thegate line 40 and thepixel electrode 70. That is, the auxiliarycommon line 183 is formed on thefirst substrate 16. Also, the auxiliarycommon line 183 is formed along thegate line 40. In other words, the auxiliarycommon line 183 is formed parallel to thegate line 40. Further, the auxiliarycommon line 183 is positioned closer to one of the two adjacent gate lines 40. - Similar to the
gate line 40 described above, the auxiliarycommon line 183 has a two-layered structure. Specifically, the auxiliarycommon line 183 includes a lowerauxiliary line 183 a made of transparent conductive material identical to thepixel electrode 70 and thelower gate line 40 a, and an upperauxiliary line 183 b layered on the lowerauxiliary line 183 a and made of material identical to theupper gate line 40 b. That is, the upperauxiliary line 183 b is made of material having a higher electrical conductivity than the transparent conductive material. - The auxiliary
common line 183 is electrically connected to thecommon electrode 180. This can reduce resistance of thecommon electrode 180. In this example, as shown inFIG. 14 , acontact hole 195 is formed in thegate insulating film 42 and the protective insulatingfilm 44. The auxiliarycommon line 183 is electrically connected to thecommon electrode 180 through thecontact hole 195. - Such an auxiliary
common line 183 can be formed at the same process as thepixel electrode 70 and thegate line 40, as shown inFIG. 5 . That is, after the transparentconductive film 79, theconductor film 49, and the resistfilm 99 are layered on the first substrate 16 (5A inFIG. 5 ), the thin resistfilm 99A having a pattern corresponding to the shape of thegate line 40 and the auxiliarycommon line 183 and the thick resistfilm 99B having a pattern corresponding to thepixel electrode 70 are formed, using a multiple gradation mask. With the above, the auxiliarycommon line 183 can be formed without increasing the number of exposure processes. - Further, the
contact hole 195 is formed at a process at which the contact holes 92, 94 shown inFIG. 7 are formed. That is, a resist film having a pattern corresponding to the contact holes 92, 94, 195 is formed on the protective insulating film 44 (see 7B inFIG. 7 ). Then, after the protective insulatingfilm 44 and thegate insulating film 42 are etched, the resist film is removed. Through the above process, the contact holes 92, 94, 195 are formed. Other processes are similar to those in the first embodiment. -
FIG. 15 is a plan view of a first substrate of aliquid crystal panel 210 according to a third embodiment.FIGS. 16 and 17 are cross sectional views of theliquid crystal panel 210 in this embodiment, showing cross sections along the line XVI-XVI and the line XVII-XVII respectively inFIG. 15 . Note that a member identical to that which is described above is given an identical reference numeral in the respective diagrams. - As shown in
FIGS. 15 and 16 , an auxiliarycommon line 283 is formed on thecommon electrode 80. The auxiliarycommon line 283 is made of material having a higher electrical conductivity than the transparent conductive material of which thecommon electrode 80 is made. Specifically, the auxiliarycommon line 283 is made of metal such as copper, molybdenum, aluminum. Therefore, the resistance of thecommon electrode 80 can be reduced. - Further, in this example, the auxiliary
common line 283 is formed along thecommon line 82, being layered on thecommon line 82. Thecommon line 82 is formed above thedrain line 56 made of metal such as copper or the like. Thus, the auxiliarycommon line 283 can not invite drop of the aperture ratio of each pixel. - As shown in
FIG. 17 , theauxiliary connecting conductor 284 is layered on the connectingconductor 84. The auxiliary connectingconductor 284 is made of material having a higher electrical conductivity than the transparent conductive material of which thecommon electrode 80 and the connectingconductor 84 are made. Specifically, similar to the auxiliarycommon line 283, theauxiliary connecting conductor 284 is made of metal such as copper, molybdenum, aluminum, and so forth. The auxiliary connectingconductor 284 can reduce resistance of the connectingconductor 84. - A manufacturing method of a first substrate according to a third embodiment will be described. The manufacturing method of the
first substrate 16 in this embodiment is substantially identical to that for forming thefirst substrate 16 of theliquid crystal panel 10 according to the first embodiment, but differs in the fourth exposure process shown inFIG. 10 .FIGS. 18A to 18D are diagrams showing the fourth exposure process in manufacturing the first substrate according to the third embodiment. InFIGS. 18A to 18D , (a) is a cross sectional view showing a cross section along the line XVI-XVI shown inFIG. 15 , and (b) is a cross sectional view showing a cross section along the line XVII-XVII shown inFIG. 15 . - In this embodiment, a multiple gradation mask is used in forming the
common electrode 80 and the connectingconductor 84 as well. Therefore, theauxiliary connecting conductor 284 and the auxiliarycommon line 283 can be formed without increasing the number of exposure processes. Specifically, as shown inFIG. 18A , the transparentconductive film 89 and aconductor film 289 for forming the auxiliarycommon line 283 and the auxiliary connectingconductor 284 are layered on the protective insulatingfilm 44, and the resistfilm 97 is further formed on theconductor film 289. - Thereafter, as shown in
FIG. 18B , the resistfilm 97 is patterned through an exposure process using a multiple gradation mask and a development process, whereby resistfilms conductor film 289. That is, the thin resistfilm 97A having a pattern corresponding to the shape of thecommon electrode 80 and the thick resistfilm 97B having a pattern corresponding to the shape of the auxiliarycommon line 283 and the auxiliary connectingconductor 284 are formed. In the above, the thick resistfilm 97B is thicker than the thin resistfilm 97A. - Thereafter, as shown in
FIG. 18C , theconductor film 289 and the transparentconductive film 89 are etched using both of the thin resistfilm 97A and the thick resistfilm 97B as a mask. Thereafter, as shown inFIG. 18D , the thin resistfilm 97A is removed. As a result of the removing process, the thick resistfilm 97B is left having become thinner. Thereafter, theconductor film 289 is etched using the residual thick resistfilm 97B as a mask, and thereafter, the thick resistfilm 97B is completely removed. As a result, the auxiliarycommon line 283 and the auxiliary connectingconductor 284 shown inFIGS. 15 and 16 are formed. Other processes are similar to those in the first embodiment. -
FIG. 19 is a plan view of a first substrate of aliquid crystal panel 310 according to a fourth embodiment of the present invention.FIGS. 20 and 21 are cross sectional views of theliquid crystal panel 310 in this embodiment, showing cross sections along the line XX-XX and the line XXI-XXI, respectively, inFIG. 19 . - As shown in
FIGS. 19 and 20 , in this embodiment, an auxiliarycommon line 383 is formed in the same layer as thedrain line 56. The auxiliarycommon line 383 is formed along thedrain line 56. Specifically, the auxiliarycommon line 383 is formed parallel to thedrain line 56 and closer to one of the two adjacent drain lines 56. - As shown in
FIG. 20 , thecommon line 382 is positioned above and covering the auxiliarycommon line 383 and thedrain line 56. That is, thecommon line 382 is formed along the auxiliarycommon line 383 and thedrain line 56, overlapping these lines in a plan view. - As shown in
FIG. 21 , the auxiliarycommon line 383 is connected to thecommon electrode 380 through thecontact hole 395 formed in the protective insulatingfilm 44. Specifically, the auxiliarycommon line 383 includes aconnection part 383 a, and thecontact hole 395 is formed on theconnection part 383 a. In this example, theconnection part 383 a projects from the auxiliarycommon line 383 in the direction along thegate line 40 to be positioned on thegate line 40. With this arrangement, drop of the aperture ratio of each pixel due to theconnection part 383 a can be prevented. Note that such aconnection part 383 a projecting from the auxiliarycommon line 383 may not be provided. That is, thecontact hole 395 may be formed on the auxiliarycommon line 383. - Similar to the
drain line 56, the auxiliarycommon line 383 as well has a two-layered structure containing thesemiconductor layer 60 and a conductor layer layered on thesemiconductor layer 60. That is, in this embodiment, thesemiconductor layer 60 is patterned into a shape corresponding to thesource electrode 54, thedrain electrode 52, thedrain line 56, and the auxiliarycommon line 383. - Such an auxiliary
common line 383 can be formed at the process at which thedrain line 56 is formed, without increasing the number of exposure processes. Specifically, at the process described with reference toFIG. 6 , thesemiconductor layer 60 and a conductor film for forming thedrain line 56, the auxiliarycommon line 383 and so forth are layered on thegate insulating film 42. Thereafter, a resist film is formed on the conductor film. Then, the resist film is patterned through an exposure process using a multiple gradation mask and a development process. That is, a thin resist film having a pattern corresponding to thechannel 53 and a thick resist film having a pattern corresponding to a part having a two-layered structure, such as thedrain line 56, the auxiliarycommon line 383 and so forth, are formed on the conductor film. Then, thechannel 53, thesource electrode 54, thedrain electrode 52, thedrain line 56, and the auxiliarycommon line 383 are formed using the thin resist film and the thick resist film. - Further, the
contact hole 395 is formed at the process at which the contact holes 92, 94 shown inFIG. 7 are formed. That is, a resist film having a pattern corresponding to the contact holes 92, 94, 395 is formed on the protective insulating film 44 (see 7B inFIG. 7 ). Then, after the protective insulatingfilm 44 and thegate insulating film 42 are etched, the patterned resist film is removed. With those processes, the contact holes 92, 94, 395 are formed. Other processes are similar to those in the first embodiment. -
FIGS. 22 and 23 are cross sectional views of aliquid crystal panel 410 according to a fifth embodiment of the present invention. The cross section shown inFIG. 22 is the same as the cross section along the line III-III shown inFIG. 2 . The cross section shown inFIG. 23 is the same as the cross section along the line IV-IV shown inFIG. 2 . - In this embodiment, similar to the first embodiment, the
common electrode 80 is formed such that it is partially positioned above thedrain line 56. Specifically, thecommon line 82 formed integral with thecommon electrode 80 is positioned above thedrain line 56. In this embodiment, an additional insulatingportion 445 is formed between thecommon line 82 and thedrain line 56. The additional insulatingportion 445 is formed along thecommon line 82 and thedrain line 56, and on the protective insulatingfilm 44. That is, the additional insulatingportion 445 is formed only between thecommon line 82 and thedrain line 56, but not in other parts. With this structure, drop of a light transmissivity due to the additional insulatingportion 445 can be prevented. - The additional insulating
portion 445 is made of material having a lower dielectric constant than the protective insulatingfilm 44. For example, in the case where SiO2 or SiNx is used for the protective insulatingfilm 44, an organic material having a relative dielectric constant equal to 4 or smaller is used for the additional insulatingportion 445. - In this embodiment, the additional insulating
portion 445 is made of material (e.g., photosensitivity acrylic resin) that can function as a resist film in an etching process for the protective insulatingfilm 44. As a result, the additional insulatingportion 445 can be formed on the protective insulatingfilm 44 without increasing the number of exposure processes. -
FIG. 24 is a diagram showing a process of forming the additional insulatingportion 445. Note that the respective processes shown in 24A, 24B, and 24C inFIG. 24 correspond to the respective processes shown in 7A, 7B, and 7C inFIG. 7 . Below, a process different from the manufacturing process according to the first embodiment will be mainly described. - Initially, the protective insulating
film 44 and a resist film 449 for forming the additional insulatingportion 445 are formed on thegate insulating film 42 so as to cover theTFT 50. Thereafter, as shown in 24A inFIG. 24 , the resist film 449 is patterned through an exposure process and a development process. At the exposure process, two resist films having different thickness that are patterned using a multiple gradation mask are formed on the protective insulatingfilm 44. That is, a thin resistfilm 449A having the contact holes 92, 94 and theopenings FIGS. 8 and 9 ) formed on the terminals of the gate lines 40, 56 and a thick resistfilm 449B having a shape corresponding to the additional insulatingportion 445 are formed. The thick resistfilm 449B is positioned above and formed along thedrain line 56. - Thereafter, as shown in 24B, the protective insulating
film 44 and thegate insulating film 42 are etched to thereby form the contact holes 92, 94 and theopenings - Thereafter, as shown in 24C, the thin resist
film 449A is removed. In this removing process, the thick resistfilm 449B becomes thinner as a result that the thick resistfilm 449B is soaked in a remover solution used in this process. Then, the residual thick resistfilm 449B constitutes the additional insulatingportion 445. Thereafter, thecommon line 82 is formed on the additional insulatingportion 445 through the process shown inFIG. 10 . - While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention.
Claims (8)
1-17. (canceled)
18. A liquid crystal panel comprising:
a first substrate,
a second substrate,
a liquid crystal material sandwiched therebetween,
a pixel electrode formed on the first substrate and made of a transparent conductive material,
a gate line formed on the first substrate and connected to a gate electrode of a thin film transistor,
a first insulating layer covering the gate line and the pixel electrode,
a semiconductor layer, a source electrode and a drain electrode of the thin film transistor formed on the first insulating layer,
a second insulating layer covering the source electrode and the drain electrode of the thin film transistor and the first insulating layer,
a common electrode formed on the second insulating layer and made of the transparent conductive material,
a first contact hole and a second contact hole penetrating to both the first insulating layer and the second insulating layer,
the pixel electrode is electrically connected to the source electrode of the thin film transistor through the first contact with a connecting conductor, and
a common line includes a transparent conductive layer positioned in a same layer as the pixel electrode and is electrically connected to the common electrode through the second contact hole.
19. A liquid crystal panel of claim 18 wherein, the common line is formed in parallel with the gate line.
20. A liquid crystal panel of claim 18 wherein,
the gate line and the common line have two-layered structure that comprises a lower line made of the same material as the pixel electrode and positioned in a same layer with the pixel electrode, and an upper line layered on the lower line and made of material having a higher electrical conductivity than the lower line.
21. A liquid crystal panel of claim 18 wherein,
the connecting conductor is made of a material identical to the common electrode.
22. The liquid crystal panel of claim 18 , wherein the source electrode overlaps the pixel electrode in a plan view.
23. The liquid crystal panel of claim 18 , wherein an end part of the source electrode is exposed from the second insulator and is connected to the connecting conductor.
24. The liquid crystal panel of claim 18 , wherein at least part of the connecting conductor is positioned in a same layer with the common electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/439,434 US20170160618A1 (en) | 2010-11-30 | 2017-02-22 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010-266443 | 2010-11-30 | ||
JP2010266443A JP2012118199A (en) | 2010-11-30 | 2010-11-30 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US13/306,416 US8917370B2 (en) | 2010-11-30 | 2011-11-29 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/543,363 US9563090B2 (en) | 2010-11-30 | 2014-11-17 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/611,864 US9201277B2 (en) | 2010-11-30 | 2015-02-02 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/922,865 US9612493B2 (en) | 2010-11-30 | 2015-10-26 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US15/439,434 US20170160618A1 (en) | 2010-11-30 | 2017-02-22 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/922,865 Continuation US9612493B2 (en) | 2010-11-30 | 2015-10-26 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170160618A1 true US20170160618A1 (en) | 2017-06-08 |
Family
ID=46126408
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/306,416 Active 2032-08-01 US8917370B2 (en) | 2010-11-30 | 2011-11-29 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/543,363 Active US9563090B2 (en) | 2010-11-30 | 2014-11-17 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/611,864 Active US9201277B2 (en) | 2010-11-30 | 2015-02-02 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/922,865 Active US9612493B2 (en) | 2010-11-30 | 2015-10-26 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US15/439,434 Abandoned US20170160618A1 (en) | 2010-11-30 | 2017-02-22 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/306,416 Active 2032-08-01 US8917370B2 (en) | 2010-11-30 | 2011-11-29 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/543,363 Active US9563090B2 (en) | 2010-11-30 | 2014-11-17 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/611,864 Active US9201277B2 (en) | 2010-11-30 | 2015-02-02 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
US14/922,865 Active US9612493B2 (en) | 2010-11-30 | 2015-10-26 | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
Country Status (3)
Country | Link |
---|---|
US (5) | US8917370B2 (en) |
JP (1) | JP2012118199A (en) |
CN (2) | CN102566185B (en) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012118199A (en) * | 2010-11-30 | 2012-06-21 | Panasonic Liquid Crystal Display Co Ltd | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
CN102645803B (en) * | 2011-10-17 | 2014-06-18 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, liquid crystal panel, display device and manufacturing methods thereof |
JP5546525B2 (en) * | 2011-12-13 | 2014-07-09 | 株式会社ジャパンディスプレイ | Liquid crystal display |
JP2014021449A (en) * | 2012-07-23 | 2014-02-03 | Panasonic Liquid Crystal Display Co Ltd | Liquid crystal display device and manufacturing method of liquid crystal display device |
JP6050985B2 (en) * | 2012-08-23 | 2016-12-21 | 株式会社ジャパンディスプレイ | Liquid crystal display |
WO2014038482A1 (en) * | 2012-09-05 | 2014-03-13 | シャープ株式会社 | Semiconductor device and method for producing same |
TWI468826B (en) * | 2012-10-08 | 2015-01-11 | Au Optronics Corp | Pixel array substrate |
KR20140064112A (en) * | 2012-11-19 | 2014-05-28 | 삼성디스플레이 주식회사 | Liquid crystal display device |
JP2014126674A (en) | 2012-12-26 | 2014-07-07 | Japan Display Inc | Liquid crystal display device |
JP2014228565A (en) * | 2013-05-17 | 2014-12-08 | パナソニック液晶ディスプレイ株式会社 | Liquid crystal display device and manufacturing method of liquid crystal display device |
JP2015012048A (en) | 2013-06-27 | 2015-01-19 | 三菱電機株式会社 | Active matrix substrate and method for manufacturing the same |
JP6315966B2 (en) * | 2013-12-11 | 2018-04-25 | 三菱電機株式会社 | Active matrix substrate and manufacturing method thereof |
KR102065764B1 (en) | 2013-12-31 | 2020-03-03 | 삼성디스플레이 주식회사 | Thin film transistor array panel |
JP6334179B2 (en) * | 2014-01-23 | 2018-05-30 | 株式会社ジャパンディスプレイ | Display device |
KR20160003357A (en) | 2014-06-30 | 2016-01-11 | 삼성디스플레이 주식회사 | Liquid crystal dislplay and method of manufacturing the same |
JP2016024304A (en) * | 2014-07-18 | 2016-02-08 | 株式会社ジャパンディスプレイ | Display device |
JP6497876B2 (en) | 2014-09-01 | 2019-04-10 | 三菱電機株式会社 | Liquid crystal display panel and manufacturing method thereof |
KR20160043575A (en) | 2014-10-13 | 2016-04-22 | 삼성디스플레이 주식회사 | Liquid crystal display and manufacturing method thereof |
US10146084B2 (en) * | 2014-10-24 | 2018-12-04 | Lg Display Co., Ltd. | Display device |
KR102467215B1 (en) * | 2014-10-24 | 2022-11-16 | 엘지디스플레이 주식회사 | Display Device |
US20160178978A1 (en) * | 2014-12-22 | 2016-06-23 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | FFS Mode Array Substrate and LCD Panel |
WO2017002144A1 (en) * | 2015-06-29 | 2017-01-05 | パナソニック液晶ディスプレイ株式会社 | Liquid crystal display device and method for manufacturing same |
KR102381082B1 (en) * | 2015-07-31 | 2022-03-30 | 엘지디스플레이 주식회사 | Liquid crystal display apparatus |
CN105742293A (en) * | 2016-03-01 | 2016-07-06 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor |
TWI597830B (en) * | 2016-05-13 | 2017-09-01 | 群創光電股份有限公司 | Display device |
CN107068691B (en) * | 2017-03-28 | 2020-10-23 | 上海天马微电子有限公司 | Array substrate and manufacturing method thereof |
CN107845644B (en) * | 2017-09-27 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
CN108594547B (en) * | 2018-05-02 | 2021-08-10 | 京东方科技集团股份有限公司 | Pixel structure, manufacturing method thereof, array substrate and display device |
CN111103734A (en) | 2018-10-25 | 2020-05-05 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
CN109752891B (en) | 2019-01-14 | 2021-03-19 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6710835B2 (en) * | 2001-01-29 | 2004-03-23 | Hitachi, Ltd. | Liquid crystal display device with stacked insulating film of different layers |
US7782435B2 (en) * | 2007-04-30 | 2010-08-24 | Lg Display Co., Ltd. | Liquid crystal display panel and method for manufacturing the same |
US7859639B2 (en) * | 2004-12-24 | 2010-12-28 | Lg Display Co., Ltd. | Liquid crystal display device and fabricating method thereof using three mask process |
US8933460B2 (en) * | 2010-06-22 | 2015-01-13 | Lg Display Co., Ltd. | Array substrate for fringe field switching mode liquid crystal display device |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100477130B1 (en) | 1997-09-25 | 2005-08-29 | 삼성전자주식회사 | Thin Film Transistor Board and Manufacturing Method of Flat Drive Liquid Crystal Display |
KR100881357B1 (en) | 1999-09-07 | 2009-02-02 | 가부시키가이샤 히타치세이사쿠쇼 | Liquid crystal display |
JP3793915B2 (en) * | 2001-02-28 | 2006-07-05 | 株式会社日立製作所 | Liquid crystal display |
JP2003017706A (en) * | 2001-07-02 | 2003-01-17 | Idemitsu Kosan Co Ltd | Tft substrate, liquid crystal display device using the same, and its manufacturing method |
JP3891846B2 (en) * | 2002-01-15 | 2007-03-14 | 株式会社日立製作所 | Liquid crystal display |
JP4241238B2 (en) * | 2003-08-29 | 2009-03-18 | 株式会社 日立ディスプレイズ | Liquid crystal display |
KR101125254B1 (en) * | 2004-12-31 | 2012-03-21 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate of Fringe Field Switching Type And Fabricating Method Thereof, Liquid Crystal Display Panel Using The Same And Fabricating Method Thereof |
KR101225440B1 (en) * | 2005-06-30 | 2013-01-25 | 엘지디스플레이 주식회사 | Liquid crystal display and fabricating method thereof |
JP2007310334A (en) * | 2006-05-19 | 2007-11-29 | Mikuni Denshi Kk | Manufacturing method of liquid crystal display device using half-tone exposure method |
KR20070112954A (en) * | 2006-05-24 | 2007-11-28 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and method for fabricating the same |
JP5061505B2 (en) * | 2006-05-25 | 2012-10-31 | 日本電気株式会社 | Horizontal electric field type active matrix liquid crystal display device |
CN100580936C (en) * | 2006-10-04 | 2010-01-13 | 三菱电机株式会社 | Display device and method of manufacturing the same |
TWI414864B (en) * | 2007-02-05 | 2013-11-11 | Hydis Tech Co Ltd | Fringe field switching mode lcd |
JP5212683B2 (en) * | 2007-03-20 | 2013-06-19 | カシオ計算機株式会社 | Transistor panel and manufacturing method thereof |
JP4496237B2 (en) * | 2007-05-14 | 2010-07-07 | 株式会社 日立ディスプレイズ | Liquid crystal display |
DE102008058709B4 (en) * | 2008-06-25 | 2014-06-26 | Lg Display Co., Ltd. | A fringe field switching mode liquid crystal display device array substrate and a fringe field switching mode liquid crystal display device having the same |
JP5348521B2 (en) * | 2008-06-27 | 2013-11-20 | 株式会社ジャパンディスプレイ | LCD panel |
JP2010060967A (en) * | 2008-09-05 | 2010-03-18 | Epson Imaging Devices Corp | Liquid crystal display device and electronic apparatus |
KR101225444B1 (en) * | 2009-12-08 | 2013-01-22 | 엘지디스플레이 주식회사 | Liquid crystal display device and Method for manufacturing the same and Method for Repairing the same |
JP2012118199A (en) | 2010-11-30 | 2012-06-21 | Panasonic Liquid Crystal Display Co Ltd | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
-
2010
- 2010-11-30 JP JP2010266443A patent/JP2012118199A/en active Pending
-
2011
- 2011-11-29 CN CN201110397236.XA patent/CN102566185B/en active Active
- 2011-11-29 US US13/306,416 patent/US8917370B2/en active Active
- 2011-11-29 CN CN201610109957.9A patent/CN105589271A/en active Pending
-
2014
- 2014-11-17 US US14/543,363 patent/US9563090B2/en active Active
-
2015
- 2015-02-02 US US14/611,864 patent/US9201277B2/en active Active
- 2015-10-26 US US14/922,865 patent/US9612493B2/en active Active
-
2017
- 2017-02-22 US US15/439,434 patent/US20170160618A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6710835B2 (en) * | 2001-01-29 | 2004-03-23 | Hitachi, Ltd. | Liquid crystal display device with stacked insulating film of different layers |
US7859639B2 (en) * | 2004-12-24 | 2010-12-28 | Lg Display Co., Ltd. | Liquid crystal display device and fabricating method thereof using three mask process |
US7782435B2 (en) * | 2007-04-30 | 2010-08-24 | Lg Display Co., Ltd. | Liquid crystal display panel and method for manufacturing the same |
US8933460B2 (en) * | 2010-06-22 | 2015-01-13 | Lg Display Co., Ltd. | Array substrate for fringe field switching mode liquid crystal display device |
Also Published As
Publication number | Publication date |
---|---|
US8917370B2 (en) | 2014-12-23 |
US20150146128A1 (en) | 2015-05-28 |
US9612493B2 (en) | 2017-04-04 |
US20150070619A1 (en) | 2015-03-12 |
US20120133856A1 (en) | 2012-05-31 |
US9201277B2 (en) | 2015-12-01 |
CN105589271A (en) | 2016-05-18 |
US9563090B2 (en) | 2017-02-07 |
US20160048065A1 (en) | 2016-02-18 |
CN102566185B (en) | 2016-03-16 |
CN102566185A (en) | 2012-07-11 |
JP2012118199A (en) | 2012-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9612493B2 (en) | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof | |
KR101225440B1 (en) | Liquid crystal display and fabricating method thereof | |
JP4772200B2 (en) | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof | |
JP5351388B2 (en) | Display device | |
US7876390B2 (en) | Liquid crystal display fabrication method | |
JP5280988B2 (en) | Manufacturing method of liquid crystal display device | |
KR100841379B1 (en) | Electro-optic display and manufacturing method thereof | |
KR101137861B1 (en) | Thin film transister of fringe field switching type and fabricating method thereof | |
KR101522241B1 (en) | Liquid crystal display device controllable viewing angle and method of fabricating the same | |
CN109599362B (en) | Method for manufacturing thin film transistor substrate and thin film transistor substrate | |
KR20160028587A (en) | Thin film transistor array substrate, method for manufacturing the same and liquid crystal display comprising the same | |
EP1939674B1 (en) | Liquid crystal display device and fabrication method thereof | |
US20070090403A1 (en) | Array substrate and method of manufacturing the same | |
KR101898624B1 (en) | Fringe field switching liquid crystal display device and method of fabricating the same | |
KR101887691B1 (en) | Method of fabricating fringe field switching liquid crystal display device | |
US20080191211A1 (en) | Thin film transistor array substrate, method of manufacturing the same, and display device | |
KR20080011016A (en) | Liquid crystal display device | |
CN108701432B (en) | Method for manufacturing substrate for display panel | |
JPH0682830A (en) | Active matrix liquid crystal display device and its production | |
KR101215943B1 (en) | The array substrate for liquid crystal display device and method of fabricating the same | |
KR100695298B1 (en) | Thin film transistor array panel for liquid crystal display and manufacturing method of the same | |
JP2008032855A (en) | Liquid crystal display | |
KR101255273B1 (en) | Liquid crystal display device and the method for manufacturing the same | |
KR102093903B1 (en) | Thin film transistor array panel and manufacturing method thereof | |
KR100720096B1 (en) | thin film transistor array panel for liquid crystal display and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |