US20170147362A1 - Stand-by mode of an electronic circuit - Google Patents

Stand-by mode of an electronic circuit Download PDF

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Publication number
US20170147362A1
US20170147362A1 US15/153,118 US201615153118A US2017147362A1 US 20170147362 A1 US20170147362 A1 US 20170147362A1 US 201615153118 A US201615153118 A US 201615153118A US 2017147362 A1 US2017147362 A1 US 2017147362A1
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US
United States
Prior art keywords
circuit
power supply
microcontroller
logic
signal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/153,118
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English (en)
Inventor
Nicolas Froidevaux
Jean-Michel Gril-Maffre
Jean-Pierre Leca
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STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
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Filing date
Publication date
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Assigned to STMICROELECTRONICS (ROUSSET) SAS reassignment STMICROELECTRONICS (ROUSSET) SAS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FROIDEVAUX, NICOLAS, GRIL-MAFFRE, JEAN-MICHEL, LECA, Jean-Pierre
Publication of US20170147362A1 publication Critical patent/US20170147362A1/en
Priority to US16/026,233 priority Critical patent/US10719331B2/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/442—Shutdown
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure generally relates to electronic circuits and, more specifically, to the stand-by mode of a microcontroller.
  • the electric power consumption of an electronic circuit is desired to be minimized when the electronic circuit is not used. Stand-by mechanisms, which enable to decrease the circuit power consumption, are thus provided.
  • the microcontroller In electronic circuits comprising a microcontroller, the microcontroller generally integrates stand-by functions enabling to set its core to stand-by mode during periods when it is not used. During such stand-by periods, other circuits of the microcontroller monitor the microcontroller inputs-outputs to detect a need to wake the core.
  • An embodiment overcomes all or part of the disadvantages of usual circuits for setting a microcontroller to stand-by mode.
  • An embodiment provides a solution which is easy to implement.
  • an embodiment provides a microcontroller comprising: a core; a circuit for managing the core power supply, comprising at least one input for receiving an external signal for leaving a stand-by mode; and a signal intercepting circuit configured to intercept said external signal and transmit it with a delay to said circuit for managing.
  • said circuit for managing comprises a logic function for storing said input signal.
  • said logic function is reset by the circuit for managing at the end of said delay.
  • said signal intercepting circuit receives the output of said logic function and combines it with data representative of the power supply voltage of the microcontroller.
  • said signal intercepting circuit triggers an interruption when the level of the power supply voltage reaches a threshold.
  • FIG. 1 schematically shows an embodiment of a microcontroller
  • FIG. 2 is a block diagram showing an embodiment of a circuit for setting the microcontroller to stand-by mode
  • FIG. 3 is a block diagram showing an embodiment of a circuit for waking the microcontroller.
  • FIGS. 4A, 4B, and 4C illustrate, in the form of timing diagrams, the operation of the circuit of FIG. 3 .
  • FIG. 1 schematically shows an embodiment of a microcontroller 1 .
  • the microcontroller comprises a core 2 (CORE) and a circuit 4 for restarting or resetting the power supply of core 2 .
  • CORE core 2
  • circuit 4 for restarting or resetting the power supply of core 2 .
  • circuits internal to microcontroller 1 For simplification, not all the circuits internal to microcontroller 1 have been shown. Only the circuits involved in the setting to stand-by and the waking have been shown.
  • the microcontroller 1 comprises volatile and non-volatile storage elements and various coprocessors and input-output circuits, which have not been illustrated. Further, the circuit restarting function is considered since, as will be seen hereafter, this function may be a problem.
  • circuit 4 generally also comprises other power supply control functions.
  • the power supply monitoring block can then be turned off.
  • the reasons for which the power supply monitoring block 4 is generally never turned off is that one must be able to detect a restart due to a drop followed by a rise of the power supply voltage.
  • the system cannot be correctly woken to restart the microcontroller.
  • certain logic circuits then take undetermined states when the power supply rises.
  • the starting of the power supply detection block can then be prevented by such undetermined states.
  • the consequence of adding this ability to stop the power supply monitoring block would then be to make the starting of the microcontroller unpredictable (impossible starting according to the undetermined state).
  • a stop/start circuit 3 SHUTDOWN
  • a function 42 (PM RESET) of restarting or resetting the power supply (Power Management), and thus the system, and a logic function 44 (SB LOGIC) of detecting the stopping/starting of function 42 , are distinguished.
  • circuit 4 communicate separately with unit 3 . Only function 42 communicates with core 2 to wake it up. Function 44 intercepts a wake-up request coming from outside of microcontroller 2 and, instead of transmitting it to circuit 42 , transmits it to unit 3 which provides the signal for controlling the resetting or restarting of the power supply of circuit 4 which manages the power supply of the rest of the product (microcontroller).
  • FIG. 2 schematically shows an embodiment of an interconnection between functions 42 , 44 , and 3 , highlighting the interception of the logic signal for resetting block 42 by unit 3 .
  • logic function 44 is carried out, for each external resource capable of waking up the microcontroller, by a flip-flop having a clock input, for example, active on a rising edge, receiving (inputs 5 ) microcontroller reactivation data (for leaving the stand-by state).
  • Output S 44 of this flip-flop is processed by unit 3 having an output activating the reset (the reactivation) of the power supply by block 42 .
  • core 2 is active again.
  • a function of circuit 3 is to interrupt the output signal of flip-flop 44 to avoid for the activation of a reset of circuit 42 to cause a reset of the flip-flop (connection 46 between the output of block 42 and the reset input of the flip-flop).
  • the number of flip-flops 44 depends on the number of possible waking inputs 5 of microcontroller 1 .
  • unit 3 only interrupts the reset signal according to the state of the power supply. In other words, circuit 3 does not modify the reset signal if the power supply is active but delays it on waking up.
  • FIG. 3 is a simplified block diagram of an embodiment of unit 3 .
  • unit 3 comprises a circuit 32 (SUPPLY MONITORING) for detecting power supply voltage Vdd of the microcontroller, which thus detects whether power supply function 42 is active or not.
  • detector 32 comprises a logic inverter 322 powered with voltage Vdd (rails Vdd and GND) applied to the microcontroller and having its input connected to the junction point of a resistor 324 and of a diode 326 .
  • the value of resistance 324 sets the switching threshold of inverter 322 .
  • Result S 32 of the detection crosses a timer 34 (TIMER) before being applied to a first input of an AND-type logic gate 36 .
  • the second input of gate 36 receives output signal S 44 of flip-flop 44 .
  • each flip-flop is associated with a logic gate (in the shown example, a second gate 36 ′) having a first input receiving the output of timer 34 and having a second input receiving the output (for example, S 44 ′) of the concerned flip-flop.
  • a logic gate in the shown example, a second gate 36 ′
  • circuit 42 also includes a function of monitoring power supply Vdd.
  • this function should be accurate for the operation of microcontroller 1 , which implies a significant power consumption.
  • the detection performed by unit 3 having as only function to mask the state of the start control signal, which may be undetermined at a very low voltage or at the beginning of the powering up, does not need such an accuracy and may be very simple (and with a low power consumption), as illustrated in FIG. 3 .
  • FIGS. 4A, 4B, and 4C illustrate in timing diagrams the operation of the circuit of FIG. 3 .
  • FIG. 4A shows an example of variation of voltage Vdd on waking up.
  • FIG. 4B shows the corresponding shape of signal S 32 .
  • FIG. 4C shows the corresponding shape of output signal S 36 of gate 36 .
  • voltage Vdd starts increasing, under the effect of a waking of the system (switching of signal 5 , FIG. 2 ).
  • voltage Vdd reaches (time t 2 ) the threshold set by resistor 324 and diode 326 , output S 32 of inverter 322 copies the value of voltage Vdd.
  • Delay T set by circuit 34 results in that at a subsequent time t 3 , output S 36 of gate 36 switches to the high state. Indeed, the output of flip-flop 44 is in the high state since signal 5 has switched.
  • Delay T is selected so that the level of voltage Vdd at the end of time T is higher than the triggering threshold of the reset input of circuit 42 .
  • voltage Vdd is sufficient for circuit 42 to be immediately activated. The starting of microcontroller power supply management circuit 42 thus occurs correctly.
  • flip-flop 44 is reset ( FIG. 2 ) and is thus ready to be subsequently restarted.
  • An advantage of the described embodiments is that they solve the possible problem of an unknown output state of flip-flop(s) 44 when the system is woken.
  • Another advantage is that the process of setting to stand-by mode (turning off) need not, in most cases, be modified. Indeed, the reset system just needs to have a start/stop control, which is in practice almost always true.
  • Another advantage of the described embodiments is that they only introduce a low residual power consumption.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Electronic Switches (AREA)
  • Microcomputers (AREA)
US15/153,118 2015-11-20 2016-05-12 Stand-by mode of an electronic circuit Abandoned US20170147362A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/026,233 US10719331B2 (en) 2015-11-20 2018-07-03 Stand-by mode of an electronic circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1561202 2015-11-20
FR1561202A FR3044120B1 (fr) 2015-11-20 2015-11-20 Mise en veille d'un circuit electronique

Related Child Applications (1)

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US16/026,233 Continuation US10719331B2 (en) 2015-11-20 2018-07-03 Stand-by mode of an electronic circuit

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US15/153,118 Abandoned US20170147362A1 (en) 2015-11-20 2016-05-12 Stand-by mode of an electronic circuit
US16/026,233 Active 2036-12-01 US10719331B2 (en) 2015-11-20 2018-07-03 Stand-by mode of an electronic circuit

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US (2) US20170147362A1 (zh)
EP (1) EP3171244B1 (zh)
CN (2) CN106774784B (zh)
FR (1) FR3044120B1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11385708B2 (en) * 2018-08-14 2022-07-12 Winbond Electronics Corp. Memory devices and control methods thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3044120B1 (fr) * 2015-11-20 2017-12-15 Stmicroelectronics Rousset Mise en veille d'un circuit electronique
FR3110442A1 (fr) 2020-05-22 2021-11-26 Laurent Berneman Procédé de communication coordonné entre au moins deux capsules de stimulation sans fils pour un système de stimulation musculaire ou nerveuse
FR3113746B1 (fr) * 2020-08-27 2022-07-29 St Microelectronics Rousset Circuit intégré, procédé de réinitialisation et produit programme d’ordinateur

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US20140089708A1 (en) * 2012-09-21 2014-03-27 Atmel Corporation Delaying interrupts in a microcontroller system

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US20100064160A1 (en) * 2008-09-10 2010-03-11 Thomas James Wilson Circuit Having a Low Power Mode
US20140089708A1 (en) * 2012-09-21 2014-03-27 Atmel Corporation Delaying interrupts in a microcontroller system

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11385708B2 (en) * 2018-08-14 2022-07-12 Winbond Electronics Corp. Memory devices and control methods thereof

Also Published As

Publication number Publication date
EP3171244B1 (fr) 2022-09-28
CN106774784A (zh) 2017-05-31
EP3171244A1 (fr) 2017-05-24
FR3044120B1 (fr) 2017-12-15
CN206058183U (zh) 2017-03-29
FR3044120A1 (fr) 2017-05-26
CN106774784B (zh) 2020-02-28
US20180329721A1 (en) 2018-11-15
US10719331B2 (en) 2020-07-21

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Owner name: STMICROELECTRONICS (ROUSSET) SAS, FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FROIDEVAUX, NICOLAS;GRIL-MAFFRE, JEAN-MICHEL;LECA, JEAN-PIERRE;REEL/FRAME:038567/0916

Effective date: 20160425

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION