US20170077924A1 - Semiconductor device and driving method for the same - Google Patents

Semiconductor device and driving method for the same Download PDF

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US20170077924A1
US20170077924A1 US15/232,526 US201615232526A US2017077924A1 US 20170077924 A1 US20170077924 A1 US 20170077924A1 US 201615232526 A US201615232526 A US 201615232526A US 2017077924 A1 US2017077924 A1 US 2017077924A1
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wide bandgap
semiconductor element
bandgap semiconductor
current
fault
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US9595958B1 (en
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Hayato Nakano
Ryohei Takayanagi
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
    • H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
    • H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
    • H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters

Definitions

  • the present invention relates to a semiconductor device in which a switching arm unit is constituted by connecting at least a first wide bandgap semiconductor element and a second wide bandgap semiconductor element in series, and to a method of driving the semiconductor device.
  • This type of semiconductor device has been proposed in the form of a power conversion device that includes, for example, an inverter circuit configured to perform synchronous rectification using six switching elements, with a SiC-MOSFET, which is a unipolar element employing a wide bandgap semiconductor, being used for each switching element and the synchronous rectification being performed by using parasitic diodes of the SiC-MOSFETs as flyback diodes (see Patent Document 1, for example).
  • the power conversion device has a problem in that stacking faults grow when a current flows in the body diode, which is the parasitic diode, of the SiC-MOSFET, thereby causing an on-state resistance in the SiC-MOSFET to rise and increasing conduction loss.
  • the present invention is directed to a scheme that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
  • the present disclosure provides a semiconductor device, including: a switching arm unit including a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the switching arm unit having a node between the first and second wide bandgap semiconductor elements that is configured to be connected to a load; a current detecting unit that detects a current in the second wide bandgap semiconductor element that indicates a flyback current flowing in the second wide bandgap semiconductor element, the flyback current being generated as a result of the load been driven by the first wide bandgap semiconductor element; a driving unit that drives the first wide bandgap semiconductor element and the second wide bandgap semiconductor element; and a memory storing a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region for a crystalline semiconductor constitu
  • the present disclosure provides a method of driving a semiconductor device, the semiconductor device including a switching arm unit having a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the method including: a step of detecting a flyback current in the second wide bandgap semiconductor element; and a step of determining, by referring to a fault inhibiting characteristic curve expressing a border between a fault growth region and a fault inhibiting region, whether the detected flyback current in the second wide bandgap semiconductor element is within the fault growth region or within the fault inhibiting region.
  • the present disclosure provides a method of driving a semiconductor device, the semiconductor device including: a switching arm unit including: a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series, a first diode connected in reverse-parallel to the first wide bandgap semiconductor element, and a second diode connected in reverse-parallel to the second wide bandgap semiconductor element; and a memory storing: a characteristic line map, having a plurality of characteristic lines, each of which expresses, using a flyback current flowing in the body diode of the second wide bandgap semiconductor element as a parameter, a relationship between a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of the diode connected in reverse-parallel to the second wide bandgap semiconductor element and a pulsewidth of a pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element
  • the present disclosure provides a method of driving a semiconductor device, the semiconductor device including a switching arm unit including: a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series, a first diode connected in reverse-parallel to the first wide bandgap semiconductor element, and a second diode connected in reverse-parallel to the second wide bandgap semiconductor element, the method including: a step of calculating a flyback current in a body diode of the second wide bandgap semiconductor element from a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of the diode connected in reverse-parallel to the second wide bandgap semiconductor element and a detected current flowing in the second wide bandgap semiconductor element; a step of determining, by referring to a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region on a basis of the calculated flyback current,
  • stacking faults arising in a wide bandgap semiconductor element can be sufficiently inhibited, and conduction loss can be reduced.
  • FIG. 1 is a circuit diagram illustrating the overall configuration of a power conversion device including a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram illustrating an example of a semiconductor device according to the present invention.
  • FIG. 3 is a block diagram illustrating in detail the configuration of a processing unit illustrated in FIG. 2 .
  • FIG. 4 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth used in the processing unit and a drain current.
  • FIG. 5 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth and a body diode current.
  • FIG. 6 is an equivalent circuit diagram of a switching arm.
  • FIG. 7 is a schematic diagram illustrating a current path in the case where a switching arm is constituted by semiconductor modules.
  • FIG. 8 is a flowchart illustrating an example of a sequence of a gate driving process executed by the processing unit illustrated in FIG. 2 .
  • FIG. 9 is a flowchart illustrating an example of a sequence of a dead time detection process executed by the processing unit illustrated in FIG. 2 .
  • FIGS. 10A to 10G are timing charts illustrating operating waveforms of the semiconductor device according to Embodiment 1 of the present invention.
  • FIGS. 11A to 11C are schematic diagrams illustrating current paths in respective modes of a switching arm, where 11 A indicates a mode MD 1 , 11 B indicates a mode MD 2 , and 11 C indicates a mode MD 3 .
  • FIG. 12 is a characteristic line map illustrating a relationship between a pulsewidth and an inductance ratio used in Embodiment 2 of the present invention.
  • FIG. 13 is a fault inhibiting characteristic line map illustrating a relationship between a maximum current and the slope of a threshold curve, based on FIG. 12 .
  • FIG. 14 is a body diode current calculation characteristic line map illustrating a relationship between a body diode current and an inductance ratio used in Embodiment 3 of the present invention.
  • FIG. 15 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth and a body diode current used in Embodiment 3.
  • a semiconductor device and driving method thereof according to an embodiment of the present invention will be described with reference to the drawings.
  • the present embodiment will describe a voltage-driven semiconductor element as an example of a semiconductor element and a power conversion device as an example of the semiconductor device.
  • a power conversion device 10 including the semiconductor device according to the present embodiment will be described using FIG. 1 .
  • the power conversion device 10 is connected to a three-phase AC power source 14 .
  • the power conversion device 10 includes a rectifying circuit 15 that performs full-wave rectification of three-phase AC power inputted from the three-phase AC power source 14 , and a smoothing capacitor 16 that smoothes the power rectified by the rectifying circuit 15 .
  • the rectifying circuit 15 is constituted by six diodes in a full-bridge connection or six switching elements in a full-bridge connection.
  • a positive line Lp is connected to a positive output terminal of the rectifying circuit 15
  • a negative line Ln is connected to a negative output terminal of the rectifying circuit 15 .
  • the smoothing capacitor 16 is connected between the positive line Lp and the negative line Ln.
  • the power conversion device 10 further includes semiconductor modules 2 a , 2 c , and 2 e that constitute an upper arm unit connected to the positive-side line Lp and semiconductor modules 2 b , 2 d , and 2 f that constitute a lower arm unit connected to the negative-side line Ln.
  • the semiconductor module 2 a and the semiconductor module 2 b constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln.
  • the semiconductor module 2 c and the semiconductor module 2 d constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln.
  • the semiconductor module 2 e and the semiconductor module 2 f constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln.
  • a connection point between the semiconductor module 2 a and the semiconductor module 2 b , a connection point between the semiconductor module 2 c and the semiconductor module 2 d , and a connection point between the semiconductor module 2 e and the semiconductor module 2 f are connected to a three-phase electric motor 17 serving as an inductive load.
  • the semiconductor module 2 a includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 a , a body diode 4 a parasitic to the MOSFET 3 a , and a free-wheeling Schottky barrier diode 5 a connected in reverse parallel to the MOSFET 3 a , and constitutes an arm unit.
  • the respective cathodes of the body diode 4 a and the Schottky barrier diode 5 a are connected to a drain terminal D of the MOSFET 3 a
  • the respective anodes of the body diode 4 a and the Schottky barrier diode 5 a are connected to a source terminal S of the MOSFET 3 a.
  • the semiconductor module 2 b includes an N-type SiC-MOSFET 3 b (an example of a second wide bandgap semiconductor element), a body diode 4 b , and a Schottky barrier diode 5 b , and constitutes an arm unit.
  • the semiconductor module 2 c also includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 c , a body diode 4 c , and a Schottky barrier diode 5 c , and constitutes an arm unit.
  • N-type SiC-MOSFET an example of a first wide bandgap semiconductor element
  • the semiconductor module 2 d also includes an N-type SiC-MOSFET (an example of a second wide bandgap semiconductor element) 3 d , a body diode 4 d , and a Schottky barrier diode 5 d , and constitutes an arm unit.
  • N-type SiC-MOSFET an example of a second wide bandgap semiconductor element
  • the semiconductor module 2 e also includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 e , a body diode 4 e , and a Schottky barrier diode 5 e , and constitutes an arm unit.
  • N-type SiC-MOSFET an example of a first wide bandgap semiconductor element
  • the semiconductor module 2 f also includes an N-type SiC-MOSFET (an example of a second wide bandgap semiconductor element) 3 f , a body diode 4 f , and a Schottky barrier diode 5 f , and constitutes an arm unit.
  • N-type SiC-MOSFET an example of a second wide bandgap semiconductor element
  • the SiC-MOSFETs 3 a , 3 b , 3 c , 3 d , 3 e , and 3 f are unipolar power semiconductor elements, and are bidirectional.
  • the wide bandgap semiconductor elements that constitute the arm units are not limited to SiC-based semiconductor elements, and may instead be wide bandgap semiconductor elements having at least one of gallium nitride and diamond as their primary material.
  • the Schottky barrier diodes 5 a to 5 f are not limited to Si-based semiconductor elements, and may instead be wide bandgap semiconductor elements having at least one of silicon carbide, gallium nitride, and diamond as their primary material.
  • a wide bandgap semiconductor element has high-temperature and high-voltage performance superior to an Si element, and has low loss.
  • the power conversion device 10 includes a gate driving unit (GDU) 1 a that controls a switching operation of the semiconductor module 2 a , a gate driving unit (GDU) 1 b that controls a switching operation of the semiconductor module 2 b , a gate driving unit (GDU) 1 c that controls a switching operation of the semiconductor module 2 c , a gate driving unit (GDU) 1 d that controls a switching operation of the semiconductor module 2 d , a gate driving unit (GDU) 1 e that controls a switching operation of the semiconductor module 2 e , and a gate driving unit (GDU) 1 f that controls a switching operation of the semiconductor module 2 f.
  • GDU gate driving unit
  • Output terminals of the gate driving units 1 a to 1 f are connected to corresponding gate terminals G serving as control terminals of the SiC-MOSFETs 3 a to 3 f.
  • the semiconductor module 2 a and the semiconductor module 2 b constitute a U-phase switching arm unit, for example; the semiconductor module 2 c and the semiconductor module 2 d constitute a V-phase switching arm unit, for example; and the semiconductor module 2 e and the semiconductor module 2 f constitute a W-phase switching arm unit, for example.
  • an inverter circuit is constituted by a three-phase full bridge circuit in which the U-phase switching arm unit, the V-phase switching arm unit, and the W-phase switching arm unit are connected in parallel, the gate driving units 1 a and 1 b that control switching operations of the U-phase arm, the gate driving units 1 c and 1 d that control switching operations of the V-phase arm, and the gate driving units 1 e and 1 f that control switching operations of the W-phase arm.
  • FIGS. 2 to 5 the semiconductor device according to the present embodiment will be described using FIGS. 2 to 5 , with reference to FIG. 1 , using the U-phase switching arm unit as an example.
  • the V-phase switching arm unit and the W-phase switching arm unit have the same configuration as the U-phase switching arm unit.
  • the gate driving unit 1 a includes a current sensor 21 a serving as a current detecting unit that detects a drain current (an example of a main current) Id(b) flowing in the SiC-MOSFET 3 b , which corresponds to a second wide bandgap semiconductor element, and a gate driving unit 22 a serving as a semiconductor element driving unit that drives the SiC-MOSFET 3 a , which corresponds to a first wide bandgap semiconductor element, in response to the input of a current value of the drain current Id(b) detected by the current sensor 21 a.
  • a current sensor 21 a serving as a current detecting unit that detects a drain current (an example of a main current) Id(b) flowing in the SiC-MOSFET 3 b , which corresponds to a second wide bandgap semiconductor element
  • a gate driving unit 22 a serving as a semiconductor element driving unit that drives the SiC-MOSFET 3 a , which corresponds to a first wide band
  • the gate driving unit 22 a includes a processing unit 23 a serving as a first driving unit, constituted by a microcomputer, for example, inputted with an upper arm control signal CS(a) from the exterior.
  • the drain current Id(b), detected by the current sensor 21 a , of the SiC-MOSFET 3 b corresponding to the second wide bandgap semiconductor element is inputted to the processing unit 23 a.
  • the processing unit 23 a includes a central processing unit (CPU) 25 a .
  • a RAM 26 a and a ROM 27 a are connected to the central processing unit 25 a by a system bus.
  • a gate driving signal Sgd(a) outputted from the output-side interface circuit 29 a is supplied to a base of a first switching element 30 U constituted by an NPN-type bipolar transistor and a base of a second switching element 30 D constituted by a PNP-type bipolar transistor, which are connected in series between a positive pole source P 1 and a negative pole source N 1 of an AC power source.
  • a connection point between the first switching element 30 U and the second switching element 30 D is connected to a gate of the SiC-MOSFET 3 a via a gate resistance Rg.
  • a fault inhibiting characteristic map is stored in the ROM 28 b in advance. As illustrated in FIG. 4 , this fault inhibiting characteristic map takes a pulsewidth of a pulse-form current produced when a flyback current begins flowing in the body diode 4 b of the SiC-MOSFET 3 b serving as a second wide bandgap semiconductor element on the horizontal axis, and the drain current Id(b) resulting from the flyback current on the horizontal axis; a hyperbolic fault inhibiting characteristic curve L 1 indicating a border between a fault growth region 31 and a fault inhibiting region 32 of the SiC-MOSFET is set.
  • This fault inhibiting characteristic map is obtained by converting a flyback current I BD of the body diode 4 b as indicated in the fault inhibiting characteristic map illustrated in FIG. 5 , which represents a relationship between the pulsewidth and the flyback current of the body diode 4 b , into the drain current Id(b).
  • a hyperbolic fault inhibiting characteristic curve Ld indicating a border between a fault growth region and a fault inhibiting region is set.
  • a region on an origin (0,0) side of the fault inhibiting characteristic line Ld corresponds to a fault inhibiting region ADi, whereas a side of the fault inhibiting characteristic line Ld opposite from the origin (0,0) corresponds to a fault growth region ADg.
  • the fault inhibiting characteristic line Ld is derived from the results of experiments, simulations, and so on.
  • the drain current Id(b) is a value obtained by multiplying an inductance ratio L MOS /L SBD between a flyback inductance L MOS of the SiC-MOSFET 3 a and a flyback inductance L SBD of the Schottky barrier diode 5 a by the flyback current I BD of the body diode.
  • Id ( b ) ( L MOS /L SBD ) ⁇ I BD 0.4 (1)
  • drain current Id(b) (A/cm 2 ) is calculated from Formula (1) and the fault inhibiting characteristic map illustrated in FIG. 4 is formed.
  • the SiC-MOSFET 3 a turns off and a flyback current flows in the SiC-MOSFET 3 b corresponding to the lower arm
  • an equivalent circuit is established as illustrated in FIG. 6 ;
  • the flyback current Id(b) from the U-phase coil Lu of the three-phase electric motor 17 traverses the inductance L MOS , traverses the body diode 4 b and returns to the U-phase coil Lu, and traverses the inductance L BD , traverses the Schottky barrier diode 5 b , and returns to the U-phase coil Lu.
  • a current path in the modules is as indicated in FIG. 7 when the SiC-MOSFET 3 a is turned off. That is, the semiconductor module 2 a is formed, for example, by surface-mounting a SiC-MOSFET chip 42 a on an upper surface of a substrate 41 a in which a conductive plate portion is bonded to an insulative substrate as with a DCB (Direct Copper Bond) substrate, with a drain electrode facing the substrate.
  • a DCB Direct Copper Bond
  • a SiC-MOSFET chip 42 b and a Schottky barrier diode chip 43 b are surface-mounted on an upper surface of a substrate 41 b that is the same type of substrate as the substrate 41 a , with a drain of the SiC-MOSFET chip 42 b and a cathode of the Schottky barrier diode chip 43 b separated by a prescribed distance Lc.
  • a printed board 44 is disposed above the substrates 41 a and 41 b ; the printed board 44 is electrically connected to a source electrode and a gate electrode formed on upper surfaces of the SiC-MOSFET chips 42 a and 42 b and an anode electrode formed on an upper surface of the Schottky barrier diode 43 b by conductive pins 45 . Additionally, the substrate 41 a of the semiconductor module 2 a and the printed board 44 are electrically connected by a conductive pin 46 .
  • a positive terminal pin 47 connected to the positive line Lp is connected to the upper surface of the substrate 41 a of the semiconductor module 2 a
  • an output terminal pin 48 connected to the U-phase coil Lu of the three-phase electric motor 17 is connected to the upper surface of the substrate 41 b of the semiconductor module 2 b.
  • a turn-on current path is formed as indicated by the dotted line in FIG. 7 , in which a current supplied from the positive terminal pin 47 traverses the conductive plate portion of the substrate 41 a , the drain-source of the SiC-MOSFET 3 a , the conductive pin 45 , a printed wiring of the printed board 44 , and proceeds toward the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48 .
  • flyback current paths two types of turn-off current paths, or in other words, flyback current paths, are formed as indicated by the solid lines in FIG. 7 , namely a first current path IL 1 in which a flyback current supplied from another end of the U-phase coil Lu of the three-phase electric motor 17 traverses the body diode 4 b of the MOSFET 3 b , and a second current path IL 2 in which the stated flyback current traverses the Schottky barrier diode 5 b.
  • a first current path IL 1 in which a flyback current supplied from another end of the U-phase coil Lu of the three-phase electric motor 17 traverses the body diode 4 b of the MOSFET 3 b
  • a second current path IL 2 in which the stated flyback current traverses the Schottky barrier diode 5 b.
  • the first current path IL 1 extends from the substrate 41 a of the semiconductor module 2 a to the printed board 44 through the conductive pin 46 .
  • the current transmitted to the printed board 44 follows a current path that traverses the printed board, the conductive pins 45 , and traverses the drain from the source of the SiC-MOSFET 3 b of the semiconductor module 2 b , and furthermore traverses the conductive plate portion of the substrate 41 b and returns to the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48 .
  • the second current path IL 2 is a current path in which the current is transmitted from the substrate 41 a of the semiconductor module 2 a to the printed board 44 through the conductive pin 46 , traverses the printed wiring of the printed board, traverses the conductive pins 45 and travels from the anode to the cathode of the Schottky barrier diode 5 b of the semiconductor module 2 b , furthermore traverses the conductive plate portion of the substrate 41 b , and returns to the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48 .
  • an inductance of the first current path IL 1 traversing the SiC-MOSFET 3 b is a module inductance M LMOS
  • an inductance of the second current path traversing the Schottky barrier diode 5 b is a module inductance M LSBD .
  • a chip inductance of the SiC-MOSFET 3 b itself is represented by C MOSL
  • a chip inductance of the Schottky barrier diode 5 b itself is represented by C LSBD
  • an external inductance is represented by B LMS
  • the inductance L MOS of the SiC-MOSFET 3 a and the inductance L SBD of the Schottky barrier diode 5 a can be expressed through the following Formula (2) and Formula (3).
  • L SBD B LMS +M LSBD +C LSBD (3)
  • the module inductance M LMOS is determined by the position in the semiconductor module 2 b where the SiC-MOSFET chip 42 b is disposed on the conductive plate portion of the substrate 41 b , and the number, thickness, and so on of the conductive pins 45 ; likewise, the module inductance M LSBD is determined by the position in the semiconductor module 2 b where the Schottky barrier diode chip 43 b is disposed on the conductive plate portion of the substrate 41 b , and the number, thickness, and so on of the conductive pins 45 .
  • the module inductances M LMOS and M LSBD are determined at the design stage of the semiconductor module 2 b .
  • the module inductance M LMOS is no greater than 10 nH
  • the module inductance M LSBD is also no greater than 10 nH.
  • the external inductance B LMS is no greater than 10 nH
  • the chip inductance C LMOS is no greater than 20 nH
  • the chip inductance C LSBD is no greater than 5 nH.
  • the fault inhibiting characteristic map illustrated in FIG. 4 which takes the drain current Id(b) on the vertical axis, has its vertical axis extended to four times the vertical axis in the fault inhibiting characteristic map illustrated in FIG. 5 , which takes the flyback current I BD of the body diode 4 b on the vertical axis.
  • the pulsewidth PW can be detected without actually measuring the pulsewidth of the body diode 4 b ; whether the drain current Id(b) falls within the fault inhibiting region ADi or falls within the fault growth region ADg can be determined with ease from the detected pulsewidth PW and the drain current Id(b), detected by the current sensor 21 a , of the SiC-MOSFET 3 b serving as the second wide bandgap semiconductor element.
  • the central processing unit 25 a of the processing unit 23 a executing a gate driving process illustrated in FIG. 8 the driving of the SiC-MOSFET 3 a can be controlled so that the pulsewidth PW and the flyback current I BD of the body diode 4 b fall within the fault inhibiting region ADi.
  • step S 1 it is first determined, in step S 1 , whether or not the SiC-MOSFET 3 a has transitioned from a mode MD 1 , indicated in FIGS. 10A to 10G , in which the SiC-MOSFET remains turned on, to a mode MD 2 , indicated in FIGS. 10A to 10G , in which the SiC-MOSFET is turned off.
  • the SiC-MOSFET has not yet transitioned to the mode MD 2 , the process stands by until the transition is made.
  • step S 2 When the SiC-MOSFET has transitioned to the mode MD 2 , the process moves to step S 2 , where a negative drain current Id(b) produced by the flyback current detected by the current sensor 21 a is loaded. The process then moves to step S 3 .
  • step S 3 it is determined whether or not the drain current Id(b) has reached a peak value.
  • the process stands by until the peak value is reached.
  • the process moves to step S 4 , where the peak value is temporarily stored in the RAM 26 a , for example, after which the process moves to step S 5 .
  • step S 5 the dead time Tdt, detected by a dead time detection process that detects the dead time Tdt between the control signal CS(a) and the control signal CS(b), is loaded.
  • step S 7 the fault characteristics map illustrated in FIG. 4 is loaded from the ROM 27 a .
  • step S 8 it is judged whether coordinates corresponding to the peak value of the drain current Id(b) and the pulsewidth PW fall within the fault inhibiting region ADi or fall within the fault growth region ADg by referring to the fault characteristics map on the basis of the peak value of the drain current Id(b) and the pulsewidth PW.
  • step S 9 the fault characteristics map illustrated in FIG. 4 is loaded from the ROM 27 a .
  • step S 9 it is determined, as a result of the judgment, whether or not the coordinates fall within the fault inhibiting region ADi.
  • the process moves directly to step S 12 without calculating a corrected duty ratio for the control signal CS(a).
  • the process moves to step S 10 , where a corrected drain current IAd(b) for the SiC-MOSFET 3 b that falls within the fault inhibiting region ADi at the same pulsewidth PW is calculated. The process then moves to step S 11 .
  • step S 11 a corrected duty ratio DA(a) of the control signal CS(a), corresponding to the calculated corrected drain current IAd(b), is calculated, and the process then moves to step S 12 .
  • step S 12 it is determined whether or not the SiC-MOSFET 3 a in the upper arm has transitioned from a mode MD 4 , in which the SiC-MOSFET is turned off, to the mode MD 1 , in which the SiC-MOSFET is turned on.
  • the SiC-MOSFET has not yet transitioned to the mode MD 1 , the process stands by until the transition occurs, and when the SiC-MOSFET has transited to the mode MD 1 , the process moves to step S 13 .
  • step S 13 it is determined whether or not the corrected duty ratio DA(a) is stored in a corrected duty ratio storage region of the RAM 26 a .
  • the process moves to step S 14 , where a gate driving signal of a pulsewidth based on the corrected duty ratio DA(a) is outputted instead of the control signal CS(a), and the process then returns to step S 1 .
  • the control signal CS(a) is outputted as-is as the gate driving signal, after which the process returns to step S 1 .
  • the central processing unit 25 a of the processing unit 23 a executes the dead time detection process. As illustrated in FIG. 9 , this dead time detection process is executed as a timer interrupt process every prescribed amount of time (100 nsec, for example).
  • step S 21 the control signal CS(a) is loaded.
  • step S 22 it is determined whether or not the control signal CS(a) is in an on state.
  • the timer interrupt process is ended directly and the process returns to a prescribed main program, whereas when the control signal CS(a) is in an on state, the process moves to step S 23 .
  • step S 23 it is determined whether or not the previous value of the control signal CS(a) was an off state.
  • the previous value was an on state, it is determined that the on state is being maintained, the timer interrupt process ends directly and the process returns to the prescribed main program.
  • step S 23 When the result of the determination made in step S 23 indicates that the previous value of the control signal CS(a) was in an off state, it is determined that the state has switched from an off state to an on state, and the process moves to step S 24 .
  • step S 24 a software timer is reset and the measurement of time is started anew; the process then moves to step S 25 .
  • step S 25 the control signal CS(b) is loaded, and the process then moves to step S 26 , where it is determined whether or not the state has changed to an on state.
  • the process returns to step S 25 , whereas when the state has changed to an on state, the process moves to step S 27 , where the software timer is stopped and the measured time is loaded as the dead time Tdt, after which the process moves to step S 28 .
  • step S 28 the loaded dead time Tdt is updated and stored in a dead time storage region of the RAM 26 a , after which the timer interrupt process is ended and the process returns to the prescribed main program.
  • the dead time Tdt between the control signal CS(a) and the control signal CS(b) is detected and the detected dead time between the control signal CS(a) and the control signal CS(b) is updated and stored in the dead time storage region of the RAM 26 a every prescribed amount of time, and thus the most recent dead time Tdt is always stored in the dead time storage region of the RAM 26 a.
  • the pulsewidth PW can be calculated on the basis of the most recent dead time in the gate driving process described above with reference to FIG. 8 , and by referring to the fault characteristics map on the basis of the calculated pulsewidth PW and the detected drain current Id(b), a gate driving signal can be formed such that the current drain current Id(b) falls within the fault inhibiting region ADi.
  • the electrical energy stored in the U-phase coil Lu of the three-phase electric motor 17 can be controlled to an appropriate value, and the flyback current flowing in the body diode 4 b of the SiC-MOSFET 3 b , which serves as the second wide bandgap semiconductor element, can be controlled to a current value that inhibits the growth of stacking faults.
  • the growth of stacking faults in the SiC-MOSFET 3 b can be inhibited, a rise in the on-state resistance can be inhibited, and an increase in conduction loss can be inhibited.
  • control signal CS(a) inputted to the gate driving unit 1 a of the SiC-MOSFET 3 a is at high level, as indicated in FIG. 10A
  • control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b is at low level, as indicated in FIG. 10B .
  • a gate-source voltage Vgs(a) of the MOSFET 3 a is the same voltage as a first power source voltage P 1
  • a gate-source voltage Vgs(b) of the SiC-MOSFET 3 b is the same voltage as a negative voltage N 1
  • the SiC-MOSFET 3 a is in an on state
  • the SiC-MOSFET 3 b is in an off state
  • a drain current Id(a) of the SiC-MOSFET 3 a flows in the U-phase coil of the three-phase electric motor 17 (see FIG. 1 ) as an output current Iu.
  • the drain current Id(a) of the SiC-MOSFET 3 a therefore increases as indicated in FIG. 10F
  • the output current Iu gradually increases as indicated in FIG. 10E .
  • the output current Iu has a positive value.
  • the control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b is at low level, as indicated in FIG. 10B , and thus the first switching element 30 U is in an off state and the second switching element 30 D is in an on state.
  • the negative voltage N 1 is applied to the gate terminal G of the SiC-MOSFET 3 b .
  • a reference potential M (0 (V), for example) is being applied to the source terminal S of the SiC-MOSFET 3 b , and thus the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b matches the negative voltage N 1 , as indicated in FIG. 10D . Accordingly, a forward bias voltage is not outputted to the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b , and the SiC-MOSFET 3 b remains in an off state.
  • the operations for the one phase of the power conversion device then change from the mode MD 1 to the mode MD 2 at time t 12 .
  • the mode MD 2 is a mode that turns off the SiC-MOSFET 3 a and puts both the SiC-MOSFETs 3 a and 3 b in an off state in order to form a dead time that prevents the SiC-MOSFET 3 a and the SiC-MOSFET 3 b from being in an on state simultaneously and a through current flowing between the SiC-MOSFET 3 a and the SiC-MOSFET 3 b .
  • the control signal CS(a) inputted to the gate driving unit 1 a of the SiC-MOSFET 3 a switches from high level to low level, as indicated in FIG. 10A
  • the control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b stays at low level, as indicated in FIG. 10B .
  • the gate-source voltage Vgs(a) of the SiC-MOSFET 3 a and the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b are at the same voltage as the negative voltage N 1 , as indicated in FIGS. 10C and D. Accordingly, as illustrated in FIG. 11B , the SiC-MOSFET 3 a switches from an on state to a turned-off state, and the SiC-MOSFET 3 b remains in an off state. The SiC-MOSFETs 3 a and 3 b are thus both in an off state.
  • a flyback current from the three-phase electric motor 17 flows to the three-phase electric motor 17 , through the body diode 4 b and the Schottky barrier diode 5 b of the semiconductor module 2 b , as the output current Iu, as indicated by the broken line arrow in FIG. 11B .
  • This flyback current is a current based on a discharge of an electric charge accumulated in the coil of the three-phase electric motor 17 , and thus as indicated in FIG. 10G , the drain current Id(b), which corresponds to the current value of the flyback current, gradually approaches 0 (A) after an overshoot has temporarily arisen immediately after entering the mode MD 2 .
  • the current value of the output current Iu gradually drops in response to this, as indicated in FIG. 10E .
  • the SiC-MOSFET 3 a is in an off state in the mode MD 2 , and thus the drain current Id(a) of the SiC-MOSFET 3 a is 0 (A), as indicated in FIG. 10F .
  • the central processing unit 25 a of the processing unit 23 a in the gate driving unit 1 a executes the gate driving process illustrated in FIG. 8 and the dead time detection process illustrated in FIG. 9 , and thus the dead time Tdt between the control signal CS(a) and the control signal CS(b) can be detected and continually kept updated in the dead time storage region of the RAM 26 a through the dead time detection process, as described above.
  • the pulsewidth PW can be calculated on the basis of the most recent dead time in the gate driving process, and by referring to the fault characteristics map on the basis of the calculated pulsewidth PW and the detected drain current Id(b), the gate driving signal of the SiC-MOSFET 3 a can be formed such that the current drain current Id(b) falls within the fault inhibiting region ADi.
  • the corrected duty ratio DA(a) is calculated so as to reduce the drain current Id(a) of the SiC-MOSFET 3 a .
  • the drain current Id(a) is reduced and the electrical energy stored in the U-phase coil Lu of the three-phase electric motor 17 is reduced by controlling the gate of the SiC-MOSFET 3 a in the upper arm according to the corrected duty ratio DA(a).
  • the drain current Id(b) which is the flyback current flowing in the body diode 4 b in the lower arm, is reduced and controlled to a flyback current value that falls within the fault inhibiting region ADi.
  • the flyback current flowing in the body diode 4 b of the SiC-MOSFET 3 b in the lower arm is inhibited and an increase in stacking faults in the SiC-MOSFET 3 b is inhibited, which in turn makes it possible to inhibit a rise in the on-state resistance of the SiC-MOSFET 3 b and inhibit an increase in conduction loss.
  • the SiC-MOSFET 3 b upon transitioning from the mode MD 2 to the mode MD 3 , in which the SiC-MOSFET 3 b is in a turned-on state, the SiC-MOSFET 3 b enters an on state, and a flyback current also flows through the SiC-MOSFET 3 b .
  • the on-state resistances of the SiC-MOSFET 3 b , the body diode 4 b , and the Schottky barrier diode 5 b become parallel, and thus the on-state resistance can be reduced and conduction loss can be reduced.
  • a dead time period is entered again, resulting in the SiC-MOSFET 3 a in the upper arm and the SiC-MOSFET 3 b in the lower arm both entering an off state.
  • a flyback current is distributed between the body diode 4 b and the Schottky barrier diode 5 b at an on-state voltage ratio between the two in the mode MD 4 .
  • the on-state voltage ratio is higher than a transient on-state voltage ratio of the mode MD 2 , and the flyback current flowing in the body diode 4 b becomes extremely low.
  • the growth of stacking faults in the second wide bandgap semiconductor element can be inhibited with certainty in a dead time period in which the control signal CS(a) goes from on to a turned-off state and the control signal CS(b) stays in an off state.
  • This makes it possible to inhibit a rise in the on-state resistance, inhibit an increase in conduction loss, and prevent degradation of the second wide bandgap semiconductor element.
  • Embodiment 1 describes a case where the fault characteristics map takes the origin side of the characteristic line Ld as the fault inhibiting region ADi as indicated in FIG. 5 , the invention is not limited thereto. If a hyperbolic fault inhibiting characteristic curve Ld 1 located on the origin side of the characteristic line Ld indicated in FIG. 5 is set and the region on the inner side of the fault inhibiting characteristic curve Ld 1 is taken as the fault inhibiting region ADi, the growth of stacking faults can be prevented with more certainty, and degradation of the SiC-MOSFETs 3 a and 3 b can be prevented with more certainty.
  • Embodiment 1 describes a case where control is carried out for inhibiting the growth of stacking faults in the SiC-MOSFET on the lower arm by controlling the SiC-MOSFET 3 a on the upper arm, the invention is not limited thereto.
  • the same processing may be carried out by the gate driving unit 1 b of the SiC-MOSFET 3 b in the case where a flyback current flows in the body diode 4 a and the Schottky barrier diode 5 a of the SiC-MOSFET 3 a in the upper arm as well.
  • Embodiment 2 of a semiconductor device according to the present invention will be described according to FIGS. 12 and 13 .
  • a pulsewidth that inhibits the growth of stacking faults is set according to an inductance ratio that is a ratio between the inductance of a SiC-MOSFET and an inductance of a Schottky barrier diode.
  • a net inductance L SBDN constituted by only the module inductance M LSBD and the chip inductance C LSBD , excluding the external inductance B LMS from the above-described Formula (3) is set as the inductance L SBD of the Schottky barrier diodes 5 a and 5 b .
  • an inductance ratio is expressed as L MOSN /L SBDN .
  • the characteristic line L 33 is represented by a line segment passing through a point (0.8,0.1) and a point (1.4,1.0)
  • the characteristic line L 32 is represented by a line segment passing through a point (1.6,0.1) and (2.9,1.0)
  • the characteristic line L 31 is represented by a line segment passing through a point (3.3,0.1) and a point (6,1.0). Sections of the respective characteristic lines L 31 to L 33 have the same values.
  • a maximum current value Imax is taken on the horizontal axis and slopes of the characteristic lines L 31 to L 33 in FIG. 12 are taken on the vertical axis
  • the maximum current value Imax and the slopes of the characteristic lines L 31 to L 33 are in a linear relationship represented by a characteristic line L 34 , which is represented by a line segment passing through a point (0,0) and a point (24,1.600), as illustrated in FIG. 13 .
  • a region to the left of the characteristic line L 34 is a region in which the slopes of the characteristic lines L 31 to L 33 in FIG. 12 are greater and a range of selection for the pulsewidth PW narrows, and an effect of inhibiting the growth of stacking faults can be achieved.
  • a region to the right of the characteristic line L 34 is a region in which the slopes of the characteristic lines L 31 to L 33 in FIG. 12 are lower and the range of selection for the pulsewidth PW broadens, and is thus a region where the pulsewidth PW that can inhibit the growth of stacking faults is exceeded and stacking faults grow as a result.
  • the region to the left of the characteristic line L 34 in FIG. 13 can be taken as the fault inhibiting region, and the region to the right can be taken as the fault growth region.
  • the chip inductance C LSBD of the Schottky barrier diodes 5 a and 5 b is lower than the chip inductance C LMOS of the SiC-MOSFETs 3 a and 3 b , and with respect to flyback current, it is easy for flyback current to flow in the body diodes 4 a and 4 b of the SiC-MOSFETs 3 a and 3 b .
  • the chip inductances C LMOS and C LSBD are values unique to the semiconductor chip and therefore cannot be adjusted.
  • the module inductance M LMOS of the SiC-MOSFETs 3 a and 3 b and the module inductance M LSBD of the Schottky barrier diodes 5 a and 5 b change at the stage of designing the inductance of wiring within the semiconductor module 2 a , and can therefore be adjusted.
  • an inductance ratio L MOSN /L SBDN in a region that inhibits the growth of stacking faults can be set by adjusting the inductance ratio L MOSN /L SBDN at the design stage of the semiconductor module 2 a.
  • the inductance L MOS of the SiC-MOSFETs 3 a and 3 b and the inductance L SBD of the Schottky barrier diodes 5 a and 5 b incorporate the external inductance B LMS , as indicated by Formula (2) and Formula (3) in Embodiment 1.
  • the inductance ratio L MOS /L SBD is adjusted in the direction where the slopes of the characteristic lines L 31 to L 33 indicated in FIG. 12 increase, which makes it possible to inhibit the growth of stacking faults, inhibit a rise in the on-state resistance, and inhibit an increase in conduction loss.
  • a method of driving a semiconductor device capable of preventing degradation of the SiC-MOSFETs 3 a and 3 b can be provided as a result.
  • Embodiment 3 of a semiconductor device according to the present invention will be described according to FIGS. 14 and 15 .
  • Embodiment 3 focuses on the inductance ratio L MOS /L SBD between the SiC-MOSFET 3 a and the Schottky barrier diode 5 a serving as the upper arm unit and the inductance ratio L MOS /L SBD between the SiC-MOSFET 3 b and the Schottky barrier diode 5 b serving as the lower arm unit in the semiconductor module 2 a that constitutes the power conversion device 10 , and makes it possible to drive the SiC-MOSFETs 3 a and 3 b within the fault inhibiting region ADi in which stacking faults do not grow, in the same manner as in Embodiment 1.
  • a customer who has purchased the power conversion device 10 or the semiconductor modules 2 a to 2 c can use the power conversion device 10 or the semiconductor modules 2 a to 2 c without any degradation arising.
  • Embodiment 3 a body diode current calculation characteristic line map 41 , illustrated in FIG. 14 , and a fault characteristic line map 42 , illustrated in FIG. 15 , are prepared first.
  • the body diode current calculation characteristic line map 41 takes the body diode current I BD on the horizontal axis and the inductance ratio L MOS /L SBD on the vertical axis, and for example, the drain current Id(b) flowing in the body diode 4 b and the Schottky barrier diode 5 b of the SiC-MOSFET 3 b that constitutes the lower arm unit is set as a parameter.
  • a straight line L 43 indicating a recommended inductance ratio L MOSD /L SBDD determined at the design stage of the semiconductor module 2 a is set as well.
  • the module inductance M LMOS , the chip inductance C LMOS , and a recommended inductance L MOSD of the SiC-MOSFET 3 b , determined at the design stage, and the module inductance M LSBD , the chip inductance C LMOS , and a recommended inductance L SBDD of the Schottky barrier diode 5 a , are indicated in this body diode current calculation characteristic line map 41 . These items are not limited to being indicated in the body diode current calculation characteristic line map 41 , and may be indicated in other papers as well.
  • the fault characteristic line map 42 illustrated in FIG. 15 has the same format as the fault characteristics map described earlier in Embodiment 1 with reference to FIG. 5 ; the pulsewidth is taken on the horizontal axis, the body diode current I BD of the body diode 4 b is taken on the vertical axis, and a hyperbolic fault inhibiting characteristic curve L 44 corresponding to a border between the fault inhibiting region ADi and the fault growth region ADg is indicated.
  • the body diode current calculation characteristic line map 41 and the fault characteristic line map 42 are provided with the product when the power conversion device 10 or the semiconductor module 2 a is sold.
  • the inductance L MOS of the SiC-MOSFET 3 b is expressed as a sum of the external inductance B LMS , the module inductance M LMS , and the chip inductance C LMO , as indicated by Formula (2) in the above-described Embodiment 1.
  • the inductance L SBD of the Schottky barrier diode 5 b is expressed as a sum of the external inductance B LMS , the module inductance M LSBD , and the chip inductance C LSBD .
  • the inductance ratio L MOS /L SBD can be changed by adjusting the external inductance B LMS .
  • the external inductance B LMS becomes dominant in the inductances L MOS and L SBD as the value of the external inductance B LMS is increased, and thus the inductance ratio L MOS /L SBD approaches “1” as a result.
  • the drain current Id(b) and the body diode current I BD become equal, and almost no flyback current flows in the Schottky barrier diode 5 b .
  • the width of the fault inhibiting region ADi from the fault characteristic line map 42 indicated in FIG. 15 decreases, and the range of selection for the pulsewidth narrows.
  • the recommended inductance ratio L MOSD /L SBDD expressed by the straight line L 43 and set by the manufacturer be set so that the range of selection for the pulsewidth PW in the fault inhibiting region ADi is relatively broad.
  • the body diode current I BD is set to a low value, the width of the fault inhibiting region ADi from the fault characteristic line map 42 indicated in FIG. 15 will broaden, but it is then necessary to reduce the amount of flyback current that flows.
  • the recommended inductance L MOSD /L SBDD is set to the characteristic line 43 in the body diode current calculation characteristic line map 41 indicated in FIG. 14 so that a comparatively high value I BD 10, which makes it possible to broaden the range of selection of the pulsewidth in the fault inhibiting region ADi, can be obtained for the body diode current I BD .
  • an inductance L MOS 1 of the SiC-MOSFET 3 b is first calculated by adding the external inductance to be used to a total value of the module inductance M LMOS and the chip inductance C LMOS of the SiC-MOSFET 3 b indicated in the body diode current calculation characteristic line map 41 illustrated in FIG. 14 .
  • an inductance L SBD 1 of the Schottky barrier diode 5 b is calculated by adding the external inductance to be used to a total value of the module inductance M LSBD and the chip inductance C LMOS of the Schottky barrier diode 5 a indicated in the body diode current calculation characteristic line map 41 .
  • the calculated inductance ratio L MOS 1/L SBD 1 is taken on the vertical axis of the body diode current calculation characteristic line map 41 indicated in FIG. 14 , and one of the characteristic line L 41 and L 42 of the drain current Id(b) to be used is selected.
  • a body diode current I BD 11 is calculated by drawing a horizontal line from the inductance ratio L MOS 1/L SBD 1 to the selected characteristic line L 41 , and drawing a vertical line from a point of intersection with the characteristic line L 41 toward the horizontal axis, as indicated by the dotted line in FIG. 14 .
  • a pulsewidth PW in the selected range in FIG. 15 makes it possible to inhibit the growth of stacking faults in the SiC-MOSFET 3 b , inhibit a rise in the on-state resistance, and inhibit an increase in conduction loss, even in the case where a flyback current flows in the body diode 4 b of the SiC-MOSFET 3 b . This makes it possible to prevent degradation of the SiC-MOSFETs 3 a and 3 b.
  • Embodiment 3 by setting the inductance ratio L MOS /L SBD , calculating the body diode current I BD from the inductance ratio L MOS /L SBD by referring to the body diode current calculation characteristic line map illustrated in FIG. 14 , and referring to the fault inhibiting characteristic line map illustrated in FIG. 15 on the basis of the calculated body diode current I BD , the range of the pulsewidth PW for usage within the fault inhibiting region ADi can be confirmed. As such, a user can, based on the inductance ratio, easily confirm driving conditions that can inhibit the SiC-MOSFETs 3 a and 3 b from degrading.
  • a hyperbolic fault inhibiting characteristic curve L 45 may be set in the fault inhibiting characteristic line map 42 illustrated in FIG. 15 , in the same manner as in the fault inhibiting characteristic map illustrated in FIG. 5 .
  • Embodiment 3 describes a case where the body diode current calculation characteristic line map 41 and the fault characteristic line map 42 are prepared, the invention is not limited thereto.
  • the body diode current calculation characteristic line map 41 and the fault characteristic line map 42 may be stored as maps in a storage unit such as a ROM in advance, and the external inductance may be inputted into a processing unit such as a microcomputer through an input unit such as a keyboard.
  • the inductance L MOS and L SBD may be calculated and the inductance ratio L MOS /L SBC may be calculated; the body diode current I BD may then be calculated by referring to the body diode current calculation map on the basis of the calculated inductance ratio L MOS /L SBD , and the range of selection of the pulsewidth PW may be calculated by referring to the fault characteristics map on the basis of the calculated body diode current I BD . The range of selection may then be displayed in a monitor or printed using a printer.
  • the invention is not limited thereto, and another wide bandgap semiconductor element such as a GaN-MOSFET or a diamond-MOSFET may be applied instead.
  • flyback diodes such as a Si-flyback diode, an SiC-flyback diode, an SiC-Schottky barrier diode, a GaN-flyback diode, a GaN Schottky barrier diode, a diamond-flyback diode, or a diamond-Schottky barrier diode.

Abstract

The semiconductor device includes a switching arm unit in which first and second wide bandgap semiconductor elements, each having a body diode, are connected in series between a positive line and a negative line; a current detecting unit that detects a current in at least a wide bandgap semiconductor element in which a flyback current flows; and a semiconductor element driving unit that drives the first and second wide bandgap semiconductor elements. When driving one of the wide bandgap semiconductor elements, the semiconductor element driving unit determines, by referring to a fault inhibiting characteristic curve, whether a flyback current detection value of the other wide bandgap semiconductor elements falls within a fault growth region or a fault inhibiting region, and when a result of the determination indicates that the flyback current detection value is within the fault growth region, inhibits a current flowing in the one wide bandgap semiconductor element.

Description

    BACKGROUND OF THE INVENTION
  • Technical Field
  • The present invention relates to a semiconductor device in which a switching arm unit is constituted by connecting at least a first wide bandgap semiconductor element and a second wide bandgap semiconductor element in series, and to a method of driving the semiconductor device.
  • Background Art
  • This type of semiconductor device has been proposed in the form of a power conversion device that includes, for example, an inverter circuit configured to perform synchronous rectification using six switching elements, with a SiC-MOSFET, which is a unipolar element employing a wide bandgap semiconductor, being used for each switching element and the synchronous rectification being performed by using parasitic diodes of the SiC-MOSFETs as flyback diodes (see Patent Document 1, for example).
    • RELATED ART DOCUMENT Patent Document
    • Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2009-183115
    SUMMARY OF THE INVENTION
  • However, the power conversion device according to the above-described Patent Document 1 has a problem in that stacking faults grow when a current flows in the body diode, which is the parasitic diode, of the SiC-MOSFET, thereby causing an on-state resistance in the SiC-MOSFET to rise and increasing conduction loss.
  • In light of the problem with the conventional example, it is an object of the present invention to provide a semiconductor device capable of reducing conduction loss by sufficiently inhibiting stacking faults from arising in a wide bandgap semiconductor element, and to provide a method of driving the semiconductor device. Accordingly, the present invention is directed to a scheme that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
  • Additional or separate features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
  • To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a semiconductor device, including: a switching arm unit including a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the switching arm unit having a node between the first and second wide bandgap semiconductor elements that is configured to be connected to a load; a current detecting unit that detects a current in the second wide bandgap semiconductor element that indicates a flyback current flowing in the second wide bandgap semiconductor element, the flyback current being generated as a result of the load been driven by the first wide bandgap semiconductor element; a driving unit that drives the first wide bandgap semiconductor element and the second wide bandgap semiconductor element; and a memory storing a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region for a crystalline semiconductor constituting the second wide bandgap semiconductor element, wherein the driving unit determines, by referring to the fault inhibiting characteristic curve, whether the detected current of the second wide bandgap semiconductor element falls within the fault growth region or within the fault inhibiting region, and when a result of the determination indicates that the detected current is within the fault growth region, the driving unit outputs, to the first wide bandgap semiconductor element, a driving signal that reduces a current flowing in the first wide bandgap semiconductor element when driving the load therethrough so that a resultant current detected by the current detecting unit falls within the fault inhibiting region.
  • In another aspect, the present disclosure provides a method of driving a semiconductor device, the semiconductor device including a switching arm unit having a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the method including: a step of detecting a flyback current in the second wide bandgap semiconductor element; and a step of determining, by referring to a fault inhibiting characteristic curve expressing a border between a fault growth region and a fault inhibiting region, whether the detected flyback current in the second wide bandgap semiconductor element is within the fault growth region or within the fault inhibiting region.
  • In another aspect, the present disclosure provides a method of driving a semiconductor device, the semiconductor device including: a switching arm unit including: a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series, a first diode connected in reverse-parallel to the first wide bandgap semiconductor element, and a second diode connected in reverse-parallel to the second wide bandgap semiconductor element; and a memory storing: a characteristic line map, having a plurality of characteristic lines, each of which expresses, using a flyback current flowing in the body diode of the second wide bandgap semiconductor element as a parameter, a relationship between a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of the diode connected in reverse-parallel to the second wide bandgap semiconductor element and a pulsewidth of a pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element at a beginning of the flyback current, the relationship inhibiting occurrence of stacking fault in a crystalline semiconductor constituting the second wide bandgap semiconductor element; and a slope characteristic line map that indicates, as a function of a maximum current of the flyback current, a permissible range of slopes from slopes of the characteristic lines in the characteristic line map within which occurrence of the stacking fault in the crystalline semiconductor constituting the second wide bandgap semiconductor element is inhibited, the method including: selecting a slope of a characteristic line from the permissible range of slopes indicated in the slope characteristic line map on the basis of the maximum current of the flyback current; determining a desired pulsewidth of the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element in accordance with the selected slope of the characteristic line; and driving the first and second wide bandgap semiconductor elements in such a manner as to generate the desired pulsewidth for the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element, thereby inhibiting occurrence of the stacking fault in the crystalline semiconductor constituting the second wide bandgap semiconductor element.
  • In another aspect, the present disclosure provides a method of driving a semiconductor device, the semiconductor device including a switching arm unit including: a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series, a first diode connected in reverse-parallel to the first wide bandgap semiconductor element, and a second diode connected in reverse-parallel to the second wide bandgap semiconductor element, the method including: a step of calculating a flyback current in a body diode of the second wide bandgap semiconductor element from a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of the diode connected in reverse-parallel to the second wide bandgap semiconductor element and a detected current flowing in the second wide bandgap semiconductor element; a step of determining, by referring to a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region on a basis of the calculated flyback current, a desired pulsewidth of a pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element at a beginning of the flyback current that falls within the fault inhibiting region; driving the first and second wide bandgap semiconductor elements in such a manner as to generate the determined desired pulsewidth for the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element, thereby inhibiting occurrence of stacking fault in a crystalline semiconductor constituting the second wide bandgap semiconductor element.
  • According to an aspect of the present invention, stacking faults arising in a wide bandgap semiconductor element can be sufficiently inhibited, and conduction loss can be reduced.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a circuit diagram illustrating the overall configuration of a power conversion device including a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram illustrating an example of a semiconductor device according to the present invention.
  • FIG. 3 is a block diagram illustrating in detail the configuration of a processing unit illustrated in FIG. 2.
  • FIG. 4 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth used in the processing unit and a drain current.
  • FIG. 5 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth and a body diode current.
  • FIG. 6 is an equivalent circuit diagram of a switching arm.
  • FIG. 7 is a schematic diagram illustrating a current path in the case where a switching arm is constituted by semiconductor modules.
  • FIG. 8 is a flowchart illustrating an example of a sequence of a gate driving process executed by the processing unit illustrated in FIG. 2.
  • FIG. 9 is a flowchart illustrating an example of a sequence of a dead time detection process executed by the processing unit illustrated in FIG. 2.
  • FIGS. 10A to 10G are timing charts illustrating operating waveforms of the semiconductor device according to Embodiment 1 of the present invention.
  • FIGS. 11A to 11C are schematic diagrams illustrating current paths in respective modes of a switching arm, where 11A indicates a mode MD1, 11B indicates a mode MD2, and 11C indicates a mode MD3.
  • FIG. 12 is a characteristic line map illustrating a relationship between a pulsewidth and an inductance ratio used in Embodiment 2 of the present invention.
  • FIG. 13 is a fault inhibiting characteristic line map illustrating a relationship between a maximum current and the slope of a threshold curve, based on FIG. 12.
  • FIG. 14 is a body diode current calculation characteristic line map illustrating a relationship between a body diode current and an inductance ratio used in Embodiment 3 of the present invention.
  • FIG. 15 is a fault inhibiting characteristic map illustrating a relationship between a pulsewidth and a body diode current used in Embodiment 3.
    •  DETAILED DESCRIPTION OF EMBODIMENTS
  • A semiconductor device and driving method thereof according to an embodiment of the present invention will be described with reference to the drawings. The present embodiment will describe a voltage-driven semiconductor element as an example of a semiconductor element and a power conversion device as an example of the semiconductor device. First, a power conversion device 10 including the semiconductor device according to the present embodiment will be described using FIG. 1.
  • As illustrated in FIG. 1, the power conversion device 10 is connected to a three-phase AC power source 14. The power conversion device 10 includes a rectifying circuit 15 that performs full-wave rectification of three-phase AC power inputted from the three-phase AC power source 14, and a smoothing capacitor 16 that smoothes the power rectified by the rectifying circuit 15. Although not illustrated, the rectifying circuit 15 is constituted by six diodes in a full-bridge connection or six switching elements in a full-bridge connection. A positive line Lp is connected to a positive output terminal of the rectifying circuit 15, and a negative line Ln is connected to a negative output terminal of the rectifying circuit 15. The smoothing capacitor 16 is connected between the positive line Lp and the negative line Ln.
  • The power conversion device 10 further includes semiconductor modules 2 a, 2 c, and 2 e that constitute an upper arm unit connected to the positive-side line Lp and semiconductor modules 2 b, 2 d, and 2 f that constitute a lower arm unit connected to the negative-side line Ln.
  • The semiconductor module 2 a and the semiconductor module 2 b constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln. The semiconductor module 2 c and the semiconductor module 2 d constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln. The semiconductor module 2 e and the semiconductor module 2 f constitute a switching arm unit connected in series between the positive line Lp and the negative line Ln.
  • A connection point between the semiconductor module 2 a and the semiconductor module 2 b, a connection point between the semiconductor module 2 c and the semiconductor module 2 d, and a connection point between the semiconductor module 2 e and the semiconductor module 2 f are connected to a three-phase electric motor 17 serving as an inductive load.
  • The semiconductor module 2 a includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 a, a body diode 4 a parasitic to the MOSFET 3 a, and a free-wheeling Schottky barrier diode 5 a connected in reverse parallel to the MOSFET 3 a, and constitutes an arm unit. The respective cathodes of the body diode 4 a and the Schottky barrier diode 5 a are connected to a drain terminal D of the MOSFET 3 a, and the respective anodes of the body diode 4 a and the Schottky barrier diode 5 a are connected to a source terminal S of the MOSFET 3 a.
  • Like the semiconductor module 2 a, the semiconductor module 2 b includes an N-type SiC-MOSFET 3 b (an example of a second wide bandgap semiconductor element), a body diode 4 b, and a Schottky barrier diode 5 b, and constitutes an arm unit.
  • Like the semiconductor modules 2 a and 2 b, the semiconductor module 2 c also includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 c, a body diode 4 c, and a Schottky barrier diode 5 c, and constitutes an arm unit.
  • The semiconductor module 2 d also includes an N-type SiC-MOSFET (an example of a second wide bandgap semiconductor element) 3 d, a body diode 4 d, and a Schottky barrier diode 5 d, and constitutes an arm unit.
  • The semiconductor module 2 e also includes an N-type SiC-MOSFET (an example of a first wide bandgap semiconductor element) 3 e, a body diode 4 e, and a Schottky barrier diode 5 e, and constitutes an arm unit.
  • The semiconductor module 2 f also includes an N-type SiC-MOSFET (an example of a second wide bandgap semiconductor element) 3 f, a body diode 4 f, and a Schottky barrier diode 5 f, and constitutes an arm unit.
  • The SiC- MOSFETs 3 a, 3 b, 3 c, 3 d, 3 e, and 3 f are unipolar power semiconductor elements, and are bidirectional. Here, the wide bandgap semiconductor elements that constitute the arm units are not limited to SiC-based semiconductor elements, and may instead be wide bandgap semiconductor elements having at least one of gallium nitride and diamond as their primary material. Additionally, the Schottky barrier diodes 5 a to 5 f are not limited to Si-based semiconductor elements, and may instead be wide bandgap semiconductor elements having at least one of silicon carbide, gallium nitride, and diamond as their primary material. A wide bandgap semiconductor element has high-temperature and high-voltage performance superior to an Si element, and has low loss.
  • Additionally, the power conversion device 10 includes a gate driving unit (GDU) 1 a that controls a switching operation of the semiconductor module 2 a, a gate driving unit (GDU) 1 b that controls a switching operation of the semiconductor module 2 b, a gate driving unit (GDU) 1 c that controls a switching operation of the semiconductor module 2 c, a gate driving unit (GDU) 1 d that controls a switching operation of the semiconductor module 2 d, a gate driving unit (GDU) 1 e that controls a switching operation of the semiconductor module 2 e, and a gate driving unit (GDU) 1 f that controls a switching operation of the semiconductor module 2 f.
  • Output terminals of the gate driving units 1 a to 1 f are connected to corresponding gate terminals G serving as control terminals of the SiC-MOSFETs 3 a to 3 f.
  • The semiconductor module 2 a and the semiconductor module 2 b constitute a U-phase switching arm unit, for example; the semiconductor module 2 c and the semiconductor module 2 d constitute a V-phase switching arm unit, for example; and the semiconductor module 2 e and the semiconductor module 2 f constitute a W-phase switching arm unit, for example. Accordingly, an inverter circuit is constituted by a three-phase full bridge circuit in which the U-phase switching arm unit, the V-phase switching arm unit, and the W-phase switching arm unit are connected in parallel, the gate driving units 1 a and 1 b that control switching operations of the U-phase arm, the gate driving units 1 c and 1 d that control switching operations of the V-phase arm, and the gate driving units 1 e and 1 f that control switching operations of the W-phase arm.
  • Next, the semiconductor device according to the present embodiment will be described using FIGS. 2 to 5, with reference to FIG. 1, using the U-phase switching arm unit as an example. Note that the V-phase switching arm unit and the W-phase switching arm unit have the same configuration as the U-phase switching arm unit.
  • As illustrated in FIG. 2, the gate driving unit 1 a includes a current sensor 21 a serving as a current detecting unit that detects a drain current (an example of a main current) Id(b) flowing in the SiC-MOSFET 3 b, which corresponds to a second wide bandgap semiconductor element, and a gate driving unit 22 a serving as a semiconductor element driving unit that drives the SiC-MOSFET 3 a, which corresponds to a first wide bandgap semiconductor element, in response to the input of a current value of the drain current Id(b) detected by the current sensor 21 a.
  • The gate driving unit 22 a includes a processing unit 23 a serving as a first driving unit, constituted by a microcomputer, for example, inputted with an upper arm control signal CS(a) from the exterior.
  • The drain current Id(b), detected by the current sensor 21 a, of the SiC-MOSFET 3 b corresponding to the second wide bandgap semiconductor element is inputted to the processing unit 23 a.
  • Meanwhile, as illustrated in FIG. 3, the processing unit 23 a includes a central processing unit (CPU) 25 a. A RAM 26 a and a ROM 27 a, as well as an input-side interface circuit 28 a, an A/D conversion circuit 24 a, and an output-side interface circuit 29 a, are connected to the central processing unit 25 a by a system bus. A gate driving signal Sgd(a) outputted from the output-side interface circuit 29 a is supplied to a base of a first switching element 30U constituted by an NPN-type bipolar transistor and a base of a second switching element 30D constituted by a PNP-type bipolar transistor, which are connected in series between a positive pole source P1 and a negative pole source N1 of an AC power source. A connection point between the first switching element 30U and the second switching element 30D is connected to a gate of the SiC-MOSFET 3 a via a gate resistance Rg.
  • A fault inhibiting characteristic map is stored in the ROM 28 b in advance. As illustrated in FIG. 4, this fault inhibiting characteristic map takes a pulsewidth of a pulse-form current produced when a flyback current begins flowing in the body diode 4 b of the SiC-MOSFET 3 b serving as a second wide bandgap semiconductor element on the horizontal axis, and the drain current Id(b) resulting from the flyback current on the horizontal axis; a hyperbolic fault inhibiting characteristic curve L1 indicating a border between a fault growth region 31 and a fault inhibiting region 32 of the SiC-MOSFET is set.
  • In this fault inhibiting characteristic map, a pulsewidth PW is set to approximately 30% of a dead time Tdt between the control signal CS(a) of the SiC-MOSFET 3 a serving as the first wide bandgap semiconductor element and a control signal CS(b) of the SiC-MOSFET 3 b, and thus detecting the dead time Tdt makes it possible to calculate the pulsewidth PW (=0.3×Tdt).
  • This fault inhibiting characteristic map is obtained by converting a flyback current IBD of the body diode 4 b as indicated in the fault inhibiting characteristic map illustrated in FIG. 5, which represents a relationship between the pulsewidth and the flyback current of the body diode 4 b, into the drain current Id(b). In the fault inhibiting characteristic map illustrated in FIG. 5, when the pulsewidth takes the horizontal axis and the flyback current IBD of the body diode 4 b takes the vertical axis, a hyperbolic fault inhibiting characteristic curve Ld indicating a border between a fault growth region and a fault inhibiting region is set.
  • A region on an origin (0,0) side of the fault inhibiting characteristic line Ld corresponds to a fault inhibiting region ADi, whereas a side of the fault inhibiting characteristic line Ld opposite from the origin (0,0) corresponds to a fault growth region ADg. The fault inhibiting characteristic line Ld is derived from the results of experiments, simulations, and so on.
  • Accordingly, in FIG. 5, when the pulsewidth is PW1=10 (μsec), for example, a flyback current IBD of the body diode 4 b no greater than IBD1=77 (A/cm2) falls within the fault inhibiting region ADi. Accordingly, stacking faults are inhibited from growing, the on-state resistance of the SiC-MOSFET 3 b is inhibited from rising, and conduction loss is inhibited from increasing in the case where a flyback current IBD of less than or equal to IBD1=77 (A/cm2) flows in the body diode 4 b.
  • On the other hand, when the pulsewidth is PW1=10 (μsec), a flyback current IBD of more than IBD1=77 (A/cm2) falls within the fault growth region ADg. Accordingly, stacking faults grow, the on-state resistance of the SiC-MOSFET 3 b rises, and conduction loss increases when a flyback current IBD exceeding IBD1=77 (A/cm2) flows in the body diode 4 b.
  • Accordingly, by driving the SiC-MOSFET 3 a on the upper arm side so that coordinates expressed by the pulsewidth and the flyback current IBD of the body diode 4 b are within the fault inhibiting region ADi, energy stored in a U-phase coil Lu of the three-phase electric motor 17 while the SiC-MOSFET 3 a is turned on can inhibit flyback current flowing in the body diode 4 b on the lower arm side when the SiC-MOSFET 3 a turns off, making it possible to control the driving while inhibiting the growth of stacking faults.
  • As expressed by the following Formula (1), of the flyback current IBD of the body diode 4 b and the drain current Id(b), the drain current Id(b) is a value obtained by multiplying an inductance ratio LMOS/LSBD between a flyback inductance LMOS of the SiC-MOSFET 3 a and a flyback inductance LSBD of the Schottky barrier diode 5 a by the flyback current IBD of the body diode.

  • Id(b)=(L MOS /L SBD)×I BD0.4  (1)
  • Accordingly, the drain current Id(b) (A/cm2) is calculated from Formula (1) and the fault inhibiting characteristic map illustrated in FIG. 4 is formed.
  • Here, when the SiC-MOSFET 3 a turns off and a flyback current flows in the SiC-MOSFET 3 b corresponding to the lower arm, an equivalent circuit is established as illustrated in FIG. 6; the flyback current Id(b) from the U-phase coil Lu of the three-phase electric motor 17 traverses the inductance LMOS, traverses the body diode 4 b and returns to the U-phase coil Lu, and traverses the inductance LBD, traverses the Schottky barrier diode 5 b, and returns to the U-phase coil Lu.
  • A current path in the modules is as indicated in FIG. 7 when the SiC-MOSFET 3 a is turned off. That is, the semiconductor module 2 a is formed, for example, by surface-mounting a SiC-MOSFET chip 42 a on an upper surface of a substrate 41 a in which a conductive plate portion is bonded to an insulative substrate as with a DCB (Direct Copper Bond) substrate, with a drain electrode facing the substrate. In the semiconductor module 2 b, a SiC-MOSFET chip 42 b and a Schottky barrier diode chip 43 b are surface-mounted on an upper surface of a substrate 41 b that is the same type of substrate as the substrate 41 a, with a drain of the SiC-MOSFET chip 42 b and a cathode of the Schottky barrier diode chip 43 b separated by a prescribed distance Lc.
  • A printed board 44 is disposed above the substrates 41 a and 41 b; the printed board 44 is electrically connected to a source electrode and a gate electrode formed on upper surfaces of the SiC-MOSFET chips 42 a and 42 b and an anode electrode formed on an upper surface of the Schottky barrier diode 43 b by conductive pins 45. Additionally, the substrate 41 a of the semiconductor module 2 a and the printed board 44 are electrically connected by a conductive pin 46. Furthermore, a positive terminal pin 47 connected to the positive line Lp is connected to the upper surface of the substrate 41 a of the semiconductor module 2 a, and an output terminal pin 48 connected to the U-phase coil Lu of the three-phase electric motor 17 is connected to the upper surface of the substrate 41 b of the semiconductor module 2 b.
  • When the SiC-MOSFET 3 a of the semiconductor module 2 a turns on, a turn-on current path is formed as indicated by the dotted line in FIG. 7, in which a current supplied from the positive terminal pin 47 traverses the conductive plate portion of the substrate 41 a, the drain-source of the SiC-MOSFET 3 a, the conductive pin 45, a printed wiring of the printed board 44, and proceeds toward the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48.
  • On the other hand, when the SiC-MOSFET 3 a of the semiconductor module 2 a turns off, two types of turn-off current paths, or in other words, flyback current paths, are formed as indicated by the solid lines in FIG. 7, namely a first current path IL1 in which a flyback current supplied from another end of the U-phase coil Lu of the three-phase electric motor 17 traverses the body diode 4 b of the MOSFET 3 b, and a second current path IL2 in which the stated flyback current traverses the Schottky barrier diode 5 b.
  • The first current path IL1 extends from the substrate 41 a of the semiconductor module 2 a to the printed board 44 through the conductive pin 46. The current transmitted to the printed board 44 follows a current path that traverses the printed board, the conductive pins 45, and traverses the drain from the source of the SiC-MOSFET 3 b of the semiconductor module 2 b, and furthermore traverses the conductive plate portion of the substrate 41 b and returns to the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48.
  • The second current path IL2 is a current path in which the current is transmitted from the substrate 41 a of the semiconductor module 2 a to the printed board 44 through the conductive pin 46, traverses the printed wiring of the printed board, traverses the conductive pins 45 and travels from the anode to the cathode of the Schottky barrier diode 5 b of the semiconductor module 2 b, furthermore traverses the conductive plate portion of the substrate 41 b, and returns to the U-phase coil Lu of the three-phase electric motor 17 from the output terminal pin 48.
  • Here, of the flyback current paths, an inductance of the first current path IL1 traversing the SiC-MOSFET 3 b is a module inductance MLMOS, and an inductance of the second current path traversing the Schottky barrier diode 5 b is a module inductance MLSBD.
  • Assuming a chip inductance of the SiC-MOSFET 3 b itself is represented by CMOSL, a chip inductance of the Schottky barrier diode 5 b itself is represented by CLSBD, and furthermore, an external inductance is represented by BLMS, the inductance LMOS of the SiC-MOSFET 3 a and the inductance LSBD of the Schottky barrier diode 5 a can be expressed through the following Formula (2) and Formula (3).

  • L MOS =B LMS +M LMOS +C LMOS  (2)

  • L SBD =B LMS +M LSBD +C LSBD  (3)
  • The module inductance MLMOS is determined by the position in the semiconductor module 2 b where the SiC-MOSFET chip 42 b is disposed on the conductive plate portion of the substrate 41 b, and the number, thickness, and so on of the conductive pins 45; likewise, the module inductance MLSBD is determined by the position in the semiconductor module 2 b where the Schottky barrier diode chip 43 b is disposed on the conductive plate portion of the substrate 41 b, and the number, thickness, and so on of the conductive pins 45.
  • Accordingly, the module inductances MLMOS and MLSBD are determined at the design stage of the semiconductor module 2 b. Here, the module inductance MLMOS is no greater than 10 nH, and the module inductance MLSBD is also no greater than 10 nH. Additionally, the external inductance BLMS is no greater than 10 nH, the chip inductance CLMOS is no greater than 20 nH, and the chip inductance CLSBD is no greater than 5 nH.
  • Accordingly, the inductance LMOS is a maximum of 10 nH+10 nH+20 nH=40 nH, and the inductance LSBD is a maximum of 10 nH+10 nH+5 nH=25 nH.
  • Accordingly, assuming that the inductance LMOS is 40 nH and the inductance LSBD is 10 nH, the inductance ratio LMOS/LSBD=40 nH/10 nH=4; in the case where the drain current Id(b) is 50 A, 50AX(LMOS/(LMOS+LSBD)=ISBD, and a current of 40 A flows on the SBD side and 10 A in the MOS body diode.
  • As a result, the fault inhibiting characteristic map illustrated in FIG. 4, which takes the drain current Id(b) on the vertical axis, has its vertical axis extended to four times the vertical axis in the fault inhibiting characteristic map illustrated in FIG. 5, which takes the flyback current IBD of the body diode 4 b on the vertical axis.
  • Then, by setting 30% of the dead time Tdt between the control signal CS(a) that drives the SiC-MOSFET 3 a and the control signal CS(b) that drives the SiC-MOSFET 3 b as the pulsewidth PW, the pulsewidth PW can be detected without actually measuring the pulsewidth of the body diode 4 b; whether the drain current Id(b) falls within the fault inhibiting region ADi or falls within the fault growth region ADg can be determined with ease from the detected pulsewidth PW and the drain current Id(b), detected by the current sensor 21 a, of the SiC-MOSFET 3 b serving as the second wide bandgap semiconductor element.
  • Accordingly, by the central processing unit 25 a of the processing unit 23 a executing a gate driving process illustrated in FIG. 8, the driving of the SiC-MOSFET 3 a can be controlled so that the pulsewidth PW and the flyback current IBD of the body diode 4 b fall within the fault inhibiting region ADi.
  • That is, in the gate driving process, as illustrated in FIG. 8, it is first determined, in step S1, whether or not the SiC-MOSFET 3 a has transitioned from a mode MD1, indicated in FIGS. 10A to 10G, in which the SiC-MOSFET remains turned on, to a mode MD2, indicated in FIGS. 10A to 10G, in which the SiC-MOSFET is turned off. When the SiC-MOSFET has not yet transitioned to the mode MD2, the process stands by until the transition is made. When the SiC-MOSFET has transitioned to the mode MD2, the process moves to step S2, where a negative drain current Id(b) produced by the flyback current detected by the current sensor 21 a is loaded. The process then moves to step S3.
  • In step S3, it is determined whether or not the drain current Id(b) has reached a peak value. When the drain current Id(b) has not reached the peak value, the process stands by until the peak value is reached. When the peak value is reached, the process moves to step S4, where the peak value is temporarily stored in the RAM 26 a, for example, after which the process moves to step S5.
  • In step S5, the dead time Tdt, detected by a dead time detection process that detects the dead time Tdt between the control signal CS(a) and the control signal CS(b), is loaded. The process then moves to step S6, where 30% of the dead time Tdt is set to the pulsewidth PW (=0.3× Tdt), after which the process moves to step S7.
  • In step S7, the fault characteristics map illustrated in FIG. 4 is loaded from the ROM 27 a. The process then moves to step S8, where it is judged whether coordinates corresponding to the peak value of the drain current Id(b) and the pulsewidth PW fall within the fault inhibiting region ADi or fall within the fault growth region ADg by referring to the fault characteristics map on the basis of the peak value of the drain current Id(b) and the pulsewidth PW. The process then moves to step S9.
  • In step S9, it is determined, as a result of the judgment, whether or not the coordinates fall within the fault inhibiting region ADi. In the case where the coordinates fall within the fault inhibiting region ADi, the process moves directly to step S12 without calculating a corrected duty ratio for the control signal CS(a). In the case where the result of the judgment indicates that the coordinates fall within the fault growth region ADg, the process moves to step S10, where a corrected drain current IAd(b) for the SiC-MOSFET 3 b that falls within the fault inhibiting region ADi at the same pulsewidth PW is calculated. The process then moves to step S11.
  • In step S11, a corrected duty ratio DA(a) of the control signal CS(a), corresponding to the calculated corrected drain current IAd(b), is calculated, and the process then moves to step S12.
  • In step S12, it is determined whether or not the SiC-MOSFET 3 a in the upper arm has transitioned from a mode MD4, in which the SiC-MOSFET is turned off, to the mode MD1, in which the SiC-MOSFET is turned on. When the SiC-MOSFET has not yet transitioned to the mode MD1, the process stands by until the transition occurs, and when the SiC-MOSFET has transited to the mode MD1, the process moves to step S13.
  • In step S13, it is determined whether or not the corrected duty ratio DA(a) is stored in a corrected duty ratio storage region of the RAM 26 a. When the corrected duty ratio DA(a) is stored, the process moves to step S14, where a gate driving signal of a pulsewidth based on the corrected duty ratio DA(a) is outputted instead of the control signal CS(a), and the process then returns to step S1. When the corrected duty ratio DA(a) is not stored, the control signal CS(a) is outputted as-is as the gate driving signal, after which the process returns to step S1.
  • The central processing unit 25 a of the processing unit 23 a executes the dead time detection process. As illustrated in FIG. 9, this dead time detection process is executed as a timer interrupt process every prescribed amount of time (100 nsec, for example). First, in step S21, the control signal CS(a) is loaded. The process then moves to step S22, where it is determined whether or not the control signal CS(a) is in an on state. When the control signal CS(a) is in an off state, the timer interrupt process is ended directly and the process returns to a prescribed main program, whereas when the control signal CS(a) is in an on state, the process moves to step S23.
  • In step S23, it is determined whether or not the previous value of the control signal CS(a) was an off state. When the previous value was an on state, it is determined that the on state is being maintained, the timer interrupt process ends directly and the process returns to the prescribed main program.
  • When the result of the determination made in step S23 indicates that the previous value of the control signal CS(a) was in an off state, it is determined that the state has switched from an off state to an on state, and the process moves to step S24.
  • In step S24, a software timer is reset and the measurement of time is started anew; the process then moves to step S25.
  • In step S25, the control signal CS(b) is loaded, and the process then moves to step S26, where it is determined whether or not the state has changed to an on state. In the case where the control signal CS(b) remains in an off state, the process returns to step S25, whereas when the state has changed to an on state, the process moves to step S27, where the software timer is stopped and the measured time is loaded as the dead time Tdt, after which the process moves to step S28.
  • In step S28, the loaded dead time Tdt is updated and stored in a dead time storage region of the RAM 26 a, after which the timer interrupt process is ended and the process returns to the prescribed main program.
  • In this dead time detection process, the dead time Tdt between the control signal CS(a) and the control signal CS(b) is detected and the detected dead time between the control signal CS(a) and the control signal CS(b) is updated and stored in the dead time storage region of the RAM 26 a every prescribed amount of time, and thus the most recent dead time Tdt is always stored in the dead time storage region of the RAM 26 a.
  • Accordingly, the pulsewidth PW can be calculated on the basis of the most recent dead time in the gate driving process described above with reference to FIG. 8, and by referring to the fault characteristics map on the basis of the calculated pulsewidth PW and the detected drain current Id(b), a gate driving signal can be formed such that the current drain current Id(b) falls within the fault inhibiting region ADi.
  • By controlling the gate of the SiC-MOSFET 3 a, which serves as the first wide bandgap semiconductor element, using this gate driving signal, the electrical energy stored in the U-phase coil Lu of the three-phase electric motor 17 can be controlled to an appropriate value, and the flyback current flowing in the body diode 4 b of the SiC-MOSFET 3 b, which serves as the second wide bandgap semiconductor element, can be controlled to a current value that inhibits the growth of stacking faults.
  • Accordingly, the growth of stacking faults in the SiC-MOSFET 3 b can be inhibited, a rise in the on-state resistance can be inhibited, and an increase in conduction loss can be inhibited.
  • Next, operations performed when applying the gate driving units 1 a and 1 b will be described with respect to one phase of the power conversion device 10 (the U-phase arm, for example), with reference to FIGS. 10A to 10G. Note that the other two phases not described below (the V phase and W phase, for example) also operate in the same manner as this one phase. The operations in the one phase of the power conversion device 10 are divided into three operations, for the mode MD1, the mode MD2, a mode MD3, and the mode MD4.
  • In the operations in mode MD1 from time t11 to time t12 in FIGS. 10A to 10G, the control signal CS(a) inputted to the gate driving unit 1 a of the SiC-MOSFET 3 a is at high level, as indicated in FIG. 10A, and the control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b is at low level, as indicated in FIG. 10B.
  • Accordingly, as indicated in FIG. 10C, a gate-source voltage Vgs(a) of the MOSFET 3 a is the same voltage as a first power source voltage P1, and as indicated in FIG. 10D, a gate-source voltage Vgs(b) of the SiC-MOSFET 3 b is the same voltage as a negative voltage N1. Accordingly, as illustrated in FIG. 11A, the SiC-MOSFET 3 a is in an on state, the SiC-MOSFET 3 b is in an off state, and a drain current Id(a) of the SiC-MOSFET 3 a flows in the U-phase coil of the three-phase electric motor 17 (see FIG. 1) as an output current Iu. The drain current Id(a) of the SiC-MOSFET 3 a therefore increases as indicated in FIG. 10F, and the output current Iu gradually increases as indicated in FIG. 10E. The output current Iu has a positive value.
  • In the mode MD1, the control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b is at low level, as indicated in FIG. 10B, and thus the first switching element 30U is in an off state and the second switching element 30D is in an on state. As a result, the negative voltage N1 is applied to the gate terminal G of the SiC-MOSFET 3 b. A reference potential M (0 (V), for example) is being applied to the source terminal S of the SiC-MOSFET 3 b, and thus the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b matches the negative voltage N1, as indicated in FIG. 10D. Accordingly, a forward bias voltage is not outputted to the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b, and the SiC-MOSFET 3 b remains in an off state.
  • The operations for the one phase of the power conversion device then change from the mode MD1 to the mode MD2 at time t12. The mode MD2 is a mode that turns off the SiC-MOSFET 3 a and puts both the SiC- MOSFETs 3 a and 3 b in an off state in order to form a dead time that prevents the SiC-MOSFET 3 a and the SiC-MOSFET 3 b from being in an on state simultaneously and a through current flowing between the SiC-MOSFET 3 a and the SiC-MOSFET 3 b. At this time, the control signal CS(a) inputted to the gate driving unit 1 a of the SiC-MOSFET 3 a switches from high level to low level, as indicated in FIG. 10A, and the control signal CS(b) inputted to the gate driving unit 1 b of the SiC-MOSFET 3 b stays at low level, as indicated in FIG. 10B.
  • In the mode MD2, the gate-source voltage Vgs(a) of the SiC-MOSFET 3 a and the gate-source voltage Vgs(b) of the SiC-MOSFET 3 b are at the same voltage as the negative voltage N1, as indicated in FIGS. 10C and D. Accordingly, as illustrated in FIG. 11B, the SiC-MOSFET 3 a switches from an on state to a turned-off state, and the SiC-MOSFET 3 b remains in an off state. The SiC- MOSFETs 3 a and 3 b are thus both in an off state.
  • At this time, a flyback current from the three-phase electric motor 17 flows to the three-phase electric motor 17, through the body diode 4 b and the Schottky barrier diode 5 b of the semiconductor module 2 b, as the output current Iu, as indicated by the broken line arrow in FIG. 11B. This flyback current is a current based on a discharge of an electric charge accumulated in the coil of the three-phase electric motor 17, and thus as indicated in FIG. 10G, the drain current Id(b), which corresponds to the current value of the flyback current, gradually approaches 0 (A) after an overshoot has temporarily arisen immediately after entering the mode MD2. The current value of the output current Iu gradually drops in response to this, as indicated in FIG. 10E. Additionally, the SiC-MOSFET 3 a is in an off state in the mode MD2, and thus the drain current Id(a) of the SiC-MOSFET 3 a is 0 (A), as indicated in FIG. 10F.
  • In this manner, upon transitioning from the mode MD 1 to the mode MD2, the central processing unit 25 a of the processing unit 23 a in the gate driving unit 1 a executes the gate driving process illustrated in FIG. 8 and the dead time detection process illustrated in FIG. 9, and thus the dead time Tdt between the control signal CS(a) and the control signal CS(b) can be detected and continually kept updated in the dead time storage region of the RAM 26 a through the dead time detection process, as described above.
  • Meanwhile, the pulsewidth PW can be calculated on the basis of the most recent dead time in the gate driving process, and by referring to the fault characteristics map on the basis of the calculated pulsewidth PW and the detected drain current Id(b), the gate driving signal of the SiC-MOSFET 3 a can be formed such that the current drain current Id(b) falls within the fault inhibiting region ADi.
  • In the case where the drain current Id(b) of the SiC-MOSFET 3 b is within the fault growth region ADg, the corrected duty ratio DA(a) is calculated so as to reduce the drain current Id(a) of the SiC-MOSFET 3 a. Upon transitioning from the mode MD4 to the mode MD1, the drain current Id(a) is reduced and the electrical energy stored in the U-phase coil Lu of the three-phase electric motor 17 is reduced by controlling the gate of the SiC-MOSFET 3 a in the upper arm according to the corrected duty ratio DA(a).
  • Accordingly, in the next transition from the mode MD 1 to the mode MD2, the drain current Id(b), which is the flyback current flowing in the body diode 4 b in the lower arm, is reduced and controlled to a flyback current value that falls within the fault inhibiting region ADi.
  • By controlling the SiC-MOSFET 3 a in the upper arm according to the flyback current in the lower arm in this manner, the flyback current flowing in the body diode 4 b of the SiC-MOSFET 3 b in the lower arm is inhibited and an increase in stacking faults in the SiC-MOSFET 3 b is inhibited, which in turn makes it possible to inhibit a rise in the on-state resistance of the SiC-MOSFET 3 b and inhibit an increase in conduction loss.
  • Note that upon transitioning from the mode MD2 to the mode MD3, in which the SiC-MOSFET 3 b is in a turned-on state, the SiC-MOSFET 3 b enters an on state, and a flyback current also flows through the SiC-MOSFET 3 b. The on-state resistances of the SiC-MOSFET 3 b, the body diode 4 b, and the Schottky barrier diode 5 b become parallel, and thus the on-state resistance can be reduced and conduction loss can be reduced.
  • In the mode MD3, electrons flow through the channel of the SiC-MOSFET 3 b. At this time, electron holes entering from the source side do not combine with the electrons, and thus no degradation in the on voltage of the body diode 4 b occurs due to recombination energy.
  • Furthermore, upon transitioning from the mode MD3 to the mode MD4, a dead time period is entered again, resulting in the SiC-MOSFET 3 a in the upper arm and the SiC-MOSFET 3 b in the lower arm both entering an off state. As in the mode MD2, a flyback current is distributed between the body diode 4 b and the Schottky barrier diode 5 b at an on-state voltage ratio between the two in the mode MD4. The on-state voltage ratio is higher than a transient on-state voltage ratio of the mode MD2, and the flyback current flowing in the body diode 4 b becomes extremely low.
  • According to the present embodiment as described above, in the case where a switching arm unit is formed by connecting a first wide bandgap semiconductor element and a second wide bandgap semiconductor element in series between the positive line Lp and the negative line Ln, the growth of stacking faults in the second wide bandgap semiconductor element can be inhibited with certainty in a dead time period in which the control signal CS(a) goes from on to a turned-off state and the control signal CS(b) stays in an off state. This makes it possible to inhibit a rise in the on-state resistance, inhibit an increase in conduction loss, and prevent degradation of the second wide bandgap semiconductor element.
  • Although the foregoing Embodiment 1 describes a case where the fault characteristics map takes the origin side of the characteristic line Ld as the fault inhibiting region ADi as indicated in FIG. 5, the invention is not limited thereto. If a hyperbolic fault inhibiting characteristic curve Ld1 located on the origin side of the characteristic line Ld indicated in FIG. 5 is set and the region on the inner side of the fault inhibiting characteristic curve Ld1 is taken as the fault inhibiting region ADi, the growth of stacking faults can be prevented with more certainty, and degradation of the SiC- MOSFETs 3 a and 3 b can be prevented with more certainty.
  • Furthermore, although the foregoing Embodiment 1 describes a case where control is carried out for inhibiting the growth of stacking faults in the SiC-MOSFET on the lower arm by controlling the SiC-MOSFET 3 a on the upper arm, the invention is not limited thereto. The same processing may be carried out by the gate driving unit 1 b of the SiC-MOSFET 3 b in the case where a flyback current flows in the body diode 4 a and the Schottky barrier diode 5 a of the SiC-MOSFET 3 a in the upper arm as well.
  • Next, Embodiment 2 of a semiconductor device according to the present invention will be described according to FIGS. 12 and 13.
  • In Embodiment 2, a pulsewidth that inhibits the growth of stacking faults is set according to an inductance ratio that is a ratio between the inductance of a SiC-MOSFET and an inductance of a Schottky barrier diode.
  • In other words, in Embodiment 2, a net inductance LMOSN constituted by only the module inductance MLMOS and the chip inductance CLMOS, excluding the external inductance BLMS from the above-described Formula (2), is set as the inductance of the SiC- MOSFETs 3 a and 3 b. Likewise, a net inductance LSBDN constituted by only the module inductance MLSBD and the chip inductance CLSBD, excluding the external inductance BLMS from the above-described Formula (3), is set as the inductance LSBD of the Schottky barrier diodes 5 a and 5 b. As such, an inductance ratio is expressed as LMOSN/LSBDN.
  • Meanwhile, results of various experiments and simulations carried out by the inventors of the present invention and others indicate that to inhibit the growth of stacking faults, a relationship between the pulsewidth PW and the inductance ratio LMOSN/LSBDN may be set as indicated by the characteristic line map in FIG. 12. That is, the characteristic line map in FIG. 12 takes the pulsewidth PW on the horizontal axis and the inductance ratio on the vertical axis, and a case where a maximum current when the drain currents Id(a) and Id(b) flyback (a total of the flyback current flowing in the body diodes 4 a and 4 b of the SiC- MOSFETs 3 a and 3 b and the flyback current flowing in the Schottky barrier diode 5 a and 5 b; the same applies hereinafter) is 5 A is represented by a characteristic line L31, a case where a maximum current when the drain currents Id(a) and Id(b) flyback is 10 A is represented by a characteristic line L32, and a case where a maximum current when the drain currents Id(a) and Id(b) flyback is 20 A is represented by a characteristic line L33.
  • Here, the characteristic line L33 is represented by a line segment passing through a point (0.8,0.1) and a point (1.4,1.0), the characteristic line L32 is represented by a line segment passing through a point (1.6,0.1) and (2.9,1.0), and the characteristic line L31 is represented by a line segment passing through a point (3.3,0.1) and a point (6,1.0). Sections of the respective characteristic lines L31 to L33 have the same values.
  • As such, when a maximum current value Imax is taken on the horizontal axis and slopes of the characteristic lines L31 to L33 in FIG. 12 are taken on the vertical axis, the maximum current value Imax and the slopes of the characteristic lines L31 to L33 are in a linear relationship represented by a characteristic line L34, which is represented by a line segment passing through a point (0,0) and a point (24,1.600), as illustrated in FIG. 13.
  • A region to the left of the characteristic line L34 is a region in which the slopes of the characteristic lines L31 to L33 in FIG. 12 are greater and a range of selection for the pulsewidth PW narrows, and an effect of inhibiting the growth of stacking faults can be achieved. However, a region to the right of the characteristic line L34 is a region in which the slopes of the characteristic lines L31 to L33 in FIG. 12 are lower and the range of selection for the pulsewidth PW broadens, and is thus a region where the pulsewidth PW that can inhibit the growth of stacking faults is exceeded and stacking faults grow as a result.
  • Accordingly, the region to the left of the characteristic line L34 in FIG. 13 can be taken as the fault inhibiting region, and the region to the right can be taken as the fault growth region.
  • Normally, the chip inductance CLSBD of the Schottky barrier diodes 5 a and 5 b is lower than the chip inductance CLMOS of the SiC- MOSFETs 3 a and 3 b, and with respect to flyback current, it is easy for flyback current to flow in the body diodes 4 a and 4 b of the SiC- MOSFETs 3 a and 3 b. The chip inductances CLMOS and CLSBD are values unique to the semiconductor chip and therefore cannot be adjusted.
  • On the other hand, the module inductance MLMOS of the SiC- MOSFETs 3 a and 3 b and the module inductance MLSBD of the Schottky barrier diodes 5 a and 5 b change at the stage of designing the inductance of wiring within the semiconductor module 2 a, and can therefore be adjusted.
  • As such, an inductance ratio LMOSN/LSBDN in a region that inhibits the growth of stacking faults can be set by adjusting the inductance ratio LMOSN/LSBDN at the design stage of the semiconductor module 2 a.
  • However, the inductance LMOS of the SiC- MOSFETs 3 a and 3 b and the inductance LSBD of the Schottky barrier diodes 5 a and 5 b incorporate the external inductance BLMS, as indicated by Formula (2) and Formula (3) in Embodiment 1.
  • Accordingly, by connecting the external inductance BLMS, even if a pulsewidth PW is set for the semiconductor modules 2 a and 2 b so as to inhibit stacking faults from growing, connecting the external inductance BLMS will cause a total inductance LMOS and LSBD to change, and the SiC- MOSFETs 3 a and 3 b can no longer be driven at a pulsewidth that inhibits stacking faults as intended.
  • As such, in the case where the external inductance BLMS is connected, the inductance ratio LMOS/LSBD is adjusted in the direction where the slopes of the characteristic lines L31 to L33 indicated in FIG. 12 increase, which makes it possible to inhibit the growth of stacking faults, inhibit a rise in the on-state resistance, and inhibit an increase in conduction loss. A method of driving a semiconductor device capable of preventing degradation of the SiC- MOSFETs 3 a and 3 b can be provided as a result.
  • Next, Embodiment 3 of a semiconductor device according to the present invention will be described according to FIGS. 14 and 15.
  • Embodiment 3 focuses on the inductance ratio LMOS/LSBD between the SiC-MOSFET 3 a and the Schottky barrier diode 5 a serving as the upper arm unit and the inductance ratio LMOS/LSBD between the SiC-MOSFET 3 b and the Schottky barrier diode 5 b serving as the lower arm unit in the semiconductor module 2 a that constitutes the power conversion device 10, and makes it possible to drive the SiC- MOSFETs 3 a and 3 b within the fault inhibiting region ADi in which stacking faults do not grow, in the same manner as in Embodiment 1.
  • According to Embodiment 3, a customer who has purchased the power conversion device 10 or the semiconductor modules 2 a to 2 c can use the power conversion device 10 or the semiconductor modules 2 a to 2 c without any degradation arising.
  • In Embodiment 3, a body diode current calculation characteristic line map 41, illustrated in FIG. 14, and a fault characteristic line map 42, illustrated in FIG. 15, are prepared first.
  • As illustrated in FIG. 14, the body diode current calculation characteristic line map 41 takes the body diode current IBD on the horizontal axis and the inductance ratio LMOS/LSBD on the vertical axis, and for example, the drain current Id(b) flowing in the body diode 4 b and the Schottky barrier diode 5 b of the SiC-MOSFET 3 b that constitutes the lower arm unit is set as a parameter. In other words, a slope characteristic line L41 for the case where the drain current Id(b) of the SiC-MOSFET 3 b is Id1 (30 A, for example) and a slope characteristic line L42 for when the drain current Id(b) of the SiC-MOSFET 3 b is Id2, which is lower than Id1 (<Id1) (10 A, for example), are indicated in the body diode current calculation characteristic line map 41. A straight line L43 indicating a recommended inductance ratio LMOSD/LSBDD determined at the design stage of the semiconductor module 2 a is set as well. The module inductance MLMOS, the chip inductance CLMOS, and a recommended inductance LMOSD of the SiC-MOSFET 3 b, determined at the design stage, and the module inductance MLSBD, the chip inductance CLMOS, and a recommended inductance LSBDD of the Schottky barrier diode 5 a, are indicated in this body diode current calculation characteristic line map 41. These items are not limited to being indicated in the body diode current calculation characteristic line map 41, and may be indicated in other papers as well.
  • The fault characteristic line map 42 illustrated in FIG. 15, meanwhile, has the same format as the fault characteristics map described earlier in Embodiment 1 with reference to FIG. 5; the pulsewidth is taken on the horizontal axis, the body diode current IBD of the body diode 4 b is taken on the vertical axis, and a hyperbolic fault inhibiting characteristic curve L44 corresponding to a border between the fault inhibiting region ADi and the fault growth region ADg is indicated.
  • Next, a method of driving the semiconductor device using the body diode current calculation characteristic line map 41 and the fault characteristic line map 42, which prevents degradation by inhibiting stacking faults in the SiC-MOSFET 3 a, will be described.
  • The body diode current calculation characteristic line map 41 and the fault characteristic line map 42 are provided with the product when the power conversion device 10 or the semiconductor module 2 a is sold.
  • When using the power conversion device 10 or the semiconductor modules 2 a to 2 c after purchase, a user of the power conversion device 10 or the semiconductor modules 2 a to 2 c first sets the inductance ratio LMOS/LSBD. Here, the inductance LMOS of the SiC-MOSFET 3 b is expressed as a sum of the external inductance BLMS, the module inductance MLMS, and the chip inductance CLMO, as indicated by Formula (2) in the above-described Embodiment 1.
  • Meanwhile, the inductance LSBD of the Schottky barrier diode 5 b is expressed as a sum of the external inductance BLMS, the module inductance MLSBD, and the chip inductance CLSBD.
  • Of these inductances, only the external inductance BLMS can be set by the user.
  • Accordingly, the inductance ratio LMOS/LSBD can be changed by adjusting the external inductance BLMS. Here, the external inductance BLMS becomes dominant in the inductances LMOS and LSBD as the value of the external inductance BLMS is increased, and thus the inductance ratio LMOS/LSBD approaches “1” as a result. In this case, based on the above-described Formula (1), the drain current Id(b) and the body diode current IBD become equal, and almost no flyback current flows in the Schottky barrier diode 5 b. As such, as the body diode current IBD rises, the width of the fault inhibiting region ADi from the fault characteristic line map 42 indicated in FIG. 15 decreases, and the range of selection for the pulsewidth narrows.
  • As such, it is desirable that the recommended inductance ratio LMOSD/LSBDD expressed by the straight line L43 and set by the manufacturer be set so that the range of selection for the pulsewidth PW in the fault inhibiting region ADi is relatively broad. On the other hand, if the body diode current IBD is set to a low value, the width of the fault inhibiting region ADi from the fault characteristic line map 42 indicated in FIG. 15 will broaden, but it is then necessary to reduce the amount of flyback current that flows. To do so, it is necessary to limit the amount of current supplied to the three-phase electric motor 17 through the SiC-MOSFET 3 a in the arm unit, which forms the basis of the flyback current, and this limits the range of current that can be supplied to the three-phase electric motor.
  • Accordingly, as indicated in the fault characteristic line map 42 in FIG. 15, the recommended inductance LMOSD/LSBDD is set to the characteristic line 43 in the body diode current calculation characteristic line map 41 indicated in FIG. 14 so that a comparatively high value IBD10, which makes it possible to broaden the range of selection of the pulsewidth in the fault inhibiting region ADi, can be obtained for the body diode current IBD.
  • In the case where a user has purchased and uses the power conversion device or the semiconductor modules 2 a to 2 c, and the user wishes to use an external inductance BLMS that deviates from an inductance that satisfies a recommended external inductance at which the external inductance BLMS achieves the recommended inductance ratio LMOS/LSBD, there has conventionally been no way to determine whether or not the fault inhibiting region ADi is adhered to.
  • According to the present embodiment, first, in the case where the external inductance to be used deviates from the recommended external inductance, an inductance L MOS1 of the SiC-MOSFET 3 b is first calculated by adding the external inductance to be used to a total value of the module inductance MLMOS and the chip inductance CLMOS of the SiC-MOSFET 3 b indicated in the body diode current calculation characteristic line map 41 illustrated in FIG. 14. At the same time, an inductance L SBD1 of the Schottky barrier diode 5 b is calculated by adding the external inductance to be used to a total value of the module inductance MLSBD and the chip inductance CLMOS of the Schottky barrier diode 5 a indicated in the body diode current calculation characteristic line map 41.
  • An inductance ratio L MOS1/L SBD1 of the calculated inductance L MOS1 and inductance L SBD1 is then calculated.
  • Next, the calculated inductance ratio L MOS1/L SBD1 is taken on the vertical axis of the body diode current calculation characteristic line map 41 indicated in FIG. 14, and one of the characteristic line L41 and L42 of the drain current Id(b) to be used is selected.
  • Here, assuming the characteristic line L41 has been selected, a body diode current IBD11 is calculated by drawing a horizontal line from the inductance ratio L MOS1/L SBD1 to the selected characteristic line L41, and drawing a vertical line from a point of intersection with the characteristic line L41 toward the horizontal axis, as indicated by the dotted line in FIG. 14.
  • Next, by placing the calculated body diode current IBD11 on the vertical axis of the fault characteristic line map 42 illustrated in FIG. 15, a range up to a point of intersection P (12.5,72) between the vertical axis and the characteristic line L44, indicated by the dotted line in the drawing, is taken as the range of selection of the pulsewidth PW in the fault inhibiting region ADi.
  • Accordingly, using a pulsewidth PW in the selected range in FIG. 15 makes it possible to inhibit the growth of stacking faults in the SiC-MOSFET 3 b, inhibit a rise in the on-state resistance, and inhibit an increase in conduction loss, even in the case where a flyback current flows in the body diode 4 b of the SiC-MOSFET 3 b. This makes it possible to prevent degradation of the SiC- MOSFETs 3 a and 3 b.
  • In this manner, according to Embodiment 3, by setting the inductance ratio LMOS/LSBD, calculating the body diode current IBD from the inductance ratio LMOS/LSBD by referring to the body diode current calculation characteristic line map illustrated in FIG. 14, and referring to the fault inhibiting characteristic line map illustrated in FIG. 15 on the basis of the calculated body diode current IBD, the range of the pulsewidth PW for usage within the fault inhibiting region ADi can be confirmed. As such, a user can, based on the inductance ratio, easily confirm driving conditions that can inhibit the SiC- MOSFETs 3 a and 3 b from degrading.
  • In Embodiment 3 as well, a hyperbolic fault inhibiting characteristic curve L45, indicated by the dotted line in the drawing, which sets a fault inhibiting region with certainty, may be set in the fault inhibiting characteristic line map 42 illustrated in FIG. 15, in the same manner as in the fault inhibiting characteristic map illustrated in FIG. 5.
  • Although Embodiment 3 describes a case where the body diode current calculation characteristic line map 41 and the fault characteristic line map 42 are prepared, the invention is not limited thereto. The body diode current calculation characteristic line map 41 and the fault characteristic line map 42 may be stored as maps in a storage unit such as a ROM in advance, and the external inductance may be inputted into a processing unit such as a microcomputer through an input unit such as a keyboard. The inductance LMOS and LSBD may be calculated and the inductance ratio LMOS/LSBC may be calculated; the body diode current IBD may then be calculated by referring to the body diode current calculation map on the basis of the calculated inductance ratio LMOS/LSBD, and the range of selection of the pulsewidth PW may be calculated by referring to the fault characteristics map on the basis of the calculated body diode current IBD. The range of selection may then be displayed in a monitor or printed using a printer.
  • Although the foregoing embodiments describe a case where a SiC-MOSFET is applied as the wide bandgap semiconductor element, the invention is not limited thereto, and another wide bandgap semiconductor element such as a GaN-MOSFET or a diamond-MOSFET may be applied instead.
  • Additionally, although the foregoing embodiments describe a case where a Schottky barrier diode is connected in parallel to the body diode of the wide bandgap semiconductor element, the invention is not limited thereto, and various types of flyback diodes can be applied, such as a Si-flyback diode, an SiC-flyback diode, an SiC-Schottky barrier diode, a GaN-flyback diode, a GaN Schottky barrier diode, a diamond-flyback diode, or a diamond-Schottky barrier diode.
  • The technical scope of the present invention is not intended to be limited to the exemplary embodiments depicted in the drawings, and includes all embodiments providing effects equivalent to those set forth as objects of the present invention. Furthermore, the technical scope of the present invention is not limited to combinations of features of the invention delimited by the claims, and can be delimited by all desired combinations of specific features among all the features disclosed herein.
  • It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.

Claims (8)

What is claimed is:
1. A semiconductor device, comprising:
a switching arm unit including a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the switching arm unit having a node between the first and second wide bandgap semiconductor elements that is configured to be connected to a load;
a current detecting unit that detects a current in the second wide bandgap semiconductor element that indicates a flyback current flowing in the second wide bandgap semiconductor element, the flyback current being generated as a result of said load been driven by the first wide bandgap semiconductor element;
a driving unit that drives said first wide bandgap semiconductor element and said second wide bandgap semiconductor element; and
a memory storing a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region for a crystalline semiconductor constituting the second wide bandgap semiconductor element,
wherein said driving unit determines, by referring to said fault inhibiting characteristic curve, whether the detected current of the second wide bandgap semiconductor element falls within the fault growth region or within the fault inhibiting region, and when a result of said determination indicates that the detected current is within the fault growth region, the driving unit outputs, to the first wide bandgap semiconductor element, a driving signal that reduces a current flowing in the first wide bandgap semiconductor element when driving said load therethrough so that a resultant current detected by the current detecting unit falls within the fault inhibiting region.
2. The semiconductor device according to claim 1,
wherein said fault inhibiting characteristic curve represents a current flowing in the second wide bandgap semiconductor element as a function of a pulsewidth of a pulse-form current occurring in the flyback current of the body diode of the second wide bandgap semiconductor element at a beginning of the flyback current, and
wherein said driving unit determines whether the detected current in the second wide bandgap semiconductor element falls within the fault growth region or falls within the fault inhibiting region by referring to said fault inhibiting characteristic curve at the pulsewidth of said pulse-form current generated under a current driving condition.
3. A method of driving a semiconductor device, the semiconductor device including a switching arm unit having a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series between a positive line and a negative line, the method comprising:
a step of detecting a flyback current in said second wide bandgap semiconductor element; and
a step of determining, by referring to a fault inhibiting characteristic curve expressing a border between a fault growth region and a fault inhibiting region, whether the detected flyback current in the second wide bandgap semiconductor element is within the fault growth region or within the fault inhibiting region.
4. The method of driving the semiconductor device according to claim 3,
wherein said fault inhibiting characteristic curve is formed as a map that takes a pulsewidth of a pulse-form current occurring in the flyback current at a beginning of the flyback current of the body diode of the second wide bandgap semiconductor element on a horizontal axis and the flyback current value on a vertical axis.
5. A method of driving a semiconductor device, the semiconductor device including:
a switching arm unit including:
a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series,
a first diode connected in reverse-parallel to said first wide bandgap semiconductor element, and
a second diode connected in reverse-parallel to said second wide bandgap semiconductor element; and
a memory storing:
a characteristic line map, having a plurality of characteristic lines, each of which expresses, using a flyback current flowing in the body diode of the second wide bandgap semiconductor element as a parameter, a relationship between a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of said diode connected in reverse-parallel to the second wide bandgap semiconductor element and a pulsewidth of a pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element at a beginning of the flyback current, said relationship inhibiting occurrence of stacking fault in a crystalline semiconductor constituting the second wide bandgap semiconductor element; and
a slope characteristic line map that indicates, as a function of a maximum current of the flyback current, a permissible range of slopes from slopes of the characteristic lines in said characteristic line map within which occurrence of the stacking fault in the crystalline semiconductor constituting the second wide bandgap semiconductor element is inhibited,
the method comprising:
selecting a slope of a characteristic line from said permissible range of slopes indicated in the slope characteristic line map on the basis of said maximum current of the flyback current;
determining a desired pulsewidth of the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element in accordance with the selected slope of the characteristic line; and
driving the first and second wide bandgap semiconductor elements in such a manner as to generate said desired pulsewidth for the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element, thereby inhibiting occurrence of the stacking fault in the crystalline semiconductor constituting the second wide bandgap semiconductor element.
6. A method of driving a semiconductor device, the semiconductor device including
a switching arm unit including:
a first wide bandgap semiconductor element and a second wide bandgap semiconductor element, each having a body diode, connected in series,
a first diode connected in reverse-parallel to said first wide bandgap semiconductor element, and
a second diode connected in reverse-parallel to said second wide bandgap semiconductor element,
the method comprising:
a step of calculating a flyback current in a body diode of the second wide bandgap semiconductor element from a ratio of an inductance of the second wide bandgap semiconductor element to an inductance of said diode connected in reverse-parallel to the second wide bandgap semiconductor element and a detected current flowing in the second wide bandgap semiconductor element;
a step of determining, by referring to a fault inhibiting characteristic curve defining a border between a fault growth region and a fault inhibiting region on a basis of the calculated flyback current, a desired pulsewidth of a pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element at a beginning of the flyback current that falls within the fault inhibiting region;
driving the first and second wide bandgap semiconductor elements in such a manner as to generate said determined desired pulsewidth for the pulse-form current occurring in the flyback current in the body diode of the second wide bandgap semiconductor element, thereby inhibiting occurrence of stacking fault in a crystalline semiconductor constituting the second wide bandgap semiconductor element.
7. The method of driving the semiconductor device according to claim 6,
wherein the inductance of said second wide bandgap semiconductor element is calculated as a sum of a chip inductance of a chip including the second wide bandgap semiconductor element, an inductance of a module including the second wide bandgap semiconductor element, and an external inductance, and
wherein the inductance of said diode is calculated as a sum of a chip inductance of a chip including the diode, an inductance of a module including the diode, and an external inductance.
8. The method of driving the semiconductor device according to claim 7, further including adjusting said ratio by adjusting the external inductance of said wide bandgap semiconductor element and adjusting the external inductance of the diode.
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