US20170048973A1 - Circuit board structure and method for manufacturing the same - Google Patents
Circuit board structure and method for manufacturing the same Download PDFInfo
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- US20170048973A1 US20170048973A1 US14/821,819 US201514821819A US2017048973A1 US 20170048973 A1 US20170048973 A1 US 20170048973A1 US 201514821819 A US201514821819 A US 201514821819A US 2017048973 A1 US2017048973 A1 US 2017048973A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0274—Optical details, e.g. printed circuits comprising integral optical means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Definitions
- the present disclosure relates to a circuit board structure and a method for manufacturing the circuit board structure.
- the R & D of electronic products is gradually directed to the pursuit of versatile and high performance.
- the requirements of circuit boards also increase.
- the line width and pitch of a circuit board are required to be smaller and smaller, the layout density of the circuit board is required to be higher and higher.
- the circuit board with embedded lines becomes a mainstream trend.
- This disclosure provides a method for manufacturing a circuit board structure to improve the layout density of the circuit board structure.
- a method for manufacturing a circuit board structure includes forming a first circuit layer on a carrier; forming a first dielectric layer on the carrier and the first circuit layer; forming at least one first hole in the first dielectric layer, in which the first hole exposes a portion of the first circuit layer; forming a second dielectric layer on the first dielectric layer and the first circuit layer; forming at least one trench in the second dielectric layer, and forming a second hole in a part of the second dielectric layer corresponding to the first hole, in which the trench exposes a portion of the first dielectric layer, the second hole exposes the portion of the first circuit layer and is disposed in the first hole, and a diameter of the second hole is smaller than a diameter of the first hole; and forming a metal layer filling in the trench and the second hole, in which a portion of the metal layer filling the trench becomes a second circuit layer, and another portion of the metal layer filling the second hole becomes a conductive via.
- the trench and the second hole are formed simultaneously.
- the trench and the second hole are formed by the same machine.
- the trench and the second hole are formed by exposing and developing the second dielectric layer, and the first dielectric layer and the first circuit layer function as stop layers.
- the operation of forming the metal layer includes forming a conductive seed layer on the portion of the first dielectric layer exposed by the trench and the portion of the first circuit layer exposed by the second hole; forming the metal layer by electroplating; and planarizing the metal layer to remove an upper portion of the metal layer, thereby exposing the second dielectric layer.
- the method further includes baking the first dielectric layer to cure the first dielectric layer before the second dielectric layer is formed.
- a circuit board structure in another aspect of the disclosure, includes a first circuit layer, a first dielectric layer, a second dielectric layer, a second circuit layer, and a conductive via.
- the first dielectric layer is disposed on the first circuit layer, in which the first dielectric layer has at least one first hole exposing a portion of the first circuit layer.
- the second dielectric layer is disposed on the first circuit layer and the first dielectric layer, in which the second dielectric layer has at least one trench and at least one second hole disposed in the first hole, the second hole exposes the first circuit layer, and the trench exposes the first dielectric layer.
- the second circuit layer is disposed in the trench.
- the conductive via is disposed in the second hole without contacting the first hole, in which a diameter of the second hole is smaller than a diameter of the first hole, and the conductive via has a bottom surface, a top surface, and a side surface connecting the bottom surface and the top surface.
- the trench is connected to the second hole, and the second circuit layer is connected to the conductive via.
- the second dielectric layer is formed from a photosensitive dielectric material.
- the diameter of the upper part of the second hole needs not to be greater than the diameter of the lower part of the second hole, and the upper part of the conductive via filling the second hole does not have a ring structure. Consequently, the space occupied by the conductive via in the second dielectric layer is effectively reduced, and there is more space in the second dielectric layer for disposing the second circuit layer, such that the layout density of the circuit board structure can be higher.
- FIGS. 1A to 1I are schematic cross-sectional views of intermediate stages showing a method for manufacturing a circuit board structure according to one embodiment of this invention.
- FIG. 2 is a schematic cross-sectional view of the circuit board structure according to another embodiment of this invention.
- the layout density of the circuit boards is required to become higher.
- a method for manufacturing a circuit board structure is provided, and the layout density of the circuit board structure can be increased by using the specially designed manufacturing process.
- FIGS. 1A to 1I are schematic cross-sectional views of intermediate stages showing a method for manufacturing a circuit board structure 100 according to one embodiment of this invention. It is noted that due to the characteristics of process machine, each element by each operation of the manufacturing method is symmetrically disposed on both sides of a carrier 110 , but only the elements formed on one side of the carrier 110 are discussed below. Embodiments of this disclosure are not limited thereto. In other embodiments, the manufacturing method forms the elements on only one side of the carrier 110 .
- the carrier 110 includes a core layer 112 and conductive layers 114 and 116 respectively disposed on two sides of the core layer 112 .
- the core layer 114 may be formed from a metal, a dielectric material, or a combination thereof.
- the core layer 112 may be copper clad laminate (CCL).
- the conductive layers 114 and 116 may be copper foils or conductive seed layers. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the conductive layers 114 , 116 depending on actual applications.
- a first circuit layer 120 is formed on the carrier 110 .
- the first circuit layer 120 may be formed by the following operations. First, a photoresist layer (not shown), such as a dry film, is formed on the carrier 110 . Then, the photoresist layer is patterned to expose a portion of the carrier 110 by a lithography process. Then, the first circuit layer 120 is formed by plating, and then the photoresist layer is removed.
- a photoresist layer such as a dry film
- the first circuit layer 120 may be formed from a metal, such as silver, nickel, copper, gold, palladium, or a combination thereof. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the first circuit layer 120 depending on the actual application.
- a first dielectric layer 130 is formed on the carrier 110 and the first circuit layer 120 .
- the first dielectric layer 130 may be formed from a photosensitive dielectric material, such as DIF03 manufactured by Hitachi. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the first dielectric layer 130 depending on the actual application.
- the first dielectric layer 130 may be formed by lamination or coating. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the first dielectric layer 130 depending on the actual application.
- At least one first hole 132 is formed in the first dielectric layer 130 , and the first hole 132 exposes a portion of the first circuit layer 120 .
- the first hole 132 is formed by exposing and developing the first dielectric layer 130 , and the first dielectric layer 130 functions as a stop layer. After the first hole 132 is formed, the first dielectric layer 130 is baked to cure the first dielectric layer 130 .
- the first hole 132 is formed by ablating the first dielectric layer 130 by laser, in which the first circuit layer 120 functions as the stop layer.
- the first dielectric layer 130 may be a photosensitive dielectric material or a non-photosensitive dielectric material. If the first dielectric layer 130 is a photosensitive dielectric material, the first dielectric layer 130 is baked to cure the first dielectric layer 130 before the first hole 132 is formed.
- a second dielectric layer 140 is formed on the first dielectric layer 130 and the first circuit layer 120 . Therefore, a portion of the second dielectric layer 140 is disposed in the first hole 132 .
- the second dielectric layer 140 is formed from a photosensitive dielectric material, such as DIF03 manufactured by Hitachi. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the second dielectric layer 140 depending on the actual application.
- the second dielectric layer 140 may be formed by lamination or coating. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the second dielectric layer 140 depending on the actual application.
- the thickness t of the second dielectric layer 140 (for example, the thickness of the portion of the second dielectric layer 140 disposed on the first dielectric layer 130 ) may be in a range from about 10 ⁇ m to about 20 ⁇ m. Or, the thickness t of the second dielectric layer 140 may be about 15 ⁇ m.
- At least one trench 142 is formed in the second dielectric layer 140 , and a second hole 144 is formed in a portion of the second dielectric layer 140 corresponding to the first hole 132 .
- the trench 142 exposes a portion of the first dielectric layer 130
- the second hole 144 exposes a portion of the first circuit layer 120 and is disposed in the first hole 132 .
- the diameter of the second hole 144 is smaller than the diameter of the first hole 132 .
- the trench 142 and the second hole 144 are formed by exposing and developing the second dielectric layer 140 , and the first dielectric layer 130 and the first circuit layer 120 function as stop layers. After the trench 142 and the second hole 144 are formed, the second dielectric layer 140 is baked to cure the second dielectric layer 140 .
- Some of the trenches 142 may be connected to some of the second holes 144 , and some of the trenches 142 may be connected to each other.
- the trench 142 and the second hole 144 are formed simultaneously, and the trench 142 and the second hole 144 are formed by the same mask.
- the trench 142 and the second hole 144 are formed by direct image exposure.
- the second dielectric layer 140 is exposed by using a laser head of a direct image exposure device with a lower energy to form the trench 142 .
- the second dielectric layer 140 is exposed by the laser head of the direct image exposure device with higher energy to form the second hole 144 .
- the order of forming the trench 142 and the second hole 144 can be changed, i.e., the second hole 144 can be formed before the trench 142 is formed.
- the trench 142 and the second hole 144 are formed by the same machine without moving the carrier 110 .
- a metal layer 150 fills the trench 142 and the second hole 144 .
- a conductive seed layer 160 is formed on the portion of the first dielectric layer 130 exposed by the trench 142 and the portion of the first circuit layer 120 exposed by the second hole 144 . Then, the metal layer 150 is formed by electroplating.
- the metal layer 150 may be formed from silver, nickel, copper, gold, palladium, or a combination thereof.
- the conductive seed layer 160 may be formed from electroplated copper, electroplated palladium, or sputtered metal such as sputtered copper or sputtered titanium copper (Ti/Cu). Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the metal layer 150 and the conductive seed layer 160 depending on actual applications.
- the metal layer 150 is planarized to remove an upper portion of the metal layer 150 , such that the second dielectric layer 140 is exposed. Therefore, the metal layer 150 filling the trench 142 and the second hole 144 forms lines embedded in the second dielectric layer 140 (such as embedded lines).
- the portion of the metal layer 150 filling the trench 142 becomes a second circuit layer 152
- the portion of the metal layer 150 filling the second hole 144 becomes a conductive via 154 .
- the conductive via 154 has a bottom surface 154 b , a top surface 154 t , and a side surface 154 s connecting the bottom surface 154 b and the top surface 154 t .
- the side surface 154 s is a continuously extending curved surface or a plane surface.
- the conductive via 154 is a column such as a circular column or a trapezoidal column.
- the height of the conductive via 154 (such as the distance between the top surface 154 t and the bottom surface 154 b ) may be in a range from about 30 m to about 50 ⁇ m.
- the height of the conductive via 154 may be about 40 ⁇ m.
- the diameter of the top surface 154 t may be in a range from about 10 ⁇ m to about 60 ⁇ m, in a range from about 15 ⁇ m to about 50 ⁇ m, or in a range from about 20 ⁇ m to 30 ⁇ m. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the diameter of the top surface 154 t depending on actual applications.
- the trenches 142 may be connected to each other, different portions of the metal layer 150 filling the trenches 142 (such as the second circuit layer 152 ) may be connected to each other. Because some of the trenches 142 may be connected to some of the second holes 144 , the portion of the metal layer 150 filling the trenches 142 (for example, the second circuit layer 152 ) is connected to the portion of the metal layer 150 filling the second hole 144 (such as the conductive via 154 ).
- the planarization may be performed by brushing, chemical-mechanical polishing (CMP), etc.
- CMP chemical-mechanical polishing
- Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the planarization depending on the actual application.
- the core layer 112 is removed, i.e., the conductive layer 114 is separated from the core layer 112 (meanwhile the conductive layer 116 is also separated from the core layer 112 ).
- the operation of removing the core layer 112 has no specific limitation.
- the core layer 112 may be removed before the circuit board structure 100 is packaged or after the circuit board structure 100 is packaged.
- the conductive layer 114 is removed to form the coreless circuit board structure 100 .
- the lower part of the second hole are formed by a process different from the process forming the trench and the upper part of the second hole. Therefore, deviations may be generated when the upper part and the lower part of the second hole are formed.
- the diameter of the upper part of the second hole is made to be greater than the diameter of the lower part of the second hole, such that the upper part of the second hole is aligned with the lower part of the second hole. Consequently, compared to the lower part of the conductive via filling the second hole, the upper part of the conductive via have a ring structure.
- the diameter of the upper part of the second hole 144 need not to be greater than the diameter of the lower part of the second hole 144 , and the upper part of the conductive via 154 filling the second hole 144 does not have the ring structure. Consequently, the space occupied by the conductive via 154 in the second dielectric layer 140 is effectively reduced, and there is more space in the second dielectric layer 140 to dispose the second circuit layer 152 , such that the layout density of the circuit board structure 100 can be higher.
- the circuit board structure 100 includes the first circuit layer 120 , the first dielectric layer 130 , the second dielectric layer 140 , the second circuit layer 152 , and the conductive via 154 .
- the first dielectric layer 130 is disposed on the first circuit layer 120 , in which the first dielectric layer 130 has at least one first hole 132 to expose a part of the first circuit layer 120 .
- the second dielectric layer 140 is disposed on the first circuit layer 120 and the first dielectric layer 130 , in which the second dielectric layer 140 has at least one trench 142 and at least one second hole 144 , the second hole 144 is disposed in the first hole 132 , the second hole 144 exposes the first circuit layer 120 , and the trench 142 exposes the first dielectric layer 130 .
- the second circuit layer 152 is disposed in the trench 142 .
- the conductive via 154 is disposed in the second hole 144 , in which the conductive via 154 does not contact the first hole 132 , the diameter of the second hole 144 is smaller than the diameter of the first hole 132 , and the conductive via 154 has a bottom surface 154 b , a top surface 154 t , and a side surface 154 s connecting the bottom surface 154 b and the top surface 154 t.
- FIG. 2 is a cross-sectional view of the circuit board structure 100 according to another embodiment of this invention.
- the circuit board structure 100 of FIG. 2 is similar to the circuit board structure 100 of FIG. 1I , and the differences are discussed below.
- the circuit board structure 100 further includes the carrier 110 .
- the first circuit layer 120 is disposed on the carrier 110 .
- the first dielectric layer 130 is disposed on the carrier 110 and the first circuit layer 120 .
- the circuit board structure 100 further includes a conductive seed layer 170 , and the conductive seed layer 170 is disposed between the carrier 110 and the first circuit layer 120 .
- the function of the conductive seed layer 170 is to form the first circuit layer 120 , which is similar to the function of the conductive layer 114 , 116 of FIG. 1A .
- the conductive seed layer 170 may be made of electroplated copper, electroplated palladium, or sputtered metal such as sputtered copper or sputtered titanium copper. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the conductive seed layer 170 depending on the actual application.
- the diameter of the upper part of the second hole 144 does not have to be greater than the diameter of the lower part of the second hole 144 , and the upper part of the conductive via 154 filling the second hole 144 does not have the ring structure. Consequently, the space occupied by the conductive via 154 in the second dielectric layer 140 is effectively reduced, and there is more space in the second dielectric layer 140 to dispose the second circuit layer 152 , such that the layout density of the circuit board structure 100 can be higher.
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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- Optics & Photonics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.
Description
- Technical Field
- The present disclosure relates to a circuit board structure and a method for manufacturing the circuit board structure.
- Description of Related Art
- With the rapid growth of electronic industry, the R & D of electronic products is gradually directed to the pursuit of versatile and high performance. In order to achieve the requirements of high integration and miniaturization of semiconductor components, the requirements of circuit boards also increase. For example, the line width and pitch of a circuit board are required to be smaller and smaller, the layout density of the circuit board is required to be higher and higher. In addition, in order to increase the layout density of the circuit board, the circuit board with embedded lines becomes a mainstream trend.
- To further improve various characteristics of a circuit board, persons in the industry all endeavor to search the solutions. How to provide a circuit board with better characteristics is one of the important research topics, and is also a target that needs to be improved in the related fields.
- This disclosure provides a method for manufacturing a circuit board structure to improve the layout density of the circuit board structure.
- In one aspect of the disclosure, a method for manufacturing a circuit board structure is provided. The method includes forming a first circuit layer on a carrier; forming a first dielectric layer on the carrier and the first circuit layer; forming at least one first hole in the first dielectric layer, in which the first hole exposes a portion of the first circuit layer; forming a second dielectric layer on the first dielectric layer and the first circuit layer; forming at least one trench in the second dielectric layer, and forming a second hole in a part of the second dielectric layer corresponding to the first hole, in which the trench exposes a portion of the first dielectric layer, the second hole exposes the portion of the first circuit layer and is disposed in the first hole, and a diameter of the second hole is smaller than a diameter of the first hole; and forming a metal layer filling in the trench and the second hole, in which a portion of the metal layer filling the trench becomes a second circuit layer, and another portion of the metal layer filling the second hole becomes a conductive via.
- In one or more specific embodiments, the trench and the second hole are formed simultaneously.
- In one or more embodiments, the trench and the second hole are formed by the same machine.
- In one or more specific embodiments, the trench and the second hole are formed by exposing and developing the second dielectric layer, and the first dielectric layer and the first circuit layer function as stop layers.
- In one or more specific embodiments, the operation of forming the metal layer includes forming a conductive seed layer on the portion of the first dielectric layer exposed by the trench and the portion of the first circuit layer exposed by the second hole; forming the metal layer by electroplating; and planarizing the metal layer to remove an upper portion of the metal layer, thereby exposing the second dielectric layer.
- In one or more specific embodiments, the method further includes baking the first dielectric layer to cure the first dielectric layer before the second dielectric layer is formed.
- In another aspect of the disclosure, a circuit board structure is provided. The circuit board structure includes a first circuit layer, a first dielectric layer, a second dielectric layer, a second circuit layer, and a conductive via. The first dielectric layer is disposed on the first circuit layer, in which the first dielectric layer has at least one first hole exposing a portion of the first circuit layer. The second dielectric layer is disposed on the first circuit layer and the first dielectric layer, in which the second dielectric layer has at least one trench and at least one second hole disposed in the first hole, the second hole exposes the first circuit layer, and the trench exposes the first dielectric layer. The second circuit layer is disposed in the trench. The conductive via is disposed in the second hole without contacting the first hole, in which a diameter of the second hole is smaller than a diameter of the first hole, and the conductive via has a bottom surface, a top surface, and a side surface connecting the bottom surface and the top surface.
- In one or more specific embodiments, the trench is connected to the second hole, and the second circuit layer is connected to the conductive via.
- In one or more specific embodiments, the second dielectric layer is formed from a photosensitive dielectric material.
- Since the trench and the second hole are formed simultaneously or by the same machine, associated deviations can be basically avoided. Therefore, the diameter of the upper part of the second hole needs not to be greater than the diameter of the lower part of the second hole, and the upper part of the conductive via filling the second hole does not have a ring structure. Consequently, the space occupied by the conductive via in the second dielectric layer is effectively reduced, and there is more space in the second dielectric layer for disposing the second circuit layer, such that the layout density of the circuit board structure can be higher.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
-
FIGS. 1A to 1I are schematic cross-sectional views of intermediate stages showing a method for manufacturing a circuit board structure according to one embodiment of this invention; and -
FIG. 2 is a schematic cross-sectional view of the circuit board structure according to another embodiment of this invention. - In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically depicted in order to simplify the drawings.
- In order to achieve high integration and miniaturization of the semiconductor components, standards of the circuit boards are also raised. For example, the layout density of the circuit boards is required to become higher. Herein, a method for manufacturing a circuit board structure is provided, and the layout density of the circuit board structure can be increased by using the specially designed manufacturing process.
-
FIGS. 1A to 1I are schematic cross-sectional views of intermediate stages showing a method for manufacturing acircuit board structure 100 according to one embodiment of this invention. It is noted that due to the characteristics of process machine, each element by each operation of the manufacturing method is symmetrically disposed on both sides of acarrier 110, but only the elements formed on one side of thecarrier 110 are discussed below. Embodiments of this disclosure are not limited thereto. In other embodiments, the manufacturing method forms the elements on only one side of thecarrier 110. - The
carrier 110 includes acore layer 112 andconductive layers core layer 112. - The
core layer 114 may be formed from a metal, a dielectric material, or a combination thereof. For example, thecore layer 112 may be copper clad laminate (CCL). - The
conductive layers conductive layers - As shown in
FIG. 1A , afirst circuit layer 120 is formed on thecarrier 110. - The
first circuit layer 120 may be formed by the following operations. First, a photoresist layer (not shown), such as a dry film, is formed on thecarrier 110. Then, the photoresist layer is patterned to expose a portion of thecarrier 110 by a lithography process. Then, thefirst circuit layer 120 is formed by plating, and then the photoresist layer is removed. - The
first circuit layer 120 may be formed from a metal, such as silver, nickel, copper, gold, palladium, or a combination thereof. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to thefirst circuit layer 120 depending on the actual application. - As shown in
FIG. 1B , a firstdielectric layer 130 is formed on thecarrier 110 and thefirst circuit layer 120. - The
first dielectric layer 130 may be formed from a photosensitive dielectric material, such as DIF03 manufactured by Hitachi. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to thefirst dielectric layer 130 depending on the actual application. - The
first dielectric layer 130 may be formed by lamination or coating. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to thefirst dielectric layer 130 depending on the actual application. - As shown in
FIG. 1C , at least onefirst hole 132 is formed in thefirst dielectric layer 130, and thefirst hole 132 exposes a portion of thefirst circuit layer 120. - The
first hole 132 is formed by exposing and developing thefirst dielectric layer 130, and thefirst dielectric layer 130 functions as a stop layer. After thefirst hole 132 is formed, thefirst dielectric layer 130 is baked to cure thefirst dielectric layer 130. - In another embodiment, the
first hole 132 is formed by ablating thefirst dielectric layer 130 by laser, in which thefirst circuit layer 120 functions as the stop layer. In addition, in the embodiment, thefirst dielectric layer 130 may be a photosensitive dielectric material or a non-photosensitive dielectric material. If thefirst dielectric layer 130 is a photosensitive dielectric material, thefirst dielectric layer 130 is baked to cure thefirst dielectric layer 130 before thefirst hole 132 is formed. - As shown in
FIG. 1D , asecond dielectric layer 140 is formed on thefirst dielectric layer 130 and thefirst circuit layer 120. Therefore, a portion of thesecond dielectric layer 140 is disposed in thefirst hole 132. - The
second dielectric layer 140 is formed from a photosensitive dielectric material, such as DIF03 manufactured by Hitachi. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to thesecond dielectric layer 140 depending on the actual application. - The
second dielectric layer 140 may be formed by lamination or coating. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to thesecond dielectric layer 140 depending on the actual application. - The thickness t of the second dielectric layer 140 (for example, the thickness of the portion of the
second dielectric layer 140 disposed on the first dielectric layer 130) may be in a range from about 10 μm to about 20 μm. Or, the thickness t of thesecond dielectric layer 140 may be about 15 μm. - As shown in
FIG. 1E , at least onetrench 142 is formed in thesecond dielectric layer 140, and asecond hole 144 is formed in a portion of thesecond dielectric layer 140 corresponding to thefirst hole 132. Thetrench 142 exposes a portion of thefirst dielectric layer 130, and thesecond hole 144 exposes a portion of thefirst circuit layer 120 and is disposed in thefirst hole 132. The diameter of thesecond hole 144 is smaller than the diameter of thefirst hole 132. - The
trench 142 and thesecond hole 144 are formed by exposing and developing thesecond dielectric layer 140, and thefirst dielectric layer 130 and thefirst circuit layer 120 function as stop layers. After thetrench 142 and thesecond hole 144 are formed, thesecond dielectric layer 140 is baked to cure thesecond dielectric layer 140. - Some of the
trenches 142 may be connected to some of thesecond holes 144, and some of thetrenches 142 may be connected to each other. - In the embodiment, the
trench 142 and thesecond hole 144 are formed simultaneously, and thetrench 142 and thesecond hole 144 are formed by the same mask. - In another embodiment, the
trench 142 and thesecond hole 144 are formed by direct image exposure. First, thesecond dielectric layer 140 is exposed by using a laser head of a direct image exposure device with a lower energy to form thetrench 142. Then, without moving thecarrier 110, thesecond dielectric layer 140 is exposed by the laser head of the direct image exposure device with higher energy to form thesecond hole 144. The order of forming thetrench 142 and thesecond hole 144 can be changed, i.e., thesecond hole 144 can be formed before thetrench 142 is formed. In sum, thetrench 142 and thesecond hole 144 are formed by the same machine without moving thecarrier 110. - As shown in
FIG. 1F , ametal layer 150 fills thetrench 142 and thesecond hole 144. - First, a
conductive seed layer 160 is formed on the portion of thefirst dielectric layer 130 exposed by thetrench 142 and the portion of thefirst circuit layer 120 exposed by thesecond hole 144. Then, themetal layer 150 is formed by electroplating. - The
metal layer 150 may be formed from silver, nickel, copper, gold, palladium, or a combination thereof. Theconductive seed layer 160 may be formed from electroplated copper, electroplated palladium, or sputtered metal such as sputtered copper or sputtered titanium copper (Ti/Cu). Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to themetal layer 150 and theconductive seed layer 160 depending on actual applications. - As shown in
FIG. 1G , themetal layer 150 is planarized to remove an upper portion of themetal layer 150, such that thesecond dielectric layer 140 is exposed. Therefore, themetal layer 150 filling thetrench 142 and thesecond hole 144 forms lines embedded in the second dielectric layer 140 (such as embedded lines). - The portion of the
metal layer 150 filling thetrench 142 becomes asecond circuit layer 152, and the portion of themetal layer 150 filling thesecond hole 144 becomes a conductive via 154. The conductive via 154 has abottom surface 154 b, atop surface 154 t, and aside surface 154 s connecting thebottom surface 154 b and thetop surface 154 t. Theside surface 154 s is a continuously extending curved surface or a plane surface. In other words, the conductive via 154 is a column such as a circular column or a trapezoidal column. - The height of the conductive via 154 (such as the distance between the
top surface 154 t and thebottom surface 154 b) may be in a range from about 30 m to about 50 μm. The height of the conductive via 154 may be about 40 μm. - The diameter of the
top surface 154 t may be in a range from about 10 μm to about 60 μm, in a range from about 15 μm to about 50 μm, or in a range from about 20 μm to 30 μm. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the diameter of thetop surface 154 t depending on actual applications. - Because some of the
trenches 142 may be connected to each other, different portions of themetal layer 150 filling the trenches 142 (such as the second circuit layer 152) may be connected to each other. Because some of thetrenches 142 may be connected to some of thesecond holes 144, the portion of themetal layer 150 filling the trenches 142 (for example, the second circuit layer 152) is connected to the portion of themetal layer 150 filling the second hole 144 (such as the conductive via 154). - The planarization may be performed by brushing, chemical-mechanical polishing (CMP), etc. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to the planarization depending on the actual application.
- As shown in
FIG. 1H , after themetal layer 150 is planarized to remove the upper portion of themetal layer 150, thecore layer 112 is removed, i.e., theconductive layer 114 is separated from the core layer 112 (meanwhile theconductive layer 116 is also separated from the core layer 112). - The operation of removing the
core layer 112 has no specific limitation. For example, thecore layer 112 may be removed before thecircuit board structure 100 is packaged or after thecircuit board structure 100 is packaged. - As shown in
FIG. 1H andFIG. 1I , theconductive layer 114 is removed to form the corelesscircuit board structure 100. - In conventional progress, although the trench and the upper part of the second hole are generally formed by the same process, the lower part of the second hole are formed by a process different from the process forming the trench and the upper part of the second hole. Therefore, deviations may be generated when the upper part and the lower part of the second hole are formed. In order to prevent the deviations from affecting the entire structure, the diameter of the upper part of the second hole is made to be greater than the diameter of the lower part of the second hole, such that the upper part of the second hole is aligned with the lower part of the second hole. Consequently, compared to the lower part of the conductive via filling the second hole, the upper part of the conductive via have a ring structure.
- In contrast, in the aforementioned method, since the
trench 142 and thesecond hole 144 are formed simultaneously or formed by the same machine, associated deviations can be avoided basically. Therefore, the diameter of the upper part of thesecond hole 144 need not to be greater than the diameter of the lower part of thesecond hole 144, and the upper part of the conductive via 154 filling thesecond hole 144 does not have the ring structure. Consequently, the space occupied by the conductive via 154 in thesecond dielectric layer 140 is effectively reduced, and there is more space in thesecond dielectric layer 140 to dispose thesecond circuit layer 152, such that the layout density of thecircuit board structure 100 can be higher. - As shown in
FIG. 1I , which shows thecircuit board structure 100 manufactured by the method ofFIGS. 1A to 1I , thecircuit board structure 100 includes thefirst circuit layer 120, thefirst dielectric layer 130, thesecond dielectric layer 140, thesecond circuit layer 152, and the conductive via 154. Thefirst dielectric layer 130 is disposed on thefirst circuit layer 120, in which thefirst dielectric layer 130 has at least onefirst hole 132 to expose a part of thefirst circuit layer 120. Thesecond dielectric layer 140 is disposed on thefirst circuit layer 120 and thefirst dielectric layer 130, in which thesecond dielectric layer 140 has at least onetrench 142 and at least onesecond hole 144, thesecond hole 144 is disposed in thefirst hole 132, thesecond hole 144 exposes thefirst circuit layer 120, and thetrench 142 exposes thefirst dielectric layer 130. Thesecond circuit layer 152 is disposed in thetrench 142. The conductive via 154 is disposed in thesecond hole 144, in which the conductive via 154 does not contact thefirst hole 132, the diameter of thesecond hole 144 is smaller than the diameter of thefirst hole 132, and the conductive via 154 has abottom surface 154 b, atop surface 154 t, and aside surface 154 s connecting thebottom surface 154 b and thetop surface 154 t. -
FIG. 2 is a cross-sectional view of thecircuit board structure 100 according to another embodiment of this invention. Thecircuit board structure 100 ofFIG. 2 is similar to thecircuit board structure 100 ofFIG. 1I , and the differences are discussed below. - As shown in
FIG. 2 , thecircuit board structure 100 further includes thecarrier 110. Thefirst circuit layer 120 is disposed on thecarrier 110. Thefirst dielectric layer 130 is disposed on thecarrier 110 and thefirst circuit layer 120. - In addition, the
circuit board structure 100 further includes aconductive seed layer 170, and theconductive seed layer 170 is disposed between thecarrier 110 and thefirst circuit layer 120. The function of theconductive seed layer 170 is to form thefirst circuit layer 120, which is similar to the function of theconductive layer FIG. 1A . - The
conductive seed layer 170 may be made of electroplated copper, electroplated palladium, or sputtered metal such as sputtered copper or sputtered titanium copper. Embodiments of this disclosure are not limited thereto. People having ordinary skill in the art can make proper modifications to theconductive seed layer 170 depending on the actual application. - Since the
trench 142 and thesecond hole 144 are formed simultaneously or formed by the same machine, associated deviations can be basically avoided. Therefore, the diameter of the upper part of thesecond hole 144 does not have to be greater than the diameter of the lower part of thesecond hole 144, and the upper part of the conductive via 154 filling thesecond hole 144 does not have the ring structure. Consequently, the space occupied by the conductive via 154 in thesecond dielectric layer 140 is effectively reduced, and there is more space in thesecond dielectric layer 140 to dispose thesecond circuit layer 152, such that the layout density of thecircuit board structure 100 can be higher. - All the features disclosed in this specification (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
- Any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. §112, 6th paragraph. In particular, the use of “step of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. §112, 6th paragraph.
Claims (9)
1. A method for manufacturing a circuit board structure, the method comprising:
forming a first circuit layer on a carrier;
forming a first dielectric layer on the carrier and the first circuit layer;
forming at least one first hole in the first dielectric layer, wherein the first hole exposes a portion of the first circuit layer;
forming a second dielectric layer on the first dielectric layer and the first circuit layer;
forming at least one trench in the second dielectric layer, and forming a second hole in a portion of the second dielectric layer corresponding to the first hole, the trench exposing a portion of the first dielectric layer, the second hole exposing the portion of the first circuit layer, wherein the second hole is disposed in the first hole, and a diameter of the second hole is smaller than a diameter of the first hole; and
forming a metal layer filling the trench and the second hole, wherein a portion of the metal layer filling the trench becomes a second circuit layer, and another portion of the metal layer filling the second hole becomes a conductive via.
2. The method of claim 1 , wherein the trench and the second hole are formed simultaneously.
3. The method of claim 1 , wherein the trench and the second hole are formed by the same machine.
4. The method of claim 1 , wherein the trench and the second hole are formed by exposing and developing the second dielectric layer, and the first dielectric layer and the first circuit layer function as stop layers.
5. The method of claim 1 , wherein the operation of forming the metal layer comprises:
forming a conductive seed layer on the portion of the first dielectric layer exposed by the trench and the portion of the first circuit layer exposed by the second hole;
forming the metal layer by electroplating; and
planarizing the metal layer to remove an upper portion of the metal layer, thereby exposing the second dielectric layer.
6. The method of claim 1 , further comprising:
baking the first dielectric layer to cure the first dielectric layer before the second dielectric layer is formed.
7. A circuit board structure, comprising:
a first circuit layer;
a first dielectric layer disposed on the first circuit layer, wherein the first dielectric layer has at least one first hole exposing a portion of the first circuit layer;
a second dielectric layer disposed on the first circuit layer and the first dielectric layer, wherein the second dielectric layer has at least one trench and at least one second hole disposed in the first hole, the second hole exposing the first circuit layer, the trench exposing the first dielectric layer;
a second circuit layer disposed in the trench; and
a conductive via disposed in the second hole without contacting the first hole, wherein a diameter of the second hole is smaller than a diameter of the first hole, and the conductive via has a bottom surface, a top surface, and a side surface connecting the bottom surface and the top surface.
8. The circuit board structure of claim 7 , wherein the trench is connected to the second hole, and the second circuit layer is connected to the conductive via.
9. The circuit board structure of claim 7 , wherein the second dielectric layer is formed from a photosensitive dielectric material.
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CN111816636A (en) * | 2019-04-10 | 2020-10-23 | 欣兴电子股份有限公司 | Package carrier and package structure |
WO2023073396A1 (en) * | 2021-10-29 | 2023-05-04 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Stamping surface profile in design layer and filling an indentation with metallic base structure and electroplating structure |
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TWI253714B (en) | 2004-12-21 | 2006-04-21 | Phoenix Prec Technology Corp | Method for fabricating a multi-layer circuit board with fine pitch |
TWI484600B (en) | 2012-08-15 | 2015-05-11 | Unimicron Technology Corp | Coreless package and method of fabricating the same |
TW201513753A (en) | 2013-09-26 | 2015-04-01 | Unimicron Technology Corp | Manufacturing method of circuit board |
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CN111816636A (en) * | 2019-04-10 | 2020-10-23 | 欣兴电子股份有限公司 | Package carrier and package structure |
US10881006B2 (en) * | 2019-04-10 | 2020-12-29 | Unimicron Technology Corp. | Package carrier and package structure |
WO2023073396A1 (en) * | 2021-10-29 | 2023-05-04 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Stamping surface profile in design layer and filling an indentation with metallic base structure and electroplating structure |
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