US20160372372A1 - Backside contact to final substrate - Google Patents
Backside contact to final substrate Download PDFInfo
- Publication number
- US20160372372A1 US20160372372A1 US14/744,681 US201514744681A US2016372372A1 US 20160372372 A1 US20160372372 A1 US 20160372372A1 US 201514744681 A US201514744681 A US 201514744681A US 2016372372 A1 US2016372372 A1 US 2016372372A1
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- US
- United States
- Prior art keywords
- layer
- buried insulator
- insulator layer
- electrically
- conducting connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- 239000012212 insulator Substances 0.000 claims abstract description 98
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 173
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 5
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- 238000011049 filling Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
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- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
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- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- 238000007667 floating Methods 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
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- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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Definitions
- an SOI wafer includes a thin device layer of semiconductor material, a handle substrate, and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the device layer from the handle substrate.
- Integrated circuits are fabricated using the semiconductor material of the device layer.
- FIGS. 1-3 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an embodiment of the invention.
- FIG. 6 is a cross-sectional view similar to FIG. 5 of a portion of a substrate in accordance with an alternative embodiment of the invention.
- Shallow trench isolation regions 22 may be formed in the device layer 16 of the SOI substrate 12 to define a device region in the device layer 16 .
- the shallow trench isolation regions 22 may be formed by depositing a hardmask, patterning the hardmask and device layer 16 with lithography and etching processes to define trenches, depositing an electrical insulator to fill the trenches, planarizing the electrical insulator relative to the hardmask using a chemical mechanical polishing (CMP) process, and removing the hardmask.
- CMP chemical mechanical polishing
- a trench 24 is formed that extends from a top surface 16 a of the device layer 16 through the device layer 16 , beyond a front surface 18 a of the buried insulator layer 18 forming an interface with the device layer 16 , and partially through the buried insulator layer 18 .
- the sidewalls 26 of the trench 24 do not penetrate through the interface 19 between the buried insulator layer 18 and the handle wafer 20 .
- the trench 24 has a bottom surface 28 that is separated from the interface 19 by a partial thickness, t, or portion of the buried insulator layer 18 .
- a mask layer may be applied on a top surface 16 a of the device layer 16 and patterned with photolithography.
- the contact plug 30 may be comprised of a semiconductor material.
- the semiconductor material comprising the contact plug 30 may be polysilicon (i.e. polycrystalline silicon) representative that is deposited by chemical vapor deposition (CVD).
- the polysilicon of the contact plug 30 may contain a dopant (e.g., an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) or a p-type dopant from Group III of the Periodic Table (e.g., boron)) in a concentration effective to enhance its electrical conductivity and to either impart either n-type or p-type conductivity to the polysilicon.
- a dopant e.g., an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)
- Front-end-of-line (FEOL) processing is used to fabricate device structures of one or more integrated circuits using the device layer 16 and form a chip.
- the device structures may be bipolar junction transistors, field effect transistors, and/or coplanar waveguide (CPW) transmission lines, and the integrated circuits on chips formed from the assembly 10 may be configured for end use in high-frequency and high-power applications (e.g., power amplifiers for wireless communications systems and mobile devices) and in high-speed logic circuits.
- the integrated circuits may include various functional blocks, such as switches, power amplifiers, power management units, filters, etc.
- the interconnect structure 40 includes a wiring level 32 with a wire 34 located in a dielectric layer 33 and a wiring level 36 with a conductor-filled via 38 located in a dielectric layer 39 .
- the contact plug 30 is coupled with the wire 34 by the conductor-filled via 38 .
- the wiring levels 32 , 36 may be formed by deposition, polishing, lithography, and etching techniques characteristic of a damascene process and/or subtractive patterning.
- Candidate conductors for the wire 34 and the conductor filling the via 38 are metals such as copper (Cu), aluminum (Al), and tungsten (W). These types of metals may be deposited by chemical vapor deposition or by an electrochemical process like electroplating or electroless plating.
- the dielectric layers 33 , 39 may be comprised of any suitable organic or inorganic dielectric material, such as silicon dioxide, hydrogen-enriched silicon oxycarbide (SiCOH), fluorosilicate glass (FSG), or another type of low-k dielectric material that may be deposited by chemical vapor deposition, such as low-pressure chemical vapor phase deposition or plasma-enhanced chemical vapor deposition (PECVD).
- any suitable organic or inorganic dielectric material such as silicon dioxide, hydrogen-enriched silicon oxycarbide (SiCOH), fluorosilicate glass (FSG), or another type of low-k dielectric material that may be deposited by chemical vapor deposition, such as low-pressure chemical vapor phase deposition or plasma-enhanced chemical vapor deposition (PECVD).
- the back surface 18 b of the buried insulator layer 18 is placed in contact with a top surface 42 a of the final substrate 42 , and these surfaces 18 b, 42 a are subsequently bonded together by, for example, a thermal process (e.g., oxide bonding).
- a thermal process e.g., oxide bonding
- additional layers may be disposed between the back surface 18 b of the buried insulator layer 18 and the top surface 42 a of the final substrate 42 .
- the device layer 16 , the buried insulator layer 18 , and the interconnect structure 40 are positioned between the temporary substrate 14 and the final substrate 42 .
- the handle wafer 20 which may be an inexpensive substrate (e.g., a common silicon wafer), is present during processing to fabricate the integrated circuits of the chip and is then replaced by the final substrate 42 to provide the final assembly 44 that may be expected to exhibit improved performance metrics.
- an inexpensive substrate e.g., a common silicon wafer
- the formation of the recess 46 may be omitted so that the layer 48 only coats the back surface 18 b of the buried insulator layer 18 and is electrically connected in the plane of the back surface 18 b with the contact plug 30 .
- the contact plug 30 is formed entirely from the initially deposited material.
- the contact plug 30 may be completely removed from the trench 24 and a new contact plug may be formed in the trench 24 that is comprised entirely of the material of the layer 48 and that replaces the contact plug 30 .
- the new contact plug may be formed entirely from trap-rich material.
- the contact plug 30 may be comprised of a trap-rich material when it is initially deposited in the trench 24 .
- the process flow continues with the thinning of the buried insulator layer to reveal the contact plug 30 and the attachment of the final substrate 42 to form an assembly 64 in which the contact plug 30 provides the electrically-conducting connection.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
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Abstract
Description
- The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to device structures and fabrication methods for a backside contact to a final substrate.
- Devices fabricated using semiconductor-on-insulator (SOI) technologies may exhibit certain performance improvements in comparison with comparable devices built directly in a bulk silicon substrate. Generally, an SOI wafer includes a thin device layer of semiconductor material, a handle substrate, and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the device layer from the handle substrate. Integrated circuits are fabricated using the semiconductor material of the device layer.
- Wafer thinning has been driven by the need to make packages thinner to accommodate stacking and high density packaging of chips. An SOI wafer may be thinned by removing the handle wafer from its construction. Once thinned, the backside surface of the SOI wafer may be subjected to additional operations. To lend mechanical support during thinning and the additional operations performed subsequent to thinning, the frontside surface bearing the integrated circuits may be adhesively bonded to a temporary substrate. After the additional operations are performed, a final substrate may be attached to the backside surface and the temporary substrate may be removed.
- Improved device structures and fabrication methods are needed for a backside contact to a final substrate.
- In an embodiment of the invention, a method is provided for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. An electrically-conducting connection is formed that extends through the device layer and partially through the buried insulator layer. After the electrically-conducting connection is formed, the handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection contacts the final substrate. The backside contact comprises the electrically-conducting connection.
- In an embodiment of the invention, a device structure formed using a silicon-on-insulator substrate. The device structure includes a device layer of the silicon-on-insulator substrate and a buried insulator layer of the silicon-on-insulator substrate. The buried insulator layer has a first surface in contact with the device layer and a second surface. A trap-rich layer is disposed on the second surface of the buried insulator layer and is located between a substrate and the buried insulator layer. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate, the electrically-conducting connection at least partially comprised of trap-rich material.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIGS. 1-3 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an embodiment of the invention. -
FIGS. 4-5 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an alternative embodiment of the invention. -
FIG. 6 is a cross-sectional view similar toFIG. 5 of a portion of a substrate in accordance with an alternative embodiment of the invention. -
FIGS. 7-8 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an alternative embodiment of the invention. - With reference to
FIG. 1 and in accordance with an embodiment of the invention, anassembly 10 includes a semiconductor-on-insulator (SOI)substrate 12 and atemporary substrate 14 that is removably attached to theSOI substrate 12. TheSOI substrate 12 may include adevice layer 16, a buriedinsulator layer 18, and a handle wafer 20. Thedevice layer 16 is separated from thehandle wafer 20 by the intervening buriedinsulator layer 18 and is considerably thinner than thehandle wafer 20. Thedevice layer 16 is in direct contact with afront surface 18 a of the buriedinsulator layer 18, and the buriedinsulator layer 18 includes a backside orback surface 18 b in direct contact with thehandle wafer 20. The buriedinsulator layer 18 may be comprised of an electrical insulator and, in particular, may be a buried oxide layer comprised of silicon dioxide (e.g., SiO2). - Shallow
trench isolation regions 22 may be formed in thedevice layer 16 of theSOI substrate 12 to define a device region in thedevice layer 16. The shallowtrench isolation regions 22 may be formed by depositing a hardmask, patterning the hardmask anddevice layer 16 with lithography and etching processes to define trenches, depositing an electrical insulator to fill the trenches, planarizing the electrical insulator relative to the hardmask using a chemical mechanical polishing (CMP) process, and removing the hardmask. In one embodiment, the shallowtrench isolation regions 22 may be comprised of silicon dioxide (SiO2) deposited by low-pressure chemical vapor phase deposition (LPCVD), and may penetrate completely through thedevice layer 16 to thefront surface 18 a of the buriedinsulator layer 18. - A
trench 24 is formed that extends from atop surface 16 a of thedevice layer 16 through thedevice layer 16, beyond afront surface 18 a of the buriedinsulator layer 18 forming an interface with thedevice layer 16, and partially through the buriedinsulator layer 18. Thesidewalls 26 of thetrench 24 do not penetrate through theinterface 19 between the buriedinsulator layer 18 and the handle wafer 20. Thetrench 24 has a bottom surface 28 that is separated from theinterface 19 by a partial thickness, t, or portion of the buriedinsulator layer 18. To form thetrench 24, a mask layer may be applied on atop surface 16 a of thedevice layer 16 and patterned with photolithography. Specifically, an opening is defined in the mask layer at the intended location of thetrench 24 to be subsequently formed. To that end, the mask layer may comprise a light-sensitive material, such as a photoresist, that is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an etch mask. An etching process is used, with the mask layer present on thetop surface 16 a of thedevice layer 16, to form thetrench 24 at the location of the opening. The etching process may be conducted in a single etching step or multiple etching steps, may rely on one or more etch chemistries, and may be performed under conditions controlled to provide the limited penetration depth into theSOI substrate 10. The mask layer may be removed after thetrench 24 is formed by the etching process. If comprised of a photoresist, the mask layer may be removed by ashing or solvent stripping, followed by a conventional cleaning process. - A
contact plug 30 is formed in thetrench 24 and conforms in geometrical shape to the geometrical shape of thetrench 24. In that regard, the sidewalls and bottom surface of thecontact plug 30 are respectively coextensive with thesidewalls 26 and bottom surface 28 of thetrench 24. Thecontact plug 30 extends from one end adjacent to thetop surface 16 a of thedevice layer 16 through thedevice layer 16 and partially through the buriedinsulator layer 18 to an opposite end that is proximate to theinterface 19. As a consequence of the limited depth of thetrench 24, thecontact plug 30 terminates within the buriedinsulator layer 18. - The
contact plug 30 may be comprised of a semiconductor material. In a representative embodiment, the semiconductor material comprising thecontact plug 30 may be polysilicon (i.e. polycrystalline silicon) representative that is deposited by chemical vapor deposition (CVD). The polysilicon of thecontact plug 30 may contain a dopant (e.g., an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) or a p-type dopant from Group III of the Periodic Table (e.g., boron)) in a concentration effective to enhance its electrical conductivity and to either impart either n-type or p-type conductivity to the polysilicon. - Front-end-of-line (FEOL) processing is used to fabricate device structures of one or more integrated circuits using the
device layer 16 and form a chip. The device structures may be bipolar junction transistors, field effect transistors, and/or coplanar waveguide (CPW) transmission lines, and the integrated circuits on chips formed from theassembly 10 may be configured for end use in high-frequency and high-power applications (e.g., power amplifiers for wireless communications systems and mobile devices) and in high-speed logic circuits. The integrated circuits may include various functional blocks, such as switches, power amplifiers, power management units, filters, etc. - Middle-of-line (MOL) and back-end-of-line (BEOL) processing follows FEOL processing to form an
interconnect structure 40 on thedevice layer 16 of theSOI substrate 12. Theinterconnect structure 40 is coupled with the integrated circuits of the chip. Other active and passive circuit elements, such as diodes, resistors, capacitors, varactors, and inductors, may be integrated into theinterconnect structure 40 and available for use in the integrated circuit. Theinterconnect structure 40 may be comprised of a plurality of wiring levels that supply conductive paths for signals, clock, power, etc. - In the representative embodiment, the
interconnect structure 40 includes awiring level 32 with awire 34 located in adielectric layer 33 and awiring level 36 with a conductor-filled via 38 located in adielectric layer 39. Thecontact plug 30 is coupled with thewire 34 by the conductor-filled via 38. Thewiring levels wire 34 and the conductor filling the via 38 are metals such as copper (Cu), aluminum (Al), and tungsten (W). These types of metals may be deposited by chemical vapor deposition or by an electrochemical process like electroplating or electroless plating. The dielectric layers 33, 39 may be comprised of any suitable organic or inorganic dielectric material, such as silicon dioxide, hydrogen-enriched silicon oxycarbide (SiCOH), fluorosilicate glass (FSG), or another type of low-k dielectric material that may be deposited by chemical vapor deposition, such as low-pressure chemical vapor phase deposition or plasma-enhanced chemical vapor deposition (PECVD). - The
temporary substrate 14 is removably attached to atop surface 40 a of theinterconnect structure 40 at the frontside of theSOI substrate 12 while thehandle wafer 20 is intact and after thecontact plug 30 and theinterconnect structure 40 are formed. For example, thetemporary substrate 14 may be adhesively bonded by anadhesive layer 41 to thetop surface 40 a ofinterconnect structure 40 in order to provide the removability. Thetemporary substrate 14 is sufficiently thick for mechanical handling when thehandle wafer 20 is removed in subsequent fabrication stage to thin theSOI substrate 10 at its backside. Thetemporary substrate 14 may be comprised of quartz or a glass, and theadhesive layer 41 may be comprised of a polymer adhesive. The adhesive strength of theadhesive layer 41 may be selected such that thetemporary substrate 14 is readily removable from the top surface of theinterconnect structure 40 in a subsequent debonding operation. - With reference to
FIG. 2 in which like reference numerals refer to like features inFIG. 1 and at a subsequent fabrication stage of the processing method, thehandle wafer 20 is removed in its entirety by grinding, etching, and/or polishing to expose theback surface 18 b of the buriedinsulator layer 18. The removal of thehandle wafer 20 may be performed selective to the removal of the buriedinsulator layer 18 so that the buriedinsulator layer 18 remains intact after thehandle wafer 20 is removed. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate for the targeted material is higher than the removal rate for at least another material exposed to the material removal process. - After the
handle wafer 20 is removed and with thetemporary substrate 14 attached, the buriedinsulator layer 18 may be partially removed at itsback surface 18 b selective to the material (e.g., polysilicon) of thecontact plug 30 so that the buriedinsulator layer 18 is thinned before proceeding to the next fabrication stage. The partial removal of the buriedinsulator layer 18 may be accomplished by polishing and/or etching processes so that thecontact plug 30 is revealed at the bottom surface 28 of thetrench 24. In other words, the buriedinsulator layer 18 is thinned at least to reach the bottom surface 28 of thetrench 24. After exposure, the tip of thecontact plug 30 may project by a short distance beyond theback surface 18 b of the buriedinsulator layer 18. In an alternative embodiment, the tip of thecontact plug 30 may be coplanar with theback surface 18 b. If the buriedinsulator layer 18 is comprised of silicon dioxide and thecontact plug 30 is comprised of polysilicon, a hydrofluoric acid based etchant may be used to remove the material of the buriedinsulator layer 18 selective to (i.e., at a higher etch rate than) the material of thecontact plug 30. - With reference to
FIG. 3 in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of the processing method, afinal substrate 42 is attached to the buriedinsulator layer 18 to create an intermediate assembly. Thetemporary substrate 14 is subsequently removed without disturbing the bond between thefinal substrate 42 and the buriedinsulator layer 18 to provide afinal assembly 44, which includes thedevice layer 16, the buriedinsulator layer 18, theinterconnect structure 40, and thefinal substrate 42. In particular, theback surface 18 b of the buriedinsulator layer 18 is placed in contact with atop surface 42 a of thefinal substrate 42, and thesesurfaces back surface 18 b of the buriedinsulator layer 18 and thetop surface 42 a of thefinal substrate 42. In this intermediate assembly, thedevice layer 16, the buriedinsulator layer 18, and theinterconnect structure 40 are positioned between thetemporary substrate 14 and thefinal substrate 42. - After attachment to the
final substrate 42, thetemporary substrate 14 is removed without disturbing the bond between thefinal substrate 42 and the buriedinsulator layer 18 to provide afinal assembly 44 that includes thedevice layer 16 and theinterconnect structure 40. Thetemporary substrate 14 functions to facilitate the transfer of the integrated circuits in and on thedevice layer 16 to thefinal substrate 42, which carries thedevice layer 16, the buriedinsulator layer 18, and theinterconnect structure 40. Thefinal substrate 42 in thefinal assembly 44 replaces thehandle wafer 20 of theSOI substrate 10 in theinitial assembly 10. - The
final substrate 42 may be engineered to reduce harmonics, which may improve linearity in advanced generation switch technology by reducing harmonic distortion (e.g., the linearity observed at the output of coplanar waveguide transmission lines) in comparison with the harmonic distortion that may be expected to be observed with thehandle wafer 20 intact and in place at the backside. For example, the second and third harmonics may be improved by more than 20 dB, which may permit devices to meet or surpass inter-modulation distortion switch specifications. In various embodiments, thefinal substrate 42 may be an engineered high-resistance wafer comprised of high resistance silicon, sapphire, quartz, alumina, etc. Thehandle wafer 20, which may be an inexpensive substrate (e.g., a common silicon wafer), is present during processing to fabricate the integrated circuits of the chip and is then replaced by thefinal substrate 42 to provide thefinal assembly 44 that may be expected to exhibit improved performance metrics. - The
contact plug 30 provides an electrical contact (i.e., an ohmic contact) that contributes to an electrically-conducting connection between thedevice layer 16 and thehandle wafer 20, and ultimately between thedevice layer 16 and thefinal substrate 42 in theassembly 44 and in the final assembly formed fromassembly 44 by removing thetemporary substrate 14. Thecontact plug 30 allows the substrate potential to be controlled by a terminal on the integrated circuit side of theassembly 44 and thereby used to prevent charging events/effects at the times of testing or use that may otherwise arise due to thehandle wafer 20 orfinal substrate 42 floating to a high and unstable potential. - The electrical contact provided by the
contact plug 30 is formed and terminated, when formed, within the buriedinsulator layer 18 of theSOI substrate 12. During the removal of thehandle wafer 20, thecontact plug 30 is not removed and is protected within the buriedinsulator layer 18. Subsequent to the removal of thehandle wafer 20, the buriedinsulator layer 18 is thinned to reveal thecontact plug 30 so that thefinal substrate 42 can make electrical contact with thecontact plug 30 upon bonding of thefinal substrate 42 to the buriedinsulator layer 18. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of a processing method in accordance with an alternative embodiment, thecontact plug 30 may be recessed relative to theback surface 18 b of the buriedinsulator layer 18 to define a cavity or recess 46 at the former location of the removed section of thecontact plug 30. The recess 46 extends into thetrench 24 in which the residual material of thecontact plug 30 resides. In an embodiment, the recess 46 may be formed by etching thecontact plug 30 using an etching process that removes the material of thecontact plug 30 selective to (i.e., at a higher rate than) the material of the buriedinsulator layer 18. An exemplary etching process that may be used is a reactive ion etch process using SF6 or Ar/NF3 gas chemistries. - After the
contact plug 30 is recessed, alayer 48 may be deposited that coats (i.e., is in direct contact with) theback surface 18 b of the buriedinsulator layer 18. Aportion 50 of the material of thelayer 48 may fill the recess 46 to reform thecontact plug 30. Thelayer 48 is in contact with thecontact plug 30 and buriedinsulator layer 18, and is eventually in contact with thefinal substrate 42. Thelayer 48 may be comprised of a trap-rich material, such as a polycrystalline semiconductor material like polysilicon or another type of engineered low-mobility silicon layer, and may be deposited by chemical vapor deposition with deposition conditions (e.g., temperature and pressure) selected to impart a high density of electrically-active carrier traps. For example, the layer may be deposited with low-temperature chemical vapor deposition. In an embodiment, the carrier traps may impart thelayer 48 with a resistivity greater than 1 kΩ-cm. Thecontact plug 30 may be considered to be a composite structure composed of the residual portion of the original material (e.g., polysilicon) filling thetrench 24 and theportion 50 of the trap-rich material contributed bylayer 48 filling the recess 46. - In an alternative embodiment, the
layer 48 may be deposited in a condition that is not trap-rich and subsequently modified, after deposition, by ion implantation so that the deposited semiconductor material is altered to become enriched with traps. The implanted ions may be generated, for example, from a noble gas (e.g., argon) or from a silicon source gas. The implantation parameters may be selected to provide a projected range and a range straggle confined within the thickness oflayer 48, and may also be selected to include multiple energies and ion doses. - In an alternative embodiment, the formation of the recess 46 may be omitted so that the
layer 48 only coats theback surface 18 b of the buriedinsulator layer 18 and is electrically connected in the plane of theback surface 18 b with thecontact plug 30. Accordingly, thecontact plug 30 is formed entirely from the initially deposited material. In an alternative embodiment, thecontact plug 30 may be completely removed from thetrench 24 and a new contact plug may be formed in thetrench 24 that is comprised entirely of the material of thelayer 48 and that replaces thecontact plug 30. The new contact plug may be formed entirely from trap-rich material. In an alternative embodiment, thecontact plug 30 may be comprised of a trap-rich material when it is initially deposited in thetrench 24. For example, thecontact plug 30 may be comprised of polysilicon deposited under conditions to provide a trap-rich material containing a high density of electrically-active carrier traps instead of being deposited under conditions (e.g., at a high substrate temperature) at which the polysilicon is not deposited in a trap-rich state. - With reference to
FIG. 5 in which like reference numerals refer to like features inFIG. 4 and at a subsequent fabrication stage of the processing method, the process flow continues with the attachment of thefinal substrate 42 to form theassembly 44. The attachment may be provided by aninterface layer 52 between confronting surfaces of thefinal substrate 42 and thelayer 48. Theinterface layer 52 intervenes between thefinal substrate 42 and thelayer 48 so that they are non-contacting and so that thefinal substrate 42 and theback surface 18 b are indirectly attached. In one embodiment, theinterface layer 52 may comprise a conductive material, such as an adhesive like a conductive, low-mobility epoxy, that adhesively bonds thefinal substrate 42 to thelayer 48. - In an alternative embodiment, the
layer 48 may be omitted and the material of theinterface layer 52 may be used to directly attach thetop surface 42 a of thefinal substrate 42 to theback surface 18 b of the buriedinsulator layer 18. If a recess 46 is present in thetrench 24 when theinterface layer 52 is formed, the material of theinterface layer 52 may also occupy the space inside of the recess 46 that is not occupied by thecontact plug 30. - With reference to
FIG. 6 in which like reference numerals refer to like features inFIG. 5 and in accordance with an alternative embodiment, anassembly 54 includes device structures in the form of switches 56, 58 that may be formed using thedevice layer 16 by FEOL processing. The switches 56, 58 may be constructed from transistors and, specifically, may comprise NPN or PNP bipolar junction transistors, non-fin-type or planar field effect transistors, or fin-type field effect transistors. - The
assembly 54 is otherwise similar in construction toassembly 10. Thetrench isolation regions 22, along with the buriedinsulator layer 18, electrically isolate the device region used to form switch 56 from the device region used to form switch 58. Another trench 59 is formed when thetrench 24 is formed and anothercontact plug 60 is formed in the trench 59 when thecontact plug 30 is formed in thetrench 24. In the representative embodiment, thecontact plug 60 is also a composite structure similar to contactplug 30 in that anotherportion 51 of thelayer 48 fills a recess 47 similar to recess 46. In alternative embodiments, thecontact plug 60 may be comprised of the semiconductor material initially deposited in the trench 59, or thecontact plug 60 may be comprised entirely of the material of the trap-rich layer 48. The contact plugs 30, 60 may have the same construction (e.g., both contact plugs 30, 60 may be composite structures comprised in part of material from the trap-rich layer 48). The contact plugs 30, 60 are arranged in theassembly 54 to surround the switch 56, which effectively isolates the switch 56 from the harmonics generated by switch 58. Collectively, the contact plugs 30, 60 may be considered to provide the electrically-conducting connection. - With reference to
FIG. 7 in which like reference numerals refer to like features inFIG. 1 and in accordance with an alternative embodiment, thetrench 24 may be lined with a layer 62 positioned between thecontact plug 30 and thedevice layer 16 and buriedinsulator layer 18. Specifically, the layer 62 may be formed on thesidewalls 26 and bottom surface 28 oftrench 24 before thecontact plug 30 is formed. The layer 62 functions as an etch stop when the buriedinsulator layer 18 is thinned to reveal thecontact plug 30 and may be comprised of a dielectric material, such as silicon nitride (Si3N4) or silicon dioxide formed by a high density plasma process. - With reference to
FIG. 8 in which like reference numerals refer to like features inFIG. 7 and at a subsequent fabrication stage of the processing method, the process flow continues with the thinning of the buried insulator layer to reveal thecontact plug 30 and the attachment of thefinal substrate 42 to form anassembly 64 in which thecontact plug 30 provides the electrically-conducting connection. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refers to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a dimension within the horizontal plane.
- A feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
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US20180175063A1 (en) * | 2016-12-15 | 2018-06-21 | Vanguard International Semiconductor Corporation | Semiconductor device and method for manufacturing the same |
US10043824B2 (en) * | 2016-12-15 | 2018-08-07 | Vanguard International Semiconductor Corporation | Semiconductor device including a vacuum gap and method for manufacturing the same |
US11107881B2 (en) * | 2019-04-25 | 2021-08-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor package devices having conductive layer, semiconductor wall, conductive wall, and insulation layer |
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US20170011962A1 (en) | 2017-01-12 |
US10573554B2 (en) | 2020-02-25 |
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US20190267285A1 (en) | 2019-08-29 |
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US10074561B2 (en) | 2018-09-11 |
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US10361123B2 (en) | 2019-07-23 |
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US10629482B2 (en) | 2020-04-21 |
US20180040509A1 (en) | 2018-02-08 |
US20180068891A1 (en) | 2018-03-08 |
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