CN104051419A - Interconnect Structure for Stacked Device - Google Patents
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- CN104051419A CN104051419A CN201310463691.4A CN201310463691A CN104051419A CN 104051419 A CN104051419 A CN 104051419A CN 201310463691 A CN201310463691 A CN 201310463691A CN 104051419 A CN104051419 A CN 104051419A
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Abstract
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers. The invention also discloses an interconnect structure for stacked device.
Description
It is No.61/798 that this patent requires the sequence number that on March 15th, 2013 submits to, the priority of 459 patent application, and present patent application is incorporated herein by reference.
Technical field
The present invention relates to technical field of semiconductors, more specifically, relate to the interconnection structure for stack device.
Background technology
Semiconductor integrated circuit (IC) industry has experienced rapid growth.In the course developing at IC, functional density (, the number of the interconnect devices of per unit chip area) has increased, and physical dimension (minimal parts (or circuit) that, can use manufacturing process to manufacture) has reduced.The advantage that this dimension reduction technique provides is that it has improved production efficiency and has reduced relevant cost.
Along with semiconductor technology further develops, stacked IC device occurs as effective optional mode, further to reduce the physical size of semiconductor device.In stacked IC device, active circuit (for example, logical circuit, memory circuitry, processor circuit etc.) is manufactured on different semiconductor crystal wafers.Then, the semiconductor crystal wafer of two or more is arranged on mutual top to form stacked IC.For example, two semiconductor crystal wafers can be bonded together by suitable joining technique, are then assembled into single stacked IC device.A kind of advantage of stacked IC device is to realize high density.Although the method for existing stacked IC device and manufacture stacked IC device has met people's expection phase object conventionally, people can't all be met in all respects.Being desirably in this field improves.
Summary of the invention
In order to solve existing problem in prior art, according to an aspect of the present invention, provide a kind of device, comprising:
The first semiconductor element, comprising:
The first substrate;
Dielectric block in described the first substrate; With
Multiple the first conductive components, are formed in the first metal intermetallic dielectric layer of described the first substrate top;
The second semiconductor element, is engaged to described the first semiconductor element, and wherein, described the second semiconductor element comprises:
The second substrate; With
Multiple the second conductive components, are formed in the second metal intermetallic dielectric layer of described the second substrate top; And
The dark interconnection of conduction connector, is connected between described the first conductive component and described the second conductive component and by described dielectric block, described the first metal intermetallic dielectric layer and described the second metal intermetallic dielectric layer and isolates, and the described conduction connector that deeply interconnects comprises:
Be formed on the top in described dielectric block and described the first metal intermetallic dielectric layer, described top has the first width; With
Be formed on the bottom in described the first metal intermetallic dielectric layer and described the second metal intermetallic dielectric layer, described bottom has the second width that is less than described the first width.
In optional embodiment, described the first conductive component interconnects during the bottom of connector as etch hard mask deeply forming described conduction.
In optional embodiment, described conduction interconnects the top of connector deeply by described dielectric block and described the first metal intermetallic dielectric layer isolation.
In optional embodiment, described conduction interconnects the bottom of connector deeply by described the second metal intermetallic dielectric layer isolation.
In optional embodiment, described device also comprises: be formed on the groove area in the first side of described the first conductive component.
In optional embodiment, multiple conductions connector that deeply interconnects is formed in single dielectric block.
In optional embodiment, the single conduction connector that deeply interconnects is formed in described dielectric block.
According to a further aspect in the invention, also provide a kind of stacked integrated circuit device, having comprised:
The first semiconductor element, has the first substrate, is arranged on the first conductive component of dielectric block in described the first substrate and described the first substrate top;
The second semiconductor element, is engaged to described the first semiconductor element, and described the second semiconductor element comprises the second substrate and is positioned at the second conductive component of described the second substrate top; And
Be connected to conduction between described the first conductive component and described the second conductive component connector that deeply interconnects, wherein, the described conduction connector that deeply interconnects comprises:
Have the top of the first width, the described top of part isolates by described dielectric block; With
There is the bottom of the second width.
In optional embodiment, deeply interconnect first width on top of connector of described conduction is greater than the second width of described bottom substantially.
In optional embodiment, described device also comprises: be formed on the groove area in the first side of described the first conductive component.
In optional embodiment, described device also comprises: be arranged on the first intermetallic dielectric (IMD) layer in described the first semiconductor element; And, be arranged on the second intermetallic dielectric (IMD) layer in described the second semiconductor element.
In optional embodiment, deeply the interconnect top of connector of described conduction is arranged in described dielectric block and a described IMD layer, and deeply the interconnect bottom of connector of described conduction is arranged in a described IMD layer and described the 2nd IMD layer.
In optional embodiment, multiple conductions connector that deeply interconnects is formed in single dielectric block.
In optional embodiment, the single conduction connector that deeply interconnects is formed in described dielectric block.
According to another aspect of the invention, also provide a kind of method, having comprised:
The first semiconductor element is provided, and described the first semiconductor element comprises:
The first substrate;
The first intermetallic dielectric (IMD) layer of described the first substrate top; With
The first conductive component in a described IMD layer;
Described the first semiconductor element is engaged to the second semiconductor element, and wherein, described the second semiconductor element comprises:
The second substrate;
The second intermetallic dielectric (IMD) layer of described the second substrate top; And
The second conductive component in described the 2nd IMD layer;
In described the first substrate, form substrate trenches;
Fill described substrate trenches with dielectric material and there is the dielectric block on the substantially flat surface concordant with described the first substrate to form;
Above smooth described the first substrate and described dielectric block, form pattern mask;
Through dielectric block, a described IMD layer and described the 2nd IMD layer of part described in described pattern mask etching to form dark interconnection channel; And
Fill described dark interconnection channel with electric conducting material and connect described the first conductive component and described the second conductive component to form dark interconnection connector.
In optional embodiment, the substantially flat surface of described dielectric block and described the first substrate forms by chemico-mechanical polishing (CMP).
In optional embodiment, described dark interconnection channel by photoetching and with respect to described the first conductive component have sufficient etching selectivity selective etch technique form.
In optional embodiment, described the first conductive component is as etch hard mask.
In optional embodiment, described dark interconnection connector has upper and lower.
In optional embodiment, the width on the top of described dark interconnection connector is greater than the width of bottom substantially.
Brief description of the drawings
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.Should be emphasized that, according to the standard practices in industry, various parts not drawn on scale and the only object for illustrating.In fact,, in order clearly to discuss, the size of various parts can be increased arbitrarily or be reduced.
Fig. 1 is the sectional view of stacked integrated circuit (IC) device of the each side according to the present invention.
Fig. 2 is the flow chart of the exemplary method of the manufacture stacked IC device of the each side according to the present invention.
Fig. 3 A to Fig. 3 B and Fig. 4 to Fig. 7 are according to the sectional view of the example stacked IC device in the fabrication stage of the method construct of Fig. 2.
Embodiment
Following discloses text provides multiple different embodiment or example, for realizing different characteristic of the present invention.The particular instance of assembly and layout is described below to simplify the present invention.Certainly, these are only examples and are not intended to limit the present invention.For example, in the following description, above second component or above form first component and can comprise that first component and second component directly contact the embodiment of shaping, thereby and also can comprise that other is formed with the embodiment that other parts make first component directly not contact with second component between first component and second component.In addition, the present invention can be in Multi-instance repeat reference numerals and/or character.This be recycled and reused for simplify and clear, and itself do not specify described multiple embodiment and/or configuration between relation.
In addition, this can use such as " ... under ", " ... below ", " below ", " ... above " and the spatial relationship term of " above " etc., to describe element as shown in FIG. or the relation of parts and another element or parts.Except the orientation shown in figure, spatial relationship term will comprise the different azimuth of device in using or operating.For example, if the device shown in flipchart, be described as be in other element or parts " below " or " under " element will be positioned in " above " of other element or parts.Therefore, exemplary term " ... be included in above and orientation below below ".Device can otherwise be located (90-degree rotation or in other orientation), and correspondingly explains by spatial relation description symbol as used herein.
Fig. 1 is the sectional view of the stacked IC device before joint technology of each side according to the present invention.For the sake of clarity, Fig. 1 is simplified, so that summary of the invention of the present invention to be described better.This accompanying drawing shows the first semiconductor crystal wafer 100, is stacked on the top of the second semiconductor crystal wafer 200.For example, the first semiconductor crystal wafer 100 is imageing sensor, such as back side illumination image sensor (BIS), complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor (CIS), charge-coupled device (CCD), CMOS active pixel sensor (APS) or passive pixel sensor.Imageing sensor can be by the manufacture of complementary metal oxide semiconductors (CMOS) known in the art (CMOS) technology.For example, P type photosensitive region and N-type photosensitive region are formed on the substrate top of imageing sensor wafer to form PN junction, and this PN junction is as photodiode.Imageing sensor wafer 100 can comprise that transistor is to produce the signal relevant with striking light intensity on photosensitive region or brightness.Continue this example, the second semiconductor crystal wafer 200 is application-specific integrated circuit (ASIC) (ASIC) wafer.
As shown in Figure 1, the first semiconductor crystal wafer 100(illustrates to be inverted orientation) comprise the first substrate 102 and one or more the first intermetallic dielectrics (IMD) layers 104 that form above the first substrate.In addition, multiple the first conductive components (for example, conductive component 106 and 108) form in IMD layer 104.
The first substrate 102 comprises elemental semiconductor, for example silicon or germanium; And/or compound semiconductor, for example SiGe, carborundum, GaAs, indium arsenide, gallium nitride and indium phosphide.Other exemplary substrate materials comprises alloy semiconductor, for example, and carbonization SiGe, gallium arsenide phosphide and InGaP.The first substrate 102 also can comprise non-semiconductor material, for example, and soda-lime glass, vitreous silica, vitreosil, calcirm-fluoride (CaF
2) and/or other suitable material.In certain embodiments, the first substrate 102 has restriction one deck or multilayer therein, for example, and epitaxial loayer.For example, in such embodiment, the first substrate 102 comprises the epitaxial loayer that covers bulk semiconductor top.Other laminate substrate comprises semiconductor-on-insulator (SOI) substrate.In a this SOI substrate, the first substrate 102 comprises and buries oxygen (BOX) layer by what form such as note oxygen isolation (SIMOX) technique.In various embodiments, the first substrate 102 can adopt form and/or other form well known by persons skilled in the art of planar substrate, fin-shaped substrate, nano wire.
The first substrate 102 can comprise one or more doped region.In described embodiment, the first substrate 102 is doped with P type dopant.Suitable P type dopant comprises boron, gallium, indium, other suitable P type dopant and/or their combination.The first substrate 102 also can comprise one or more district doped with the N-type dopant such as phosphorus, arsenic and other suitable N-type dopant and/or their combination.In plurality of step and technology, can use the process implementing doping such as Implantation or diffusion.
In various embodiments, the first substrate 102 can adopt planar substrate, fin-shaped substrate, nano wire and/or other form well known by persons skilled in the art.
The first semiconductor crystal wafer 100 can comprise various passive and active microelectronic components.These parts can comprise critical piece (for example, image sensor element) and peripheral circuit element (for example, one or more field-effect transistor).Other example comprises P-channel field-effect transistor (PEFT) transistor (PFET), N slot field-effect transistor (NFET), mos field effect transistor (MOSFET), CMOS transistor, FinFET, high voltage transistor, high frequency transistor, bipolar junction transistor, resistor, capacitor, diode, electric fuse and other suitable device and/or their combination.In certain embodiments, peripheral circuit element can operate with or control main element mutual with main element.But, in further embodiments, on being configured in same substrate 102, peripheral circuit element and main element do not have functional relationship.
The one IMD layer 104 can comprise silica, silicon nitride, silicon oxynitride, polymer or other suitable material.The one IMD layer 104 can form by chemical vapor deposition (CVD), high density ionomer cvd (HDP-CVD), physical vapor deposition (PVD), ald (ALD) and/or other suitable depositing operation.The one IMD layer 104 can comprise multiple layers of being manufactured by different dielectric material.
The first conductive component 106 and 108 can by any suitable formation technique (for example, with etching, inlay, the photoetching of dual damascene etc.) manufacture, and can use such as the suitable electric conducting material such as copper, aluminium, aluminium alloy, copper alloy and form.
Other parts can be attached in the first semiconductor crystal wafer 100, and for other embodiment of the first semiconductor crystal wafer 100, some above-mentioned structures can be replaced or remove.
Compared with the first semiconductor crystal wafer 100, the second semiconductor crystal wafer 200 can comprise identical or different elements.For example, the second semiconductor crystal wafer 200 comprises the second substrate 202, the 2nd IMD layer 204 and multiple the second conductive component 206 and 208.
Fig. 2 is the flow chart of the method that is used to form stacked IC device 300 of each side according to the present invention.Fig. 3 A, Fig. 3 B and Fig. 4 to Fig. 7 are through according to the sectional view of the handled exemplary stack formula of the method for Fig. 2 IC device 400.Should be appreciated that can be before the method, between and additional step is provided afterwards, and for other embodiment of the method, more described steps can be replaced or remove.
With reference to Fig. 2 and Fig. 3 A, method 300 starts from step 302, by the suitable joining technique such as direct joint, the first semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 is combined.In one embodiment, in the first semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200, be formed with respectively multiple bond pads.In this embodiment, the bond pad that is positioned at the second semiconductor crystal wafer 200 is aimed at face-to-face with the bond pad of answering in contrast that is positioned at the first semiconductor crystal wafer 100.According to some embodiment, in direct joint technology, connection between the first semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 can be by metal and metal bond (for example, copper engages with copper), dielectric (for example engages with dielectric, oxide engages with oxide), metal engages (for example, copper engages with oxide) with dielectric or their combination realizes.In certain embodiments, the first semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 are connected to each other by suitable three-dimensional structure.Also can use adhesion layer.
In addition, can carry out thinning technique with the back side thinning from any or two substrates.Thinning technique can comprise mechanical milling tech and/or chemical thinning technique.For example, during mechanical milling tech, a large amount of backing materials can be removed from the first substrate 102.Afterwards, chemical thinning technique can be to the back side application based etch chemistry of the first substrate 102 with further thinning the first substrate 102.
Continue with reference to Fig. 2 and Fig. 3 A, method 300 proceeds to step 304, removes part the first substrate 102 to form substrate trenches 120.In one embodiment, above the back side of the first substrate 102, be formed with bottom anti-reflective and be coated with (BARC) layer 110.BARC layer 110 can comprise nitride material, organic material, oxide material etc.BARC layer 110 can use such as the suitable technology of CVD, PVD etc. and form.
Substrate trenches 120 can form by chemical etching technique.As an example, above the first substrate 102, form the photoresist layer of patterning by spin coating, exposure and developing process.Then by the photoresist of patterning, the first substrate 102 is carried out to etching.This etch process can comprise dry method etch technology, wet etching process and/or their combination.Etch process also can comprise selectivity wet etching or selectivity dry etching.The wet etching solution of example comprises tetramethyl ammonium hydroxide (TMAH), HF/HNO
3/ CH
3cOOH solution or other suitable solution.The dry method etch technology of example can comprise the biasing plasma etch process that uses chloro chemical agent.Other example dry etchant gas comprises CF4, NF3, SF6 and He.In certain embodiment, with respect to an IMD layer 104, the selective etch carrying out has sufficient etching selectivity.
As shown in Figure 3A, in one embodiment, the size of the substrate trenches 120 of formation makes it comprise more than one dark interconnection connector.This will be discussed in more detail below.As shown in Figure 3 B, in another embodiment, the size of the substrate trenches 120 of formation makes it comprise dark interconnection in single future connector.For the purpose of example, below open by the embodiment for Fig. 3 A.Should be appreciated that and can on the embodiment of Fig. 3 B, implement identical step.
With reference to Fig. 2 and Fig. 4, method 300 proceeds to step 306, fills dielectric layer 130 to form dielectric block 135 in the first substrate 102 at substrate trenches 120.Dielectric layer 130 can comprise silica, noncrystal carbon fluoride, Parylene, polyimides, low k dielectric, other suitable material and/or their combination such as silicon dioxide, silicon nitride, silicon oxynitride, TEOS oxide, phosphosilicate glass (PEG), boron phosphorus silicate glass (BPSG), fluorosilicate glass (FSG), carbon doping.Common methods for dielectric layer 130 comprises thermal oxidation, CVD, high-density plasma CVD (HDP-CVD), PVD, ALD, spin-on deposition and/or other suitable depositing operation.
In the present embodiment, application such as the technique of chemico-mechanical polishing (CMP) is carried out and the first substrate 102(BARC layer 110 dielectric block 135 planarizations) end face concordant, thereby obtain the surface of the substantially flat that is used for photoetching process below.
With reference to Fig. 2 and Fig. 5, method 300 proceeds to step 308, above comprising the first substrate 102 of dielectric block 135, forms the pattern mask 140 with dark interconnection channel (DIT) opening 145.Pattern mask 140 can be photoresist layer or hard mask.Pattern mask 140 is formed on the end face of the first substrate 102 and dielectric block 135 by suitable deposition, chemical etching technology.In the present embodiment, pattern mask 140 is formed on the substantially flat surface of being manufactured by the first substrate 102 and dielectric block 135, and it can improve the process window of photoetching process.DIT opening 145 be arranged on the second semiconductor crystal wafer 200 in corresponding conductive component 206 and 208 aim at.
With reference to Fig. 2 and Fig. 6, method 300 proceeds to step 310, forms the dark interconnection channel (DIT) 150 that extends to the second semiconductor crystal wafer 200 from the first semiconductor crystal wafer 100.DIT150 is formed as having respectively top 156,158 and bottom 256,258.Through DIT opening 145, the top (156 and 158) of DIT150 forms by etching dielectric block 135 and an IMD layer 104, and the bottom of DIT150 (256 and 258) form by etching the one IMD layer 104 and the 2nd IMD layer 204 and the composition surface that is connected two stacking wafers.Conductive component 106,108,206 and 208 is at least partially exposed through in DIT150.
Suitable etch process comprises dry etching, anisotropic wet etch or any other suitable etching.In the present embodiment, applied the selective etch technique with sufficient etching selectivity with respect to conductive component 106,108.Therefore,, for the etch process of IMD layer 104 and 204, conductive component 106 and 108 can play hard mask layer (a kind of " built-in " hard mask).In one embodiment, can adopt selective etch technique with fast-etching IMD layer 104 and 204, the only fraction of etching conductive component 106 and 108 of while.The expose portion (for example, conductive component 106 and 108) of hard mask layer is partly etched away, thereby forms the groove such as groove 157 and groove 159.The degree of depth of groove 157 and groove 159 can need to change according to different application & designs.
With reference to Fig. 2 and Fig. 7, method 300 proceeds to step 312, and in DIT150, filled conductive material is to form dark interconnection connector (DIP) 160.DIP160 comprises high conductivity and low resistive metal, metal element, transition metal etc.For example, DIP160 comprises copper, copper alloy (for example, copper magnesium alloy (CuMn), albronze (CuAl) or cupro silicon (CuSi)), but, also alternately use other material (as, tungsten, aluminium).DIP160 can for example, form by any suitable method known in the art (, PVD, sputter CVD, plating etc.).In one embodiment, DIP160 is further blocked layer and surrounds prevent diffusion and/or provide material bonding.Barrier layer can comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) or tantalum nitride silicon (TaSiN).DIP160 is formed as having the first width w
1top and there is the second width w
2bottom.In the present embodiment, the first width w
1substantially be greater than the second width w
2.The top of dielectric block 135 and 104 couples of DIP160 of an IMD layer provides electricity isolation, and the bottom of an IMD layer 104 and 204 couples of DIP160 of the 2nd IMD layer provides electricity isolation.In addition, if need expect pattern, can apply chemico-mechanical polishing (CMP) thus obtain smooth effect to remove electric conducting material.
Although it should be noted that Fig. 7 shows two semiconductor crystal wafers that are stacked, those of ordinary skill in the art should be understood that the stacked semiconductor device shown in Fig. 7 is only example.Can there is plurality of optional mode, distortion and amendment.For example, this stacked semiconductor device can hold more than two wafers.
Based on more than, the invention provides stacked IC device, it has adopted structure and the formation of dielectric block and dark interconnection channel.Dielectric block has shown process window improvement for the photoetching process of dark interconnection channel provides the surface of substantially flat and it.Dark interconnection channel forms to use " built-in " hard mask to obtain technological flexibility and control by having the selective etch technique of abundant etching selectivity.
The invention provides the multiple different embodiment of stacked integrated circuit (IC) device.Stacked IC device comprises the first semiconductor element.The first semiconductor element comprises the dielectric block in the first substrate, the first substrate and is formed on multiple the first conductive components in first substrate top the first metal intermetallic dielectric layer.Stacked IC device also comprises the second semiconductor element being bonded on the first semiconductor element.The second semiconductor element comprises the second substrate and is formed on multiple the second conductive components in second substrate top the second metal intermetallic dielectric layer.Stacked IC device also comprises the dark interconnection connector being connected between the first conductive component and the second conductive component.The dark interconnection of conduction connector is by dielectric block, the first metal intermetallic dielectric layer and the isolation of the second metal intermetallic dielectric layer.The dark interconnection of conduction connector comprises the top of the first side top that is formed on hard mask layer.Top has the first width.The dark interconnection of conduction connector also has the bottom of the second side top that is formed on hard mask layer.Bottom has the second width that is substantially less than the first width.
In another embodiment, stacked integrated circuit (IC) device comprises the first semiconductor element, and it has the first substrate, is arranged on dielectric block and the first conductive component in the first substrate.Stacked IC device also has the second semiconductor element being bonded on the first semiconductor element.The second semiconductor element comprises the second conductive component of the second substrate and the second substrate top.Stacked integrated circuit (IC) device also comprises the conduction being connected between the first conductive component and the second conductive component connector that deeply interconnects.The dark interconnection of conduction connector comprises the top that isolated by dielectric block and the width bottom much smaller than upper width.
In another embodiment, one comprises for the manufacture of the method for stacked integrated circuit (IC) device: the first semiconductor element is provided.The first semiconductor element comprises the conductive component in the first intermetallic dielectric (IMD) layer and an IMD layer of the first substrate, the first substrate top.The method also comprises the first semiconductor element is engaged on the second semiconductor element.The second semiconductor element comprises the second conductive component in the second intermetallic dielectric (IMD) layer and the 2nd IMD layer of the second substrate, the second substrate top.The method is also included in the first substrate and forms substrate trenches, there is the dielectric block on the substantially flat surface concordant with the first substrate with formation with dielectric material filling substrate trenches, above the first smooth substrate and dielectric block, form pattern mask, be connected first and second conductive components to form dark interconnection channel and to fill dark interconnection channel with electric conducting material to form dark interconnection connector with part the 2nd IMD layer through pattern mask etching dielectric block, an IMD layer.
Summarize the feature of some embodiment above, made those of ordinary skill in the art's each side that the present invention may be better understood.It will be understood by those skilled in the art that they can be easily by the present invention as basis design or change other for reach with here the identical object of the embodiment that introduces and/or realize technique and the structure of same advantage.Those of ordinary skill in the art should also be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and in the situation that not deviating from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.
Claims (10)
1. a device, comprising:
The first semiconductor element, comprising:
The first substrate;
Dielectric block in described the first substrate; With
Multiple the first conductive components, are formed in the first metal intermetallic dielectric layer of described the first substrate top;
The second semiconductor element, is engaged to described the first semiconductor element, and wherein, described the second semiconductor element comprises:
The second substrate; With
Multiple the second conductive components, are formed in the second metal intermetallic dielectric layer of described the second substrate top; And
The dark interconnection of conduction connector, is connected between described the first conductive component and described the second conductive component and by described dielectric block, described the first metal intermetallic dielectric layer and described the second metal intermetallic dielectric layer and isolates, and the described conduction connector that deeply interconnects comprises:
Be formed on the top in described dielectric block and described the first metal intermetallic dielectric layer, described top has the first width; With
Be formed on the bottom in described the first metal intermetallic dielectric layer and described the second metal intermetallic dielectric layer, described bottom has the second width that is less than described the first width.
2. device according to claim 1, wherein, described the first conductive component interconnects during the bottom of connector as etch hard mask deeply forming described conduction.
3. device according to claim 1, wherein, described conduction interconnects the top of connector deeply by described dielectric block and described the first metal intermetallic dielectric layer isolation.
4. device according to claim 1, wherein, described conduction interconnects the bottom of connector deeply by described the second metal intermetallic dielectric layer isolation.
5. a stacked integrated circuit device, comprising:
The first semiconductor element, has the first substrate, is arranged on the first conductive component of dielectric block in described the first substrate and described the first substrate top;
The second semiconductor element, is engaged to described the first semiconductor element, and described the second semiconductor element comprises the second substrate and is positioned at the second conductive component of described the second substrate top; And
Be connected to conduction between described the first conductive component and described the second conductive component connector that deeply interconnects, wherein, the described conduction connector that deeply interconnects comprises:
Have the top of the first width, the described top of part isolates by described dielectric block; With
There is the bottom of the second width.
6. device according to claim 5, wherein, deeply interconnect first width on top of connector of described conduction is greater than the second width of described bottom substantially.
7. a method, comprising:
The first semiconductor element is provided, and described the first semiconductor element comprises:
The first substrate;
The first intermetallic dielectric (IMD) layer of described the first substrate top; With
The first conductive component in a described IMD layer;
Described the first semiconductor element is engaged to the second semiconductor element, and wherein, described the second semiconductor element comprises:
The second substrate;
The second intermetallic dielectric (IMD) layer of described the second substrate top; And
The second conductive component in described the 2nd IMD layer;
In described the first substrate, form substrate trenches;
Fill described substrate trenches with dielectric material and there is the dielectric block on the substantially flat surface concordant with described the first substrate to form;
Above smooth described the first substrate and described dielectric block, form pattern mask;
Through dielectric block, a described IMD layer and described the 2nd IMD layer of part described in described pattern mask etching to form dark interconnection channel; And
Fill described dark interconnection channel with electric conducting material and connect described the first conductive component and described the second conductive component to form dark interconnection connector.
8. method according to claim 7, the substantially flat surface of described dielectric block and described the first substrate forms by chemico-mechanical polishing (CMP).
9. method according to claim 7, wherein, described dark interconnection channel by photoetching and with respect to described the first conductive component have sufficient etching selectivity selective etch technique form.
10. method according to claim 9, wherein, described the first conductive component is as etch hard mask.
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| US201361798459P | 2013-03-15 | 2013-03-15 | |
| US61/798,459 | 2013-03-15 | ||
| US13/937,055 US10096515B2 (en) | 2013-03-15 | 2013-07-08 | Interconnect structure for stacked device |
| US13/937,055 | 2013-07-08 |
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| CN104051419A true CN104051419A (en) | 2014-09-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111490004A (en) * | 2019-01-28 | 2020-08-04 | 中芯长电半导体（江阴）有限公司 | Method for preparing rewiring layer and semiconductor structure |
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| US20120256311A1 (en) * | 2011-04-11 | 2012-10-11 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
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| CN111490004A (en) * | 2019-01-28 | 2020-08-04 | 中芯长电半导体（江阴）有限公司 | Method for preparing rewiring layer and semiconductor structure |
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