US20160240486A1 - Chip package structure having a shielded molding compound - Google Patents

Chip package structure having a shielded molding compound Download PDF

Info

Publication number
US20160240486A1
US20160240486A1 US14/623,517 US201514623517A US2016240486A1 US 20160240486 A1 US20160240486 A1 US 20160240486A1 US 201514623517 A US201514623517 A US 201514623517A US 2016240486 A1 US2016240486 A1 US 2016240486A1
Authority
US
United States
Prior art keywords
carrier substrate
layer
chip
circuit layer
shielding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/623,517
Other versions
US9412703B1 (en
Inventor
Chien-Wen Huang
Ming-Hung Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to US14/623,517 priority Critical patent/US9412703B1/en
Assigned to POWERTECH TECHNOLOGY INC. reassignment POWERTECH TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, MING-HUNG, HUANG, CHIEN-WEN
Application granted granted Critical
Publication of US9412703B1 publication Critical patent/US9412703B1/en
Publication of US20160240486A1 publication Critical patent/US20160240486A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a chip package structure.
  • Electromagnetic interference is a disturbance caused by an electromagnetic field which impedes the proper performance of an electronic device. Since EMI can arise from a number of sources, EMI is present in all areas of electronics. Hence, for the electronic devices, it is important to have efficient EMI protection to reduce the level of EMI to an acceptable level and to ensure the normal operation.
  • the embodiments of the present invention are directed to chip package structures with effective EMI shielding.
  • the present invention provides a chip package structure including a main substrate, a carrier substrate disposed over the main substrate, at least a chip disposed on and electrically connected to the carrier substrate, a molding compound, a shielding layer disposed directly on the molding compound and a plurality of first connection structures and a plurality of second connection structures located between the main substrate and the carrier substrate.
  • the main substrate has a first circuit layer including a plurality of pads
  • the carrier substrate has a second circuit layer including a plurality of contacts.
  • the molding compound disposed over the carrier substrate at least encapsulates the chip and a portion of the carrier substrate.
  • the shielding layer conformally covers a top surface and sidewalls of the molding compound and covers an upper sidewall portion of the carrier substrate.
  • the at least one chip and the carrier substrate are electrically connected to the main substrate through the plurality of first metal connection structures.
  • the shielding layer is electrically connected to the carrier substrate through the plurality of second connection structures.
  • the second circuit layer of the carrier substrate functions as a ground layer and the shielding layer is electrically connected to the ground layer through the plurality of second connection structures and is grounded.
  • the first circuit layer of the main substrate functions as a ground layer and the shielding layer is electrically connected to the ground layer through the plurality of second connection structures and is grounded.
  • a material of the shielding layer comprises aluminum, copper, chromium, gold, silver, nickel, a solder material, or the combinations thereof.
  • the chip is a power chip or a radio-frequency chip.
  • a material of the molding compound includes an epoxy resin.
  • a material of the plurality of the second connection structures includes a eutectic Sn—Pb alloy or a tin/silver/copper alloy (SAC alloy) or a lead-free solder material.
  • the shielding layer fully covering the molding compound and a portion of the carrier substrate of the chip package provide effective EMI shield of the chip package. Also, because of the full coverage of the shielding layer, the moisture barrier and the reliability of the package can be improved.
  • FIG. 1 is a schematic cross-sectional view showing a chip package before assembly according to one preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing the chip package according to one preferred embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view showing a chip package before assembly according to another preferred embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing the chip package according to another preferred embodiment of the present invention.
  • the manufacturing methods as described in the present invention can be used for fabricating various package structures and are suitable for fabricating packages of surface mounted devices packages or packages of multiple chip or electronic devices.
  • FIG. 1 is a schematic cross-sectional view showing a chip package before assembly according to one preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing the chip package after assembly according to one preferred embodiment of the present invention.
  • a carrier substrate 100 having a dielectric layer 101 , an upper circuit layer 102 including a plurality of bonding pads 103 thereon and a lower circuit layer 104 including a plurality of contacts 105 is provided.
  • the carrier substrate 100 also includes an upper insulating layer 106 disposed on and partially covering the upper circuit layer 102 and a lower insulating layer 108 disposed on and partially covering the lower circuit layer 104 .
  • the lower circuit layer 104 may function as a ground layer.
  • the contacts 105 may function as bump pads for flip chip connecting technology.
  • the carrier substrate 100 can be a laminate substrate, for example, a printed circuit board (PCB) or a flexible printed circuit board (FPCB).
  • a chip 200 is disposed on the top surface 100 a of the carrier substrate 100 .
  • a chip is provided herein, other surface mount devices (SMD) or surface mount components may be installed and are encompassed within the scope of this invention.
  • the contacts 202 of the chip 200 is electrically connected to the bonding pads 103 on the upper circuit layer 102 of the carrier substrate 100 through a plurality of wires 204 .
  • wire bonding technology is described herein, it is well encompassed within the scope of this invention to employ flip chip connecting technology for connecting the chip and the carrier substrate.
  • the chip 200 preferably is disposed within a central portion of the carrier substrate 100 .
  • a molding compound 206 is disposed on the carrier substrate 100 and encapsulates the chip 200 , the contacts 202 and the wires 204 .
  • the molding compound 206 may be formed by an over-molding process, for example.
  • the material of the molding compound 206 may be epoxy resins, for example.
  • a shielding layer 208 is conformally formed over the molding compound 206 and conformally covers the top surface 206 a and the sidewalls 206 b of the molding compound 206 and the upper sidewalls (the upper sidewall portion) 100 b of the carrier substrate 100 . That is, although the shielding layer 208 is connected with the upper circuit layer 102 , the shielding layer 208 is not in physical contact with the lower circuit layer 104 .
  • the shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded.
  • the shielding layer 208 can be formed by spray coating, plating a sputtering, for example.
  • the material of the shielding layer 208 may be, for example, aluminum, copper, chromium, gold, silver, nickel, solder materials, or the combinations thereof.
  • the integrated structure of the carrier substrate 100 , the chip 200 , the molding compound 206 and the shielding layer 208 may be considered as a land grid array type package portion.
  • a main substrate 300 having a core dielectric layer 301 , an upper circuit layer 302 including a plurality of pads 303 and a lower circuit layer 304 is provided.
  • the main substrate 300 also includes an upper insulating layer 306 disposed on and partially covering the upper circuit layer 302 and a lower insulating layer 308 covering the lower circuit layer 304 .
  • the upper circuit layer 302 may function as a ground layer.
  • the pads 303 may function as bump pads or ball pads, for example.
  • the main substrate 300 can be a multi-layered substrate, for example, a printed circuit board (PCB).
  • a plurality of bumps 400 and a plurality of solder balls 500 are disposed on the pads 303 of the main substrate 300 .
  • the carrier substrate 100 is assembled to the main substrate 300 by placing the carrier substrate 100 on the main substrate 300 , and the position of the carrier substrate 100 is adjusted so that the contacts 105 (bumps pads) are aligned with bumps 400 respectively and the shielding layer 208 located on the upper sidewalls 100 b aligned with the solder balls 500 .
  • the shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded.
  • a chip package structure 20 is obtained.
  • the same reference numbers will be used and no further details will be discussed herein again.
  • the bumps 400 melt and become connection structures 402 attached to the contacts 105
  • the solder balls 500 melt and becomes connection structures 502 for connecting the shielding layer 208 , the ground layer 104 and the pads 303 . That is, the assembled chip package structure 20 includes the carrier substrate 100 laminated and bonded to the main substrate 300 through the connection structures 402 and 502 .
  • the shielding layer 208 is connected to the ground layer 104 of the carrier substrate 100 through the connection structures 502 , the shielding layer 208 is grounded. It is understood that the shielding layer 208 may be further connected to the ground layer of the main substrate 300 .
  • the chip package 20 of the present embodiment includes a carrier substrate 100 having at least a circuit layer 104 including a plurality of contacts 105 , at least a chip 200 , a molding compound 206 , a shielding layer 208 , a main substrate 300 having at least a circuit layer 302 including a plurality of pads 303 and a plurality of connection structures 402 and 502 between the contacts 105 of the circuit layer 104 and the pads 303 of the circuit layer 302 .
  • the carrier substrate 100 may be a laminated substrate, for example, a FPCB, while the main substrate 300 may be a multi-layered substrate, such as two-layered or a four-layered laminated PCB.
  • the chip 200 can be a semiconductor chip, for example, a power chip or a radio-frequency chip.
  • the material of the shielding layer 208 may be copper, chromium, gold, silver, nickel, aluminum or alloys thereof, for example.
  • the molding compound 206 encapsulates a portions of the carrier substrates 100 , the wires 204 , and the chip 200 .
  • the shielding layer 208 is disposed over the molding compound 206 , covering the top surface 206 a , the sidewalls 206 b of the molding compound 130 .
  • the chip 200 and the carrier substrate 100 are electrically connected to the main substrate 300 through the metal connection structures 402 .
  • the shielding layer 208 is electrically connected to at least the circuit layer 104 of the carrier substrates 100 through the connection structures 502 , so that the shielding layer 208 is electrically grounded.
  • the connection structures 402 , 502 are reflowed bumps or reflowed solder balls
  • the material of the connection structures 402 , 502 may include eutectic tin-lead (Sn—Pb) alloys, tin/silver/copper alloys (SAC alloys) or lead-free solder materials.
  • the shielding layer of the present invention can be grounded within the package structure using the ground plane of the carrier substrate and/or the main substrate.
  • the shielding layer can establish an electrical ground path within the package structure, devoid of using an extra ground plane.
  • the shielding layer 208 covers up the upper sidewalls 100 b of the carrier substrate 100 , the moisture barrier of the package structure is further improved.
  • the material or the thickness of the shielding layer 208 may be altered depending on the shielding requisites or other electrical properties of the package structure or even varied in accordance with the processing parameters.
  • the material selection and the size of the metal connection structures 502 may be modified according to the size of the chip, the layout and the arrangement of the shielding layer. As long as the shielding layer 208 is electrically connected to the ground layer 104 through the metal connection structures 502 (i.e. reflowed solder balls), proper EMI shielding can be achieved.
  • FIG. 3 is a schematic cross-sectional view showing a chip package before assembly according to another preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing the chip package after assembly according to another preferred embodiment of the present invention.
  • the structural details and the materials of the carrier substrate 100 and the main substrate 300 are substantially the same as described in the previous paragraphs for describing FIG. 1 , the same reference numbers will be used and no further details will be discussed herein again.
  • FIG. 3 is a schematic cross-sectional view showing a chip package before assembly according to another preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing the chip package after assembly according to another preferred embodiment of the present invention.
  • a plurality of bumps 400 is disposed on the contacts 105 of the lower circuit layer 104 of the carrier substrate 100 before assembly, while a plurality of solder balls 500 is disposed on the pads 303 of the upper circuit layer 302 of the main substrate 300 .
  • the integrated structure of the carrier substrate 100 , the chip 200 , the molding compound 206 , the shielding layer 208 and the bumps 400 may be considered as a ball grid array type package portion.
  • the carrier substrate 100 is assembled to the main substrate 300 by placing the carrier substrate 100 on the main substrate 300 , and the position of the carrier substrate 100 is adjusted so that the bumps 400 are aligned with the pads 303 respectively and the shielding layer 208 located on the upper sidewalls 100 b aligned with the solder balls 500 .
  • the shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded.
  • a chip package structure 40 is obtained.
  • the bumps 400 melt and become connection structures 402 attached to the contacts 105
  • the solder balls 500 melt and becomes connection structures 502 for connecting the shielding layer 208 , the ground layer 104 and the pads 303 .
  • the assembled chip package structure 40 includes the carrier substrate 100 laminated and bonded to the main substrate 300 through the connection structures 402 and 502 .
  • the shielding layer 208 is connected to the ground layer 104 of the carrier substrate 100 and the ground layer 302 of the main substrate 300 through the connection structures 502 , the shielding layer 208 is grounded.
  • the chip package 40 of the present embodiment includes a carrier substrate 100 having at least a circuit layer 104 including a plurality of contacts 105 , at least a chip 200 , a molding compound 206 , a shielding layer 208 , a main substrate 300 having at least a circuit layer 302 including a plurality of pads 303 and a plurality of connection structures 402 and 502 between the contacts 105 of the circuit layer 104 and the pads 303 of the circuit layer 302 .
  • the shielding layer 208 is disposed over the molding compound 206 , covering the top surface 206 a , the sidewalls 206 b of the molding compound 130 .
  • the chip 200 and the carrier substrate 100 are electrically connected to the main substrate 300 through the metal connection structures 402 .
  • the shielding layer 208 is electrically connected to the circuit layer 104 of the carrier substrates 100 as well as the circuit layer 302 of the main substrate 300 through the connection structures 502 , so that the shielding layer 208 is electrically grounded.
  • the shielding layer disposed over the molding compound and a portion of the carrier substrate function as an EMI shield, so as to protect the chip from the EMI radiation of the surrounding radiation sources and enhance the EMI shielding efficacy of the package.
  • the full coverage of the shielding layer over the molding compound and a portion of the carrier substrate also improves the moisture barrier of the package and the reliability of the package.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection structures between the main substrate and the carrier substrate. The shielding layer covers the top surface and the sidewalls of the molding compound and a portion of the carrier substrate. The shielding layer is electrically grounded through the connection structures.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device, and more particularly to a chip package structure.
  • 2. Description of Related Art
  • Electromagnetic interference (EMI) is a disturbance caused by an electromagnetic field which impedes the proper performance of an electronic device. Since EMI can arise from a number of sources, EMI is present in all areas of electronics. Hence, for the electronic devices, it is important to have efficient EMI protection to reduce the level of EMI to an acceptable level and to ensure the normal operation.
    • SUMMARY OF THE INVENTION
  • The embodiments of the present invention are directed to chip package structures with effective EMI shielding.
  • The present invention provides a chip package structure including a main substrate, a carrier substrate disposed over the main substrate, at least a chip disposed on and electrically connected to the carrier substrate, a molding compound, a shielding layer disposed directly on the molding compound and a plurality of first connection structures and a plurality of second connection structures located between the main substrate and the carrier substrate. The main substrate has a first circuit layer including a plurality of pads, and the carrier substrate has a second circuit layer including a plurality of contacts. The molding compound disposed over the carrier substrate at least encapsulates the chip and a portion of the carrier substrate. The shielding layer conformally covers a top surface and sidewalls of the molding compound and covers an upper sidewall portion of the carrier substrate. The at least one chip and the carrier substrate are electrically connected to the main substrate through the plurality of first metal connection structures. The shielding layer is electrically connected to the carrier substrate through the plurality of second connection structures.
  • According to one embodiment of the present invention, the second circuit layer of the carrier substrate functions as a ground layer and the shielding layer is electrically connected to the ground layer through the plurality of second connection structures and is grounded.
  • According to one embodiment of the present invention, the first circuit layer of the main substrate functions as a ground layer and the shielding layer is electrically connected to the ground layer through the plurality of second connection structures and is grounded.
  • According to one embodiment of the present invention, a material of the shielding layer comprises aluminum, copper, chromium, gold, silver, nickel, a solder material, or the combinations thereof.
  • According to one embodiment of the present invention, the chip is a power chip or a radio-frequency chip.
  • According to one embodiment of the present invention, a material of the molding compound includes an epoxy resin.
  • According to one embodiment of the present invention, a material of the plurality of the second connection structures includes a eutectic Sn—Pb alloy or a tin/silver/copper alloy (SAC alloy) or a lead-free solder material.
  • Based on the above, the shielding layer fully covering the molding compound and a portion of the carrier substrate of the chip package provide effective EMI shield of the chip package. Also, because of the full coverage of the shielding layer, the moisture barrier and the reliability of the package can be improved.
  • In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a schematic cross-sectional view showing a chip package before assembly according to one preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing the chip package according to one preferred embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view showing a chip package before assembly according to another preferred embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing the chip package according to another preferred embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • The manufacturing methods as described in the present invention can be used for fabricating various package structures and are suitable for fabricating packages of surface mounted devices packages or packages of multiple chip or electronic devices.
  • FIG. 1 is a schematic cross-sectional view showing a chip package before assembly according to one preferred embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing the chip package after assembly according to one preferred embodiment of the present invention.
  • Referring to FIG. 1, a carrier substrate 100 having a dielectric layer 101, an upper circuit layer 102 including a plurality of bonding pads 103 thereon and a lower circuit layer 104 including a plurality of contacts 105 is provided. The carrier substrate 100 also includes an upper insulating layer 106 disposed on and partially covering the upper circuit layer 102 and a lower insulating layer 108 disposed on and partially covering the lower circuit layer 104. The lower circuit layer 104 may function as a ground layer. The contacts 105 may function as bump pads for flip chip connecting technology. The carrier substrate 100 can be a laminate substrate, for example, a printed circuit board (PCB) or a flexible printed circuit board (FPCB).
  • Referring to FIG. 1, at least a chip 200 is disposed on the top surface 100 a of the carrier substrate 100. Although a chip is provided herein, other surface mount devices (SMD) or surface mount components may be installed and are encompassed within the scope of this invention. The contacts 202 of the chip 200 is electrically connected to the bonding pads 103 on the upper circuit layer 102 of the carrier substrate 100 through a plurality of wires 204. Although wire bonding technology is described herein, it is well encompassed within the scope of this invention to employ flip chip connecting technology for connecting the chip and the carrier substrate. The chip 200 preferably is disposed within a central portion of the carrier substrate 100. Also, a molding compound 206 is disposed on the carrier substrate 100 and encapsulates the chip 200, the contacts 202 and the wires 204. The molding compound 206 may be formed by an over-molding process, for example. The material of the molding compound 206 may be epoxy resins, for example. A shielding layer 208 is conformally formed over the molding compound 206 and conformally covers the top surface 206 a and the sidewalls 206 b of the molding compound 206 and the upper sidewalls (the upper sidewall portion) 100 b of the carrier substrate 100. That is, although the shielding layer 208 is connected with the upper circuit layer 102, the shielding layer 208 is not in physical contact with the lower circuit layer 104. The shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded. The shielding layer 208 can be formed by spray coating, plating a sputtering, for example. The material of the shielding layer 208 may be, for example, aluminum, copper, chromium, gold, silver, nickel, solder materials, or the combinations thereof. Considering the contacts 105 arranged in arrays, the integrated structure of the carrier substrate 100, the chip 200, the molding compound 206 and the shielding layer 208 may be considered as a land grid array type package portion.
  • Referring to FIG. 1, a main substrate 300 having a core dielectric layer 301, an upper circuit layer 302 including a plurality of pads 303 and a lower circuit layer 304 is provided. The main substrate 300 also includes an upper insulating layer 306 disposed on and partially covering the upper circuit layer 302 and a lower insulating layer 308 covering the lower circuit layer 304. The upper circuit layer 302 may function as a ground layer. The pads 303 may function as bump pads or ball pads, for example. The main substrate 300 can be a multi-layered substrate, for example, a printed circuit board (PCB). A plurality of bumps 400 and a plurality of solder balls 500 are disposed on the pads 303 of the main substrate 300.
  • As shown in FIG. 1, the carrier substrate 100 is assembled to the main substrate 300 by placing the carrier substrate 100 on the main substrate 300, and the position of the carrier substrate 100 is adjusted so that the contacts 105 (bumps pads) are aligned with bumps 400 respectively and the shielding layer 208 located on the upper sidewalls 100 b aligned with the solder balls 500. The shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded.
  • In FIG. 2, after the assembly and reflowing, a chip package structure 20 is obtained. As the structural details and the materials of the carrier substrate 100 and the main substrate 300 are substantially the same as described in the previous paragraphs for describing FIG. 1, the same reference numbers will be used and no further details will be discussed herein again. During the reflowing process, the bumps 400 melt and become connection structures 402 attached to the contacts 105, while the solder balls 500 melt and becomes connection structures 502 for connecting the shielding layer 208, the ground layer 104 and the pads 303. That is, the assembled chip package structure 20 includes the carrier substrate 100 laminated and bonded to the main substrate 300 through the connection structures 402 and 502. In this case, as the shielding layer 208 is connected to the ground layer 104 of the carrier substrate 100 through the connection structures 502, the shielding layer 208 is grounded. It is understood that the shielding layer 208 may be further connected to the ground layer of the main substrate 300.
  • Referring to FIG. 2, the chip package 20 of the present embodiment includes a carrier substrate 100 having at least a circuit layer 104 including a plurality of contacts 105, at least a chip 200, a molding compound 206, a shielding layer 208, a main substrate 300 having at least a circuit layer 302 including a plurality of pads 303 and a plurality of connection structures 402 and 502 between the contacts 105 of the circuit layer 104 and the pads 303 of the circuit layer 302. The carrier substrate 100 may be a laminated substrate, for example, a FPCB, while the main substrate 300 may be a multi-layered substrate, such as two-layered or a four-layered laminated PCB. The chip 200 can be a semiconductor chip, for example, a power chip or a radio-frequency chip. The material of the shielding layer 208 may be copper, chromium, gold, silver, nickel, aluminum or alloys thereof, for example. The molding compound 206 encapsulates a portions of the carrier substrates 100, the wires 204, and the chip 200. The shielding layer 208 is disposed over the molding compound 206, covering the top surface 206 a, the sidewalls 206 b of the molding compound 130. The chip 200 and the carrier substrate 100 are electrically connected to the main substrate 300 through the metal connection structures 402. The shielding layer 208 is electrically connected to at least the circuit layer 104 of the carrier substrates 100 through the connection structures 502, so that the shielding layer 208 is electrically grounded. As the connection structures 402, 502 are reflowed bumps or reflowed solder balls, the material of the connection structures 402, 502 may include eutectic tin-lead (Sn—Pb) alloys, tin/silver/copper alloys (SAC alloys) or lead-free solder materials. Taking advantage of the metal connection structures 502, the shielding layer of the present invention can be grounded within the package structure using the ground plane of the carrier substrate and/or the main substrate. The shielding layer can establish an electrical ground path within the package structure, devoid of using an extra ground plane.
  • In addition, as the shielding layer 208 covers up the upper sidewalls 100 b of the carrier substrate 100, the moisture barrier of the package structure is further improved.
  • In general, the material or the thickness of the shielding layer 208 may be altered depending on the shielding requisites or other electrical properties of the package structure or even varied in accordance with the processing parameters. The material selection and the size of the metal connection structures 502 may be modified according to the size of the chip, the layout and the arrangement of the shielding layer. As long as the shielding layer 208 is electrically connected to the ground layer 104 through the metal connection structures 502 (i.e. reflowed solder balls), proper EMI shielding can be achieved.
  • In accordance with the present invention, the chip package structure may be assembled differently as described in the following embodiment. FIG. 3 is a schematic cross-sectional view showing a chip package before assembly according to another preferred embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing the chip package after assembly according to another preferred embodiment of the present invention. As the structural details and the materials of the carrier substrate 100 and the main substrate 300 are substantially the same as described in the previous paragraphs for describing FIG. 1, the same reference numbers will be used and no further details will be discussed herein again. In FIG. 3, a plurality of bumps 400 is disposed on the contacts 105 of the lower circuit layer 104 of the carrier substrate 100 before assembly, while a plurality of solder balls 500 is disposed on the pads 303 of the upper circuit layer 302 of the main substrate 300. Herein, considering the bumps 400 on the contacts 105 arranged in arrays, the integrated structure of the carrier substrate 100, the chip 200, the molding compound 206, the shielding layer 208 and the bumps 400 may be considered as a ball grid array type package portion.
  • As shown in FIG. 3, the carrier substrate 100 is assembled to the main substrate 300 by placing the carrier substrate 100 on the main substrate 300, and the position of the carrier substrate 100 is adjusted so that the bumps 400 are aligned with the pads 303 respectively and the shielding layer 208 located on the upper sidewalls 100 b aligned with the solder balls 500. Before assembly, the shielding layer 208 is not connected to the ground layer 104 of the carrier substrate 100 and therefore is not yet grounded.
  • In FIG. 4, after the assembly and reflowing, a chip package structure 40 is obtained. As the structural details and the materials of the carrier substrate 100 and the main substrate 300 are substantially the same as described in the previous paragraphs for describing FIGS. 1 and 3, the same reference numbers will be used and no further details will be discussed herein again. During the reflowing process, the bumps 400 melt and become connection structures 402 attached to the contacts 105, while the solder balls 500 melt and becomes connection structures 502 for connecting the shielding layer 208, the ground layer 104 and the pads 303. That is, the assembled chip package structure 40 includes the carrier substrate 100 laminated and bonded to the main substrate 300 through the connection structures 402 and 502. In this case, as the shielding layer 208 is connected to the ground layer 104 of the carrier substrate 100 and the ground layer 302 of the main substrate 300 through the connection structures 502, the shielding layer 208 is grounded.
  • Referring to FIG. 4, the chip package 40 of the present embodiment includes a carrier substrate 100 having at least a circuit layer 104 including a plurality of contacts 105, at least a chip 200, a molding compound 206, a shielding layer 208, a main substrate 300 having at least a circuit layer 302 including a plurality of pads 303 and a plurality of connection structures 402 and 502 between the contacts 105 of the circuit layer 104 and the pads 303 of the circuit layer 302. The shielding layer 208 is disposed over the molding compound 206, covering the top surface 206 a, the sidewalls 206 b of the molding compound 130. The chip 200 and the carrier substrate 100 are electrically connected to the main substrate 300 through the metal connection structures 402. The shielding layer 208 is electrically connected to the circuit layer 104 of the carrier substrates 100 as well as the circuit layer 302 of the main substrate 300 through the connection structures 502, so that the shielding layer 208 is electrically grounded.
  • In the chip package structures of the present embodiment, the shielding layer disposed over the molding compound and a portion of the carrier substrate function as an EMI shield, so as to protect the chip from the EMI radiation of the surrounding radiation sources and enhance the EMI shielding efficacy of the package. In this case, the full coverage of the shielding layer over the molding compound and a portion of the carrier substrate also improves the moisture barrier of the package and the reliability of the package.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (7)

1. A chip package structure, comprising:
a main substrate having a first circuit layer including a plurality of pads;
a carrier substrate having a second circuit layer and a third circuit layer, wherein the second circuit layer and third circuit layer are respectively located on two opposite surfaces of the carrier substrate, the second circuit layer has a plurality of contacts and a ground layer, and the carrier substrate is disposed over the main substrate;
at least one chip disposed on the carrier substrate and electrically connected to the carrier substrate;
a molding compound disposed over the carrier substrate, at least encapsulating the chip and a portion of the carrier substrate;
a shielding layer disposed directly on the molding compound, wherein the shielding layer conformally covers a top surface and sidewalls of the molding compound and covers an upper sidewall portion of the carrier substrate, wherein the shielding layer is directly coupled with the third circuit layer through physical contact; and
a plurality of first connection structures and a plurality of second connection structures located between the plurality of pads of the first circuit layer and the plurality of contacts of the second circuit layer, wherein the at least one chip and the carrier substrate are electrically connected to the main substrate through the plurality of first connection structures, and the shielding layer is electrically connected to and indirectly coupled with the second circuit layer of the carrier substrate through the plurality of second connection structures.
2. (canceled)
3. The package structure as claimed in claim 1, wherein the first circuit layer of the main substrate includes a ground layer and the shielding layer is electrically connected to the ground layer of the first circuit layer through the plurality of second connection structures and is grounded.
4. The package structure as claimed in claim 1, wherein a material of the shielding layer comprises aluminum, copper, chromium, gold, silver, nickel, a solder material, or the combinations thereof.
5. The package structure as claimed in claim 1, wherein the chip is a power chip or a radio-frequency chip.
6. The package structure as claimed in claim 1, wherein a material of the molding compound includes an epoxy resin.
7. The package structure as claimed in claim 1, wherein a material of the plurality of the second connection structures includes an eutectic Sn—Pb alloy or a tin/silver/copper alloy (SAC alloy) or a lead-free solder material.
US14/623,517 2015-02-17 2015-02-17 Chip package structure having a shielded molding compound Active US9412703B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/623,517 US9412703B1 (en) 2015-02-17 2015-02-17 Chip package structure having a shielded molding compound

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/623,517 US9412703B1 (en) 2015-02-17 2015-02-17 Chip package structure having a shielded molding compound

Publications (2)

Publication Number Publication Date
US9412703B1 US9412703B1 (en) 2016-08-09
US20160240486A1 true US20160240486A1 (en) 2016-08-18

Family

ID=56556017

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/623,517 Active US9412703B1 (en) 2015-02-17 2015-02-17 Chip package structure having a shielded molding compound

Country Status (1)

Country Link
US (1) US9412703B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108976451A (en) * 2017-06-01 2018-12-11 苏州国动环保节能科技有限公司 A kind of coating application method for eliminating the electromagnetic radiation generated when electric appliance use

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI615925B (en) * 2013-03-04 2018-02-21 盧森堡商經度半導體責任有限公司 Semiconductor device
US9907169B1 (en) * 2016-08-30 2018-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Printed circuit board (PCB) and PCB assembly having an encapsulating mold material on a bottom surface thereof and methods for molding an encapsulating mold material on a bottom surface of a PCB
CN112563249A (en) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 Integrated packaging structure
CN116230694A (en) * 2021-12-06 2023-06-06 华为技术有限公司 Chip system and communication equipment

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650659A (en) * 1995-08-04 1997-07-22 National Semiconductor Corporation Semiconductor component package assembly including an integral RF/EMI shield
US6294731B1 (en) * 1999-03-16 2001-09-25 Performance Interconnect, Inc. Apparatus for multichip packaging
US7187060B2 (en) * 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
DE102005025083B4 (en) * 2005-05-30 2007-05-24 Infineon Technologies Ag Thermoplastic thermoset composite and method for bonding a thermoplastic material to a thermoset material
US7906371B2 (en) * 2008-05-28 2011-03-15 Stats Chippac, Ltd. Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
US8101460B2 (en) * 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US9123663B2 (en) * 2008-06-10 2015-09-01 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer grounded through metal pillars formed in peripheral region of the semiconductor
US8110441B2 (en) * 2008-09-25 2012-02-07 Stats Chippac, Ltd. Method of electrically connecting a shielding layer to ground through a conductive via disposed in peripheral region around semiconductor die
US7799602B2 (en) * 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
KR101715761B1 (en) * 2010-12-31 2017-03-14 삼성전자주식회사 Semiconductor packages and methods for fabricating the same
US8268677B1 (en) * 2011-03-08 2012-09-18 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
KR20120131530A (en) * 2011-05-25 2012-12-05 삼성전자주식회사 Memory device and and fabricating method thereof
KR20130010359A (en) * 2011-07-18 2013-01-28 삼성전자주식회사 Substrate for semiconductor package and semiconductor package comprising thereof
TWI553825B (en) * 2013-01-11 2016-10-11 日月光半導體製造股份有限公司 Stacked package device and manufacation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108976451A (en) * 2017-06-01 2018-12-11 苏州国动环保节能科技有限公司 A kind of coating application method for eliminating the electromagnetic radiation generated when electric appliance use

Also Published As

Publication number Publication date
US9412703B1 (en) 2016-08-09

Similar Documents

Publication Publication Date Title
KR102522322B1 (en) Semiconductor package
KR100714917B1 (en) Chip stack structure interposing shield plate and system in package comprising the same
US6707168B1 (en) Shielded semiconductor package with single-sided substrate and method for making the same
US7906835B2 (en) Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US9362209B1 (en) Shielding technique for semiconductor package including metal lid
US8623753B1 (en) Stackable protruding via package and method
US9412703B1 (en) Chip package structure having a shielded molding compound
TW201630084A (en) Semiconductor package structure and semiconductor process
US11482500B2 (en) Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
KR102451167B1 (en) Semiconductor package
US9780047B1 (en) Semiconductor package
US20230343603A1 (en) Electronic package and method for fabricating the same
US9887163B2 (en) Semiconductor package and method of manufacturing the same
CN108074826A (en) Electronic package and manufacturing method thereof
KR101391089B1 (en) Semiconductor package and methods for fabricating the same
US11581266B2 (en) Semiconductor package
KR20120101965A (en) Semiconductor package and method of manufacturing the same
US20120248585A1 (en) Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same
KR102041666B1 (en) Semi-conductor package and method for manufacturing the same and module of electronic device using the same
KR102380834B1 (en) Printed circuit board, semiconductor package and method of manufacturing the same
KR101394647B1 (en) Semiconductor package and method for fabricating the same
CN108573879B (en) Electronic package
US20140338957A1 (en) Printing circuit board and the application the same of
US20180240738A1 (en) Electronic package and fabrication method thereof
KR101741648B1 (en) Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: POWERTECH TECHNOLOGY INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIEN-WEN;CHANG, MING-HUNG;SIGNING DATES FROM 20150129 TO 20150213;REEL/FRAME:035080/0428

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8