US20160239036A1 - Dual supply - Google Patents

Dual supply Download PDF

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Publication number
US20160239036A1
US20160239036A1 US14/621,261 US201514621261A US2016239036A1 US 20160239036 A1 US20160239036 A1 US 20160239036A1 US 201514621261 A US201514621261 A US 201514621261A US 2016239036 A1 US2016239036 A1 US 2016239036A1
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United States
Prior art keywords
lvr
voltage
ivr
fivr
output
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Abandoned
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US14/621,261
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English (en)
Inventor
Fabrice Paillet
Gerhard Schrom
Anant Deval
Rajan Vijayaraghavan
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Priority to US14/621,261 priority Critical patent/US20160239036A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DEVAL, ANANT, SCHROM, GERHARD, PAILLET, FABRICE, VIJAYARAGHAVAN, RAJAN
Priority to TW105100395A priority patent/TWI590023B/zh
Priority to CN201680007174.8A priority patent/CN107209527A/zh
Priority to KR1020177021021A priority patent/KR102454797B1/ko
Priority to PCT/US2016/013094 priority patent/WO2016130259A1/en
Priority to EP16749561.3A priority patent/EP3257144A4/en
Publication of US20160239036A1 publication Critical patent/US20160239036A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/008—Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H02M2001/0045—

Definitions

  • the present invention relates generally to power supplies and in particular, to power supply solutions for on-chip voltage domains.
  • FIG. 1A is a diagram of a computing device with a processor having multiple parallel LVR/IVR voltage supplied domains in accordance with some embodiments.
  • FIG. 1B is a schematic of an IVR portion from a single voltage domain from the computing device of FIG. 1A in accordance with some embodiments.
  • FIG. 2 is a block diagram of circuitry for a single representative FIVR in accordance with some embodiments.
  • FIG. 3 is a diagram showing a single FIVR/LVR block for supplying power to a voltage domain in accordance with some embodiments.
  • FIG. 4 is a diagram showing a routine 401 for transitioning from the FIVR to the LVR in accordance with some embodiments.
  • FIG. 5 is a diagram showing a routine for transitioning from an LVR to a FIVR for a domain power supply in accordance with some embodiments.
  • the present disclosure provides a power delivery scheme to provide a parallel regulation feature for integrated voltage regulators (IVRs).
  • IVRs integrated voltage regulators
  • this feature may provide seamless transfer of voltage regulation and power delivery from the IVR to an alternate, more efficient, parallel (linear) regulator (LVR) during specific (light) load conditions where overall IVR power efficiency may be low.
  • LVR parallel linear regulator
  • the parallel regulator can be a linear voltage regulator (LVR) or potentially another kind of efficient regulator for the specific operating condition of interest, like a switched capacitor regulator or a smaller switching mode voltage regulator.
  • FIG. 1A is a diagram showing power domains for an exemplary computing device in accordance with some embodiments. It includes a processor 105 that is powered from a power source 101 (PSU or battery) through off-chip regulators 103 .
  • the processor 105 has separate IVR/LVR voltage domains 107 for powering various different loads 109 .
  • the processor 105 could correspond to any suitable processor (e.g., high-end server chip, SoC, etc.). For example, it could be implemented with an Intel® 4th generation CoreTM microprocessor.
  • a first stage VR (from 103 ), which is on a motherboard, converts from the PSU (power supply unit) or battery voltage (e.g., 12V to 20V) to a lower voltage (e.g., 1.8 V for active modes and 1.3 for reduced power modes). These supplies are distributed through input supply rails across the microprocessor die.
  • the IVR/LVR blocks function as a second conversion stage. For example, there could be between 8 and 31 IVR/LVR domains depending on processor configuration.
  • the IVRs are implemented with FIVRs (fully integrated voltage regulators). Each IVR is independently programmable to achieve optimal operation given the requirements of the domain it is powering.
  • the settings may be optimized by a power control unit (PCU), which may specify the input voltage, output voltage, number of operating phases, and a variety of other settings to minimize the total power consumption of the die.
  • PCU power control unit
  • IVR integrated voltage regulator
  • PWM pulse width modulation
  • a FIVR fully integrated voltage regulator
  • a FIVR may be implemented with any suitable switching DC regulator technology. It will typically have most, if not all, of its components housed in a semiconductor package (package including one or more dies) for which it is supplying regulated power. For example, in some embodiments, the power FETs, control circuitry and high frequency decoupling components might be on the die, while the inductors and mid-frequency input decoupling capacitors might be in the package.
  • FIG. 2 A block diagram representing the circuitry for a single FIVR domain is shown in FIG. 2 .
  • This FIVR is a 140 MHz synchronous multiphase buck converter with 16 phases.
  • the buck regulator bridges may be formed by replacing power gates from previous designs with NMOS and PMOS cascode power switches.
  • the cascode configuration allows the power switches to be implemented with logic devices from more advanced (e.g., smaller feature size) semiconductor processes, and at the same time, they may be able to handle reasonably high input voltages (e.g., up to 1.8 VDC). This can reduce the cost of extra processing steps for high voltage devices, while achieving desired switching characteristics.
  • the bridge drivers may be controlled thru high-voltage level-shifters and may support ZVS (zero-voltage switching) and ZCS (zero-current-switching) soft-switching operation.
  • the gates of the cascode devices are coupled to a “half-rail” supply (e.g., Vccdrvn) regulated to Vin/2. This may also be used as a low-side supply for the PMOS bridge driver as well as for the high-side supply of the NMOS bridge driver.
  • the area occupied by the power switches and drivers is small, so they may be efficiently distributed across the die, for example, above a connection to their associated package inductor, which minimizes routing losses.
  • the driver circuitry is interleaved with the power switches in an array which can minimize parasitics to allow for very high switching frequencies. This also can allow the size of the bridge to be scaled based on the current requirements and optimization points for each supply domain.
  • Each FIVR domain is controlled by a FIVR Control Module (FCM).
  • FCM FIVR Control Module
  • the FCM contains the circuitry for generating the PWM signals using double-edge modulation, as indicated in FIG. 2 by the dashed box.
  • Separate circuitry also not shown) manages phase current balancing, and the resulting digital PWM signals are distributed from the FCM to individual bridges.
  • the PWM frequency, PWM gain, phase activation, and the angle of each phase may be programmable in fine increments to enable optimal efficiency and minimum voltage ripple across a span of different operating points.
  • spread-spectrum may be used for EMI and RFI (Radio Frequency Interference) control.
  • compensator circuitry feedback control circuitry.
  • the FIVR compensator closes the voltage regulation loop. It is called a compensator because of the combination of passive devices (e.g., in programmable compensation block 204 ) added around it to compensate the loop to insure stable closed loop operation. Due to the phase shift introduced in the system by the inductor (LC) output filter, the closed loop operation would likely not be stable without proper compensation (through an RC network which is part of programmable compensator 204 ).
  • the compensator output (labeled “Feedback Voltage”) drives the PWM (Pulse Width Modulator), and it sets the duty cycle of the converter to maintain proper output voltage.
  • a high-precision 9-bit DAC 206 generates a reference voltage for a programmable, high bandwidth analog fully differential type-3 compensator (formed from amplifier 202 and programmable RC compensation circuit 204 ).
  • Sense lines feed the FIVR output voltage back to the compensator.
  • the compensator may be programmed individually for each voltage domain based on its output filter, and can be reprogrammed while the domain is active to maintain optimal transient response, e.g., as phase shedding occurs. Pertinent to this disclosure, it may also be used for transitioning back to a FIVR mode from an LVR mode.
  • the compensator output voltage (Feedback Voltage) is measured before the FIVR is deactivated.
  • the amplifier 202 is disable (e.g., tri-stated output), and a separate DAC (not shown) is used to generate a priming voltage at the compensator output (output of 202 ) to precharge the output at the stored level from when the FIVR was de-activated.
  • the PWM is started at a value that should generate a FIVR output voltage equivalent to what it was before being deactivated.
  • FIG. 3 is a diagram showing a single FIVR/LVR block for supplying power to a voltage domain in accordance with some embodiments.
  • the block includes an LVR 305 coupled in parallel with the FIVR 325 to provide power to the output rail (VCCOUT) when the input supply (VCCIN) is at a reduced level.
  • VCCIN is the primary input power supply for both FIVR and Parallel LVR.
  • the VCCIN rail can likely not be fully turned off but leakage power can be reduced drastically by reducing the VCCIN voltage, e.g., from between 1.6 V and 1.8 V to a voltage between 1.2 V and 1.3 V.
  • the FIVR and LVR outputs are physically shorted (as shown in the figure) for the VCCOUT rail (although their output stages, either through switches or direct deactivation, may be disengaged from the output VCCOUT).
  • VCCIN when the processor is to be in an active state (e.g., ACPI C0-C3), VCCIN will go to an active level (e.g., 1.8 V).
  • the FIVR In this higher (active) input supply mode, the FIVR is controlled to be active to regulate the output rail(s) VCCOUT, with the LVR deactivated.
  • the processor load reduces, and thus, in order to save power, VCCIN may be lowered, e.g., to 1.3 V.
  • the LVR is activated to regulate the VCCOUT rail, while the FIVR is turned off. In some embodiments, procedures for transitioning between these regulators with very little (if any) voltage change is presented below. (The output voltage will remain substantially the same except that FIVR output ripple noise will disappear when the LVR is driving the output.)
  • a linear voltage regulator is used for LVR 305
  • a FIVR is used for an IVR.
  • An FCM control logic 335 (which may correspond to the FCM discussed with respect to the FIVR in FIG. 2 ) is configured to control operation and/or activation of the LVR and IVR.
  • the FCM can control (or adjust) the LVR output through control of the LVR trim control logic 315 .
  • the FCM may also monitor, store, and control compensator values for the FIVR, e.g., as described with respect to FIG. 2 .
  • the parallel LVR 305 is designed to deliver a smaller amount of current than can the FIVR (but enough for a low power state condition) at a greater efficiency. It should be appreciated that while a simple linear regulator is shown for use as the low voltage regulator, any suitable regulator design could be employed. For example, alternate LVRs could be implemented with a small switching mode voltage regulator or a switched capacitor voltage converter. Ideally, the LVR will provide a suitably controllable output voltage, not be too complicated so as to incur excessive overhead, and importantly, operate with increased efficiency, as compared with the FIVR, at reduced input voltages.)
  • parallel LVRs may not be used in some domains where full power is to be available during low power modes.
  • Such domains could include, for example, platform controller rails that may be the only IVR rails active in low power state C7 while other rails (e.g., CPU core, graphics and LLC) are off.
  • the parallel LVRs will be engaged in C7+ low power states where the power consumption of the CPU is low while the IVRs are used to supply those rails the rest of the time.
  • transition into the parallel LVR mode may be substantially transparent and seamless.
  • the voltage remains the same, and the load being powered is unaware of the change in power delivery source.
  • the FIVR regulates the output power rail VCCOUT.
  • low power states e.g., VCCIN reduced to between 1.2V and 1.3V
  • the FIVR is turned off and the parallel LVR is used to regulate the corresponding output power rail instead of the FIVR.
  • FIG. 4 is a diagram showing a routine 401 for transitioning from the FIVR to the LVR to regulate the output rail (VCCOUT).
  • the LVR is powered up.
  • the LVR is trimmed to match the FIVR output voltage. This may be done in any suitable manner. For example, the input reference could be compared against the VCCOUT output until it is sufficiently equal, and this trim setting could then be used, especially in cases where the LVR output offset, relative to the reference voltage, is sufficiently small.
  • the LVR output could be compared against the FIVR output (VCCOUT), while the LVR output is decoupled from the VCCOUT rail. The LVR could then be trimmed until its output was matched with the FIVR output.
  • the FIVR duty cycle is stored (e.g., by the FCM). This will allow it to be used later for restart with the same duty cycle for the LVR to FIVR transition.
  • the LVR output stage is enabled to drive the output (VCCOUT) in open loop mode.
  • the FIVR phases are shut down, as the FIVR is deactivated.
  • the LVR is then set for close loop operation. At this point, the LVR is driving the output rail.
  • the FIVR may be powered off, and the VCCIN voltage is lowered to the lower level (e.g., 1.3 V).
  • FIG. 5 is a diagram showing a routine 501 for transitioning from the LVR to the FIVR, e.g., when the VCCIN supply is to go to a higher active voltage level.
  • VCCIN is ramped to 1.8V.
  • the FIVR is primed with the duty cycle settings stored from previous operation. Priming the compensator output with the recorded voltage level needed for the PWM to generate the same duty cycle as was present before the FIVR hand off the regulation to the LVR allows the FIVR to restart generating a voltage at substantially the same (if not identical) level as what it generated before being deactivated. (Note, if this is not done, the FIVR would likely ramp its output voltage from zero and initially short the LVR to ground.
  • the IVR phases are enabled. During this time, both the IVR and LVR will drive the output for a short time.
  • the LVR output stage is disabled.
  • the LVR is powered off.
  • Coupled is used to indicate that two or more elements are in direct physical or electrical contact with each other.
  • Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
  • Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
  • Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
  • PMOS transistor refers to a P-type metal oxide semiconductor field effect transistor.
  • NMOS transistor refers to an N-type metal oxide semiconductor field effect transistor.
  • MOS transistor MOS transistor
  • NMOS transistor NMOS transistor
  • PMOS transistor PMOS transistor
  • transistor can include other suitable transistor types, e.g., junction-field-effect transistors, bipolar-junction transistors, metal semiconductor FETs, and various types of three dimensional transistors, MOS or otherwise, known today or not yet developed.
  • suitable transistor types e.g., junction-field-effect transistors, bipolar-junction transistors, metal semiconductor FETs, and various types of three dimensional transistors, MOS or otherwise, known today or not yet developed.
  • IC semiconductor integrated circuit
  • PDA programmable logic arrays
  • signal conductor lines are represented with lines. Some may be thicker, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
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US14/621,261 2015-02-12 2015-02-12 Dual supply Abandoned US20160239036A1 (en)

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US14/621,261 US20160239036A1 (en) 2015-02-12 2015-02-12 Dual supply
TW105100395A TWI590023B (zh) 2015-02-12 2016-01-07 調節輸出電壓的晶片和計算裝置
CN201680007174.8A CN107209527A (zh) 2015-02-12 2016-01-12 双电源
KR1020177021021A KR102454797B1 (ko) 2015-02-12 2016-01-12 듀얼 서플라이
PCT/US2016/013094 WO2016130259A1 (en) 2015-02-12 2016-01-12 Dual supply
EP16749561.3A EP3257144A4 (en) 2015-02-12 2016-01-12 Dual supply

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EP (1) EP3257144A4 (zh)
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US20220045611A1 (en) 2019-04-25 2022-02-10 Huawei Technologies Co., Ltd. Power Supply Circuit and Power Supply Control Method
US11256276B2 (en) * 2015-11-20 2022-02-22 Texas Instruments Incorporated Inductor detection
WO2022164499A1 (en) * 2021-01-29 2022-08-04 Nuvia, Inc. Current balancing for voltage regulator units in field programmable arrays
US11658577B2 (en) 2021-01-29 2023-05-23 Qualcomm Incorporated Power management integrated circuit with a field programmable array of voltage regulators

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Publication number Priority date Publication date Assignee Title
GB201919050D0 (en) * 2019-12-20 2020-02-05 Nordic Semiconductor Asa Powering system on chip arrangements

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