US20160197006A1 - Method for locating devices - Google Patents

Method for locating devices Download PDF

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Publication number
US20160197006A1
US20160197006A1 US14/903,961 US201414903961A US2016197006A1 US 20160197006 A1 US20160197006 A1 US 20160197006A1 US 201414903961 A US201414903961 A US 201414903961A US 2016197006 A1 US2016197006 A1 US 2016197006A1
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Prior art keywords
process according
layer
cavities
device layer
useful
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US14/903,961
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Marcel Broekaart
Ionut Radu
Chrystelle Lagahe Blanchard
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Soitec SA
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Soitec SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This disclosure relates to a process for locating devices after transfer of a useful layer to a carrier substrate.
  • a prior-art process for locating devices after transfer of a useful layer 8 to a carrier substrate 1 comprises the following steps:
  • the device layer 4 comprises devices such as transistors, (npn or pnp) junctions, interconnections and any other structure.
  • the useful layer 8 generally comprises an opaque semiconductor layer.
  • the useful layer 8 masks the devices of the device layer 4 and the alignment marks 5 .
  • the main drawback of this process is that the alignment marks 5 are no longer accessible or observable.
  • apertures 9 must be produced in the useful layer 8 in order to expose the alignment marks 5 .
  • the process for forming the apertures 9 generally comprises a photolithography step, followed by an etching step.
  • the photolithography step is intended to define the shape and position of the apertures 9 in the useful layer 8 .
  • this step carried out with no reference point other than the edge of the carrier substrate 1 , has a precision of +/ ⁇ 100 ⁇ m. Therefore, the alignment marks 5 can be localized only to within +/ ⁇ 100 ⁇ m.
  • the apertures 9 must thus have a side length (i.e., a width) of about 250 ⁇ m. Such a side length consumes too much space, and is unacceptable.
  • One aim of the disclosure is, therefore, to provide a simpler process for locating devices after transfer of a useful layer 8 , allowing smaller apertures to be formed than with prior-art techniques.
  • This disclosure aims to remedy the aforementioned drawbacks, and relates to a process for locating devices after transfer of a useful layer, the process comprising the following steps:
  • the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
  • the alignment marks are placed so as to make it possible to locate the devices.
  • the useful layer may be formed from a set of sublayers.
  • the useful layer is generally opaque and, therefore, masks the device layer after step e).
  • the cavities have walls, and the volume delimited by the walls of a cavity and its aperture makes up the volume of the cavity.
  • alignment marks placed in cavities is meant that the alignment marks are placed in the volume of the cavities.
  • the devices of the device layer may be located from the free surface of the useful layer.
  • the holes are automatically formed in the positions of the cavities at the moment of the transfer of the useful layer.
  • the through-holes in the useful layer have a shape that corresponds to the aperture of the cavities. Therefore, the through-holes in the useful layer do not encroach beyond the aperture of the cavities.
  • the cavities extend as far as into the carrier substrate.
  • the alignment marks are placed at the bottom of the cavities.
  • the device layer comprises devices regularly distributed over the entire extent of the device layer.
  • an opaque layer is present on the useful layer before the assembly step d).
  • the opaque layer comprises at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • step c) of forming the weak zone is executed by implanting at least one of the species selected from the following group: hydrogen and helium.
  • the fracturing step e) comprises a heat treatment executed at a temperature between 200° C. and 500° C.
  • the thickness of the useful layer is smaller than 8000 ⁇ and preferably smaller than 5000 ⁇ .
  • the useful layer comprises sublayers of different doping.
  • FIGS. 1A and 1B are schematic representations of a structure obtained with a process for locating devices according to prior-art techniques
  • FIG. 2 is a schematic representation of a process for locating devices according to one embodiment of the disclosure
  • FIG. 3 is a schematic representation of the structure obtained with the process for locating devices according to a second embodiment of the disclosure.
  • FIG. 4 is a schematic representation of the process for locating devices according to one embodiment of the disclosure.
  • FIGS. 2 and 3 schematically illustrate a process for locating devices.
  • Step a) of the process for locating devices comprises providing a carrier substrate 10 comprising a front side 20 and a back side 30 parallel to the front side 20 .
  • the carrier substrate 10 may comprise a bulk substrate on which a device layer 40 is formed on the front side 20 of the carrier substrate 10 .
  • the bulk substrate may consist of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • the bulk substrate may comprise at least one material selected from the following group: silicon, silicon carbide, silicon germanium, glass, a ceramic and a metal alloy.
  • the device layer 40 comprises devices, such as electronic devices (for example transistors, junctions, etc.), interconnections and/or metalized zones.
  • electronic devices for example transistors, junctions, etc.
  • the devices are formed using techniques well known to those skilled in the art.
  • the devices may be regularly distributed over the entire extent of the device layer 40 .
  • Cavities 90 are formed in the device layer 40 .
  • the cavities 90 are open and comprise an aperture flush with the free surface of the device layer 40 .
  • the cavities 90 comprise walls.
  • the walls of the cavity 90 and the aperture of the cavity 90 delimit the volume of the cavity 90 .
  • the cavities 90 may extend as far as into the carrier substrate 10 .
  • Alignment marks 50 are placed in the volume of the cavities 90 , and the alignment marks 50 are away from the aperture of the cavities 90 .
  • the alignment marks 50 are placed so as to make it possible to precisely locate the devices of the device layer 40 .
  • Alignment marks 50 are conventionally used to align photolithography masks.
  • the alignment marks 50 may take the form of crosses, chevrons or interference patterns, or any other form liable to allow the precise location of the devices to be determined.
  • the alignment marks 50 are placed at the bottom of the cavities 90 .
  • Step b) of the process for locating devices comprises providing a donor substrate 60 .
  • the donor substrate 60 may be made of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • the donor substrate 60 may comprise at least one material selected from the following group: silicon, silicon carbide and silicon germanium.
  • the donor substrate 60 may comprise a semiconductor material.
  • Step c) of the process for locating devices may comprise forming a weak zone 70 in the donor substrate 60 .
  • the donor substrate 60 comprises a first surface.
  • the weak zone 70 and the first surface of the donor substrate 60 delimit a useful layer 80 intended to be transferred to the device layer 40 .
  • the weak zone 70 may be obtained by implanting atomic species.
  • the weakening implantation may be carried out with a single species (for example, hydrogen or helium), but may also be carried out with a plurality of sequentially implanted species (for example, hydrogen and helium).
  • the hydrogen is implanted with an energy of between 20 and 70 keV, and a dose of between 4 ⁇ 10 16 and 6 ⁇ 10 16 atoms/cm 2 .
  • the helium may be implanted with an energy of between 20 and 70 keV, and a dose of between 0.5 ⁇ 10 16 and 3 ⁇ 10 16 atoms/cm 2 .
  • the useful layer 80 may have a thickness smaller than 8000 ⁇ and preferably smaller than 5000 ⁇ .
  • Step d) of the process for locating devices may comprise assembling the donor substrate 60 and the carrier substrate 10 .
  • the assembly step d) may be executed by direct bonding.
  • the assembly may be executed by bringing the useful layer 80 into direct contact with the device layer 40 .
  • the assembly is executed so as to preserve, at least in part, the volume of the cavities 90 . Therefore, the presence of cavities 90 generates unbonded zones.
  • the assembly step d) may comprise a direct bonding step executed in an environment at a pressure below 20 mbar (2000 Pa).
  • an intermediate layer 100 may be placed on the useful layer 80 before the assembly step d).
  • the intermediate layer 100 may be an opaque layer placed on the useful layer 80 .
  • the opaque layer may comprise at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • Step e) of the method for locating devices comprises fracturing the donor substrate 60 in the weak zone 70 so as to transfer the useful layer 80 to the device layer 40 .
  • the useful layer 80 masks the devices.
  • the opaque layer is then located intermediate between the useful layer 80 and the device layer 40 after the fracturing step.
  • the fracturing step e) may comprise a heat treatment executed at a temperature between 200° C. and 500° C.
  • the through-holes in the useful layer 80 are in positional correspondence with the cavities 90 , so that the through-holes extend the cavities 90 into the useful layer 80 .
  • each cavity 90 is inscribed in the aperture of a hole of the useful layer 80 .
  • each through-hole in the useful layer 80 may have an aperture that corresponds to the aperture in the cavity 90 into which it extends, such as illustrated in FIG. 3 .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Machine Tool Sensing Apparatuses (AREA)
  • Micromachines (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The disclosure relates to a process for locating devices, the process comprising the following steps:
    • a) providing a carrier substrate comprising:
      • a device layer; and
      • alignment marks;
    • b) providing a donor substrate;
    • c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer;
    • d) assembling the donor substrate and the carrier substrate; and
    • e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer;
    • wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a national phase entry under 35 U.S.C. §371 of International Patent Application PCT/FR2014/051568, filed Jun. 24, 2014, designating the United States of America and published in English as International Patent Publication WO 2015/007971 A1 on Jan. 22, 2015, which claims the benefit under Article 8 of the Patent Cooperation Treaty and under 35 U.S.C. §119(e) to French Patent Application Serial No. 1301697, filed Jul. 15, 2013, the disclosure of each of which is hereby incorporated herein in its entirety by this reference.
    • TECHNICAL FIELD
  • This disclosure relates to a process for locating devices after transfer of a useful layer to a carrier substrate.
    • BACKGROUND
  • A prior-art process for locating devices after transfer of a useful layer 8 to a carrier substrate 1, as illustrated in FIG. 1A, comprises the following steps:
      • a0) Providing a carrier substrate 1 comprising:
        • A front side 2;
        • A back side 3 parallel to the front side 2; and
        • A device layer 4 placed on the front side 2, the device layer 4 comprising alignment marks 5;
      • b0) Providing a donor substrate 6;
      • c0) Forming a weak zone 7 in the donor substrate 6, the weak zone 7 delimiting a useful layer 8;
      • d0) Assembling the donor substrate 6 and the carrier substrate 1; and
      • e0) Fracturing the donor substrate 6 in the weak zone 7 so as to transfer the useful layer 8 to the device layer 4.
  • The device layer 4 comprises devices such as transistors, (npn or pnp) junctions, interconnections and any other structure. The useful layer 8 generally comprises an opaque semiconductor layer.
  • After the fracturing step e0), the useful layer 8 masks the devices of the device layer 4 and the alignment marks 5.
  • The main drawback of this process is that the alignment marks 5 are no longer accessible or observable.
  • Therefore, such as shown in FIG. 1B, which illustrates a common practice, apertures 9 (or holes) must be produced in the useful layer 8 in order to expose the alignment marks 5.
  • The process for forming the apertures 9 generally comprises a photolithography step, followed by an etching step.
  • The photolithography step is intended to define the shape and position of the apertures 9 in the useful layer 8. However, this step, carried out with no reference point other than the edge of the carrier substrate 1, has a precision of +/−100 μm. Therefore, the alignment marks 5 can be localized only to within +/−100 μm. The apertures 9 must thus have a side length (i.e., a width) of about 250 μm. Such a side length consumes too much space, and is unacceptable.
  • One aim of the disclosure is, therefore, to provide a simpler process for locating devices after transfer of a useful layer 8, allowing smaller apertures to be formed than with prior-art techniques.
    • BRIEF SUMMARY
  • This disclosure aims to remedy the aforementioned drawbacks, and relates to a process for locating devices after transfer of a useful layer, the process comprising the following steps:
      • a) providing a carrier substrate comprising:
        • a device layer comprising a free surface; and
        • alignment marks;
      • b) providing a donor substrate;
      • c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer;
      • d) assembling the donor substrate and the carrier substrate; and
      • e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer.
  • The alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer. The alignment marks are placed so as to make it possible to locate the devices.
  • The useful layer may be formed from a set of sublayers. The useful layer is generally opaque and, therefore, masks the device layer after step e).
  • The cavities have walls, and the volume delimited by the walls of a cavity and its aperture makes up the volume of the cavity.
  • By “alignment marks placed in cavities,” is meant that the alignment marks are placed in the volume of the cavities.
  • The presence of through-holes in the useful layer has been observed after the fracturing step e), and in positional correspondence with the cavities. The holes thus extend through the cavities into the useful layer, so that the alignment marks are visible from the free surface of the useful layer.
  • Thus, the devices of the device layer may be located from the free surface of the useful layer.
  • Furthermore, it is not necessary to execute fabrication steps specific to the formation of holes in the useful layer. The holes are automatically formed in the positions of the cavities at the moment of the transfer of the useful layer.
  • According to one method of implementation, the assembly step d) comprises a direct bonding step executed in an environment at a pressure below 20 mbars.
  • Thus, it has been observed that the through-holes in the useful layer have a shape that corresponds to the aperture of the cavities. Therefore, the through-holes in the useful layer do not encroach beyond the aperture of the cavities.
  • According to one method of implementation, the cavities extend as far as into the carrier substrate.
  • According to one method of implementation, the alignment marks are placed at the bottom of the cavities.
  • According to one method of implementation, the device layer comprises devices regularly distributed over the entire extent of the device layer.
  • According to one method of implementation, an opaque layer is present on the useful layer before the assembly step d).
  • According to one method of implementation, the opaque layer comprises at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • According to one method of implementation, step c) of forming the weak zone is executed by implanting at least one of the species selected from the following group: hydrogen and helium.
  • According to one method of implementation, the fracturing step e) comprises a heat treatment executed at a temperature between 200° C. and 500° C.
  • According to one method of implementation, the thickness of the useful layer is smaller than 8000 Å and preferably smaller than 5000 Å.
  • According to one method of implementation, the useful layer comprises sublayers of different doping.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features and advantages will become apparent from the following description of methods of implementation of a process for locating devices according to the disclosure, which are given by way of nonlimiting example and with reference to the appended drawings, in which:
  • FIGS. 1A and 1B are schematic representations of a structure obtained with a process for locating devices according to prior-art techniques;
  • FIG. 2 is a schematic representation of a process for locating devices according to one embodiment of the disclosure;
  • FIG. 3 is a schematic representation of the structure obtained with the process for locating devices according to a second embodiment of the disclosure; and
  • FIG. 4 is a schematic representation of the process for locating devices according to one embodiment of the disclosure.
    •  DETAILED DESCRIPTION
  • For the various methods of implementation, the same references will be used for elements that are identical or that provide the same function, for the sake of simplicity of the description.
  • FIGS. 2 and 3 schematically illustrate a process for locating devices.
  • To facilitate the illustration, the respective thicknesses of the various layers are not shown to scale.
  • Step a) of the process for locating devices comprises providing a carrier substrate 10 comprising a front side 20 and a back side 30 parallel to the front side 20.
  • The carrier substrate 10 may comprise a bulk substrate on which a device layer 40 is formed on the front side 20 of the carrier substrate 10.
  • The bulk substrate may consist of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • In particular, the bulk substrate may comprise at least one material selected from the following group: silicon, silicon carbide, silicon germanium, glass, a ceramic and a metal alloy.
  • The device layer 40 comprises devices, such as electronic devices (for example transistors, junctions, etc.), interconnections and/or metalized zones.
  • The devices are formed using techniques well known to those skilled in the art.
  • The devices may be regularly distributed over the entire extent of the device layer 40.
  • Cavities 90 are formed in the device layer 40. The cavities 90 are open and comprise an aperture flush with the free surface of the device layer 40.
  • The cavities 90 comprise walls. The walls of the cavity 90 and the aperture of the cavity 90 delimit the volume of the cavity 90.
  • Advantageously, the cavities 90 may extend as far as into the carrier substrate 10.
  • Alignment marks 50 are placed in the volume of the cavities 90, and the alignment marks 50 are away from the aperture of the cavities 90.
  • The alignment marks 50 are placed so as to make it possible to precisely locate the devices of the device layer 40.
  • Alignment marks 50 are conventionally used to align photolithography masks.
  • The alignment marks 50 may take the form of crosses, chevrons or interference patterns, or any other form liable to allow the precise location of the devices to be determined.
  • In this respect, those skilled in the art will find a technical description of the alignment or photolithography masks in Fundamentals of Microfabrication: The Science of Miniaturization, 2nd ed., Marc J. Madou, Nanogen, Inc., San Diego, Calif.
  • Advantageously, the alignment marks 50 are placed at the bottom of the cavities 90.
  • Step b) of the process for locating devices comprises providing a donor substrate 60.
  • The donor substrate 60 may be made of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • In particular, the donor substrate 60 may comprise at least one material selected from the following group: silicon, silicon carbide and silicon germanium.
  • The donor substrate 60 may comprise a semiconductor material.
  • Step c) of the process for locating devices may comprise forming a weak zone 70 in the donor substrate 60.
  • The donor substrate 60 comprises a first surface. The weak zone 70 and the first surface of the donor substrate 60 delimit a useful layer 80 intended to be transferred to the device layer 40.
  • The weak zone 70 may be obtained by implanting atomic species. The weakening implantation may be carried out with a single species (for example, hydrogen or helium), but may also be carried out with a plurality of sequentially implanted species (for example, hydrogen and helium).
  • Advantageously, the hydrogen is implanted with an energy of between 20 and 70 keV, and a dose of between 4×1016 and 6×1016 atoms/cm2.
  • The helium may be implanted with an energy of between 20 and 70 keV, and a dose of between 0.5×1016 and 3×1016 atoms/cm2.
  • In some embodiments, the useful layer 80 may have a thickness smaller than 8000 Å and preferably smaller than 5000 Å.
  • Step d) of the process for locating devices may comprise assembling the donor substrate 60 and the carrier substrate 10.
  • In some embodiments, the assembly step d) may be executed by direct bonding.
  • The assembly may be executed by bringing the useful layer 80 into direct contact with the device layer 40. The assembly is executed so as to preserve, at least in part, the volume of the cavities 90. Therefore, the presence of cavities 90 generates unbonded zones.
  • The assembly step d) may comprise a direct bonding step executed in an environment at a pressure below 20 mbar (2000 Pa).
  • Such as illustrated in FIG. 4, an intermediate layer 100 may be placed on the useful layer 80 before the assembly step d).
  • The intermediate layer 100 may be an opaque layer placed on the useful layer 80.
  • The opaque layer may comprise at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • Step e) of the method for locating devices comprises fracturing the donor substrate 60 in the weak zone 70 so as to transfer the useful layer 80 to the device layer 40.
  • Thus, after step e), the useful layer 80 masks the devices.
  • If an opaque layer has been formed on the useful layer 80 prior to the assembly step d), the opaque layer is then located intermediate between the useful layer 80 and the device layer 40 after the fracturing step.
  • Advantageously, the fracturing step e) may comprise a heat treatment executed at a temperature between 200° C. and 500° C.
  • Particularly advantageously, after the fracturing step e), the presence of through-holes has been observed in the useful layer 80, and the opaque layer in the case where the latter is present.
  • Moreover, the through-holes in the useful layer 80 are in positional correspondence with the cavities 90, so that the through-holes extend the cavities 90 into the useful layer 80.
  • Furthermore, the aperture of each cavity 90 is inscribed in the aperture of a hole of the useful layer 80.
  • In embodiments in which step d) comprises direct bonding executed in an environment at a pressure below 20 mbar (2000 Pa), each through-hole in the useful layer 80 may have an aperture that corresponds to the aperture in the cavity 90 into which it extends, such as illustrated in FIG. 3.
  • The presence of these holes in the useful layer 80 is advantageously capitalized upon to expose the alignment marks 50 placed in the cavities 90.
  • Thus, it is possible to locate the devices masked by the useful layer 80.

Claims (18)

1. A process for locating devices after transfer of a useful layer, the process comprising the following steps:
a) providing a carrier substrate comprising:
a device layer comprising a free surface; and
alignment marks;
b) providing a donor substrate;
c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer;
d) assembling the donor substrate and the carrier substrate; and
e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer;
wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
2. The process according to claim 1, in which the assembly step d) comprises a direct bonding step executed in an environment at a pressure below 20 mbars.
3. The process according to claim 2, wherein the cavities extend into the carrier substrate.
4. The process according to claim 3, wherein the alignment marks are placed at the bottom of the cavities.
5. The process according to claim 4, wherein the device layer comprises devices distributed over an entire extent of the device layer.
6. The process according to claim 4, wherein an opaque layer is present on the useful layer before the assembly step d).
7. The process according to claim 6, wherein the opaque layer comprises at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
8. The process according to claim 4, wherein the step c) of forming the weak zone is executed by implanting at least one of the species selected from the following group: hydrogen and helium.
9. The process according to claim 4, wherein the fracturing step e) comprises a heat treatment executed at a temperature between 200° C. and 500° C.
10. The process according to claim 1, wherein the thickness of the useful layer is smaller than 8000 Å.
11. The process according to claim 1, wherein the useful layer comprises sublayers of different doping.
12. The process according to claim 10, wherein the thickness of the userful layer is smaller than 5000 Å.
13. The process according to claim 1, wherein the cavities extend into the carrier substrate.
14. The process according to claim 1, wherein the alignment marks are placed at the bottom of the cavities.
15. The process according to claim 1, wherein the device layer comprises devices distributed over an entire extent of the device layer.
16. The process according to claim 1, wherein an opaque layer is present on the useful layer before the assembly step d).
17. The process according to claim 1, wherein the step c) of forming the weak zone is executed by implanting at least one of the species selected from the following group: hydrogen and helium.
18. The process according to claim 1, wherein the fracturing step e) comprises a heat treatment executed at a temperature between 200° C. and 500° C.
US14/903,961 2013-07-15 2014-06-24 Method for locating devices Abandoned US20160197006A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1301697 2013-07-15
FR1301697A FR3008543B1 (en) 2013-07-15 2013-07-15 METHOD OF LOCATING DEVICES
PCT/FR2014/051568 WO2015007971A1 (en) 2013-07-15 2014-06-24 Method for locating devices

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US16/685,938 Continuation US11088016B2 (en) 2013-07-15 2019-11-15 Method for locating devices

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019186035A1 (en) * 2018-03-29 2019-10-03 Soitec Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure
US11401162B2 (en) * 2017-12-28 2022-08-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for transferring a useful layer into a supporting substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130037958A1 (en) * 2011-08-08 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS Image Sensor and Method for Forming the Same
US20140342487A1 (en) * 2013-05-15 2014-11-20 Commissariat A L'energie Atomique Et Aux Ene Alt Process for encapsulating a microelectronic device comprising injection of noble gas through a material permeable to this noble gas

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2628555B2 (en) 1988-03-22 1997-07-09 富士通株式会社 Method for manufacturing semiconductor device
KR0155835B1 (en) * 1995-06-23 1998-12-01 김광호 Method for forming align key pattern of semiconductor device
WO2001067509A1 (en) * 2000-03-09 2001-09-13 Fujitsu Limited Semiconductor device and method of manufacture thereof
JP2005142252A (en) * 2003-11-05 2005-06-02 Sony Corp Forming method of alignment mark, semiconductor device, and manufacturing method thereof
EP1571705A3 (en) 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Process of making a semiconductor structure on a substrate
KR101236211B1 (en) 2008-08-27 2013-02-25 소이텍 Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
JP5196160B2 (en) * 2008-10-17 2013-05-15 日亜化学工業株式会社 Semiconductor light emitting device
US8536629B2 (en) 2009-02-24 2013-09-17 Nec Corporation Semiconductor device and method for manufacturing the same
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
WO2011132654A1 (en) 2010-04-20 2011-10-27 住友電気工業株式会社 Method for producing composite substrate
JP5440442B2 (en) * 2010-08-18 2014-03-12 株式会社リコー Optical scanning apparatus and image forming apparatus
CN103119698B (en) * 2010-09-30 2016-05-18 富士电机株式会社 The manufacture method of semiconductor device
US8779539B2 (en) * 2011-09-21 2014-07-15 United Microelectronics Corporation Image sensor and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130037958A1 (en) * 2011-08-08 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS Image Sensor and Method for Forming the Same
US20140342487A1 (en) * 2013-05-15 2014-11-20 Commissariat A L'energie Atomique Et Aux Ene Alt Process for encapsulating a microelectronic device comprising injection of noble gas through a material permeable to this noble gas

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Korean Patent No.: 100543393 [machine's translation]. *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11401162B2 (en) * 2017-12-28 2022-08-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for transferring a useful layer into a supporting substrate
WO2019186035A1 (en) * 2018-03-29 2019-10-03 Soitec Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure
FR3079659A1 (en) * 2018-03-29 2019-10-04 Soitec METHOD FOR MANUFACTURING DONOR SUBSTRATE FOR CARRYING OUT A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND METHOD FOR MANUFACTURING SUCH AN INTEGRATED STRUCTURE
CN111868915A (en) * 2018-03-29 2020-10-30 Soitec公司 Process for manufacturing a donor substrate for producing a three-dimensional integrated structure and process for manufacturing such an integrated structure
US11239108B2 (en) 2018-03-29 2022-02-01 Soitec Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure

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