US20160190083A1 - Flip chip scheme and method of forming flip chip scheme - Google Patents
Flip chip scheme and method of forming flip chip scheme Download PDFInfo
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- US20160190083A1 US20160190083A1 US14/636,137 US201514636137A US2016190083A1 US 20160190083 A1 US20160190083 A1 US 20160190083A1 US 201514636137 A US201514636137 A US 201514636137A US 2016190083 A1 US2016190083 A1 US 2016190083A1
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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Definitions
- the disclosed embodiments of the present invention relate to a flip chip scheme and a method of forming the flip chip scheme, and more particularly, to a flip chip scheme and a method of forming the flip chip scheme which can fit power domains, reduce IR drops, shift bumps to enhance signal routing, and have a maximum bump number in every power domain.
- FIG. 1 is a simplified diagram of a conventional flip chip scheme 100 as shown in FIG. 3 of the U.S. Pat. No. 8,350,375.
- the conventional flip chip scheme 100 only use regular inline-bumps, and therefore the conventional flip chip scheme 100 is not capable of fitting non-uniform power domains and thus result in worse IR drops.
- FIG. 2 is a simplified diagram of a conventional flip chip scheme 200 as shown in FIG. 8 of the U.S. Pat. No. 8,350,375.
- the conventional flip chip scheme 200 only use regular stagger-bumps, and therefore the conventional flip chip scheme 200 is not capable of fitting non-uniform power domains and thus result in worse IR drops.
- a flip chip scheme and a method of forming the flip chip scheme which can fit power domains, reduce IR drops, shift bumps to enhance signal routing, and have a maximum bump number in every power domain are proposed to solve the above-mentioned problem.
- an exemplary flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- the flip chip scheme comprises: a non-uniform power domain; and a non-uniform bump map, formed by a plurality of bumps to fit the non-uniform power domain.
- an exemplary method of forming a flip chip scheme comprising a plurality of bumps.
- the method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- an exemplary method of forming a flip chip scheme comprises: forming a non-uniform power domain; and forming a non-uniform bump map by a plurality of bumps to fit the non-uniform power domain.
- the present invention can place the bumps non-uniformly based on power distributions in the flip chip scheme, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain.
- FIG. 1 is a simplified diagram of a conventional flip chip scheme as shown in FIG. 3 of the U.S. Pat. No. 8,350,375.
- FIG. 2 is a simplified diagram of a conventional flip chip scheme as shown in FIG. 8 of the U.S. Pat. No. 8,350,375.
- FIG. 3 is a simplified diagram of a flip chip scheme according to a first exemplary embodiment of the present invention.
- FIG. 4 is a simplified diagram of the first pattern, the second pattern, and a combination of the first pattern and the second pattern.
- FIG. 5 is a simplified diagram of a flip chip scheme according to a second exemplary embodiment of the present invention
- FIG. 7 is a flowchart showing a method of forming a flip chip scheme in accordance with the flip chip schemes in FIG. 3 and FIG. 5 .
- FIG. 3 is a simplified diagram of a flip chip scheme 500 according to a first exemplary embodiment of the present invention, wherein the flip chip scheme 500 can be applied to an SOC integrated circuit.
- the flip chip scheme 500 comprises a plurality of bumps 510 , wherein the bumps 510 can comprise power bumps and ground bumps. Some of the bumps 510 arranged in a first pattern, respectively, and some of the bumps 510 arranged in a second pattern different from the first pattern, respectively.
- the flip chip scheme 500 comprises a bump map formed by a plurality of first patterns and a plurality of second patterns as shown in FIG. 3 . Please refer to FIG. 4 .
- FIG. 4 FIG.
- the first pattern can be an equilateral triangle 520 arranged by three bumps 510
- the second pattern can be a square arranged 530 by four bumps 510 .
- the flip chip scheme 500 comprises non-uniform power domains 540 , 550 , and a non-uniform bump map formed by a plurality of bumps 510 to fit the non-uniform power domains 540 , 550 .
- two bumps 510 are deleted when there is no enough bump spacing, and five bumps 510 are deleted due to out of the chip boundary.
- the present invention can place the bumps 510 non-uniformly based on power distributions in the flip chip scheme 500 , and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, and having a maximum bump number in every power domain.
- FIG. 5 is a simplified diagram of a flip chip scheme 600 according to a second exemplary embodiment of the present invention, wherein the flip chip scheme 600 can be applied to an SOC integrated circuit.
- the flip chip scheme 600 comprises a plurality of bumps 610 , wherein the bumps 610 can comprise power bumps and ground bumps. Some of the bumps 610 arranged in a first pattern, respectively, and some of the bumps 610 arranged in a second pattern different from the first pattern, respectively.
- the flip chip scheme 600 comprises a bump map formed by a plurality of first patterns and a plurality of second patterns as shown in FIG. 3 . Please refer to FIG. 4 .
- FIG. 4 FIG.
- the first pattern can be an equilateral triangle 620 arranged by three bumps 610
- the second pattern can be a square arranged 630 by four bumps 610 .
- the flip chip scheme 600 comprises non-uniform power domains 640 , 650 , a non-uniform bump map formed by a plurality of bumps 610 to fit the non-uniform power domains 640 , 650 , and a signal routing 660 .
- two bumps 610 have been deleted due to no enough bump spacing and five bumps 610 have been deleted due to out of the chip boundary, which is similar to the first exemplary embodiment of the present invention.
- one bump 610 is shifted because the signal routing 660 is near the shifted bump 610 .
- the present invention can place the bumps 610 non-uniformly based on power distributions in the flip chip scheme 600 , and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain.
- FIG. 6 is a flowchart showing a method of forming a flip chip scheme comprising a plurality of bumps in accordance with the flip chip schemes 500 and 600 in the above embodiment. Provided that the result is substantially the same, the steps in FIG. 6 are not required to be executed in the exact order shown in FIG. 6 .
- the method in accordance with the above embodiment of the flip chip schemes 500 and 600 in the present invention comprises the following steps:
- Step 700 Start.
- Step 702 Arrange some of the bumps in a first pattern, respectively.
- Step 704 Arrange some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- the above method can further comprise: forming a bump map by a plurality of first patterns and a plurality of second patterns, and the above method can also further comprise: deleting at least one of the bumps when there is no enough bump spacing. Or, the above method can further comprise: deleting at least one of the bumps when the bump is out of the chip boundary. Or, the above method can further comprise: shifting at least one of the bumps when there is a signal routing near the shifted bump.
- FIG. 7 is a flowchart showing a method of forming a flip chip scheme in accordance with the flip chip schemes 500 and 600 in the above embodiment. Provided that the result is substantially the same, the steps in FIG. 7 are not required to be executed in the exact order shown in FIG. 7 .
- the method in accordance with the above embodiment of the flip chip schemes 500 and 600 in the present invention comprises the following steps:
- Step 800 Start.
- Step 802 Form a non-uniform power domain.
- Step 804 Form a non-uniform bump map by a plurality of bumps to fit the non-uniform power domain.
- the above method can further comprise: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively, wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps, and the above method can further comprise: forming a bump map by a plurality of first patterns and a plurality of second patterns.
- the above method can further comprise: deleting at least one of the bumps when there is no enough bump spacing.
- the above method can further comprise: deleting at least one of the bumps when the bump is out of the chip boundary.
- the above method can further comprise: shifting at least one of the bumps when there is a signal routing near the shifted bump.
- the present invention can place the bumps non-uniformly based on power distributions in the flip chip scheme, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain.
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Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 62/097,137, filed on Dec. 29, 2014 and included herein by reference.
- The disclosed embodiments of the present invention relate to a flip chip scheme and a method of forming the flip chip scheme, and more particularly, to a flip chip scheme and a method of forming the flip chip scheme which can fit power domains, reduce IR drops, shift bumps to enhance signal routing, and have a maximum bump number in every power domain.
- Applications of using regular inline-bumps or stagger-bumps have already been disclosed and discussed in various literatures, such as U.S. Pat. No. 8,350,375 and U.S. Pat. No. 7,081,672. Please refer to
FIG. 1 .FIG. 1 is a simplified diagram of a conventionalflip chip scheme 100 as shown inFIG. 3 of the U.S. Pat. No. 8,350,375. As shown inFIG. 1 , the conventionalflip chip scheme 100 only use regular inline-bumps, and therefore the conventionalflip chip scheme 100 is not capable of fitting non-uniform power domains and thus result in worse IR drops. - Please refer to
FIG. 2 .FIG. 2 is a simplified diagram of a conventionalflip chip scheme 200 as shown inFIG. 8 of the U.S. Pat. No. 8,350,375. As shown inFIG. 2 , the conventionalflip chip scheme 200 only use regular stagger-bumps, and therefore the conventionalflip chip scheme 200 is not capable of fitting non-uniform power domains and thus result in worse IR drops. - In accordance with exemplary embodiments of the present invention, a flip chip scheme and a method of forming the flip chip scheme which can fit power domains, reduce IR drops, shift bumps to enhance signal routing, and have a maximum bump number in every power domain are proposed to solve the above-mentioned problem.
- According to a first aspect of the present invention, an exemplary flip chip scheme is disclosed. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- According to a second aspect of the present invention, another exemplary flip chip scheme is disclosed. The flip chip scheme comprises: a non-uniform power domain; and a non-uniform bump map, formed by a plurality of bumps to fit the non-uniform power domain.
- According to a third aspect of the present invention, an exemplary method of forming a flip chip scheme comprising a plurality of bumps is disclosed. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- According to a fourth aspect of the present invention, an exemplary method of forming a flip chip scheme is disclosed. The method comprises: forming a non-uniform power domain; and forming a non-uniform bump map by a plurality of bumps to fit the non-uniform power domain.
- Briefly summarized, the present invention can place the bumps non-uniformly based on power distributions in the flip chip scheme, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 is a simplified diagram of a conventional flip chip scheme as shown inFIG. 3 of the U.S. Pat. No. 8,350,375. -
FIG. 2 is a simplified diagram of a conventional flip chip scheme as shown inFIG. 8 of the U.S. Pat. No. 8,350,375. -
FIG. 3 is a simplified diagram of a flip chip scheme according to a first exemplary embodiment of the present invention. -
FIG. 4 is a simplified diagram of the first pattern, the second pattern, and a combination of the first pattern and the second pattern. -
FIG. 5 is a simplified diagram of a flip chip scheme according to a second exemplary embodiment of the present invention -
FIG. 6 is a flowchart showing a method of forming a flip chip scheme comprising a plurality of bumps in accordance with the flip chip schemes inFIG. 3 andFIG. 5 . -
FIG. 7 is a flowchart showing a method of forming a flip chip scheme in accordance with the flip chip schemes inFIG. 3 andFIG. 5 . - Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”.
- Please refer to
FIG. 3 .FIG. 3 is a simplified diagram of aflip chip scheme 500 according to a first exemplary embodiment of the present invention, wherein theflip chip scheme 500 can be applied to an SOC integrated circuit. As shown inFIG. 3 , theflip chip scheme 500 comprises a plurality ofbumps 510, wherein thebumps 510 can comprise power bumps and ground bumps. Some of thebumps 510 arranged in a first pattern, respectively, and some of thebumps 510 arranged in a second pattern different from the first pattern, respectively. Theflip chip scheme 500 comprises a bump map formed by a plurality of first patterns and a plurality of second patterns as shown inFIG. 3 . Please refer toFIG. 4 .FIG. 4 is a simplified diagram of the first pattern, the second pattern, and a combination of the first pattern and the second pattern (i.e. a combination of the equilateral triangle and the square). As shown inFIG. 4 , the first pattern can be anequilateral triangle 520 arranged by threebumps 510, and the second pattern can be a square arranged 530 by fourbumps 510. - As shown in
FIG. 3 , theflip chip scheme 500 comprisesnon-uniform power domains bumps 510 to fit thenon-uniform power domains bumps 510 are deleted when there is no enough bump spacing, and fivebumps 510 are deleted due to out of the chip boundary. Thus, the present invention can place thebumps 510 non-uniformly based on power distributions in theflip chip scheme 500, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, and having a maximum bump number in every power domain. - Please refer to
FIG. 5 .FIG. 5 is a simplified diagram of aflip chip scheme 600 according to a second exemplary embodiment of the present invention, wherein theflip chip scheme 600 can be applied to an SOC integrated circuit. As shown inFIG. 5 , theflip chip scheme 600 comprises a plurality ofbumps 610, wherein thebumps 610 can comprise power bumps and ground bumps. Some of thebumps 610 arranged in a first pattern, respectively, and some of thebumps 610 arranged in a second pattern different from the first pattern, respectively. Theflip chip scheme 600 comprises a bump map formed by a plurality of first patterns and a plurality of second patterns as shown inFIG. 3 . Please refer toFIG. 4 .FIG. 4 is a simplified diagram of the first pattern, the second pattern, and a combination of the first pattern and the second pattern (i.e. a combination of the equilateral triangle and the square). As shown inFIG. 4 , the first pattern can be an equilateral triangle 620 arranged by threebumps 610, and the second pattern can be a square arranged 630 by fourbumps 610. - As shown in
FIG. 5 , theflip chip scheme 600 comprisesnon-uniform power domains bumps 610 to fit thenon-uniform power domains signal routing 660. In this embodiment, twobumps 610 have been deleted due to no enough bump spacing and fivebumps 610 have been deleted due to out of the chip boundary, which is similar to the first exemplary embodiment of the present invention. In addition, onebump 610 is shifted because thesignal routing 660 is near the shiftedbump 610. Thus, the present invention can place thebumps 610 non-uniformly based on power distributions in theflip chip scheme 600, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain. - Please refer to
FIG. 6 .FIG. 6 is a flowchart showing a method of forming a flip chip scheme comprising a plurality of bumps in accordance with theflip chip schemes FIG. 6 are not required to be executed in the exact order shown inFIG. 6 . The method in accordance with the above embodiment of theflip chip schemes - Step 700: Start.
- Step 702: Arrange some of the bumps in a first pattern, respectively.
- Step 704: Arrange some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
- In addition, the above method can further comprise: forming a bump map by a plurality of first patterns and a plurality of second patterns, and the above method can also further comprise: deleting at least one of the bumps when there is no enough bump spacing. Or, the above method can further comprise: deleting at least one of the bumps when the bump is out of the chip boundary. Or, the above method can further comprise: shifting at least one of the bumps when there is a signal routing near the shifted bump.
- Please refer to
FIG. 7 .FIG. 7 is a flowchart showing a method of forming a flip chip scheme in accordance with theflip chip schemes FIG. 7 are not required to be executed in the exact order shown inFIG. 7 . The method in accordance with the above embodiment of theflip chip schemes - Step 800: Start.
- Step 802: Form a non-uniform power domain.
- Step 804: Form a non-uniform bump map by a plurality of bumps to fit the non-uniform power domain.
- In addition, the above method can further comprise: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively, wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps, and the above method can further comprise: forming a bump map by a plurality of first patterns and a plurality of second patterns. Moreover, the above method can further comprise: deleting at least one of the bumps when there is no enough bump spacing. Or, the above method can further comprise: deleting at least one of the bumps when the bump is out of the chip boundary. Or, the above method can further comprise: shifting at least one of the bumps when there is a signal routing near the shifted bump.
- Briefly summarized, the present invention can place the bumps non-uniformly based on power distributions in the flip chip scheme, and comparing with the conventional bump patterns, the present invention has advantages of fitting the power domains, reducing IR drops, shifting the bumps to enhance the signal routing, and having a maximum bump number in every power domain.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (24)
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CN107393898A (en) * | 2017-06-15 | 2017-11-24 | 华为机器有限公司 | Package substrate and semiconductor integrated device |
TWI811103B (en) * | 2022-07-13 | 2023-08-01 | 創意電子股份有限公司 | Communication interface structure and die-to-die package |
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US9557370B2 (en) * | 2012-02-10 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation |
JP6818534B2 (en) * | 2016-12-13 | 2021-01-20 | キヤノン株式会社 | Printed wiring board, printed circuit board and electronic equipment |
US10477672B2 (en) * | 2018-01-29 | 2019-11-12 | Hewlett Packard Enterprise Development Lp | Single ended vias with shared voids |
CN117374039A (en) * | 2021-03-26 | 2024-01-09 | 华为技术有限公司 | Packaging substrate, semiconductor device and electronic equipment |
CN113133219B (en) * | 2021-04-25 | 2022-09-09 | 无锡江南计算技术研究所 | DDR4 signal distribution method and chip based on staggered array packaging |
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US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US7034391B2 (en) * | 2003-11-08 | 2006-04-25 | Chippac, Inc. | Flip chip interconnection pad layout |
US7081672B1 (en) | 2005-03-07 | 2006-07-25 | Lsi Logic Corporation | Substrate via layout to improve bias humidity testing reliability |
US8350375B2 (en) * | 2008-05-15 | 2013-01-08 | Lsi Logic Corporation | Flipchip bump patterns for efficient I-mesh power distribution schemes |
US8686560B2 (en) * | 2010-04-07 | 2014-04-01 | Maxim Integrated Products, Inc. | Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress |
CN103975427B (en) * | 2011-10-07 | 2017-03-01 | 沃尔泰拉半导体公司 | The power management application of interconnection substrate |
US8873209B2 (en) * | 2011-12-19 | 2014-10-28 | Arm Limited | Integrated circuit and method of providing electrostatic discharge protection within such an integrated circuit |
CN102842564B (en) * | 2012-09-12 | 2014-06-25 | 矽力杰半导体技术(杭州)有限公司 | Flip-chip package device for integrated switching power supply and flip-chip packaging method |
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CN107393898A (en) * | 2017-06-15 | 2017-11-24 | 华为机器有限公司 | Package substrate and semiconductor integrated device |
TWI811103B (en) * | 2022-07-13 | 2023-08-01 | 創意電子股份有限公司 | Communication interface structure and die-to-die package |
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