US20160087123A1 - Solar cell and method for manufacturing the same - Google Patents
Solar cell and method for manufacturing the same Download PDFInfo
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- US20160087123A1 US20160087123A1 US14/961,362 US201514961362A US2016087123A1 US 20160087123 A1 US20160087123 A1 US 20160087123A1 US 201514961362 A US201514961362 A US 201514961362A US 2016087123 A1 US2016087123 A1 US 2016087123A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
- H01L31/022458—Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
- H01L31/0516—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Definitions
- Example embodiments of the invention relate to a solar cell and a method for manufacturing the same.
- a solar cell generally includes a substrate and an emitter layer, which are formed of semiconductors of different conductive types, such as a p-type and an n-type, and electrodes respectively connected to the substrate and the emitter layer.
- a p-n junction is formed at an interface between the substrate and the emitter layer.
- electrons inside the semiconductors become free electrons (hereinafter referred to as “electrons”) by the photoelectric effect. Further, electrons and holes respectively move to the n-type semiconductor (e.g., the emitter layer) and the p-type semiconductor (e.g., the substrate) based on the principle of the p-n junction. The electrons moving to the emitter layer and the holes moving to the substrate are respectively collected by the electrode connected to the emitter layer and the electrode connected to the substrate.
- An interdigitated back contact solar cell capable of increasing the size of a light receiving area by forming both an electron electrode and a hole electrode on a back surface of the substrate, i.e., the surface of the substrate on which light is not incident, has been recently developed. Hence, the efficiency of the interdigitated back contact solar cell is improved.
- a solar cell including a semiconductor substrate, a first doped region of a first conductive type formed at one surface of the semiconductor substrate, a second doped region formed at the one surface of the semiconductor substrate at a location adjacent to the first doped region, the second doped region being a second conductive type opposite the first conductive type, a back passivation layer on the semiconductor substrate, the back passivation layer having contact holes exposing a portion of each of the first doped region and the second doped region, a first electrode formed on the first doped region exposed through the contact holes of the back passivation layer, a second electrode formed on the second doped region exposed through the contact hole of the back passivation layer, an alignment mark formed at the one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed.
- a surface of the semiconductor substrate at a formation region of the alignment mark has an etched surface that is different from the textured surface in at least one of structure and property.
- the textured surface has an anisotropically etched surface.
- the surface of the semiconductor substrate at the formation region of the alignment mark has a non-uniformly or isotropically etched surface. Because a first doped layer is formed on the semiconductor substrate of an area to form the alignment mark, and the alignment mark is formed while removing the first doped layer.
- a front surface field region into which impurities of the second conductive type are doped may be formed on the textured surface.
- An anti-reflection layer may be formed on the front surface field region.
- a method for manufacturing a solar cell including forming a first doped region of a first conductive type and an alignment mark in a semiconductor substrate, forming a second doped region in a region of the semiconductor substrate different from a formation region of the first doped region of the semiconductor substrate, forming a back passivation layer on the semiconductor substrate, the back passivation layer having contact holes exposing a portion of each of the first doped region and the second doped region, and forming a first electrode and a second electrode electrically connected to the first doped region and the second doped region through the contact holes, respectively.
- the forming of the first doped region and the alignment mark may include forming a first doped layer of the first conductive type in the semiconductor substrate, forming an insulating layer on the first doped layer, forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer, selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask, removing the first mask, and removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask.
- a surface of the semiconductor substrate in the alignment mark formation area is non-uniformly or isotropically etched and a light receiving surface of the semiconductor substrate is isotropically etched to form a textured surface.
- the forming of the second doped region may include doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask and removing the second mask.
- the doping of the impurities of the second conductive type may include doping the impurities of the second conductive type into the textured surface to form a front surface field region.
- the forming of the back passivation layer may include forming the back passivation layer on the first and second doped regions and the alignment mark, performing an alignment operation using the alignment mark, and forming the contact holes exposing the portion of each of the first doped region and the second doped region.
- an anti-reflection layer may be formed on the front surface field region.
- a method for manufacturing a solar cell including forming a first doped layer of a first conductive type in a semiconductor substrate, forming an insulating layer on the first doped layer, forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer, selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask and then removing the first mask, removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask and forming a textured surface at a light receiving surface of the semiconductor substrate, doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask, and into the textured surface, and then removing the second mask, forming a back passivation layer on the first and second doped regions and the alignment mark, forming an anti-reflection layer on a front surface field region, the front surface field region being
- a surface of the semiconductor substrate in a formation area of the alignment mark may have an etched surface that is different from the textured surface in at least one of structure and property.
- the textured surface has an anisotropically etched surface
- the surface of the semiconductor substrate at the formation area of the alignment mark has a non-uniformly or isotropically etched surface.
- the alignment mark is formed without a separate process unlike the related art.
- the number of processes for forming the solar cells according to the example embodiment of the invention may be reduced compared with the related art.
- FIG. 1 is a partial cross-sectional view of a solar cell according to an example embodiment of the invention.
- FIGS. 2A to 2J sequentially illustrate processes in a method for manufacturing a solar cell according to an example embodiment of the invention.
- FIG. 1 is a partial cross-sectional view of a solar cell according to an example embodiment of the invention.
- a solar cell includes a semiconductor substrate 100 of a first conductive type, a front surface field region 110 formed in a front surface (for example, a light receiving surface) of the semiconductor substrate 100 , an anti-reflection layer 120 formed on the front surface field region 110 , a first doped region 131 that is formed in a back surface of the semiconductor substrate 100 and is heavily doped with impurities of the first conductive type, a second doped region 132 that is formed in the back surface of the semiconductor substrate 100 at a location adjacent to the first doped region 131 and is heavily doped with impurities of a second conductive type opposite the first conductive type, a back passivation layer 140 having a contact hole 141 (refer to FIG.
- the solar cell according to the example embodiment of the invention further includes at least two alignment marks 160 formed in the back surface of the semiconductor substrate 100 .
- the light receiving surface of the semiconductor substrate 100 is textured to form a textured surface 101 corresponding to an uneven surface having a plurality of uneven portions.
- each of the front surface field region 110 and the anti-reflection layer 120 has a textured surface.
- the semiconductor substrate 100 is formed of single crystal silicon of the first conductive type (for example, n-type), though not required.
- the semiconductor substrate 100 may be of a p-type and may be formed of polycrystalline silicon.
- the semiconductor substrate 100 may be formed of other semiconductor materials other than silicon.
- the efficiency of the solar cell is improved.
- the front surface field region 110 formed at the textured surface 101 of the semiconductor substrate 100 is a region that is more heavily doped with impurities of a group V element such as phosphorus (P), arsenic (As), and antimony (Sb) than the semiconductor substrate 100 .
- a group V element such as phosphorus (P), arsenic (As), and antimony (Sb) than the semiconductor substrate 100 .
- the front surface field region 110 prevents or reduces electrons and holes separated by light incident on the light receiving surface of the semiconductor substrate 100 from being recombined and/or from disappearing at the light receiving surface of the semiconductor substrate 100 .
- the anti-reflection layer 120 on the surface of the front surface field region 110 is formed of silicon nitride (SiNx), silicon dioxide (SiO 2 ), or titanium dioxide (TiO 2 ).
- the anti-reflection layer 120 reduces a reflectance of incident light and increases a selectivity of a predetermined wavelength band, thereby increasing the efficiency of the solar cell.
- the first doped region 131 is a p-type heavily doped region
- the second doped region 132 is a region that is more heavily doped with n-type impurities than the semiconductor substrate 100 .
- the p-type first doped region 131 and the n-type semiconductor substrate 100 form a p-n junction.
- the first doped region 131 and the second doped region 132 serve as a moving path of carriers (electrons and holes).
- the first doped region 131 and the second doped region 132 may be formed so as not to be coplanar.
- the back passivation layer 140 having the contact hole 141 (refer to FIG. 2J ) exposing the portion of each of the first doped region 131 and the second doped region 132 is formed of silicon nitride (SiNx), silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), or a combination thereof.
- the back passivation layer 140 prevents or reduces a recombination and/or a disappearance of electrons and holes separated from carriers and reflects incident light to the inside of the solar cell so that the incident light is not reflected to the outside of the solar cell. Namely, the back passivation layer 140 prevents a loss of the incident light and reduces a loss amount of the incident light.
- the back passivation layer 140 may have a single-layered structure or a multi-layered structure such as a double-layered structure or a triple-layered structure.
- the back passivation layer 140 may have a step so that a portion (first portion) of the back passivation layer 140 is formed on the first doped region 131 and a portion (second portion) of the back passivation layer 140 is formed on the second doped region 132 . Accordingly, the first and second portions of the back passivation layer 140 may be formed so as not to be coplanar.
- the first electrode 151 is formed on the exposed portion of the first doped region 131 exposed by the contact hole 141 and on a portion of the back passivation layer 140 adjacent to the exposed portion of the first doped region 131 .
- the second electrode 152 is formed on the exposed portion of the second doped region 132 exposed by the contact hole 141 and on a portion of the back passivation layer 140 adjacent to the exposed portion of the second doped region 132 .
- the first electrode 151 is electrically connected to the first doped region 131
- the second electrode 152 is electrically connected to the second doped region 132 .
- the first and second electrodes 151 and 152 are spaced apart from each other at a constant distance and extend parallel to each other in one direction.
- the first and second electrodes 151 and 152 may be formed so as not to be coplanar.
- each of the first and second electrodes 151 and 152 overlaps a portion of the back passivation layer 140 and is connected to a bus bar area, a contact resistance and a series resistance generated when the first and second electrodes 151 and 152 contact an external driving circuit, etc., are reduced. Hence, the efficiency of the solar cell may be improved.
- An alignment mark 160 used to align the contact hole 141 and the first and second electrodes 151 and 152 is formed on the back surface of the semiconductor substrate 100 on which the first and second doped regions 131 and 132 are formed.
- the alignment mark 160 is formed by etching the semiconductor substrate 100 . It is preferable, but not required, that at least two alignment marks are used so as to accurately perform an alignment operation. Various shapes and various formation locations may be used for the alignment mark 160 .
- FIGS. 2A to 2J sequentially illustrate processes in a method for manufacturing a solar cell according to an example embodiment of the invention.
- the back surface of the semiconductor substrate 100 is doped with p-type impurities (for example, boron (B), gallium (Ga), indium (In), etc.) to form a first doped layer 131 a.
- p-type impurities for example, boron (B), gallium (Ga), indium (In), etc.
- a BSG layer (not shown) is formed on the surface of the first doped layer 131 a.
- a saw damage removal process and a cleansing process may be performed on the semiconductor substrate 100 to improve a surface state of the semiconductor substrate 100 . Since the saw damage removal process and the cleansing process are well known to those skilled in the art, descriptions thereof are omitted.
- an oxide layer such as a silicon dioxide (SiO 2 ) layer is grown at a high temperature to form an insulating layer 171 .
- the process for forming the insulating layer 171 may be performed at about 1,000° C.
- the insulating layer 171 may be formed using silicon nitride (SiNx).
- the insulating layer 171 may be formed using an organic insulating material as well as an inorganic insulating material such as silicon nitride (SiNx) and silicon dioxide (SiO 2 ).
- the insulating layer 171 may be formed using a chemical vapor deposition (CVD) method such as a plasma enhanced CVD (PECVD) method.
- CVD chemical vapor deposition
- PECVD plasma enhanced CVD
- a first mask 180 defining a second doped region formation area A 1 and an alignment mark formation area A 2 is formed on the insulating layer 171 .
- the formation of the first mask 180 defining the second doped region formation area A 1 and the alignment mark formation area A 2 indicates that the second doped region formation area A 1 and the alignment mark formation area A 2 are opened so that the first doped layer 131 a formed in both the second doped region formation area A 1 and the alignment mark formation area A 2 can be removed in a subsequent etching process.
- the first mask 180 having the above-described structure may be firmed by applying and curing a photosensitive layer on the insulating layer 171 and then patterning the photosensitive layer using a photolithographic process.
- an etching process is performed using the first mask 180 to selectively remove the insulating layer 171 .
- the BSG layer (not shown) formed on the surface of the first doped layer 131 a is removed.
- a hydrofluoric acid-based etchant may be used to remove the insulating layer 171 .
- a second mask 170 having the same pattern as the first mask 180 is formed by selectively removing the insulating layer 171 .
- the first mask 180 is removed.
- an etching process is performed using the second mask 170 .
- the etching process using the second mask 170 removes the first doped layer 131 a formed in the second doped region formation area A 1 and the alignment mark formation area A 2 , and at the same time, textures the light receiving surface of the semiconductor substrate 100 to form the textured surface 101 .
- a texturing process is generally performed by immersing the semiconductor substrate 100 in a bath filled with an alkali solution for a predetermined time.
- the texturing process may be performed by immersing the semiconductor substrate 100 in the alkali solution of about 80° C. for about 20 to 40 minutes. As the texturing process is performed, a portion protected by the second mask 170 is not etched, and a portion (for example, the second doped region formation area A 1 , the alignment mark formation area A 2 , and the light receiving surface of the semiconductor substrate 100 ) not protected by the second mask 170 is etched.
- alkali solution examples include KOH solution of about 2 wt % to 5 wt % and NaOH solution of about 2 wt % to 5 wt %.
- the textured surface is formed on the surface of the semiconductor substrate 100 through the texturing process.
- the first doped layer 131 a is formed on the semiconductor substrate 100 in the second doped region formation area A 1 and the alignment mark formation area A 2 .
- the light receiving surface of the semiconductor substrate 100 is not a region doped with impurities, the light receiving surface of the semiconductor substrate 100 is anisotropically etched at a very high etch rate during the texturing process.
- the textured surface 101 having an anisotropic structure having a uniform shape, for example, a pyramid shape is formed on the light receiving surface of the semiconductor substrate 100 .
- the anisotropic structure may have unequal property along different axes thereof
- the alignment mark formation area A 2 is the p-type doped region, the alignment mark formation area A 2 is etched at an etch rate slower than the textured surface 101 without a specific orientation.
- the surface of the semiconductor substrate 100 in the alignment mark formation area A 2 has an isotropic structure or a non-uniform structure unlike the textured surface 101 .
- the isotropic structure may have equal property along all axes thereof
- the first doped region 131 and the alignment mark 160 are formed on the semiconductor substrate 100 .
- the alignment mark 160 is formed by the etching of the first doped layer 131 a of the semiconductor substrate 100 in addition to a height difference of the surface of the semiconductor substrate 100 generated by the removal of the BSG layer.
- the alignment mark 160 is formed without a separate process unlike the related art. Hence, the number of processes for forming the solar cells according to the example embodiment of the invention may be reduced compared with the related art.
- a portion not protected by the second mask 170 i.e., the semiconductor substrate 100 in the second doped region formation area A 1 and the alignment mark formation area A 2 and the textured surface 101 are doped with impurities of the second conductive type, i.e., n-type impurities (for example, a group V element such as phosphorus (P), arsenic (As), and antimony (Sb)).
- impurities of the second conductive type i.e., n-type impurities (for example, a group V element such as phosphorus (P), arsenic (As), and antimony (Sb)).
- the front surface field region 110 is formed in the textured surface 101 .
- the front surface field region 110 performs an operation similar to a back surface field region and thus prevents or reduces electrons and holes separated by incident light from being recombined and/or disappeared on the light receiving surface of the semiconductor substrate 100 .
- the second mask 170 is removed, and the back passivation layer 140 is formed on the entire back surface of the semiconductor substrate 100 .
- the back passivation layer 140 may be formed by growing an oxide layer such as a silicon dioxide (SiO 2 ) layer at a high temperature.
- an oxide layer such as a silicon dioxide (SiO 2 ) layer
- SiO 2 silicon dioxide
- a silicon dioxide (SiO 2 ) layer may be additionally deposited using the CVD method such as the PECVD method.
- the back passivation layer 140 may be formed using silicon nitride (SiNx).
- the back passivation layer 140 may be formed using an organic insulating material as well as an inorganic insulating material such as silicon nitride (SiNx) and silicon dioxide (SiO 2 ).
- the back passivation layer 140 is formed along the height difference of the surface of the semiconductor substrate 100 .
- the alignment mark 160 may be continuously confirmed.
- the anti-reflection layer 120 is formed on the front surface of the front surface field region 110 .
- the anti-reflection layer 120 may be generally formed of silicon nitride (SiNx), silicon dioxide (SiO 2 ) layer, or titanium dioxide (TiO 2 ), or a combination thereof using the CVD method such as the PECVD method or a sputtering method.
- the anti-reflection layer 120 may have two layers each having different physical properties. In this case, a lower layer of the two layers may be formed of a material having a high refractive index of about 2.2 to 2.6, and an upper layer may be formed of a material having a low refractive index of about 1.3 to 1.6.
- the contact hole 141 is formed in the back passivation layer 140 .
- a process for forming the contact hole 141 is performed after performing the alignment operation using the alignment mark 160 .
- the process for forming the contact hole 141 may be performed using an etching paste.
- the etching paste is formed on the back passivation layer 140 in a region exposing the first and second doped regions 131 and 132 .
- the etching paste may include an etchant such as phosphoric acid and hydrofluoric acid. In this case, it is preferable, though not required, that the process for forming the etching paste is performed after performing the alignment operation using the alignment mark 160 .
- a thermal process is performed at a proper temperature and time to selectively etch the portion of the back passivation layer 140 where the etching paste is formed. Hence, the contact hole 141 exposing the portion of each of the first and second doped regions 131 and 132 is formed.
- the remaining etching paste is removed using water.
- the remaining etching paste may be additionally removed using ultrasonic waves.
- the process for forming the contact hole 141 may be performed using an etch resist.
- the first and second electrodes 151 and 152 are formed as shown in FIG. 1 . Hence, the solar cell shown in FIG. 1 is completed.
- Each of the first and second electrodes 151 and 152 may be formed of a multi-layered conductive material and may be formed after performing the alignment operation using the alignment mark 160 .
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Abstract
A solar cell and a method for manufacturing the same are discussed. The solar cell includes a semiconductor substrate, a first doped region of a first conductive type, a second doped region of a second conductive type opposite the first conductive type, a back passivation layer having contact holes exposing a portion of each of the first and second doped regions, a first electrode formed on the first doped region exposed through the contact holes, a second electrode formed on the second doped region exposed through the contact holes, an alignment mark formed at one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed.
Description
- This application is a Divisional of copending application Ser. No. 12/878,555, filed on Sep. 9, 2010, which claims priority under under 35 U.S.C. §119(a) to Application No. 10-2009-0085211, filed in Korea on Sep. 10, 2009, all of which are hereby expressly incorporated by reference into the present application.
- 1. Field of the Invention
- Example embodiments of the invention relate to a solar cell and a method for manufacturing the same.
- 2. Description of the Related Art
- Recently, as existing energy sources such as petroleum and coal are expected to be depleted, interests in renewable energy for replacing the existing energy sources are increasing. As the renewable energy, solar cells for generating electric energy from solar energy have been particularly spotlighted.
- A solar cell generally includes a substrate and an emitter layer, which are formed of semiconductors of different conductive types, such as a p-type and an n-type, and electrodes respectively connected to the substrate and the emitter layer. A p-n junction is formed at an interface between the substrate and the emitter layer.
- When light is incident on the solar cell having the above-described structure, electrons inside the semiconductors become free electrons (hereinafter referred to as “electrons”) by the photoelectric effect. Further, electrons and holes respectively move to the n-type semiconductor (e.g., the emitter layer) and the p-type semiconductor (e.g., the substrate) based on the principle of the p-n junction. The electrons moving to the emitter layer and the holes moving to the substrate are respectively collected by the electrode connected to the emitter layer and the electrode connected to the substrate.
- An interdigitated back contact solar cell capable of increasing the size of a light receiving area by forming both an electron electrode and a hole electrode on a back surface of the substrate, i.e., the surface of the substrate on which light is not incident, has been recently developed. Hence, the efficiency of the interdigitated back contact solar cell is improved.
- However, as described above, in the interdigitated back contact solar cell, because the p-n junction and each of the electron electrode and the hole electrode have to be formed on the back surface of the substrate, a patterning process is necessary to separately dope p-type impurities and n-type impurities. Thus, an alignment process for aligning each layer is required to manufacture the interdigitated back contact solar cell. As a result, an alignment mark used to align each layer is positioned on the back surface of the substrate.
- In one aspect, there is a solar cell including a semiconductor substrate, a first doped region of a first conductive type formed at one surface of the semiconductor substrate, a second doped region formed at the one surface of the semiconductor substrate at a location adjacent to the first doped region, the second doped region being a second conductive type opposite the first conductive type, a back passivation layer on the semiconductor substrate, the back passivation layer having contact holes exposing a portion of each of the first doped region and the second doped region, a first electrode formed on the first doped region exposed through the contact holes of the back passivation layer, a second electrode formed on the second doped region exposed through the contact hole of the back passivation layer, an alignment mark formed at the one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed.
- A surface of the semiconductor substrate at a formation region of the alignment mark has an etched surface that is different from the textured surface in at least one of structure and property. For example, the textured surface has an anisotropically etched surface. However, the surface of the semiconductor substrate at the formation region of the alignment mark has a non-uniformly or isotropically etched surface. Because a first doped layer is formed on the semiconductor substrate of an area to form the alignment mark, and the alignment mark is formed while removing the first doped layer.
- A front surface field region into which impurities of the second conductive type are doped may be formed on the textured surface. An anti-reflection layer may be formed on the front surface field region.
- In another aspect, there is a method for manufacturing a solar cell including forming a first doped region of a first conductive type and an alignment mark in a semiconductor substrate, forming a second doped region in a region of the semiconductor substrate different from a formation region of the first doped region of the semiconductor substrate, forming a back passivation layer on the semiconductor substrate, the back passivation layer having contact holes exposing a portion of each of the first doped region and the second doped region, and forming a first electrode and a second electrode electrically connected to the first doped region and the second doped region through the contact holes, respectively.
- The forming of the first doped region and the alignment mark may include forming a first doped layer of the first conductive type in the semiconductor substrate, forming an insulating layer on the first doped layer, forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer, selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask, removing the first mask, and removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask.
- As described above, when the first doped layer in the alignment mark formation area is removed, a surface of the semiconductor substrate in the alignment mark formation area is non-uniformly or isotropically etched and a light receiving surface of the semiconductor substrate is isotropically etched to form a textured surface.
- The forming of the second doped region may include doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask and removing the second mask.
- The doping of the impurities of the second conductive type may include doping the impurities of the second conductive type into the textured surface to form a front surface field region.
- The forming of the back passivation layer may include forming the back passivation layer on the first and second doped regions and the alignment mark, performing an alignment operation using the alignment mark, and forming the contact holes exposing the portion of each of the first doped region and the second doped region.
- Before the contact holes are formed, an anti-reflection layer may be formed on the front surface field region.
- In another aspect, there is a method for manufacturing a solar cell including forming a first doped layer of a first conductive type in a semiconductor substrate, forming an insulating layer on the first doped layer, forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer, selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask and then removing the first mask, removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask and forming a textured surface at a light receiving surface of the semiconductor substrate, doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask, and into the textured surface, and then removing the second mask, forming a back passivation layer on the first and second doped regions and the alignment mark, forming an anti-reflection layer on a front surface field region, the front surface field region being one that is formed by the doping of the impurities of the second conductive type into the textured surface, forming contact holes exposing a portion of each of the first doped region and the second doped region using the alignment mark, and forming a first electrode and a second electrode electrically connected to the first doped region and the second doped region through the contact holes, respectively.
- In the removing of the first doped layer, a surface of the semiconductor substrate in a formation area of the alignment mark may have an etched surface that is different from the textured surface in at least one of structure and property. For example, the textured surface has an anisotropically etched surface, and the surface of the semiconductor substrate at the formation area of the alignment mark has a non-uniformly or isotropically etched surface.
- According to the above-described characteristics, because a process for forming the alignment mark is performed simultaneously with a process for forming the textured surface and a process for removing the first doped layer in a second doped region formation area, the alignment mark is formed without a separate process unlike the related art. Hence, the number of processes for forming the solar cells according to the example embodiment of the invention may be reduced compared with the related art.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
-
FIG. 1 is a partial cross-sectional view of a solar cell according to an example embodiment of the invention; and -
FIGS. 2A to 2J sequentially illustrate processes in a method for manufacturing a solar cell according to an example embodiment of the invention. - The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventions are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
- In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “entirely” on another element, it may be on the entire surface of the other element and may not be on a portion of an edge of the other element.
- Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings.
-
FIG. 1 is a partial cross-sectional view of a solar cell according to an example embodiment of the invention. - As shown in
FIG. 1 , a solar cell according to an example embodiment of the invention includes asemiconductor substrate 100 of a first conductive type, a frontsurface field region 110 formed in a front surface (for example, a light receiving surface) of thesemiconductor substrate 100, ananti-reflection layer 120 formed on the frontsurface field region 110, a firstdoped region 131 that is formed in a back surface of thesemiconductor substrate 100 and is heavily doped with impurities of the first conductive type, a seconddoped region 132 that is formed in the back surface of thesemiconductor substrate 100 at a location adjacent to the firstdoped region 131 and is heavily doped with impurities of a second conductive type opposite the first conductive type, aback passivation layer 140 having a contact hole 141 (refer toFIG. 2J ) exposing a portion of each of the firstdoped region 131 and the seconddoped region 132, an electron electrode 151 (hereinafter referred to as “a first electrode”) electrically connected to the firstdoped region 131 exposed through the contact hole of theback passivation layer 140, and a hole electrode 152 (hereinafter referred to as “a second electrode”) electrically connected to the second dopedregion 132 exposed through thecontact hole 141 of theback passivation layer 140. Further, the solar cell according to the example embodiment of the invention further includes at least twoalignment marks 160 formed in the back surface of thesemiconductor substrate 100. - The light receiving surface of the
semiconductor substrate 100 is textured to form atextured surface 101 corresponding to an uneven surface having a plurality of uneven portions. Thus, each of the frontsurface field region 110 and theanti-reflection layer 120 has a textured surface. - The
semiconductor substrate 100 is formed of single crystal silicon of the first conductive type (for example, n-type), though not required. Alternatively, thesemiconductor substrate 100 may be of a p-type and may be formed of polycrystalline silicon. Further, thesemiconductor substrate 100 may be formed of other semiconductor materials other than silicon. - Because the light receiving surface of the
semiconductor substrate 100 is thetextured surface 101, an absorptance of light increases. Hence, the efficiency of the solar cell is improved. - The front
surface field region 110 formed at thetextured surface 101 of thesemiconductor substrate 100, and is a region that is more heavily doped with impurities of a group V element such as phosphorus (P), arsenic (As), and antimony (Sb) than thesemiconductor substrate 100. Thus, the frontsurface field region 110 prevents or reduces electrons and holes separated by light incident on the light receiving surface of thesemiconductor substrate 100 from being recombined and/or from disappearing at the light receiving surface of thesemiconductor substrate 100. - The
anti-reflection layer 120 on the surface of the frontsurface field region 110 is formed of silicon nitride (SiNx), silicon dioxide (SiO2), or titanium dioxide (TiO2). Theanti-reflection layer 120 reduces a reflectance of incident light and increases a selectivity of a predetermined wavelength band, thereby increasing the efficiency of the solar cell. - The first
doped region 131 is a p-type heavily doped region, and the seconddoped region 132 is a region that is more heavily doped with n-type impurities than thesemiconductor substrate 100. Thus, the p-type first dopedregion 131 and the n-type semiconductor substrate 100 form a p-n junction. The firstdoped region 131 and the seconddoped region 132 serve as a moving path of carriers (electrons and holes). The firstdoped region 131 and the seconddoped region 132 may be formed so as not to be coplanar. - The
back passivation layer 140 having the contact hole 141 (refer toFIG. 2J ) exposing the portion of each of the firstdoped region 131 and the seconddoped region 132 is formed of silicon nitride (SiNx), silicon dioxide (SiO2), titanium dioxide (TiO2), or a combination thereof. Theback passivation layer 140 prevents or reduces a recombination and/or a disappearance of electrons and holes separated from carriers and reflects incident light to the inside of the solar cell so that the incident light is not reflected to the outside of the solar cell. Namely, theback passivation layer 140 prevents a loss of the incident light and reduces a loss amount of the incident light. Theback passivation layer 140 may have a single-layered structure or a multi-layered structure such as a double-layered structure or a triple-layered structure. Theback passivation layer 140 may have a step so that a portion (first portion) of theback passivation layer 140 is formed on the firstdoped region 131 and a portion (second portion) of theback passivation layer 140 is formed on the seconddoped region 132. Accordingly, the first and second portions of theback passivation layer 140 may be formed so as not to be coplanar. - The
first electrode 151 is formed on the exposed portion of the firstdoped region 131 exposed by thecontact hole 141 and on a portion of theback passivation layer 140 adjacent to the exposed portion of the firstdoped region 131. Thesecond electrode 152 is formed on the exposed portion of the seconddoped region 132 exposed by thecontact hole 141 and on a portion of theback passivation layer 140 adjacent to the exposed portion of the seconddoped region 132. Thus, thefirst electrode 151 is electrically connected to the firstdoped region 131, and thesecond electrode 152 is electrically connected to the seconddoped region 132. The first andsecond electrodes second electrodes - Because a portion of each of the first and
second electrodes back passivation layer 140 and is connected to a bus bar area, a contact resistance and a series resistance generated when the first andsecond electrodes - An
alignment mark 160 used to align thecontact hole 141 and the first andsecond electrodes semiconductor substrate 100 on which the first and seconddoped regions alignment mark 160 is formed by etching thesemiconductor substrate 100. It is preferable, but not required, that at least two alignment marks are used so as to accurately perform an alignment operation. Various shapes and various formation locations may be used for thealignment mark 160. - Processes in a method for manufacturing the solar cell according to the example embodiment of the invention is described below with reference to
FIGS. 2A to 2J . -
FIGS. 2A to 2J sequentially illustrate processes in a method for manufacturing a solar cell according to an example embodiment of the invention. - As shown in
FIG. 2A , first, the back surface of thesemiconductor substrate 100 is doped with p-type impurities (for example, boron (B), gallium (Ga), indium (In), etc.) to form a first dopedlayer 131 a. When the first dopedlayer 131 a is formed, a BSG layer (not shown) is formed on the surface of the first dopedlayer 131 a. - Before the first doped
layer 131 a is formed at the back surface of thesemiconductor substrate 100, a saw damage removal process and a cleansing process may be performed on thesemiconductor substrate 100 to improve a surface state of thesemiconductor substrate 100. Since the saw damage removal process and the cleansing process are well known to those skilled in the art, descriptions thereof are omitted. - Next, as shown in
FIG. 2B , an oxide layer such as a silicon dioxide (SiO2) layer is grown at a high temperature to form an insulatinglayer 171. The process for forming the insulatinglayer 171 may be performed at about 1,000° C. - The insulating
layer 171 may be formed using silicon nitride (SiNx). The insulatinglayer 171 may be formed using an organic insulating material as well as an inorganic insulating material such as silicon nitride (SiNx) and silicon dioxide (SiO2). The insulatinglayer 171 may be formed using a chemical vapor deposition (CVD) method such as a plasma enhanced CVD (PECVD) method. - Next, as shown in
FIG. 2C , afirst mask 180 defining a second doped region formation area A1 and an alignment mark formation area A2 is formed on the insulatinglayer 171. The formation of thefirst mask 180 defining the second doped region formation area A1 and the alignment mark formation area A2 indicates that the second doped region formation area A1 and the alignment mark formation area A2 are opened so that the first dopedlayer 131 a formed in both the second doped region formation area A1 and the alignment mark formation area A2 can be removed in a subsequent etching process. - The
first mask 180 having the above-described structure may be firmed by applying and curing a photosensitive layer on the insulatinglayer 171 and then patterning the photosensitive layer using a photolithographic process. - Next, as shown in
FIG. 2D , an etching process is performed using thefirst mask 180 to selectively remove the insulatinglayer 171. In this case, the BSG layer (not shown) formed on the surface of the first dopedlayer 131 a is removed. A hydrofluoric acid-based etchant may be used to remove the insulatinglayer 171. Asecond mask 170 having the same pattern as thefirst mask 180 is formed by selectively removing the insulatinglayer 171. - Next, as shown in
FIG. 2E , thefirst mask 180 is removed. Subsequently, as shown inFIG. 2F , an etching process is performed using thesecond mask 170. - The etching process using the
second mask 170 removes the first dopedlayer 131 a formed in the second doped region formation area A1 and the alignment mark formation area A2, and at the same time, textures the light receiving surface of thesemiconductor substrate 100 to form thetextured surface 101. - A texturing process is generally performed by immersing the
semiconductor substrate 100 in a bath filled with an alkali solution for a predetermined time. - For example, the texturing process may be performed by immersing the
semiconductor substrate 100 in the alkali solution of about 80° C. for about 20 to 40 minutes. As the texturing process is performed, a portion protected by thesecond mask 170 is not etched, and a portion (for example, the second doped region formation area A1, the alignment mark formation area A2, and the light receiving surface of the semiconductor substrate 100) not protected by thesecond mask 170 is etched. - Examples of the alkali solution include KOH solution of about 2 wt % to 5 wt % and NaOH solution of about 2 wt % to 5 wt %.
- Because an etch rate of the
semiconductor substrate 100 varies depending on a crystal orientation of thesemiconductor substrate 100, the textured surface is formed on the surface of thesemiconductor substrate 100 through the texturing process. - As described above, the first doped
layer 131 a is formed on thesemiconductor substrate 100 in the second doped region formation area A1 and the alignment mark formation area A2. - Because the light receiving surface of the
semiconductor substrate 100 is not a region doped with impurities, the light receiving surface of thesemiconductor substrate 100 is anisotropically etched at a very high etch rate during the texturing process. Thus, thetextured surface 101 having an anisotropic structure having a uniform shape, for example, a pyramid shape is formed on the light receiving surface of thesemiconductor substrate 100. For example, the anisotropic structure may have unequal property along different axes thereof - However, because the alignment mark formation area A2 is the p-type doped region, the alignment mark formation area A2 is etched at an etch rate slower than the
textured surface 101 without a specific orientation. Thus, the surface of thesemiconductor substrate 100 in the alignment mark formation area A2 has an isotropic structure or a non-uniform structure unlike thetextured surface 101. For example, the isotropic structure may have equal property along all axes thereof - Further, because the first doped
layer 131 a formed on thesemiconductor substrate 100 in the second doped region formation area A1 and the alignment mark formation area A2 is removed during the texturing process, the firstdoped region 131 and thealignment mark 160 are formed on thesemiconductor substrate 100. Thealignment mark 160 is formed by the etching of the first dopedlayer 131 a of thesemiconductor substrate 100 in addition to a height difference of the surface of thesemiconductor substrate 100 generated by the removal of the BSG layer. - In the example embodiment of the invention, because the process for forming the
alignment mark 160 is performed simultaneously with the process for forming thetextured surface 101 and the process for removing the first dopedlayer 131 a in the second doped region formation area A1, thealignment mark 160 is formed without a separate process unlike the related art. Hence, the number of processes for forming the solar cells according to the example embodiment of the invention may be reduced compared with the related art. - Next, as shown in
FIGS. 2G and 2H , a portion not protected by thesecond mask 170, i.e., thesemiconductor substrate 100 in the second doped region formation area A1 and the alignment mark formation area A2 and thetextured surface 101 are doped with impurities of the second conductive type, i.e., n-type impurities (for example, a group V element such as phosphorus (P), arsenic (As), and antimony (Sb)). - When the
textured surface 101 are doped with the impurities of the second conductive type, the frontsurface field region 110 is formed in thetextured surface 101. The frontsurface field region 110 performs an operation similar to a back surface field region and thus prevents or reduces electrons and holes separated by incident light from being recombined and/or disappeared on the light receiving surface of thesemiconductor substrate 100. - Subsequently, the
second mask 170 is removed, and theback passivation layer 140 is formed on the entire back surface of thesemiconductor substrate 100. - More specifically, the
back passivation layer 140 may be formed by growing an oxide layer such as a silicon dioxide (SiO2) layer at a high temperature. When it is difficult to obtain theback passivation layer 140 having a desired thickness through a high temperature growth or a degradation of the characteristics of the solar cell is generated because the oxide layer is grown at the high temperature for a long time, a silicon dioxide (SiO2) layer may be additionally deposited using the CVD method such as the PECVD method. - The
back passivation layer 140 may be formed using silicon nitride (SiNx). Theback passivation layer 140 may be formed using an organic insulating material as well as an inorganic insulating material such as silicon nitride (SiNx) and silicon dioxide (SiO2). - The
back passivation layer 140 is formed along the height difference of the surface of thesemiconductor substrate 100. Thus, thealignment mark 160 may be continuously confirmed. - Next, as shown in
FIG. 21 , theanti-reflection layer 120 is formed on the front surface of the frontsurface field region 110. Theanti-reflection layer 120 may be generally formed of silicon nitride (SiNx), silicon dioxide (SiO2) layer, or titanium dioxide (TiO2), or a combination thereof using the CVD method such as the PECVD method or a sputtering method. Theanti-reflection layer 120 may have two layers each having different physical properties. In this case, a lower layer of the two layers may be formed of a material having a high refractive index of about 2.2 to 2.6, and an upper layer may be formed of a material having a low refractive index of about 1.3 to 1.6. - Next, as shown in
FIG. 2J , thecontact hole 141 is formed in theback passivation layer 140. A process for forming thecontact hole 141 is performed after performing the alignment operation using thealignment mark 160. - The process for forming the
contact hole 141 may be performed using an etching paste. The etching paste is formed on theback passivation layer 140 in a region exposing the first and seconddoped regions alignment mark 160. - After the etching paste is formed, a thermal process is performed at a proper temperature and time to selectively etch the portion of the
back passivation layer 140 where the etching paste is formed. Hence, thecontact hole 141 exposing the portion of each of the first and seconddoped regions - Subsequently, the remaining etching paste is removed using water. When the remaining etching paste is not completely removed, the remaining etching paste may be additionally removed using ultrasonic waves.
- The process for forming the
contact hole 141 may be performed using an etch resist. - After the
contact hole 141 is formed, the first andsecond electrodes FIG. 1 . Hence, the solar cell shown inFIG. 1 is completed. Each of the first andsecond electrodes alignment mark 160. - Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims (11)
1. A method for manufacturing a solar cell, the method comprising:
forming a first doped region of a first conductive type and an alignment mark in a semiconductor substrate;
forming a second doped region in a region of the semiconductor substrate different from a formation region of the first doped region of the semiconductor substrate;
forming a back passivation layer on the semiconductor substrate, the back passivation layer having contact holes exposing a portion of each of the first doped region and the second doped region; and
forming a first electrode and a second electrode electrically connected to the first doped region and the second doped region through the contact holes, respectively.
2. The method of claim 1 , wherein the forming of the first doped region and the alignment mark includes:
forming a first doped layer of the first conductive type in the semiconductor substrate;
forming an insulating layer on the first doped layer;
forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer;
selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask;
removing the first mask; and
removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask.
3. The method of claim 2 , wherein when the first doped layer in the alignment mark formation area is removed, a surface of the semiconductor substrate in the alignment mark formation area is non-uniformly or isotropically etched.
4. The method of claim 2 , wherein when the first doped layer in the alignment mark formation area is removed, a light receiving surface of the semiconductor substrate is isotropically etched to form a textured surface.
5. The method of claim 2 , wherein the forming of the second doped region includes:
doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask; and
removing the second mask.
6. The method of claim 5 , wherein the doping of the impurities of the second conductive type includes doping the impurities of the second conductive type into the textured surface to form a front surface field region.
7. The method of claim 6 , wherein the forming of the back passivation layer includes:
forming the back passivation layer on the first and second doped regions and the alignment mark;
performing an alignment operation using the alignment mark; and
forming the contact holes exposing the portion of each of the first doped region and the second doped region.
8. The method of claim 7 , wherein before the contact holes are formed, an anti-reflection layer is formed on the front surface field region.
9. A method for manufacturing a solar cell, the method comprising:
forming a first doped layer of a first conductive type in a semiconductor substrate;
forming an insulating layer on the first doped layer;
forming a first mask defining a second doped region formation area and an alignment mark formation area on the insulating layer;
selectively removing the insulating layer using the first mask to form a second mask having the same pattern as the first mask and then removing the first mask;
removing the first doped layer in the second doped region formation area and the alignment mark formation area using the second mask and forming a textured surface at a light receiving surface of the semiconductor substrate;
doping impurities of a second conductive type into the semiconductor substrate in the second doped region formation area and the alignment mark formation area exposed by the second mask, and into the textured surface, and then removing the second mask;
forming a back passivation layer on the first and second doped regions and the alignment mark;
forming an anti-reflection layer on a front surface field region, the front surface field region being one that is formed by the doping of the impurities of the second conductive type into the textured surface;
forming contact holes exposing a portion of each of the first doped region and the second doped region using the alignment mark; and
forming a first electrode and a second electrode electrically connected to the first doped region and the second doped region through the contact holes, respectively.
10. The method of claim 9 , wherein, in the removing of the first doped layer, a surface of the semiconductor substrate in a formation area of the alignment mark has an etched surface that is different from the textured surface in at least one of structure and property.
11. The method of claim 10 , wherein the textured surface has an anisotropically etched surface, and the surface of the semiconductor substrate at the formation area of the alignment mark has a non-uniformly or isotropically etched surface.
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US12/878,555 US9236505B2 (en) | 2009-09-10 | 2010-09-09 | Solar cell and method for manufacturing the same |
US14/961,362 US20160087123A1 (en) | 2009-09-10 | 2015-12-07 | Solar cell and method for manufacturing the same |
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EP4073849A4 (en) * | 2019-12-10 | 2023-12-13 | Maxeon Solar Pte. Ltd. | Aligned metallization for solar cells |
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CN102403399B (en) * | 2011-07-30 | 2013-10-30 | 常州天合光能有限公司 | Preparation method and structure of one-film and multipurpose masked texturing solar cell |
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KR101860919B1 (en) | 2011-12-16 | 2018-06-29 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
KR20130096822A (en) * | 2012-02-23 | 2013-09-02 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
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US9236505B2 (en) | 2016-01-12 |
KR101248163B1 (en) | 2013-03-27 |
US20110056551A1 (en) | 2011-03-10 |
EP2296182A3 (en) | 2016-06-08 |
EP2296182A2 (en) | 2011-03-16 |
KR20110027218A (en) | 2011-03-16 |
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