US20160064300A1 - Fan-out wafer level package - Google Patents

Fan-out wafer level package Download PDF

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Publication number
US20160064300A1
US20160064300A1 US14/521,893 US201414521893A US2016064300A1 US 20160064300 A1 US20160064300 A1 US 20160064300A1 US 201414521893 A US201414521893 A US 201414521893A US 2016064300 A1 US2016064300 A1 US 2016064300A1
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Prior art keywords
fan
wafer level
level package
out structure
package according
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Granted
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US14/521,893
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US9269645B1 (en
Inventor
Chu-Fu Lin
Chien-Li Kuo
Kuo-Ming Chen
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Marlin Semiconductor Ltd
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United Microelectronics Corp
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Assigned to MARLIN SEMICONDUCTOR LIMITED reassignment MARLIN SEMICONDUCTOR LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: UNITED MICROELECTRONICS CORPORATION
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Definitions

  • the disclosure relates in general to a fan-out wafer level package, and more particularly to a fan-out wafer level package having excellent heat dissipation effects.
  • FOWLP fan-out wafer level packages
  • the disclosure is directed to a fan-out wafer level package.
  • the conductive heat spreader is formed on the first fan-out structure, which is advantageous to enhancing the overall heat dissipation effects, and hence the overall stability of the fan-out wafer level package is increased.
  • a fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls.
  • the semiconductor element includes a plurality of bonding pads.
  • the molding compound covers the semiconductor element.
  • the first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads.
  • the conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material.
  • the solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.
  • FIG. 1 is a schematic view of a fan-out wafer level package according to an embodiment of the present disclosure
  • FIG. 2 is a partial schematic view of a conductive heat spreader according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view of a fan-out wafer level package according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic view of a fan-out wafer level package according to a further embodiment of the present disclosure.
  • FIG. 5 is a schematic view of a fan-out wafer level package according to a still embodiment of the present disclosure.
  • the conductive heat spreader is formed on the first fan-out structure, which is advantageous to enhancing the overall heat dissipation effects, and hence the overall stability of the fan-out wafer level package is increased.
  • the identical or similar elements of the embodiments are designated with the same reference numerals. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structures of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Ones having ordinary skills in the art may modify or change the structures according to the embodiments of the present disclosure.
  • FIG. 1 is a schematic view of a fan-out wafer level package 10 according to an embodiment of the present disclosure.
  • the fan-out wafer level package 10 includes a semiconductor element 100 , a molding compound 200 , a first fan-out structure 300 , a conductive heat spreader 400 , and a plurality of solder balls 500 .
  • the two semiconductor elements 100 as shown in FIG. 1 may be two identical semiconductor elements or two different semiconductor elements.
  • the terms of “identical” and “different” refer to the functions, the areas, the thickness, or the manufacturing technique generations (e.g. 90 nm, 65 nm, and 28 nm manufacturing technique generations) of the semiconductor elements.
  • the semiconductor element 100 includes a plurality of bonding pads 110 , and the molding compound 200 covers the semiconductor element 100 .
  • the first fan-out structure 300 is formed on the semiconductor element 100 , wherein the first fan-out structure 300 has a plurality of fan-out contacts 310 electrically connected to the bonding pads 110 .
  • the conductive heat spreader 400 is formed on the first fan-out structure 300 , wherein the conductive heat spreader 400 ha a plurality of through holes 400 T filled with a conductive material 410 .
  • the solder balls 500 are formed on the conductive heat spreader 400 , wherein the solder balls 500 are electrically connected to the first fan-out structure 300 via the through holes 400 T filled with the conductive material 410 .
  • the conductive heat spreader 400 formed on the first fan-out structure 300 is advantageous to enhancing the overall heat dissipation effects. As the heat dissipation effects are effectively enhanced, the delamination of multi-layered structures in the fan-out wafer level package resulted from different levels of deformation of the multi-layered structures caused by heat does not occur easily. As such, the overall stability of the fan-out wafer level package is increased.
  • the first fan-out structure 300 has a plurality of electrical contacts for electrically connected to elements outside the first fan-out structure 300 , such as fan-out contacts 310 . These electrical contacts are weak points in the manufacturing process. While the structures of the electrical contacts directly connect external elements, such as the solder balls 500 , failures may occur during the manufacturing process, and hence the process yield of the whole fan-out wafer level package is affected. However, according to the embodiments of the present disclosure, the solder balls 500 are electrically connected to the first fan-out structure 300 via the through holes 400 T filled with the conductive material 410 , such that the circumstance of the first fan-out structure 300 connected to the solder balls 500 via weak points can be prevented, and thus the strength and the stability of the structure is effectively increased.
  • the through holes 400 T are manufactured by such as a laser drilling process, a mechanical drilling process, and/or an etching process, followed by filling the conductive material 410 in the through holes 400 T.
  • the conductive material 410 may be filled in the through holes 400 T by such as an electroplating process, and the conductive material 410 electrically connects the solder balls 500 to the bonding pads 110 .
  • the conductive heat spreader 400 is such as a silicon interposer, and the through holes 400 T filled with the conductive material 410 are such as through silicon vias (TSVs).
  • TSVs through silicon vias
  • FIG. 2 is a partial schematic view of a conductive heat spreader 400 according to an embodiment of the present disclosure.
  • the conductive heat spreader 400 may include a plurality of insulation layers 420 .
  • the insulation layers 420 are formed between the sidewalls 400 s of the through holes 400 T, which are filled with the conductive material 410 , and the conductive material 410 .
  • the insulation layers 420 are such as oxide layers or nitride layers.
  • the conductive heat spreader 400 may include a conductive layer 430 .
  • the conductive layer 430 may include at least one of silicon, copper, or aluminum.
  • the conductive heat spreader 400 may further include two oxide layers 440 .
  • the two oxide layers 400 are formed on two opposite surfaces 430 s of the conductive layer 430 , respectively.
  • the two oxide layers 440 and the insulation layer on the sidewall 400 s may be the same insulating layer formed by the same manufacturing process.
  • the first fan-out structure 300 may further include an organic dielectric layer 320 and a plurality of fan-out wires 330 .
  • the fan-out wires are formed in the organic dielectric layer 320 .
  • the fan-out wires 330 of the first fan-out structure 300 expand outwards, which helps to enlarge the pitch between the solder balls 500 .
  • the enlargement of the pitch can increase the contact space between the whole structure and air, such that the heat dissipation effects can be improved.
  • the first fan-out structure 300 may further include at least one passive component (not shown in drawings).
  • the passive component is formed in the organic dielectric layer 320 .
  • the passive component is such as a capacitor, a resistor, an inductor, and etc.
  • the organic dielectric layer 320 includes an organic dielectric material.
  • the organic dielectric layer 320 may be manufactured by such as a CVD process, a spray coating process, or a molding process.
  • the fan-out wires have a first line width W 1
  • the through holes 400 T filled with the conductive material 410 have a second line width W 2
  • the second line width W 2 is the diameter of a through hole 400 T.
  • the second line width W 2 is such as larger than the first lien width W 1 .
  • the fan-out wires 330 of the first fan-out structure 300 has winding patterns in the organic dielectric layer 320 , as such, the first line width W 1 is relatively thin.
  • the through holes 400 T filled with the conductive material 410 are vertically arranged without any lateral extending structure, as such, the second line width W 2 is relatively thick. Accordingly, the manufacture of the through holes 400 T does not require a very delicate manufacturing process; moreover, the large cross-section (that is, the second line width W 2 ) provides superior heat dissipation effects.
  • the material of the bonding pads is a conductive material, such as including aluminum.
  • the solder balls 500 can form as a ball grid array (BGA).
  • FIG. 3 is a schematic view of a fan-out wafer level package 20 according to another embodiment of the present disclosure.
  • the elements in the present embodiment sharing the same labels with those in the previous embodiment are the same elements, and the description of which is omitted.
  • the fan-out wafer level package 20 may further include a through molding via) 200 T.
  • the through molding via 200 T is formed in the molding compound 200 .
  • the through molding via 200 T is electrically connected to at least one of the solder balls 500 .
  • the through molding via 200 T is filled with a conductive material.
  • the through molding via 200 T is used as the electrical connection between the packages.
  • the two through molding vias 400 T penetrate through the molding compound 200 , the first fan-out structure 300 , and the conductive heat spreader 400 for electrically connecting to two different solder balls 500 , respectively.
  • the semiconductor element 100 may further include an interconnection structure 120 formed on the bonding pads 110 .
  • the interconnection structure 120 is such as in direct contact with the bonding pads 110 , and the bonding pads 110 are located between the interconnection structure 120 and the first fan-out structure 300 .
  • the interconnection structure 120 may has multi-layers of electrical connection lines and dielectric materials, and the dielectric materials separated the electrical connection lines from one another.
  • FIG. 4 is a schematic view of a fan-out wafer level package 30 according to a further embodiment of the present disclosure.
  • the elements in the present embodiment sharing the same labels with those in the previous embodiments are the same elements, and the description of which is omitted.
  • the fan-out wafer level package 30 may further include a second fan-out structure 2300 .
  • the second fan-out structure 2300 is formed on the conductive heat spreader 400 , and the first fan-out structure 300 is electrically connected to the second fan-out structure 2300 .
  • the second fan-out structure 2300 is electrically connected to the solder balls 500 .
  • the pitch between the solder balls 500 may be further enlarged by additionally disposing the second fan-out structure 2300 ; as such, the line widths and the distances between lines can be further enlarged laterally, which can further increase the heat dissipation effects of the whole structure.
  • FIG. 5 is a schematic view of a fan-out wafer level package 40 according to a still embodiment of the present disclosure.
  • the elements in the present embodiment sharing the same labels with those in the previous embodiments are the same elements, and the description of which is omitted.
  • the fan-out wafer level package 40 may further include a third fan-our structure 3300 .
  • the third fan-out structure 3300 is formed on the conductive heat spreader 400 .
  • the second fan-out structure 2300 and the third fan-out structure 3300 are formed on two opposite surfaces of the conductive heat spreader 400 , and the third fan-out structure 3300 is electrically connected to the second fan-out structure 2300 .

Abstract

A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Description

  • This application claims the benefit of People's Republic of China Application Serial No. 201410430514.0, filed Aug. 28, 2014, the subject matter of which is incorporated herein by reference.
    • BACKGROUND
  • 1. Technical Field
  • The disclosure relates in general to a fan-out wafer level package, and more particularly to a fan-out wafer level package having excellent heat dissipation effects.
  • 2. Description of the Related Art
  • Recently, fan-out wafer level packages (FOWLP) have been popularly applied in making semiconductor chips due to the high performance and low cost requirements provided therefrom. For example, 28 nm node wafers have utilized FOWLP technology as a solution for mobile products.
  • However, there are still some issues, such as heat dissipation and structural delamination; therefore, there is always a continuing need to provide an improved FOWLP with reliable performances.
    • SUMMARY OF THE INVENTION
  • The disclosure is directed to a fan-out wafer level package. According to the embodiments of the present disclosure, the conductive heat spreader is formed on the first fan-out structure, which is advantageous to enhancing the overall heat dissipation effects, and hence the overall stability of the fan-out wafer level package is increased.
  • According to an embodiment of the present disclosure, a fan-out wafer level package is disclosed. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.
  • The disclosure will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic view of a fan-out wafer level package according to an embodiment of the present disclosure;
  • FIG. 2 is a partial schematic view of a conductive heat spreader according to an embodiment of the present disclosure;
  • FIG. 3 is a schematic view of a fan-out wafer level package according to another embodiment of the present disclosure;
  • FIG. 4 is a schematic view of a fan-out wafer level package according to a further embodiment of the present disclosure; and
  • FIG. 5 is a schematic view of a fan-out wafer level package according to a still embodiment of the present disclosure.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • According to the embodiments of the present disclosure, in the fan-out wafer level package, the conductive heat spreader is formed on the first fan-out structure, which is advantageous to enhancing the overall heat dissipation effects, and hence the overall stability of the fan-out wafer level package is increased. The identical or similar elements of the embodiments are designated with the same reference numerals. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structures of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Ones having ordinary skills in the art may modify or change the structures according to the embodiments of the present disclosure.
  • FIG. 1 is a schematic view of a fan-out wafer level package 10 according to an embodiment of the present disclosure. The fan-out wafer level package 10 includes a semiconductor element 100, a molding compound 200, a first fan-out structure 300, a conductive heat spreader 400, and a plurality of solder balls 500. The two semiconductor elements 100 as shown in FIG. 1 may be two identical semiconductor elements or two different semiconductor elements. The terms of “identical” and “different” refer to the functions, the areas, the thickness, or the manufacturing technique generations (e.g. 90 nm, 65 nm, and 28 nm manufacturing technique generations) of the semiconductor elements. The semiconductor element 100 includes a plurality of bonding pads 110, and the molding compound 200 covers the semiconductor element 100. The first fan-out structure 300 is formed on the semiconductor element 100, wherein the first fan-out structure 300 has a plurality of fan-out contacts 310 electrically connected to the bonding pads 110. The conductive heat spreader 400 is formed on the first fan-out structure 300, wherein the conductive heat spreader 400 ha a plurality of through holes 400T filled with a conductive material 410. The solder balls 500 are formed on the conductive heat spreader 400, wherein the solder balls 500 are electrically connected to the first fan-out structure 300 via the through holes 400T filled with the conductive material 410.
  • According to the embodiments of the present disclosure, the conductive heat spreader 400 formed on the first fan-out structure 300 is advantageous to enhancing the overall heat dissipation effects. As the heat dissipation effects are effectively enhanced, the delamination of multi-layered structures in the fan-out wafer level package resulted from different levels of deformation of the multi-layered structures caused by heat does not occur easily. As such, the overall stability of the fan-out wafer level package is increased.
  • Moreover, the first fan-out structure 300 has a plurality of electrical contacts for electrically connected to elements outside the first fan-out structure 300, such as fan-out contacts 310. These electrical contacts are weak points in the manufacturing process. While the structures of the electrical contacts directly connect external elements, such as the solder balls 500, failures may occur during the manufacturing process, and hence the process yield of the whole fan-out wafer level package is affected. However, according to the embodiments of the present disclosure, the solder balls 500 are electrically connected to the first fan-out structure 300 via the through holes 400T filled with the conductive material 410, such that the circumstance of the first fan-out structure 300 connected to the solder balls 500 via weak points can be prevented, and thus the strength and the stability of the structure is effectively increased.
  • In the embodiments, the through holes 400T are manufactured by such as a laser drilling process, a mechanical drilling process, and/or an etching process, followed by filling the conductive material 410 in the through holes 400T. The conductive material 410 may be filled in the through holes 400T by such as an electroplating process, and the conductive material 410 electrically connects the solder balls 500 to the bonding pads 110.
  • In an embodiment, the conductive heat spreader 400 is such as a silicon interposer, and the through holes 400T filled with the conductive material 410 are such as through silicon vias (TSVs).
  • FIG. 2 is a partial schematic view of a conductive heat spreader 400 according to an embodiment of the present disclosure. As shown in FIG. 2, in the embodiment, the conductive heat spreader 400 may include a plurality of insulation layers 420. The insulation layers 420 are formed between the sidewalls 400 s of the through holes 400T, which are filled with the conductive material 410, and the conductive material 410. In the embodiment, the insulation layers 420 are such as oxide layers or nitride layers.
  • As shown in FIG. 2, in the embodiment, the conductive heat spreader 400 may include a conductive layer 430. The conductive layer 430 may include at least one of silicon, copper, or aluminum.
  • As shown in FIG. 2, in the embodiment, the conductive heat spreader 400 may further include two oxide layers 440. The two oxide layers 400 are formed on two opposite surfaces 430 s of the conductive layer 430, respectively. The two oxide layers 440 and the insulation layer on the sidewall 400 s may be the same insulating layer formed by the same manufacturing process.
  • As shown in FIG. 1, in the embodiment, the first fan-out structure 300 may further include an organic dielectric layer 320 and a plurality of fan-out wires 330. The fan-out wires are formed in the organic dielectric layer 320. The fan-out wires 330 of the first fan-out structure 300 expand outwards, which helps to enlarge the pitch between the solder balls 500. The enlargement of the pitch can increase the contact space between the whole structure and air, such that the heat dissipation effects can be improved.
  • In some embodiments, the first fan-out structure 300 may further include at least one passive component (not shown in drawings). The passive component is formed in the organic dielectric layer 320. In the embodiments, the passive component is such as a capacitor, a resistor, an inductor, and etc.
  • In the embodiments, the organic dielectric layer 320 includes an organic dielectric material. The organic dielectric layer 320 may be manufactured by such as a CVD process, a spray coating process, or a molding process.
  • As shown in FIG. 1, the fan-out wires have a first line width W1, and the through holes 400T filled with the conductive material 410 have a second line width W2. In a case where the through holes 400T are circle-shaped in layout view, the second line width W2 is the diameter of a through hole 400T. In the embodiment, the second line width W2 is such as larger than the first lien width W1. The fan-out wires 330 of the first fan-out structure 300 has winding patterns in the organic dielectric layer 320, as such, the first line width W1 is relatively thin. On the other hand, the through holes 400T filled with the conductive material 410 are vertically arranged without any lateral extending structure, as such, the second line width W2 is relatively thick. Accordingly, the manufacture of the through holes 400T does not require a very delicate manufacturing process; moreover, the large cross-section (that is, the second line width W2) provides superior heat dissipation effects.
  • In some embodiments, the material of the bonding pads is a conductive material, such as including aluminum. In an embodiment, the solder balls 500 can form as a ball grid array (BGA).
  • FIG. 3 is a schematic view of a fan-out wafer level package 20 according to another embodiment of the present disclosure. The elements in the present embodiment sharing the same labels with those in the previous embodiment are the same elements, and the description of which is omitted.
  • As shown in FIG. 3, the fan-out wafer level package 20 may further include a through molding via) 200T. The through molding via 200T is formed in the molding compound 200. The through molding via 200T is electrically connected to at least one of the solder balls 500. In the embodiment, the through molding via 200T is filled with a conductive material. As the fan-out wafer level package 20 is stacked and connected to additional packages, the through molding via 200T is used as the electrical connection between the packages. In the present embodiment, as shown in FIG. 3, the two through molding vias 400T penetrate through the molding compound 200, the first fan-out structure 300, and the conductive heat spreader 400 for electrically connecting to two different solder balls 500, respectively.
  • As shown in FIG. 3, the semiconductor element 100 may further include an interconnection structure 120 formed on the bonding pads 110. As shown in FIG. 3, the interconnection structure 120 is such as in direct contact with the bonding pads 110, and the bonding pads 110 are located between the interconnection structure 120 and the first fan-out structure 300. In the embodiment, the interconnection structure 120 may has multi-layers of electrical connection lines and dielectric materials, and the dielectric materials separated the electrical connection lines from one another.
  • FIG. 4 is a schematic view of a fan-out wafer level package 30 according to a further embodiment of the present disclosure. The elements in the present embodiment sharing the same labels with those in the previous embodiments are the same elements, and the description of which is omitted.
  • As shown in FIG. 4, the fan-out wafer level package 30 may further include a second fan-out structure 2300. The second fan-out structure 2300 is formed on the conductive heat spreader 400, and the first fan-out structure 300 is electrically connected to the second fan-out structure 2300.
  • In the present embodiment, the second fan-out structure 2300 is electrically connected to the solder balls 500. The pitch between the solder balls 500 may be further enlarged by additionally disposing the second fan-out structure 2300; as such, the line widths and the distances between lines can be further enlarged laterally, which can further increase the heat dissipation effects of the whole structure.
  • FIG. 5 is a schematic view of a fan-out wafer level package 40 according to a still embodiment of the present disclosure. The elements in the present embodiment sharing the same labels with those in the previous embodiments are the same elements, and the description of which is omitted.
  • As shown in FIG. 5, the fan-out wafer level package 40 may further include a third fan-our structure 3300. The third fan-out structure 3300 is formed on the conductive heat spreader 400.
  • In the present embodiment, the second fan-out structure 2300 and the third fan-out structure 3300 are formed on two opposite surfaces of the conductive heat spreader 400, and the third fan-out structure 3300 is electrically connected to the second fan-out structure 2300.
  • While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (15)

What is claimed is:
1. A fan-out wafer level package, comprising:
a semiconductor element comprising a plurality of bonding pads;
a molding compound covering the semiconductor element;
a first fan-out structure formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads;
a conductive heat spreader formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material; and
a plurality of solder balls formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.
2. The fan-out wafer level package according to claim 1, wherein the conductive heat spreader comprises a plurality of insulation layers formed between sidewalls of the through holes and the conductive material.
3. The fan-out wafer level package according to claim 1, wherein the conductive heat spreader comprises a conductive layer, wherein the conductive layer comprises at least one of silicon, copper, or aluminum.
4. The fan-out wafer level package according to claim 3, wherein the conductive heat spreader further comprises two oxide layers formed on two opposite surfaces of the conductive layer, respectively.
5. The fan-out wafer level package according to claim 1, wherein the first fan-out structure comprises:
an organic dielectric layer; and
a plurality of fan-out wires formed in the organic dielectric layer.
6. The fan-out wafer level package according to claim 5, wherein the fan-out wires are electrically connected to the fan-out contacts of the first fan-out structure.
7. The fan-out wafer level package according to claim 5, wherein the fan-out wires have a first line width, the through holes filled with the conductive material have a second line width larger than the first line width.
8. The fan-out wafer level package according to claim 5, wherein the first fan-out structure further comprises:
at least a passive component formed in the organic dielectric layer.
9. The fan-out wafer level package according to claim 1, further comprising:
a second fan-out structure formed on the conductive heat spreader, wherein the first fan-out structure is electrically connected to the second fan-out structure.
10. The fan-out wafer level package according to claim 9, wherein the second fan-out structure is electrically connected to the solder balls.
11. The fan-out wafer level package according to claim 9, further comprising:
a third fan-out structure formed on the conductive heat spreader, wherein the second fan-out structure and the third fan-out structure are formed on two opposite surfaces of the conductive heat spreader, respectively, and the third fan-out structure is electrically connected to the second fan-out structure.
12. The fan-out wafer level package according to claim 1, wherein the bonding pads comprise aluminum.
13. The fan-out wafer level package according to claim 1, wherein the solder balls are formed as a ball grid array (BGA).
14. The fan-out wafer level package according to claim 1, further comprising:
at least a through molding via formed in the molding compound, wherein the through molding via is electrically connected to at least one of the solder balls.
15. The fan-out wafer level package according to claim 1, wherein the semiconductor element further comprises a dielectric structure formed on the bonding pads.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431563B1 (en) * 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10515929B2 (en) 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6469897B2 (en) * 2001-01-30 2002-10-22 Siliconware Precision Industries Co., Ltd. Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same
TW586208B (en) * 2002-02-26 2004-05-01 Advanced Semiconductor Eng Wafer-level packaging structure
CN2662455Y (en) * 2003-08-25 2004-12-08 威盛电子股份有限公司 Electric packaging body
JP4012496B2 (en) * 2003-09-19 2007-11-21 カシオ計算機株式会社 Semiconductor device
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
US20080203557A1 (en) * 2007-01-30 2008-08-28 Sanyo Electric Co., Ltd. Semiconductor module and method of manufacturing the same
US8310051B2 (en) * 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US8119454B2 (en) * 2008-12-08 2012-02-21 Stmicroelectronics Asia Pacific Pte Ltd. Manufacturing fan-out wafer level packaging
JP2010263080A (en) * 2009-05-07 2010-11-18 Denso Corp Semiconductor device
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
JP5636265B2 (en) * 2010-11-15 2014-12-03 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
JP2012134270A (en) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method of the same
US8890304B2 (en) 2011-06-08 2014-11-18 Tessera, Inc. Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material
US8664044B2 (en) * 2011-11-02 2014-03-04 Stmicroelectronics Pte Ltd. Method of fabricating land grid array semiconductor package
JP6142800B2 (en) * 2012-02-09 2017-06-07 パナソニック株式会社 Semiconductor device and manufacturing method thereof
US9502363B2 (en) * 2014-03-24 2016-11-22 Freescale Semiconductor, Inc. Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431563B1 (en) * 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10515929B2 (en) 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US10840214B2 (en) 2018-04-09 2020-11-17 International Business Machines Corporation Carrier and integrated memory
US10892249B2 (en) 2018-04-09 2021-01-12 International Business Machines Corporation Carrier and integrated memory

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