US20160056817A1 - Power transistor with distributed diodes - Google Patents

Power transistor with distributed diodes Download PDF

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US20160056817A1
US20160056817A1 US14/831,758 US201514831758A US2016056817A1 US 20160056817 A1 US20160056817 A1 US 20160056817A1 US 201514831758 A US201514831758 A US 201514831758A US 2016056817 A1 US2016056817 A1 US 2016056817A1
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conductor
sub
transistors
distributed
transistor
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Daniel M. Kinzer
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Navitas Semiconductor Ltd
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Navitas Semiconductor Inc
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Publication of US20160056817A1 publication Critical patent/US20160056817A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to transistors and in particular to power transistors formed in GaN-based technologies.
  • Electronic devices such as computers, servers and televisions, among others, employ one or more electrical power conversion circuits to convert one form of electrical energy to another.
  • the efficiency of this conversion is critical to avoid wasted energy and reduce waste heat generation.
  • An example of a circuit topology that requires high frequency switching is a half bridge converter. New components with higher speed and efficiency are needed for converter circuits to meet the needs of new electronic devices.
  • power transistors that can switch extremely fast are needed to enable frequency to increase without loss of efficiency. High frequency switching will reduce the size and cost of power electronic systems.
  • conventional devices rely on drivers that are external to chip, and usually also to the package that houses the power transistor.
  • GaN technology enables power transistors to be designed that are much smaller than conventional silicon devices, and capacitance can be reduced by 10-20 times. Because of this, GaN devices switch extremely fast, which can be hard to control with conventional gate drive circuits. It is essential to reduce the impedance between the driver and the power transistor as low as possible to enable good control of the switching operation.
  • the electronic circuit includes a substrate including GaN, and a distributed power switch formed on the substrate, where the distributed power switch includes a plurality of power sub-transistors, and where each power sub-transistor includes a gate, a source, and a drain.
  • the electronic circuit also includes a distributed diode formed on the substrate.
  • the distributed diode includes a plurality of sub-diodes, where each sub-diode includes an anode, and a cathode.
  • the anodes of the sub-diodes are each connected to a source of one or more corresponding power sub-transistors, and the cathodes of the sub-diodes are each connected to a drain of one or more corresponding power sub-transistors.
  • the electronic circuit includes a substrate including GaN, and a distributed power switch formed on the substrate, where the distributed power switch includes a plurality of power sub-transistors, and where each power sub-transistor includes a gate, a source, and a drain.
  • the electronic circuit also includes a distributed diode formed on the substrate.
  • the distributed diode includes a plurality of sub-diodes, where each sub-diode includes an anode, and a cathode.
  • the anodes of the sub-diodes are each connected to a source of one or more corresponding power sub-transistors, and the cathodes of the sub-diodes are each connected to a drain of one or more corresponding power sub-transistors.
  • FIG. 1 is a simplified schematic of a half bridge power conversion circuit.
  • FIG. 2 is a schematic illustration of a distributed transistor.
  • FIGS. 3A and 3B are schematic illustrations of a portion of an embodiment of a layout of a distributed transistor.
  • FIGS. 4A-4D are schematic illustrations of a portion of an embodiment of a layout of a distributed transistor.
  • FIG. 5 is a schematic illustration of a distributed transistor having a distributed driver or driver output stage.
  • FIG. 6 is a schematic illustration of portion of an embodiment of a layout of a distributed transistor and distributed driver or driver output stage.
  • FIG. 7 is a simplified schematic of a half bridge power conversion circuit having been modified to include a low side pulldown FET and a high side pulldown FET.
  • FIG. 8 is a schematic illustration of a circuit having a distributed transistor and a distributed pulldown FET.
  • FIG. 9 a schematic illustration of an embodiment of a layout of the circuit of FIG. 8 .
  • FIG. 10 is a schematic illustration of a circuit having a distributed transistor and pulldown FET, a distributed pulldown FET driver, and a distributed transistor driver.
  • FIG. 11 is a schematic illustration of a circuit, which includes a drive transistor, a pulldown FET, and an inverter.
  • FIG. 12 is a simplified schematic of a half bridge power conversion circuit having been modified to include clamping diodes.
  • FIG. 13 is a schematic illustration of a circuit having a distributed transistor and a distributed diode.
  • FIG. 14 is a schematic illustration of a portion of an embodiment of a layout of the circuit of FIG. 13 .
  • FIG. 15 a schematic illustration of a cross section of the portion illustrated in FIG. 14 .
  • FIG. 16 a schematic illustration of a cross section of the portion illustrated in FIG. 14 .
  • FIG. 17 is a flowchart diagram illustrating an embodiment of a method of forming a distributed transistor integrated with a distributed driver.
  • FIG. 18 is a flowchart diagram illustrating an embodiment of a method of forming first and second distributed transistors.
  • FIG. 19 is a flowchart diagram illustrating an embodiment of a method of forming first and second distributed transistors.
  • FIG. 20 is a flowchart diagram illustrating an embodiment of a method of forming a distributed transistor.
  • Certain embodiments of the present invention are implemented in half bridge power conversion circuits that employ one or more gallium nitride (GaN) devices. While the present invention can be useful for a wide variety of circuits, some embodiments of the invention are particularly useful for half bridge circuits designed to operate at high frequencies and/or high efficiencies with integrated driver circuits, integrated level shift circuits, integrated bootstrap capacitor charging circuits, integrated startup circuits and/or hybrid solutions using GaN and silicon devices.
  • GaN gallium nitride
  • circuit 100 may include a pair of complementary power transistors (also referred to herein as switches) that are controlled by one or more control circuits configured to regulate power delivered to a load.
  • a high side power transistor is disposed on a high side device along with a portion of the control circuit and a low side power transistor is disposed on a low side device along with a portion of the control circuit, as described in more detail below.
  • the integrated half bridge power conversion circuit 100 illustrated in FIG. 1 includes a low side GaN device 103 , a high side GaN device 105 a load 107 , a bootstrap capacitor 110 and other circuit elements, as illustrated and discussed in more detail below. Some embodiments may also have an external controller (not shown in FIG. 1 ) providing one or more inputs to circuit 100 to regulate the operation of the circuit. Circuit 100 is for illustrative purposes only and other variants and configurations are within the scope of this disclosure.
  • low side GaN device 103 may have a GaN-based low side circuit 104 that includes a low side power transistor 115 having a low side control gate 117 .
  • Low side circuit 104 may further include an integrated low side transistor driver 120 having an output 123 connected to low side transistor control gate 117 .
  • side GaN device 105 may have a GaN-based high side circuit 106 that includes a high side power transistor 125 having a high side control gate 127 .
  • High side circuit 106 may further include an integrated high side transistor driver 130 having an output 133 connected to high side transistor control gate 127 .
  • a voltage source 135 (also known as a rail voltage) may be connected to a drain 137 of high side transistor 125 , and the high side transistor may be used to control power input into power conversion circuit 100 .
  • High side transistor 125 may further have a source 140 that is coupled to a drain 143 of low side transistor 115 , forming a switch node 145 .
  • Low side transistor 115 may have a source 147 connected to ground.
  • low side transistor 115 and high side transistor 125 may be GaN-based enhancement-mode field effect transistors.
  • low side transistor 115 and high side transistor 125 may be any other type of device including, but not limited to, GaN-based depletion-mode transistors, GaN-based depletion-mode transistors connected in series with silicon based enhancement-mode field-effect transistors having the gate of the depletion-mode transistor connected to the source of the silicon-based enhancement-mode transistor, silicon carbide based transistors or silicon-based transistors.
  • high side device 105 and low side device 103 may be made from a GaN-based material.
  • the GaN-based material may include a layer of GaN on a layer of silicon.
  • the GaN based material may include, but not limited to, a layer of GaN on a layer of silicon carbide, sapphire or aluminum nitride.
  • the GaN based layer may include, but not limited to, a composite stack of other III nitrides such as aluminum nitride and indium nitride and III nitride alloys such as AlGaN and InGaN.
  • GaN-based low side circuit 104 and GaN-based high side circuit 106 may be disposed on a monolithic GaN-based device. In other embodiments GaN-based low side circuit 104 may be disposed on a first GaN-based device and GaN-based high side circuit 106 may be disposed on a second GaN-based device. In yet further embodiments, GaN-based low side circuit 104 and GaN-based high side circuit 106 may be disposed on more than two GaN-based devices. In one embodiment, GaN-based low side circuit 104 and GaN-based high side circuit 106 may contain any number of active or passive circuit elements arranged in any configuration.
  • half bridge power conversion circuit 100 is formed are on a GaN-based die secured to a package base of an electronic power conversion component.
  • the component includes multiple GaN-based die secured to the package base.
  • integrated half bridge power conversion circuit 100 may include features as described in further detail in U.S. application Ser. No. 14/737,259, filed Jun. 11, 2015, which is incorporated herein in its entirety for all purposes.
  • FIG. 2 is a schematic illustration of a transistor 200 having such a topology.
  • Transistor 200 includes three sub-transistors 202 , 204 , 206 , and 208 . As shown, sub-transistors 202 , 204 , 206 , and 208 have their respective drains, gates, and sources connected respectively to nodes D, G, and S, which respectively correspond with the drain, gate, and source of transistor 200 .
  • FIGS. 3A and 3B are schematic illustrations of a portion 220 of an embodiment of a layout of transistor 200 .
  • the embodiment of FIGS. 3A and 3B is provided as an example only. Numerous alternative layout configurations for transistor 200 are additionally contemplated.
  • Source electrode fingers 242 , 244 , 246 , and 248 each form an ohmic contact with the underlying AlGaN or similar layer 224 on substrate 222 and collectively form the source electrode of transistor 200 .
  • Source electrode fingers 242 , 244 , 246 , and 248 respectively form the source electrodes of sub-transistors 202 , 204 , 206 , and 208 .
  • the source electrode fingers 242 , 244 , 246 , and 248 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, such as those discussed in more detail below, source electrode fingers 242 , 244 , 246 , and 248 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Drain electrode fingers 252 , 254 , 256 , and 258 each form an ohmic contact with the underlying AlGaN or similar layer 224 on substrate 222 and collectively form the drain electrode of transistor 200 .
  • Drain electrode fingers 252 , 254 , 256 , and 258 respectively form the drain electrodes of sub-transistors 202 , 204 , 206 , and 208 .
  • the drain electrode fingers 252 , 254 , 256 , and 258 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, such as those discussed in more detail below, drain electrode fingers 252 , 254 , 256 , and 258 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Gate electrode fingers 232 , 234 , 236 , and 238 are separated from AlGaN or similar layer 224 by respective gate structures. Gate structures corresponding with insulated gates, Schottky gates, PN gates, recessed gates, and other gates may be used. Gate electrode fingers 232 , 234 , 236 , and 238 collectively form the gate electrode of transistor 200 , and respectively form the gates electrodes of sub-transistors 202 , 204 , 206 , and 208 . Gate electrode fingers 232 , 234 , 236 , and 238 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, such as those discussed in more detail below, gate electrode fingers 232 , 234 , 236 , and 238 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Field plate electrode fingers 262 , 264 , 266 , and 268 are separated from AlGaN or similar layer 224 by respective insulation structures, and collectively form a field plate electrode of transistor 200 .
  • Field plate electrode fingers 262 , 264 , 266 , and 268 respectively form field plate electrodes of sub-transistors 202 , 204 , 206 , and 208 .
  • Field plate electrode fingers 262 , 264 , 266 , and 268 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, such as those discussed in more detail below, field plate electrode fingers 262 , 264 , 266 , and 268 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • FIGS. 4A-4D are schematic illustrations of an embodiment of a particular one of the sub-transistors of FIGS. 3A and 3B having additional metallization.
  • the additional metallization forms electrical connections between pins and the source electrode finger 248 , drain electrode finger 258 , gate electrode finger 238 , and field plate electrode finger 268 of the underlying sub-transistor.
  • the additional metallization layers may be particularly advantageous for circuits such as half bridge power conversion circuit 100 .
  • the effective gate and/or source resistance of low side transistor 115 and high side transistor 125 may be reduced by use of additional metal layers connecting the gate and/or source fingers of low side transistor 115 and high side transistor 125 .
  • the reduced gate and/or source resistance results in, for example, faster switching times.
  • FIG. 4A is a cross sectional view of the one particular sub-transistor.
  • a first metal layer overlying and separated from the sub-transistor by one or more insulators, is formed so as to have metal 1 structures 255 , 245 a , and 245 b .
  • Metal 1 structure 255 is electrically connected with drain electrode finger 258 through one or more vias (not shown).
  • Metal 1 structure 245 a is electrically connected with field plate electrode finger 268 through one or more vias (not shown).
  • Metal 1 structure 245 b is electrically connected with source electrode finger 248 through one or more vias (not shown).
  • the first metal layer may, for example, be 0.5-2 microns thick and may comprise aluminum or copper.
  • the first metal layer may comprise other metallic or non-metallic conductive materials.
  • a second metal layer overlying and separated from the first metal layer and the sub-transistor by one or more insulators, is formed so as to have metal 2 structures 257 , 247 , and 237 .
  • Metal 2 structure 257 is electrically connected with metal 1 structure 255 through one or more vias (not shown).
  • Metal 2 structure 247 is electrically connected with metal 1 structures 245 a and 245 b through one or more vias (not shown).
  • Metal 2 structure 237 is electrically connected with gate electrode finger 238 as discussed below with reference to FIGS. 4B-4D .
  • the second metal layer may, for example, be greater than 2 microns thick and may comprise aluminum or copper.
  • the second metal layer may comprise other metallic or non-metallic conductive materials.
  • FIG. 4B is a plan view of source electrode finger 248 , gate electrode finger 238 , field plate electrode finger 268 , and drain electrode finger 258 .
  • source electrode finger 248 is not continuous, and includes multiple segments separated by gaps. Each segment of source electrode finger 248 is electrically connected with metal 1 structure 245 b through one or more vias (not shown).
  • gate electrode finger 238 includes projection portions which extend into the gaps between the segments of source electrode finger 248 .
  • FIG. 4C is a plan view of metal 1 structures 255 , 245 a , and 245 b .
  • metal 1 structure 245 b includes openings 249 , and metal 1 islands 243 within the openings 249 . Openings 249 and metal 1 islands 243 are formed in the metal 1 structure 245 b so as to overlap the projection portions of gate electrode finger 238 which extend into the gaps between the segments of source electrode finger 248 .
  • metal 1 islands 243 are electrically connected with the projection portions of gate electrode finger 238 by one or more vias (not shown).
  • FIG. 4D using plan view of metal 2 structures 257 , 247 , and 237 .
  • Metal 2 structure 237 is formed so as to overlap metal 1 structure 245 b .
  • metal 2 structure 237 is electrically connected with metal 1 islands 243 through one or more vias (not shown).
  • metal 2 structure 257 is electrically connected with drain electrode finger 258 of the sub-transistor through metal 1 structure 255 .
  • metal 2 structure 247 is electrically connected with plate electrode finger 268 and source electrode finger 248 through metal 1 structures 245 a and 245 b .
  • metal 2 structure 237 is electrically connected with gate electrode finger 238 through the metal 1 islands 243 of metal 1 structure 245 b.
  • either or both of power transistors 115 and 125 and their respective driver 120 and 130 may be implemented with a distributed or fingered topology.
  • FIG. 5 is a schematic illustration of a distributed transistor 300 connected with a distributed driver or driver output stage 400 .
  • Distributed driver or driver output stage 400 includes sub-drivers 402 , 404 , 406 , and 408 .
  • Distributed transistor 300 may be similar to distributed transistor 200 of FIG. 2 and includes sub-transistors 302 , 304 , 306 , and 308 .
  • sub-drivers 402 , 404 , 406 , and 408 have inputs connected to the same signal IN
  • the outputs, however, of sub-drivers 402 , 404 , 406 , and 408 are respectively connected with gate inputs of different sub-transistors 302 , 304 , 306 , and 308 . Because sub-drivers 402 , 404 , 406 , and 408 have identical or substantially identical functionality, the outputs generated by sub-drivers 402 , 404 , 406 , and 408 are identical or substantially identical.
  • sub-transistors 302 , 304 , 306 , and 308 have identical or substantially identical sizes.
  • sub-drivers 402 , 404 , 406 , and 408 may likewise have identical or substantially identical sizes.
  • sub-transistors 302 , 304 , 306 , and 308 do not have identical sizes.
  • sub-drivers 402 , 404 , 406 , and 408 may likewise not have identical sizes, but, instead, may have sizes which scale or correspond with the size of sub-transistors 302 , 304 , 306 , and 308 .
  • sub-driver 402 may have a size corresponding with or proportional to the size of sub-transistors 302
  • sub-driver 404 may have a size corresponding with or proportional to the size of sub-transistors 304
  • sub-driver 406 may have a size corresponding or proportional to with the size of sub-transistors 306 .
  • each sub-driver of a distributed driver has an output which is connected to multiple sub-transistors.
  • each sub-driver of a distributed driver may have an output which is electrically connected to 2, 4, 8, or another number of sub-transistors.
  • the sub-transistors of the distributed power switch may be spaced according to a first pitch, and the sub-drivers of the distributed drive circuit are spaced according to a second pitch, and the second pitch is equal to n times the first pitch, wherein n is an integer.
  • embodiments of integrated half bridge power conversion circuit 100 having power transistors and their respective drivers implemented with a distributed topology have superior timing performance. Because of the distributed topology, each segment of the power transistor is turned on or off at substantially the same time. Without the distributed technology, the time at which each particular portion of the power transistor is turned on or off is dependent on the propagation delay and arrival time of the controlling signal at each particular portion.
  • FIG. 6 is a schematic illustration of portion 450 of an embodiment of a layout of transistor 300 and driver or driver output stage 400 .
  • the embodiment of FIG. 6 is provided as an example only. Numerous alternative layout configurations for transistor 300 are additionally contemplated. To details of the layout of driver or driver output stage 400 is not illustrated, as the inventive aspects apply equally to any driver or driver output stage.
  • sub-drivers 402 , 404 , 406 , and 408 are each connected to the input signal IN with a conductor of identical length and impedance.
  • sub-drivers 402 , 404 , 406 , and 408 are respectively connected gate electrodes of sub-transistors 302 , 304 , 306 , and 308 with a conductor of identical length and impedance.
  • FIG. 7 is a simplified schematic of half bridge power conversion circuit 100 having been modified to include low side pulldown FET 122 and high side pulldown FET 132 .
  • parasitic inductances and capacitances result in transient voltages at the gate of low side transistor 115 and at the gate of high side transistor 125 .
  • Low side pulldown FET 122 is configured to be on when low side transistor 115 is off, such that the transient voltages at the gate of low side transistor 115 remain low enough that low side transistor 115 is not turned on as a result of the transient voltages.
  • high side pulldown FET 132 is configured to be on when high side transistor 125 is off, such that the transient voltages at the gate of high side transistor 125 remain low enough that high side transistor 125 is not turned on as a result of the transient voltages.
  • the low side pulldown FET 122 and high side pulldown 132 advantageously help to reduce the voltages at the gates of low side transistor 115 and high side transistor 125 , such that low side transistor 115 and high side transistor 125 are turned off quickly, thus allowing for higher frequency operation.
  • FIG. 8 is a schematic illustration of a circuit 500 having a distributed transistor and a distributed pulldown FET.
  • the distributed transistor of circuit 500 includes sub-transistors 502 , 504 , 506 , and 508 .
  • the distributed pulldown FET of circuit 500 includes sub-FETs 512 , 514 , 516 , and 518 . As shown, the gate of each sub-transistor is connected to the drain of a corresponding sub-FET.
  • FIG. 9 a schematic illustration of an embodiment of a layout 520 of circuit 500 .
  • the embodiment of FIG. 9 is provided as an example only. Numerous alternative layout configurations for circuit 500 are additionally contemplated.
  • the layout 520 illustrates the metal 2 drain D, source S, and gate G structures of circuit 500 .
  • the illustrated metal 2 drain D, source S, and gate G structures respectively correspond, for example, with metal 2 structures 257 , 247 , and 237 discussed above with reference to FIGS. 4A-4D .
  • Interconnect structure 510 includes, for example, a metal 1 layer, a metal 2 layer, and vias connecting portions of the metal 1 layer with portions of the metal 2 layer.
  • Interconnect structure 510 is configured to electrically connect metal 2 drain D structures of sub-transistors 512 , 514 , 516 , and 518 with metal 2 gate G structures of sub-transistors 502 , 504 , 506 , and 508 , respectively.
  • interconnect structure 500 is configured to electrically connect metal 2 source S structures of sub-transistors 512 , 514 , 516 , and 518 with metal 2 source S structures of sub-transistors 502 , 504 , 506 , and 508 , respectively.
  • interconnect structure 510 may comprise metal 2 jumpers configured to respectively make the appropriate connections between sub-transistors 502 , 504 , 506 , and 508 and sub-transistors 512 , 514 , 516 , and 518 .
  • FIG. 10 is a schematic illustration of a circuit 600 having a distributed transistor and pulldown FET 605 , a distributed pulldown FET driver 610 , and a distributed transistor driver 620 .
  • the distributed transistor and pulldown FET 605 of circuit 600 may be similar to circuit 500 of FIG. 8 .
  • the distributed pulldown FET driver 610 includes sub-drivers 612 , 614 , 616 , and 618 .
  • the distributed transistor driver 620 includes sub-drivers 622 , 624 , 626 , and 628 . As shown, the gate of each sub-transistor of the distributed transistor is connected to the output of a corresponding sub-driver of the distributed transistor driver 620 . Additionally, the gate of each sub-FET of the distributed pulldown FET is connected to the output of a corresponding sub-driver of the distributed pulldown FET driver 610 .
  • the distributed transistor and pulldown FET 605 of circuit 600 corresponds with low side transistor 115 and low side pulldown FET 122 .
  • distributed transistor driver 620 corresponds with low side transistor drive circuit 120
  • distributed pulldown FET driver 610 corresponds with high side transistor drive circuit 130 , as illustrated, for example, in FIG. 7 .
  • the distributed transistor and pulldown FET 605 of circuit 600 corresponds with high side transistor 125 and high side pulldown FET 132 .
  • distributed transistor driver 620 corresponds with high side transistor drive circuit 130
  • distributed pulldown FET driver 610 corresponds with low side transistor drive circuit 120 , as illustrated, for example, in FIG. 7 .
  • the gates of low side pulldown FET 122 and high side pulldown FET 132 are respectively driven by inverter circuits having their inputs respectively driven by low side transistor drive circuit 120 and high side transistor drive circuit 130 .
  • FIG. 11 is a schematic illustration of a circuit 650 , which includes drive transistor 652 , pulldown FET 653 , and an inverter comprising transistor 654 and resistor 655 .
  • Circuit 650 also includes optional Zener diodes 656 , which may provide overvoltage and/or ESD protection.
  • an instance of circuit 650 may be used instead of each of low side transistor 115 and high side transistor 125 .
  • the Gate input signal is provided both to the gate of drive transistor 652 and to the gate of transistor 654 of the inverter.
  • the output of the inverter is connected to the gate of pulldown FET 653 . Accordingly, if the drive transistor 652 is on as a result of sufficient voltage at the Gate input, the output of the inverter turns off the pulldown FET 653 to allow for the drive transistor 652 to be on. Similarly, if the drive transistor 652 is off as a result of insufficient voltage at the Gate input, the output of the inverter turns on the pulldown FET 653 to reduce the gate to source impedance of the drive transistor 652 . As a result of the pulldown FET 653 being on, transient voltages at the Gate input are minimized by pulldown FET 653 to be sufficiently low that the drive transistor 652 does not unwantedly turn on as a result of the transient voltages.
  • FIG. 12 is a simplified schematic of half bridge power conversion circuit 100 having been modified to include diodes 124 and 134 .
  • 124 and 134 have anodes respectively connected to the sources of low side transistor 115 and high side transistor 125 .
  • 124 and 134 have cathodes respectively connected to the drains of low side transistor 115 and high side transistor 125 .
  • Diodes 124 and 134 are respectively configured to conduct current from the sources of low side transistor 115 and high side transistor 125 to the drains of low side transistor 115 and high side transistor 125 if, for example, an inductive load causes current to flow in the opposite direction.
  • the inductive load may cause the voltage at the node Vsw to go significantly below ground before low side transistor 115 turns on. Once on, low side transistor 115 clamps the voltage at the node Vsw to a voltage about equal to a transistor threshold below ground.
  • the inductive load may cause the voltage at the node Vsw to go significantly above V+ before high side transistor 125 turns on. Once on, high side transistor 125 clamps the voltage at the node Vsw to a voltage about equal to a transistor threshold above V+.
  • diodes 124 and 134 In contrast, with diodes 124 and 134 the voltage at the node Vsw is clamped to a diode threshold below ground and a diode threshold above V+. With diodes 124 and 134 , current flows earlier or at less extreme voltages. To turn on diode 124 , the voltage induced by the inductive load at the node Vsw must go lower than a diode threshold below ground. Similarly, to turn on diode 134 , the voltage induced by the inductive load at the node Vsw must go above a diode threshold above V+.
  • diode threshold of diodes 124 and 134 is less than the transistor threshold voltages of low side transistor 115 and high side transistor 125 , with diodes 124 and 134 , the voltage at the node Vsw is clamped to a more preferable smaller range.
  • diodes 124 and 134 may be distributed, for example, as part of a distributed implementation of low side transistor 115 or high side transistor 125 , for example, as discussed below in further detail.
  • FIG. 13 is a schematic illustration of a circuit 690 having a distributed transistor and a distributed diode.
  • the distributed diode has its anode connected to the source of the distributed transistor and its cathode connected to the drain of the distributed transistor.
  • the distributed transistor includes sub-transistors 692 , and the distributed diode includes sub-diodes 693 . In this embodiment, there is one sub-diode for every two sub-transistors. In other embodiments, there is one sub-diode for every fewer or more sub-transistors.
  • FIG. 14 is a schematic illustration of a portion 700 of an embodiment of a layout of circuit 690 .
  • the embodiment of FIG. 14 is provided as an example only. Numerous alternative layout configurations for circuit 690 are additionally contemplated.
  • Source electrode fingers 741 , 742 , 743 , and 744 each form an ohmic contact with an underlying AlGaN or similar layer and collectively form the source electrode of the distributed transistor of circuit 690 .
  • Source electrode fingers 741 , 742 , 743 , and 744 respectively form the source electrodes of sub-transistors 692 .
  • the source electrode fingers 741 , 742 , 743 , and 744 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, source electrode fingers 743 , and 744 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 each form an ohmic contact with the underlying AlGaN or similar layer and collectively form the drain electrode of the distributed transistor of circuit 690 .
  • Drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 respectively form the drain electrodes of sub-transistors 692 .
  • the drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Gate electrode fingers 731 , 732 , 733 , and 734 are separated from the AlGaN or similar layer by respective gate structures. Gate structures corresponding with insulated gates, Schottky gates, PN gates, recessed gates, and other gates may be used. Gate electrode fingers 731 , 732 , 733 , and 734 collectively form the gate electrode of the distributed transistor of circuit 690 , and respectively form the gates electrodes of sub-transistors 692 . Gate electrode fingers 731 , 732 , 733 , and 734 are electrically connected to one another and to one or more pins through one or more conductors (not shown). In some embodiments, gate electrode fingers, 731 , 732 , 733 , and 734 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Field plate electrode fingers 761 , 762 , 764 , and 765 are separated from the AlGaN or similar layer by respective insulation structures, and collectively form a field plate electrode of the distributed transistor of circuit 690 .
  • Field plate electrode fingers 761 , 762 , 764 , and 765 respectively form field plate electrodes of sub-transistors 692 .
  • Field plate electrode fingers 761 , 762 , 764 , and 765 are electrically connected to one another and to one or more pins through one or more conductors (not shown).
  • field plate electrode fingers 761 , 762 , 764 , and 765 are electrically connected to one another and to one or more pins through overlying metallization layers.
  • Diode electrode fingers 748 and 749 form diodes 693 of circuit 690 .
  • FIG. 15 a schematic illustration of a cross section of portion 700 taken along the top or bottom edge of FIG. 14 .
  • Source electrode fingers 741 , 742 , 743 , and 744 , drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 , gate electrode fingers 731 , 732 , 733 , and 734 , and field plate electrode fingers 761 , 762 , 764 , and 765 are similar to the corresponding structures of, for example, transistor 200 , as illustrated in FIG. 3B .
  • every third sub-transistor functions as a sub-diode of the distributed diode because its gate is connected to its source.
  • diode electrode fingers 748 and 749 contact the AlGaN or similar layer and overly the gate structure, thereby forming gate to source connections.
  • diode electrode fingers 748 and 749 also form the filed plates of the diode connected sub-transistors.
  • diode connected sub-transistors have cross-sectional architecture which is identical to that of transistor 200 , as illustrated in FIG. 3B .
  • Gates and sources of the sub-transistors are connected, for example, in the additional metallization overlying the sub-transistors.
  • FIG. 16 a schematic illustration of a cross section of portion 700 taken along the top or bottom edge of FIG. 14 .
  • Source electrode fingers 741 , 742 , 743 , and 744 , drain electrode fingers 751 , 752 , 753 , 754 , 755 , and 756 , gate electrode fingers 731 , 732 , 733 , and 734 , and field plate electrode fingers 761 , 762 , 764 , and 765 are similar to the corresponding structures of, for example, transistor 200 , as illustrated in FIG. 3B .
  • the gate structure of every third sub-transistor is omitted.
  • Schottky barriers are respectively formed at the junctions of the AlGaN or similar layer and Schottky structures 750 and 755 beneath diode electrode fingers 748 and 749 .
  • Schottky structures comprise a Schottky metal.
  • diode electrode fingers 748 and 749 comprise a Schottky metal and are respectively integrated with Schottky structures 750 and 755 .
  • FIG. 17 is a flowchart diagram illustrating an embodiment of a method 800 of forming a distributed transistor integrated with a distributed driver.
  • a distributed transistor is formed.
  • a transistor having fingered gates and fingered sources may be formed by forming multiple adjacent sub-transistors each including a source and a gate.
  • the sources of the sub-transistors are electrically connected with a conductor.
  • the gates of the sub-transistors are electrically connected with a conductor.
  • the sub-transistors share a collective drain connection.
  • the sub transistors each have a separate drain connection.
  • the distributed driver includes at least an output stage which is distributed.
  • the output stage of the driver may include a distributed pull up transistor and a distributed pulldown transistor, where the distributed pull up transistor includes multiple pull up sub-transistors and the distributed pulldown transistor includes multiple pull down sub-transistors.
  • the distributed pull up transistor includes multiple pull up sub-transistors and the distributed pulldown transistor includes multiple pull down sub-transistors.
  • other or all portions of the distributed driver or also distributed.
  • the distributed pull up transistor and the distributed pulldown transistor are formed using a process similar to that described at 810 .
  • sources of the pull up sub-transistors are each connected with a drain of a corresponding one of the pulldown sub-transistors with a conductor.
  • Each pair of corresponding pull up and pulldown sub-transistors forms a sub-driver having an output electrode formed by the conductor connecting the source of the pull up sub-transistor and the drain of the pulldown sub-transistor thereof.
  • the distributed pull up transistor, the distributed pulldown transistor, and the distributed transistor of 810 are formed having the same pitch.
  • each sub-transistor of the distributed transistor of 810 may be aligned with a pair of corresponding pull up and pulldown sub-transistors forming a sub-driver.
  • the outputs of the distributed driver are connected to the fingered gates of the distributed transistor.
  • the gates of the sub-transistors of the distributed transistor may each be connected to an output electrode of a corresponding sub-driver with a conductor.
  • the conductor connecting the gates of the sub-transistors to the output electrodes of the sub-drivers is the same conductor as that connecting the sources of the pull up sub-transistors with the drains of the pulldown sub-transistors of the sub-drivers.
  • FIG. 18 is a flowchart diagram illustrating an embodiment of a method 900 of forming first and second distributed transistors.
  • a first distributed transistor is formed.
  • a first transistor having fingered gates and fingered sources may be formed by forming multiple adjacent sub-transistors each including a source and a gate.
  • the sources of the sub-transistors are electrically connected with a conductor.
  • the gates of the sub-transistors are electrically connected with a conductor.
  • the sub-transistors share a collective drain connection.
  • the sub transistors each have a separate drain connection.
  • a second distributed transistor is formed.
  • a second transistor having fingered gates and fingered sources may be formed by forming multiple adjacent sub-transistors each including a source and a gate.
  • the sources of the sub-transistors are electrically connected with a conductor.
  • the gates of the sub-transistors are electrically connected with a conductor.
  • the sub-transistors share a collective drain connection.
  • the sub transistors each have a separate drain connection.
  • the first distributed transistor and the second distributed transistor are formed having the same pitch.
  • each sub-transistor of the first distributed transistor may be aligned with one of the sub-transistors of the second distributed transistor.
  • the first distributed transistor is connected to the second distributed transistor.
  • the gates of the sub-transistors of the first distributed transistor may be connected by a first conductor with a collective drain of the second distributed transistor.
  • the sources of each of the sub-transistors of the first distributed transistor may be connected by a second conductor with the sources of the sub-transistors of the second distributed transistor.
  • the first distributed transistor may be formed with a first driver using a method such as method 800 described above.
  • the second distributed transistor be formed with a second driver using a method such as method 800 describe above.
  • FIG. 19 is a flowchart diagram illustrating an embodiment of a method 1000 of forming a distributed transistor and a distributed diode.
  • a distributed transistor is formed.
  • a transistor having fingered gates and fingered sources may be formed by forming multiple sub-transistors each including a source and a gate.
  • the sources of the sub-transistors are electrically connected with a conductor.
  • the gates of the sub-transistors are electrically connected with a conductor.
  • the sub-transistors share a collective drain connection.
  • the sub transistors each have a separate drain connection.
  • a distributed diode is formed.
  • a fingered diode may be formed such that the fingers of the fingered diode are interleaved with the fingered gates and sources of the sub-transistors of the distributed transistor.
  • the distributed diode is formed by electrically connecting gates and sources of some of the sub-transistors of the distributed transistor.
  • the distributed diode is formed by connecting a Schottky metal to the drain of the distributed transistor in multiple locations.
  • the distributed transistor is connected to the distributed diode.
  • the anodes of the sub-diodes may be connected with the sources of each of one or more sub-transistors of the distributed transistor, and the cathodes of the sub-diodes may be connected with the drain of the distributed transistor.
  • the anodes of the sub-diodes are connected with the sources of each of one or more sub-transistors of the distributed transistor by electrically connecting the gates and sources of some of the sub-transistors of the distributed transistor. In some embodiments, the anodes of the sub-diodes are connected with the sources of each of one or more sub-transistors on the distributed transistor by electrically connecting the Schottky metal/drain junctions of the distributed diode to the sources of each of one or more sub-transistors of the distributed transistor.
  • the distributed transistor may be formed with a driver using a method such as method 800 described above.
  • the distributed transistor and the distributed diode may be formed with a driver using a method such as method 800 described above.
  • the distributed transistor may be formed with a second distributed transistor using a method such as method 900 described above.
  • FIG. 20 is a flowchart diagram illustrating an embodiment of a method 1100 of forming a distributed transistor.
  • a distributed transistor is formed.
  • a transistor having fingered gates and fingered sources may be formed by forming multiple sub-transistors each including a source and a gate.
  • ohmic contacts to the gates and sources of the sub-transistors are formed by respectively contacting the gates and sources of the sub-transistors with ohmic gate and source conductors.
  • the gates of the sub-transistors are electrically connected to one another with a conductor.
  • the sources of the sub-transistors are electrically connected to one another with a conductor.
  • the sub-transistors share a collective drain connection.
  • the sub-transistors each have a separate drain connection.
  • a first additional conductive layer is formed.
  • the first additional conductive layer at least partially covers and electrically contacts the ohmic contact of the gates of the sub-transistors through one or more vias.
  • the first additional conductive layer at least partially covers and electrically contacts the ohmic contact of the sources of the sub-transistors through one or more vias.
  • a second additional conductive layer is formed.
  • the second additional conductive layer at least partially covers and electrically contacts the ohmic contact of the gates of the sub-transistors through one or more vias and through an opening in the first additional conductive layer.
  • the second additional conductive layer at least partially covers and electrically contacts the ohmic contact of the gates of the sub-transistors through one or more vias and through an opening in the first additional conductive layer.
  • the ohmic gate conductor overlaps the sources of the sub-transistors. In some embodiments, the second additional conductive layer electrically contacts the ohmic contact of the gates of the sub-transistors and a portion of the ohmic conductor which overlaps the sources of the sub-transistors.
  • the distributed transistor may be formed with a driver using a method such as method 800 described above. In some embodiments, the distributed transistor may be formed with a second distributed transistor using a method such as method 900 described above.
  • circuits discussed herein include one or more inventive features.
  • the various features of the circuits may be applied to other embodiments of circuits in combinations of features which are contemplated, but not specifically discussed for the sake of brevity.
  • the various aspects of the devices discussed herein may be practiced in other semiconductor technologies.
  • the various aspects of the devices discussed herein may be practiced in Silicon, Germanium, Gallium Arsenide, Silicon Carbide, Organic, and other technologies.

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