US20150338456A1 - Semiconductor apparatus - Google Patents
Semiconductor apparatus Download PDFInfo
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- US20150338456A1 US20150338456A1 US14/816,591 US201514816591A US2015338456A1 US 20150338456 A1 US20150338456 A1 US 20150338456A1 US 201514816591 A US201514816591 A US 201514816591A US 2015338456 A1 US2015338456 A1 US 2015338456A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 230000003111 delayed effect Effects 0.000 claims abstract description 43
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Definitions
- Various embodiments relate generally to a semiconductor apparatus, and more particularly, to a test mode of a semiconductor apparatus.
- a semiconductor apparatus typically employs a clock synchronous system to adjust operation timing in order to satisfy a high-speed operation without error.
- a semiconductor apparatus operating as a clock asynchronous system such as mobile DRAM is still used when necessary.
- the clock asynchronous semiconductor apparatus processes a received signal and data according to a delay amount set therein.
- PVT process, voltage, and temperature
- data may not be outputted at a desired time. Since a controller is utilized during a normal operation to control the clock asynchronous semiconductor apparatus when processing data outputted from the semiconductor apparatus in consideration of the aforementioned effects, data may be outputted at a desired time.
- FIG. 1 is an operation waveform diagram of a conventional clock asynchronous semiconductor apparatus.
- the semiconductor apparatus outputs data at a time according to a preset CAS latency (CL) during a read operation.
- CL indicates the number of clock cycles between when an external read command RDCMD is inputted and when a first data is outputted, based on an external clock signal CLK.
- the clock asynchronous semiconductor apparatus receives the external read command RDCMD from an external controller in synchronization with the external clock signal CLK. Then, the clock asynchronous semiconductor apparatus delays the external read command RDCMD by the CL based on the delay amount set therein, and outputs the delayed signal as an output enable flag signal OEFLAG.
- the delayed signal is not outputted immediately when the output enable flag signal OEFLAG is activated, but is rather outputted after a delay amount tREP based on an internal data output path of the semiconductor apparatus.
- the delayed signal is further delayed by the delay amount based on the internal data output path after the CL. Furthermore, since the delay amount is influenced by PVT variation, the data output time cannot be controlled precisely.
- the controller may control the semiconductor apparatus processes data in consideration of the aforementioned effects, thereby outputting data when desired.
- the test device when a test device does not have the same function as the controller while the semiconductor apparatus is being tested, the test device cannot accurately recognize and analyze data outputted from the clock asynchronous semiconductor apparatus.
- a semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode; a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode; and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
- MUX multiplexer
- a semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode; a test output timing controller configured to determine a delay amount by inputting a reference clock signal obtained by dividing an external clock signal by a value N into a DLL, delay the applied external read command by the delay amount when the DLL is locked, shift the delayed applied external read command by a CL code in synchronization with a DLL clock signal, and output the shifted delayed applied external read command as a test output enable flag signal, during a test mode; and a MUX configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
- FIG. 1 is an operation waveform diagram of a conventional clock asynchronous semiconductor apparatus
- FIG. 2 is a block diagram of a semiconductor apparatus according to an embodiment of the present invention.
- FIG. 3 is a block diagram illustrating an embodiment of the test output timing controller of FIG. 2 ;
- FIG. 4 is a waveform diagram illustrating the operation of a DLL of FIG. 3 ;
- FIG. 5 is a waveform diagram illustrating the operation of the delay control code generation unit of FIG. 3 ;
- FIG. 6 is a waveform diagram illustrating an operation of the test output timing controller of FIG. 3 ;
- FIG. 7 is a block diagram illustrating another embodiment of the test output timing controller of FIG. 2 ;
- FIGS. 8A to 8C are waveform diagrams illustrating operations of the DLL depending on various settings of a clock division unit of FIG. 7 ;
- FIG. 9 is a waveform diagram illustrating an operation of the test output timing controller of FIG. 7 .
- the semiconductor apparatus of FIG. 2 may include an output timing controller 100 , a test output timing controller 200 , and a multiplexer (MUX) 300 .
- MUX multiplexer
- the output timing controller 100 may be configured to delay an applied external read command RDCMD by a predetermined delay amount and output the delayed read command RDCMD as a normal output enable flag signal OEFLAG_NORMAL, during a normal mode. That is, when the asynchronous semiconductor apparatus according to an embodiment performs a normal operation, the semiconductor apparatus may delay the external read command RDCMD by a delay amount set therein and output the delayed read command RDCMD as the normal output enable flag signal OEFLAG_NORMAL.
- the predetermined delay amount may be set according to CL, for example.
- the output timing controller 100 may be enabled when a deactivated test mode signal TM is applied.
- the test output timing controller 200 may be configured to generate a DLL clock signal (not illustrated) from the external clock signal CLK, delay the applied external read command RDCMD in synchronization with the DLL clock signal, and output the delayed read command RDCMD as a test output enable flag signal OEFLAG_TEST, during a test mode. That is, the asynchronous semiconductor apparatus according to an embodiment may operate in synchronization with the DLL clock signal during the test mode. While the output timing controller 100 may delay the external read command RDCMD by the delay amount set therein, the test output timing controller 200 may delay the external read command RDCMD in synchronization with. the generated DLL clock signal. The test output timing controller 200 may be enabled when the activated test mode signal TM is applied.
- the MUX 300 may be configured to output any one of the normal output enable flag signal OEFLAG_NORMAL or the test output enable flag signal OEFLAG_TEST as an output enable flag signal OEFLAG, depending on whether the current mode is is normal mode or test mode. Specifically, when the deactivated test mode signal TM is applied, the MUX 300 may output the normal output enable flag signal OEFLAG_NORMAL as the output enable flag signal OEFLAG, and when the activated test mode signal TM is applied, the MUX 300 may output the test output enable flag signal OEFLAG_TEST as the output enable flag signal OEFLAG.
- the test output timing controller 200 A may include a delay locked loop (DLL) 210 A, a phase control unit 220 A, and a delay control code generation unit 230 A.
- DLL delay locked loop
- the DLL 210 A may be configured to delay the external clock signal CLK and generate a DLL clock signal DLLCLK. When the DLL 210 A is locked, the DLL 210 A may output an activated DLL locking signal DLL_LOCK.
- the phase control unit 220 A may be configured to receive the external read command RDCMD and generate the test output enable flag signal OEFLAG_TEST.
- the phase control unit 220 A may receive and delay the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, shift the delayed read command RDCMD by a delay control code CL-N in synchronization with the DLL clock signal DLLCLK, and output the shifted signal as the test output enable flag signal OEFLAG_TEST.
- the delay control code generation unit 230 A may be configured to count a counting code N, subtract the counting code N from a CL code, and generate the delay control code CL-N.
- the DLL 210 A may further include a first variably delay section 11 A, a first delay model section 12 A, and a phase comparison section 13 A.
- the first variable delay section 11 A may be configured to delay the external clock signal CLK in response to a delay amount control signal DCODE and generate the DLL clock signal DLLCLK.
- the first delay model section 12 A may be configured to delay the DLL clock signal DLLCLK by a model delay value tREP obtained by modeling time delay based on the data output path and output the delayed DLL clock signal DLLCLK as a feedback clock signal FDCLK.
- the phase comparison section 13 A may be configured to compare the phases of the external clock signal CLK and the feedback clock signal FBCLK and generate the delay amount control signal DCODE according to the comparison result.
- the delay amount control signal DCODE may be used to control the delay amount of the first variable delay section 11 A until the external clock signal CLK and the feedback clock signal FBCLK have the same phase.
- the first variable delay section 11 A may generate the DLL clock signal DLLCLK to accurately compensate for the model delay value tREP.
- the delay amount of the first variable delay section 11 A may become N*tCK-tREP.
- the DLL 210 A may be locked, and the phase comparison section 13 A may activate the DLL lock signal DLL_LOCK.
- the phase control unit 220 A may include a command receiver 21 A, a second variable delay section 22 A, and a shift register 23 A.
- the command receiver 21 A may be configured to receive the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, and output the received external read command RDCMD as a read command IRDCMD.
- the second variable delay section 22 A may be configured to delay the read command IRDCMD in response to the delay amount control signal DCODE and output the delayed read command DRDCMD.
- the shift register 23 A may be configured to shift the delayed read command DRDCMD by the delay control code CL-N in synchronization with the DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST.
- the delay control code generation unit 230 A may include a second delay model section 31 A, a counter section 32 A, and an operation section 33 A.
- the second delay model section 31 A may be configured to delay the delayed read command DRDCMD by the model delay value tREP and output the delayed read command DRDCMD as a model delayed read command DDRDCMD.
- the counter section 32 A may be configured to perform a counting operation in synchronization with a counting clock signal, for example, the external clock signal CLK.
- the counter section 32 A starts counting when the read command IRDCMD is applied and stops counting when the model delayed read command DDRDCMD is applied.
- the counter section 32 A may output the counted value as the counting code N. Therefore, the counter section 32 A may count the counting code N after the DLL 210 A is locked.
- the operation section 33 A may be configured to subtract the counting code N from the CL code and output the delay control code CL-N.
- the feedback clock signal FBCLK may have a phase delayed by the model delay value tREP from the external clock signal CLK. This is because the delay amount of the first variable delay section 11 A is not yet controlled. Since the delay amount is controlled once the feedback clock signal FBCLK and the external clock signal CLK have the same phase, the delay amount control signal DCODE may be set to control the delay amount of the first variable delay section 11 A by N*tCK-tREP. The DLL 210 A is subsequently locked.
- the command receiver 21 A receive the external read command RDCMD and generate the read command IRDCMD. Ideally, the external read command RDCMD and the read command IRDCMD are in phase.
- the phase of the read command IRDCMD may be controlled by N*tCK-tREP through the second variable delay section 22 A of the phase control unit 220 A, and then outputted as the delayed read command DRDCMD. This may occur because the second variable delay section 22 A may control substantially the same delay amount as the first variable delay section 11 A according to the fixed delay amount control signal DCODE.
- the delayed read command DRDCMD may be delayed by the model delay value tREP through the second delay model section 31 A and outputted as the model delayed read command DDRDCMD.
- the counter section 32 A may count the external clock signal CLK from when the read command IRDCMD is applied to when the model delayed read command DDRDCMD is applied, and generate the counting code N.
- the counting code N corresponds to 3.
- the operation section 33 A may subtract the counting code N from the CL code and output the delay control code CL-N.
- the counting code N may be counted to accurately set the data output timing in consideration of the data output path.
- test output enable flag signal OEFLAG_TEST may serve to enable outputting of the data D 0 to D 3 during the test mode.
- the data D 0 to D 3 may particularly be outputted when the delay amount tREP of the data output path elapses after the test output enable flag signal OEFLAG_TEST is activated.
- the test output enable flag signal OEFLAG_TEST may be generated in synchronization with the DLL clock signal DLLCLK inside the semiconductor apparatus.
- the delay amount tREP of the data output path must be considered.
- the semiconductor apparatus counts the counting code N.
- the clock delay amount (N*tCK-tREP) when the DLL 210 A is locked and the delay amount tREP of the data output path may be counted based on the external clock signal CLK, in order to generate the counting code N.
- the semiconductor apparatus may delay the read command IRDCMD by N*tCK-tREP and output the delayed read command DRDCMD. Then, the semiconductor apparatus may shift the delayed read command DRDCMD by the delay control code CL-N in synchronization with the DLL clock signal DLLCLK.
- the test output enable flag signal OEFLAG_TEST may then be outputted.
- the data D 0 to D 3 may be outputted when the CL elapses after the read command IRDCMD is received.
- the counting code N may be counted to control the data output timing during each operation. In an embodiment according to FIG. 7 , however, the counting code N may be preset to control the data output timing.
- the test output timing controller 200 B may include a DLL 210 B, a phase control unit 220 B, and a clock division unit 240 B.
- the DLL 210 B may be configured to delay a reference clock signal REFCLK and generate a DLL clock signal DLLCLK. When the DLL 210 B is locked, the DLL 210 B may output an activated DLL locking signal DLL_LOCK.
- the phase control unit 220 B may be configured to receive the external read command RDCMD and generate a test output enable flag signal OEFLAG_TEST.
- the phase control unit 220 B may receive and delay the external read command RDCMD when the DLL lock signal DLL_LOCK is activated, further shift the delayed external read command RDCMD by the CL code in synchronization with the DLL clock signal DLLCLK, and output the shifted external read command RDCMD as the test output enable flag signal OEFLAG_TEST.
- the DLL 210 B may include a first variable delay section 11 B, a first delay model section 12 B, and a phase comparison section 13 B.
- the first variable delay section 11 B may be configured to delay the reference clock signal REFCLK in response to the delay amount control signal DCODE and generate the DLL clock signal DLLCLK.
- the first delay model section 12 B may be configured to delay the DLL clock signal DLLCLK by the model delay value tREP obtained by modeling time delay based on the data output path, and output the delayed DLL clock signal DLLCLK as a feedback clock signal FBCLK.
- the phase comparison section 13 B may be configured to compare the phases of the reference clock signal CLK and the feedback clock signal FBCLK and generate the delay amount control signal DCODE according to the comparison result.
- the delay amount control signal DCODE may be used to control the delay amount of the first variable delay section 11 B until the reference clock signal REFCLK and the feedback clock signal FBCLK have the same phase.
- the first variable delay section 11 B may generate the DLL clock signal DLLCLK to accurately compensate for the model delay value tREP.
- the delay amount of the first variable delay section 11 B may become N*tCK-tREP.
- the DLL 210 B may be locked, and the phase comparison section 13 B may activate the DLL locking signal DLL_LOCK.
- the phase control unit 220 B may include a command receiver 21 B, a second variable delay section 22 B, and a shift register 23 B.
- the command receiver 21 B may be configured to receive the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, and output the received external read command RDCMD as the read command IRDCMD.
- the second variable delay section 22 B may be configured to delay the read command IRDCMD in response to the delay amount control signal DCODE and output the delayed read command DRDCMD.
- the shift register 23 B may be configured to shift the delayed read command DRDCMD by the CL code in synchronization with the DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST.
- the clock division unit 240 B may be configured to divide the external clock signal CLK and output the divided external clock signal CLK as the reference clock signal REFCLK, or output the external clock signal CLK as the reference clock signal REFCLK, depending on whether the DLL 210 B is locked or not.
- the clock division unit 240 B may include a divider 41 B and a clock selection section 42 B.
- the divider 41 B may be configured to receive the external clock signal CLK and divide the external clock signal CLK in response to a divide select signal SEL_DVD.
- the clock selection section 42 B may be configured to output any one of an output of the divider 41 B or the external clock signal CLK as the reference clock signal REFCLK in response to the DLL locking signal DLL_LOCK.
- the clock selection section 42 B may output the output of the divider 41 B as the reference clock signal REFCLK, and when the DLL locking signal DLL_LOCK is activated, the clock selection section 42 B may output the external clock signal CLK as the reference clock signal REFCLK.
- the clock division unit 240 B may divide the external clock signal CLK in response to the preset divide select signal SEL_DVD, and output the divided external clock signal CLK as the reference clock signal REFCLK.
- the DLL 210 B Before the DLL 210 B is locked, the DLL 210 B may operate by receiving the reference clock signal REFCLK generated by dividing the external clock signal CLK. Therefore, the delay amount (N*tCK-tREP) of the first variable delay section 11 B may be determined by the reference clock signal REFCLK generated by dividing the external clock signal CLK. Therefore, N may be differently determined by the divide select signal SEL_DVD set by the clock division unit 240 B.
- the DLL 210 B may be locked and the external clock signal CLK may be outputted as the reference clock signal REFCLK, the delay amount (N*tCK-tREP) of the first variable delay section 11 B may be maintained. Accordingly, N may also be maintained.
- FIG. 8A is a waveform diagram illustrating an operation of the DLL 210 B when the clock division unit 240 B outputs the external clock signal CLK as the reference clock signal REFCLK.
- the feedback clock signal FBCLK may be generated when the model delay value tREP elapses after the reference clock signal REFCLK is applied. Since the first variable delay section 11 B may control the delay amount such that the feedback clock signal FBCLK has the same phase as the reference clock signal REFCLK, the variable delay section 11 B may have a delay amount of N*tCK-tREP. Therefore, in FIG. 8A , the counting code N may be 3 as an example.
- FIG. 8B is a waveform diagram illustrating an operation of the DLL 210 B when the clock division unit 240 B divides the external clock CLK when the counting code N is five, and outputs the divided signal as the reference clock signal REFCLK.
- FIG. 8C is a waveform diagram illustrating an operation of the DLL 210 B when the clock division unit 240 B divides the external clock signal CLK when the counting code N is seven, and outputs the divided signal as the reference clock signal REFCLK.
- the delay amount (N*tCK-tREP) of the variable delay section 11 B may be determined by N.
- the counting code N may be preset by the divide select signal SEL_DVD of the clock division unit 240 B.
- FIG. 9 illustrates a case in which N is set to 5.
- the second variable delay section 22 B may delay the read command IRDCMD by N*tCK-tREP and output the delayed read command DRDCMD. Since the second variable delay section 22 B may control the delay amount according to the fixed delay amount control signal DCODE like in the first variable delay section 11 B, the second variable delay section 22 B may have substantially the same or similar delay amount as the first variable delay section 11 B.
- the shift register 23 B may shift the delayed read command DRDCMD by the CL code in synchronization with the fixed DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST.
- the data D 0 to D 3 may be outputted to the when the delay amount (tREP) of the data output path elapses after the test output enable flag signal OEFLAG_TEST is activated.
- the data D 0 to D 3 may be outputted when the CL and the external clock corresponding to the counting code N pass after the read command IRDCMD is received. Since the CL and N are setting values, the data output time during the test mode may be accurately controlled. Furthermore, the output data may be received at a desired time.
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Abstract
Description
- The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0152161 filed on Dec. 24, 2012 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
- 1. Technical Field
- Various embodiments relate generally to a semiconductor apparatus, and more particularly, to a test mode of a semiconductor apparatus.
- 2. Related Art
- A semiconductor apparatus typically employs a clock synchronous system to adjust operation timing in order to satisfy a high-speed operation without error. However, a semiconductor apparatus operating as a clock asynchronous system such as mobile DRAM is still used when necessary. The clock asynchronous semiconductor apparatus processes a received signal and data according to a delay amount set therein. However, due to process, voltage, and temperature (PVT) effects or the like, data may not be outputted at a desired time. Since a controller is utilized during a normal operation to control the clock asynchronous semiconductor apparatus when processing data outputted from the semiconductor apparatus in consideration of the aforementioned effects, data may be outputted at a desired time.
-
FIG. 1 is an operation waveform diagram of a conventional clock asynchronous semiconductor apparatus. - The semiconductor apparatus outputs data at a time according to a preset CAS latency (CL) during a read operation. The CL indicates the number of clock cycles between when an external read command RDCMD is inputted and when a first data is outputted, based on an external clock signal CLK.
- The clock asynchronous semiconductor apparatus receives the external read command RDCMD from an external controller in synchronization with the external clock signal CLK. Then, the clock asynchronous semiconductor apparatus delays the external read command RDCMD by the CL based on the delay amount set therein, and outputs the delayed signal as an output enable flag signal OEFLAG. The delayed signal is not outputted immediately when the output enable flag signal OEFLAG is activated, but is rather outputted after a delay amount tREP based on an internal data output path of the semiconductor apparatus.
- The delayed signal is further delayed by the delay amount based on the internal data output path after the CL. Furthermore, since the delay amount is influenced by PVT variation, the data output time cannot be controlled precisely.
- During the normal operation, however, the controller, as described above, may control the semiconductor apparatus processes data in consideration of the aforementioned effects, thereby outputting data when desired. However, when a test device does not have the same function as the controller while the semiconductor apparatus is being tested, the test device cannot accurately recognize and analyze data outputted from the clock asynchronous semiconductor apparatus.
- In an embodiment, a semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode; a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode; and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
- In another embodiment, a semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode; a test output timing controller configured to determine a delay amount by inputting a reference clock signal obtained by dividing an external clock signal by a value N into a DLL, delay the applied external read command by the delay amount when the DLL is locked, shift the delayed applied external read command by a CL code in synchronization with a DLL clock signal, and output the shifted delayed applied external read command as a test output enable flag signal, during a test mode; and a MUX configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
- Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:
-
FIG. 1 is an operation waveform diagram of a conventional clock asynchronous semiconductor apparatus; -
FIG. 2 is a block diagram of a semiconductor apparatus according to an embodiment of the present invention; -
FIG. 3 is a block diagram illustrating an embodiment of the test output timing controller ofFIG. 2 ; -
FIG. 4 is a waveform diagram illustrating the operation of a DLL ofFIG. 3 ; -
FIG. 5 is a waveform diagram illustrating the operation of the delay control code generation unit ofFIG. 3 ; -
FIG. 6 is a waveform diagram illustrating an operation of the test output timing controller ofFIG. 3 ; -
FIG. 7 is a block diagram illustrating another embodiment of the test output timing controller ofFIG. 2 ; -
FIGS. 8A to 8C are waveform diagrams illustrating operations of the DLL depending on various settings of a clock division unit ofFIG. 7 ; and -
FIG. 9 is a waveform diagram illustrating an operation of the test output timing controller ofFIG. 7 . - Hereinafter, a semiconductor apparatus according to the present invention will be described below with reference to the accompanying drawings through various embodiments.
- The semiconductor apparatus of
FIG. 2 may include anoutput timing controller 100, a testoutput timing controller 200, and a multiplexer (MUX) 300. - The
output timing controller 100 may be configured to delay an applied external read command RDCMD by a predetermined delay amount and output the delayed read command RDCMD as a normal output enable flag signal OEFLAG_NORMAL, during a normal mode. That is, when the asynchronous semiconductor apparatus according to an embodiment performs a normal operation, the semiconductor apparatus may delay the external read command RDCMD by a delay amount set therein and output the delayed read command RDCMD as the normal output enable flag signal OEFLAG_NORMAL. The predetermined delay amount may be set according to CL, for example. Theoutput timing controller 100 may be enabled when a deactivated test mode signal TM is applied. - The test
output timing controller 200 may be configured to generate a DLL clock signal (not illustrated) from the external clock signal CLK, delay the applied external read command RDCMD in synchronization with the DLL clock signal, and output the delayed read command RDCMD as a test output enable flag signal OEFLAG_TEST, during a test mode. That is, the asynchronous semiconductor apparatus according to an embodiment may operate in synchronization with the DLL clock signal during the test mode. While theoutput timing controller 100 may delay the external read command RDCMD by the delay amount set therein, the testoutput timing controller 200 may delay the external read command RDCMD in synchronization with. the generated DLL clock signal. The testoutput timing controller 200 may be enabled when the activated test mode signal TM is applied. - The MUX 300 may be configured to output any one of the normal output enable flag signal OEFLAG_NORMAL or the test output enable flag signal OEFLAG_TEST as an output enable flag signal OEFLAG, depending on whether the current mode is is normal mode or test mode. Specifically, when the deactivated test mode signal TM is applied, the MUX 300 may output the normal output enable flag signal OEFLAG_NORMAL as the output enable flag signal OEFLAG, and when the activated test mode signal TM is applied, the MUX 300 may output the test output enable flag signal OEFLAG_TEST as the output enable flag signal OEFLAG.
- Referring to
FIG. 3 , the testoutput timing controller 200A may include a delay locked loop (DLL) 210A, aphase control unit 220A, and a delay controlcode generation unit 230A. - The
DLL 210A may be configured to delay the external clock signal CLK and generate a DLL clock signal DLLCLK. When theDLL 210A is locked, theDLL 210A may output an activated DLL locking signal DLL_LOCK. - The
phase control unit 220A may be configured to receive the external read command RDCMD and generate the test output enable flag signal OEFLAG_TEST. Thephase control unit 220A may receive and delay the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, shift the delayed read command RDCMD by a delay control code CL-N in synchronization with the DLL clock signal DLLCLK, and output the shifted signal as the test output enable flag signal OEFLAG_TEST. - The delay control
code generation unit 230A may be configured to count a counting code N, subtract the counting code N from a CL code, and generate the delay control code CL-N. - The
DLL 210A may further include a first variablydelay section 11A, a firstdelay model section 12A, and aphase comparison section 13A. - The first
variable delay section 11A may be configured to delay the external clock signal CLK in response to a delay amount control signal DCODE and generate the DLL clock signal DLLCLK. - The first
delay model section 12A may be configured to delay the DLL clock signal DLLCLK by a model delay value tREP obtained by modeling time delay based on the data output path and output the delayed DLL clock signal DLLCLK as a feedback clock signal FDCLK. - The
phase comparison section 13A may be configured to compare the phases of the external clock signal CLK and the feedback clock signal FBCLK and generate the delay amount control signal DCODE according to the comparison result. - The delay amount control signal DCODE may be used to control the delay amount of the first
variable delay section 11A until the external clock signal CLK and the feedback clock signal FBCLK have the same phase. When the external clock signal CLK and the feedback clock signal FBCLK have the same phase, the firstvariable delay section 11A may generate the DLL clock signal DLLCLK to accurately compensate for the model delay value tREP. The delay amount of the firstvariable delay section 11A may become N*tCK-tREP. When the external clock signal CLK and the feedback clock signal FBCLK have the same phase, theDLL 210A may be locked, and thephase comparison section 13A may activate the DLL lock signal DLL_LOCK. - The
phase control unit 220A may include acommand receiver 21A, a secondvariable delay section 22A, and ashift register 23A. - The
command receiver 21A may be configured to receive the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, and output the received external read command RDCMD as a read command IRDCMD. - The second
variable delay section 22A may be configured to delay the read command IRDCMD in response to the delay amount control signal DCODE and output the delayed read command DRDCMD. - The
shift register 23A may be configured to shift the delayed read command DRDCMD by the delay control code CL-N in synchronization with the DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST. - The delay control
code generation unit 230A may include a seconddelay model section 31A, acounter section 32A, and anoperation section 33A. - The second
delay model section 31A may be configured to delay the delayed read command DRDCMD by the model delay value tREP and output the delayed read command DRDCMD as a model delayed read command DDRDCMD. - The
counter section 32A may be configured to perform a counting operation in synchronization with a counting clock signal, for example, the external clock signal CLK. Thecounter section 32A starts counting when the read command IRDCMD is applied and stops counting when the model delayed read command DDRDCMD is applied. Thecounter section 32A may output the counted value as the counting code N. Therefore, thecounter section 32A may count the counting code N after theDLL 210A is locked. - The
operation section 33A may be configured to subtract the counting code N from the CL code and output the delay control code CL-N. - Referring to
FIG. 4 , when theDLL 210A is reset and then starts to operate, the feedback clock signal FBCLK may have a phase delayed by the model delay value tREP from the external clock signal CLK. This is because the delay amount of the firstvariable delay section 11A is not yet controlled. Since the delay amount is controlled once the feedback clock signal FBCLK and the external clock signal CLK have the same phase, the delay amount control signal DCODE may be set to control the delay amount of the firstvariable delay section 11A by N*tCK-tREP. TheDLL 210A is subsequently locked. - Referring to
FIG. 5 , only when the DLL locking signal DLL_LOCK is activated may thecommand receiver 21A receive the external read command RDCMD and generate the read command IRDCMD. Ideally, the external read command RDCMD and the read command IRDCMD are in phase. - The phase of the read command IRDCMD may be controlled by N*tCK-tREP through the second
variable delay section 22A of thephase control unit 220A, and then outputted as the delayed read command DRDCMD. This may occur because the secondvariable delay section 22A may control substantially the same delay amount as the firstvariable delay section 11A according to the fixed delay amount control signal DCODE. The delayed read command DRDCMD may be delayed by the model delay value tREP through the seconddelay model section 31A and outputted as the model delayed read command DDRDCMD. - The
counter section 32A may count the external clock signal CLK from when the read command IRDCMD is applied to when the model delayed read command DDRDCMD is applied, and generate the counting code N. InFIG. 5 , the counting code N corresponds to 3. - The
operation section 33A may subtract the counting code N from the CL code and output the delay control code CL-N. - That is, according to an embodiment, the counting code N may be counted to accurately set the data output timing in consideration of the data output path.
- Referring to
FIG. 6 , during the test mode, when the read command IRDCMD is applied in synchronization with the external clock signal CLK, data D0 to D3 (not illustrate inFIG. 3 ) may be outputted after the CL according to the specifications as mentioned above. The test output enable flag signal OEFLAG_TEST may serve to enable outputting of the data D0 to D3 during the test mode. The data D0 to D3 may particularly be outputted when the delay amount tREP of the data output path elapses after the test output enable flag signal OEFLAG_TEST is activated. The test output enable flag signal OEFLAG_TEST may be generated in synchronization with the DLL clock signal DLLCLK inside the semiconductor apparatus. - When the test output enable flag signal OEFLAG_TEST is generated, the delay amount tREP of the data output path must be considered. The semiconductor apparatus counts the counting code N. The clock delay amount (N*tCK-tREP) when the
DLL 210A is locked and the delay amount tREP of the data output path may be counted based on the external clock signal CLK, in order to generate the counting code N. First, the semiconductor apparatus may delay the read command IRDCMD by N*tCK-tREP and output the delayed read command DRDCMD. Then, the semiconductor apparatus may shift the delayed read command DRDCMD by the delay control code CL-N in synchronization with the DLL clock signal DLLCLK. The test output enable flag signal OEFLAG_TEST may then be outputted. - Therefore, during the test mode, the data D0 to D3 may be outputted when the CL elapses after the read command IRDCMD is received.
- In an embodiment according to
FIG. 6 , the counting code N may be counted to control the data output timing during each operation. In an embodiment according toFIG. 7 , however, the counting code N may be preset to control the data output timing. - Referring to
FIG. 7 , the testoutput timing controller 200B may include aDLL 210B, aphase control unit 220B, and aclock division unit 240B. - The
DLL 210B may be configured to delay a reference clock signal REFCLK and generate a DLL clock signal DLLCLK. When theDLL 210B is locked, theDLL 210B may output an activated DLL locking signal DLL_LOCK. - The
phase control unit 220B may be configured to receive the external read command RDCMD and generate a test output enable flag signal OEFLAG_TEST. In particular, thephase control unit 220B may receive and delay the external read command RDCMD when the DLL lock signal DLL_LOCK is activated, further shift the delayed external read command RDCMD by the CL code in synchronization with the DLL clock signal DLLCLK, and output the shifted external read command RDCMD as the test output enable flag signal OEFLAG_TEST. - Specifically, the
DLL 210B may include a firstvariable delay section 11B, a firstdelay model section 12B, and aphase comparison section 13B. - The first
variable delay section 11B may be configured to delay the reference clock signal REFCLK in response to the delay amount control signal DCODE and generate the DLL clock signal DLLCLK. - The first
delay model section 12B may be configured to delay the DLL clock signal DLLCLK by the model delay value tREP obtained by modeling time delay based on the data output path, and output the delayed DLL clock signal DLLCLK as a feedback clock signal FBCLK. - The
phase comparison section 13B may be configured to compare the phases of the reference clock signal CLK and the feedback clock signal FBCLK and generate the delay amount control signal DCODE according to the comparison result. - The delay amount control signal DCODE may be used to control the delay amount of the first
variable delay section 11B until the reference clock signal REFCLK and the feedback clock signal FBCLK have the same phase. When the external clock signal CLK and the feedback clock signal FBCLK have the same phase, the firstvariable delay section 11B may generate the DLL clock signal DLLCLK to accurately compensate for the model delay value tREP. The delay amount of the firstvariable delay section 11B may become N*tCK-tREP. When the reference clock signal REFCLK and the feedback clock signal FBCLK have the same phase, theDLL 210B may be locked, and thephase comparison section 13B may activate the DLL locking signal DLL_LOCK. - The
phase control unit 220B may include acommand receiver 21B, a secondvariable delay section 22B, and ashift register 23B. - The
command receiver 21B may be configured to receive the external read command RDCMD when the DLL locking signal DLL_LOCK is activated, and output the received external read command RDCMD as the read command IRDCMD. - The second
variable delay section 22B may be configured to delay the read command IRDCMD in response to the delay amount control signal DCODE and output the delayed read command DRDCMD. - The
shift register 23B may be configured to shift the delayed read command DRDCMD by the CL code in synchronization with the DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST. - The
clock division unit 240B may be configured to divide the external clock signal CLK and output the divided external clock signal CLK as the reference clock signal REFCLK, or output the external clock signal CLK as the reference clock signal REFCLK, depending on whether theDLL 210B is locked or not. - The
clock division unit 240B may include adivider 41B and aclock selection section 42B. - The
divider 41B may be configured to receive the external clock signal CLK and divide the external clock signal CLK in response to a divide select signal SEL_DVD. - The
clock selection section 42B may be configured to output any one of an output of thedivider 41B or the external clock signal CLK as the reference clock signal REFCLK in response to the DLL locking signal DLL_LOCK. When the DLL locking signal DLL_LOCK is deactivated, theclock selection section 42B may output the output of thedivider 41B as the reference clock signal REFCLK, and when the DLL locking signal DLL_LOCK is activated, theclock selection section 42B may output the external clock signal CLK as the reference clock signal REFCLK. - When the
DLL 210B is reset and starts to operate, that is, when the DLL locking signal DLL_LOCK is deactivated, theclock division unit 240B may divide the external clock signal CLK in response to the preset divide select signal SEL_DVD, and output the divided external clock signal CLK as the reference clock signal REFCLK. Before theDLL 210B is locked, theDLL 210B may operate by receiving the reference clock signal REFCLK generated by dividing the external clock signal CLK. Therefore, the delay amount (N*tCK-tREP) of the firstvariable delay section 11B may be determined by the reference clock signal REFCLK generated by dividing the external clock signal CLK. Therefore, N may be differently determined by the divide select signal SEL_DVD set by theclock division unit 240B. Then, although theDLL 210B may be locked and the external clock signal CLK may be outputted as the reference clock signal REFCLK, the delay amount (N*tCK-tREP) of the firstvariable delay section 11B may be maintained. Accordingly, N may also be maintained. -
FIG. 8A is a waveform diagram illustrating an operation of theDLL 210B when theclock division unit 240B outputs the external clock signal CLK as the reference clock signal REFCLK. - When the
DLL 210B starts to operate, the feedback clock signal FBCLK may be generated when the model delay value tREP elapses after the reference clock signal REFCLK is applied. Since the firstvariable delay section 11B may control the delay amount such that the feedback clock signal FBCLK has the same phase as the reference clock signal REFCLK, thevariable delay section 11B may have a delay amount of N*tCK-tREP. Therefore, inFIG. 8A , the counting code N may be 3 as an example. -
FIG. 8B is a waveform diagram illustrating an operation of theDLL 210B when theclock division unit 240B divides the external clock CLK when the counting code N is five, and outputs the divided signal as the reference clock signal REFCLK. - When the
DLL 210B starts to operate, the feedback clock signal FBCLK may be generated when the model delay value tREP elapses after the reference clock signal REFCLK is applied. Since thevariable delay section 11B may control the delay amount such that the feedback clock signal FBCLK has the same phase as the reference clock signal REFCLK, the firstvariable delay section 11B may have a delay amount of N*tCK-tREP. Therefore, inFIG. 8B , the counting code N may be 5 as an example. Then, when theDLL 210B is locked, the reference clock signal REFCLK having the same phase as the external clock signal CLK may be applied, but the delay amount of N*tCK-tREP (N=5) will not change. -
FIG. 8C is a waveform diagram illustrating an operation of theDLL 210B when theclock division unit 240B divides the external clock signal CLK when the counting code N is seven, and outputs the divided signal as the reference clock signal REFCLK. - When the
DLL 210B starts to operate, the feedback clock signal FBCLK may be generated when the model delay value tREP elapses after the reference clock signal REFCLK is applied. Since thevariable delay section 11B may control the delay amount such that the feedback clock signal FBCLK has the same phase as the reference clock signal REFCLK, the firstvariable delay section 11B may have a delay amount of N*tCK-tREP. Therefore, inFIG. 8C , the counting code N may be 7 as an example. Then, when theDLL 210B is locked, the reference clock signal REFCLK having the same phase as the external clock signal CLK may be applied, but the delay amount of N*tCK-tREP (N=7) will not change. - As described with reference to
FIGS. 8B and 8C , when theclock division unit 240B divides the external clock signal CLK by a sufficiently large counting code N, the delay amount (N*tCK-tREP) of thevariable delay section 11B may be determined by N. - According to an embodiment, the counting code N may be preset by the divide select signal SEL_DVD of the
clock division unit 240B.FIG. 9 illustrates a case in which N is set to 5. - When the read command IRDCMD is applied in synchronization with the external clock signal CLK after the
DLL 210B is locked, the secondvariable delay section 22B may delay the read command IRDCMD by N*tCK-tREP and output the delayed read command DRDCMD. Since the secondvariable delay section 22B may control the delay amount according to the fixed delay amount control signal DCODE like in the firstvariable delay section 11B, the secondvariable delay section 22B may have substantially the same or similar delay amount as the firstvariable delay section 11B. - The
shift register 23B may shift the delayed read command DRDCMD by the CL code in synchronization with the fixed DLL clock signal DLLCLK, and output the shifted delayed read command DRDCMD as the test output enable flag signal OEFLAG_TEST. The data D0 to D3 may be outputted to the when the delay amount (tREP) of the data output path elapses after the test output enable flag signal OEFLAG_TEST is activated. - Therefore, in the test
output timing controller 200B according to an embodiment, the data D0 to D3 may be outputted when the CL and the external clock corresponding to the counting code N pass after the read command IRDCMD is received. Since the CL and N are setting values, the data output time during the test mode may be accurately controlled. Furthermore, the output data may be received at a desired time. - While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.
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US6944039B1 (en) * | 2003-12-12 | 2005-09-13 | Netlogic Microsystems, Inc. | Content addressable memory with mode-selectable match detect timing |
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US8405435B2 (en) * | 2004-11-10 | 2013-03-26 | Lsi Corporation | Delay locked loop having internal test path |
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US8595575B2 (en) * | 2010-12-30 | 2013-11-26 | Hynix Semiconductor Inc. | Semiconductor memory device, test circuit, and test operation method thereof |
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