US20150333067A1 - Devices and methods of forming finfets with self aligned fin formation - Google Patents
Devices and methods of forming finfets with self aligned fin formation Download PDFInfo
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- US20150333067A1 US20150333067A1 US14/812,500 US201514812500A US2015333067A1 US 20150333067 A1 US20150333067 A1 US 20150333067A1 US 201514812500 A US201514812500 A US 201514812500A US 2015333067 A1 US2015333067 A1 US 2015333067A1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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Definitions
- the present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to FinFETs and methods of fabricating semiconductor devices with self aligned fin formation and a source and drain junction compatible with planar fabrication processes.
- the fin is formed first. Then the gate, spacer and junction/contact may be formed. As the gate, spacer and junction are formed they must be formed over and around the high topology fins. The high topology fins may cause challenges during deposition, lithography and etching to form the gate, spacer, and junction. Further, epitaxy must be grown on the three dimensional fin rather than the previous two dimensional planar substrate, this results in less epitaxy volume on the three dimensional fin than was previously on the planar substrate thereby limiting the stress enhancement. With a limited epitaxy volume on the three dimensional fins, the silicidation cannot consume too much epitaxy material. Currently, titanium silicide is being used because it consumes less epitaxy, however titanium silicide has poor contact properties.
- a method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate.
- an intermediate semiconductor device which includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate
- FIG. 1 depicts one embodiment of a process for fabricating, for instance, semiconductor devices with self aligned fin formation and source and drain contact compatible with the planar process, in accordance with one or more aspects of the present invention
- FIG. 2 depicts one embodiment of an intermediate semiconductor device with a fin hard mask layer applied over the device, in accordance with one or more aspects of the present invention
- FIGS. 3A-3B depict the intermediate device of FIG. 2 after etching to create at least one fin hard mask, in accordance with one or more aspects of the present invention
- FIGS. 4A-4C depict the intermediate device of FIGS. 3A-3B after forming a sacrificial gate structure over the at least one fin hard mask, in accordance with one or more aspects of the present invention
- FIGS. 5A-5C depict the intermediate device of FIGS. 4A-4C after etching of the at least one fin hard mask and a portion of the first oxide layer, in accordance with one or more aspects of the present invention
- FIGS. 6A-6B depict the intermediate device of FIGS. 5A-5C after application of a first spacer to the side walls of the sacrificial gate structure, in accordance with one or more aspects of the present invention
- FIGS. 7A-7B depict the intermediate device of FIGS. 6A-6B after performing sigma etching to form the pFET regions, in accordance with one or more aspects of the present invention
- FIGS. 8A-8B depict the intermediate device of FIGS. 7A-7B after application of a second spacer and performing sigma etching to form the nFET regions, in accordance with one or more aspects of the present invention
- FIGS. 9A-9B depict the intermediate device of FIGS. 8A-8B after depositing a flowable oxide layer over the intermediate device, in accordance with one or more aspects of the present invention
- FIGS. 10A-10C depict the intermediate device of FIGS. 9A-9B after removal of the sacrificial gate structure, in accordance with one or more aspects of the present invention
- FIGS. 11A-11B depict the intermediate device of FIGS. 10A-10C after etching at least one fin into the substrate, in accordance with one or more aspects of the present invention
- FIGS. 12A-12B depict an intermediate semiconductor device during the formation of at least one fin, in accordance with one or more aspects of the present invention
- FIGS. 13A-13C depict the intermediate device of FIGS. 11A-11B after application of a barrier layer and deposition of an oxide into the gate opening, in accordance with one or more aspects of the present invention
- FIGS. 14A-14C depict the intermediate device of FIGS. 13A-13C after etching the oxide in the gate opening, in accordance with one or more aspects of the present invention
- FIGS. 15A-15D depict the intermediate device of FIGS. 14A-14C after etching the barrier layer to form an inner side wall spacer, in accordance with one or more aspects of the present invention
- FIGS. 16A-16D depict the intermediate device of FIGS. 15A-15D after a portion of the at least one fin is etched and replaced with a high mobility material, in accordance with one or more aspects of the present invention
- FIGS. 17A-17D depict the intermediate device of FIGS. 15A-15D after deposition of a dielectric layer and the gate material over the at least one fin, in accordance with one or more aspects of the present invention.
- FIG. 18 depicts the intermediate device of FIGS. 12A-12B after deposition of a dielectric layer and gate material over the at least one fin, in accordance with one or more aspects of the present invention.
- the FinFET device fabrication processes disclosed herein provide for a FinFET fabrication process with self aligned fin formation and easier fabrication of source and drain epi contacts.
- the FinFET fabrication process enables fin lines to be etched into a hard mask without etching into the substrate.
- the device has a low topology and the spacer, source and drain junction or epitaxy contact may be formed without having to work around the fin.
- the fin may be etched into the substrate during the replacement metal gate (RMG) process allowing for the fin to be self aligned to the gate.
- RMG replacement metal gate
- FinFET device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining an intermediate semiconductor device 100 ; depositing a hard mask layer over the intermediate semiconductor device 110 ; etching the hard mask layer to form at least one fin hard mask 120 ; depositing at least one sacrificial gate structure over the at least one fin hard mask and the substrate 130 ; etching the intermediate semiconductor device to remove a portion of the at least one fin hard mask using the at least one sacrificial gate structure as a mask 140 ; forming at least one pFET region and at least one nFET region 150 ; removing the at least one sacrificial gate structure to create at least one opening 160 ; etching over the at least one fin hard mask to form at least one fin and removing the at least one fin hard mask 170 ; forming a side wall spacer in the at least one opening 180 ; and depositing at least one gate material into the at least one opening 190
- FIGS. 2-18 depict, by way of example only, one detailed embodiment of a FinFET device formation process of FIG. 1 , and the resultant FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements.
- An intermediate semiconductor device 200 is schematically illustrated in FIGS. 2-18 at several intermediate stages of manufacturing.
- the terms “intermediate semiconductor device,” “intermediate device,” “semiconductor device,” and “device” may be used interchangeably herein.
- the semiconductor device 200 as shown in FIG. 2 , may have been processed through, for example, shallow trench isolation (STI) and well doping.
- the intermediate device 200 may include a substrate 202 which may be made of, for example, a semiconductor material.
- the semiconductor material may include, e.g., silicon, germanium, a compound semiconductor material, a layered semiconductor material, a silicon-on-insulator (SOI) material, a SiGe-on-insulator (SGOI) material, a germanium-on-insulator (GOI) material, and/or the like.
- the intermediate structure 200 may also include at least one shallow trench isolation (STI) region 204 in the substrate 202 .
- the intermediate structure 200 may further include a first oxide layer 206 , for example, a sacrificial gate oxide, deposited over the substrate 202 and the at least one STI region 204 .
- a fin hard mask layer 208 for example, a SiN layer, may be applied over the first oxide layer 206 .
- the intermediate device 200 may be patterned with, for example, lithography and then the fin hard mask layer may be etched to form at least one fin hard mask 210 .
- the fin hard mask layer may be etched to form at least one fin hard mask 210 .
- two fin hard masks 210 are shown in FIGS. 3A and 3B .
- the fin hard mask 210 enables the device 200 to have a low topology during spacer and junction formation.
- FIGS. 4A-4C show the intermediate device 200 after a sacrificial gate structure 212 is applied over the at least one fin hard mask 210 and a portion of the first oxide layer 206 .
- the sacrificial gate structure 212 may include a sacrificial material 214 , for example, an a-Si, a mask 216 made of, for example, SiN, and an oxide material 218 made of, for example, SiO 2 .
- the sacrificial gate structure 212 may be formed using known methods, which may include, for example, deposition, lithography, polygate etching, and cut mask etching.
- the sacrificial gate structure 212 may be used as a mask during etching of the at least one fin hard mask 210 and the first oxide layer 206 .
- the device 200 has been etched to remove a portion of the at least one fin hard mask 210 and a portion of the first oxide layer 206 .
- the sacrificial gate structure 212 preserves the portion of the at least one fin hard mask 210 and the portion of the first oxide layer 206 covered by the sacrificial gate structure 212 .
- the remaining at least one fin hard mask 210 is self-aligned with the sacrificial gate structure 212 .
- a first spacer 220 may then be applied to the side walls of the sacrificial gate structure 212 .
- the first spacer 220 may then be etched back to form the desired shape for the first spacer 220 .
- the first spacer 220 may be, for example, a SiN spacer.
- sigma etching may be performed to form the pFET regions 222 .
- epitaxial growth may then be performed in the pFET regions 222 .
- the pFET epitaxial growth may be, for example, eSiGe or any other pFET material.
- a second spacer 224 may be applied over the first spacer 220 to the side of the sacrificial gate structure 212 .
- the second spacer 224 may then be etched back to form the desired shape second spacer 224 .
- the second spacer 224 may be, for example, a SiN spacer.
- sigma etching may be performed to form the nFET regions 226 .
- epitaxial growth may be performed in the nFET regions 226 .
- the nFET expitaxial growth may be, for example, SiP or any other nFET material.
- a flowable oxide layer 228 may then be deposited over the device 200 and the surface of the device 200 may be planarized, as shown in FIGS. 9A-9B .
- the flowable oxide layer 228 may be, for example, a flowable chemical vapor deposition (FCVD) oxide or DUOTM.
- FCVD flowable chemical vapor deposition
- DUOTM DUOTM.
- Planarization of the device 200 may be performed by, for example, chemical mechanical planarization (CMP).
- the replacement metal gate (RMG) process may be performed.
- the RMG process may include etching the sacrificial gate structure 212 to remove the mask 216 and the oxide material 218 to create an opening 230 between the first spacer 220 .
- the fin hard mask 210 is revealed.
- etching may be performed using the fin hard mask 210 to etch into the substrate 202 to form at least one fin 232 .
- the fin is self-aligned to the gate.
- the fin hard mask 210 may be removed as well as the first oxide layer 206 , as shown in FIGS. 11A-11B .
- an intermediate device 250 with a silicon on insulator (SOI) substrate 202 may also be used. Dry anistropic etching may be performed on the intermediate device 250 to form the at least one fin 232 , as shown in FIGS. 12A-12B . Then the fin hard mask 210 may be removed, as shown in FIG. 12B .
- SOI silicon on insulator
- FIGS. 13A-13C show the intermediate device 200 with a thin barrier layer 234 applied over the flowable oxide layer 228 and into the opening 230 .
- the barrier layer 234 may be, for example, SiN.
- an oxide 236 may be deposited over the barrier layer 234 of the device 200 to fill the rest of the opening 230 .
- the device 200 may be planarized to remove any extra oxide 236 over the barrier layer 234 on the top surface of the device 200 by, for example, CMP.
- the oxide 236 may then be etched back to reveal the tip of the at least one fin 232 .
- a portion of the oxide 236 may remain in the bottom of the openings 230 for isolation, as shown in FIG. 14C .
- the barrier layer 234 may be etched to form an inner side wall spacer 238 and to reveal the fins 232 , as shown in FIGS. 15A-15D .
- the inner spacer 238 may be aligned at least partially with the first and second spacers 220 , 224 , as shown in FIGS. 15B-15C .
- the inner spacer 238 may be, for example, wider at the top of the opening 230 and narrower at the bottom of the opening 230 , as shown in FIG. 15B . This shape may enable better deposition of the gate material.
- the fins 232 of the device 200 may include high mobility channels 240 made of high mobility materials.
- the high mobility materials for the channels 240 may include, for example, SiGe or other materials from Groups III-V. If high mobility channels 240 are desired for the device 200 , then a portion of the revealed fins 232 may be etched away. Next an epitaxy process may be performed to grow new channels 240 in place of the removed portions of the fins 232 .
- the gate deposition process may be performed, as shown in FIGS. 17A-17D .
- the gate deposition process may include applying a dielectric layer 242 over the fins 232 , as shown in FIGS. 17B and 17D .
- the dielectric layer 242 may be, for example, a high-k dielectric material, such as an oxide.
- a gate material 244 may be deposited into the opening 230 over the dielectric layer 242 .
- the gate material 244 may be, for example, a metal gate, a polysilicon gate, or any other known gate material.
- CMP may be performed to remove any extra material on the surface of the device 200 left during depositing of the gate material 244 .
- the device 250 with a SOI substrate may skip the fabrication steps described above with reference to FIGS. 13A-15D for exposing the fins 232 and proceed to gate deposition.
- a dielectric layer 242 may be deposited over the fins 232 .
- a gate material 244 may be deposited over the device 250 .
- CMP may be performed on the device to remove any extra material left on the device during deposition of the gate material 244 and stopping on the flowable oxide layer 228 .
- the devices 200 , 250 may be passed to MOL and BEOL processes to continue with the fabrication process. If silicidation is performed on the devices 200 , 250 , it may be performed as it would be on a planar device making the silicidation process easier than the silicidation process performed during conventional FinFET fabrication.
- a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
- a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
- a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
Abstract
Description
- This application is a divisional of U.S. application Ser. No. 14/043,243 filed Oct. 1, 2013, which is hereby incorporated herein by reference in its entirety.
- The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to FinFETs and methods of fabricating semiconductor devices with self aligned fin formation and a source and drain junction compatible with planar fabrication processes.
- Conventional planar MOSFET devices have been scaling down over the last few decades to provide higher integration density, higher operation speed and lower cost. However, the scaling down of MOSFET devices is restricted by the short channel effect which causes a high leakage current. In order to counteract the short channel effect, FinFETs have started being used due to the FinFETs stronger gate electrostatic control over the channel which can mitigate the short channel effect. However, the fabrication of FinFETs is more challenging than conventional planar device fabrication because of the high topology of the fins.
- During conventional FinFET fabrication, the fin is formed first. Then the gate, spacer and junction/contact may be formed. As the gate, spacer and junction are formed they must be formed over and around the high topology fins. The high topology fins may cause challenges during deposition, lithography and etching to form the gate, spacer, and junction. Further, epitaxy must be grown on the three dimensional fin rather than the previous two dimensional planar substrate, this results in less epitaxy volume on the three dimensional fin than was previously on the planar substrate thereby limiting the stress enhancement. With a limited epitaxy volume on the three dimensional fins, the silicidation cannot consume too much epitaxy material. Currently, titanium silicide is being used because it consumes less epitaxy, however titanium silicide has poor contact properties.
- Thus, the fabrication of FinFET devices can be problematic with existing fabrication techniques and improved FinFET fabrication techniques are needed for forming FinFET devices to improve the performance of the resultant semiconductors.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, a method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate.
- In another aspect, an intermediate semiconductor device which includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
- One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 depicts one embodiment of a process for fabricating, for instance, semiconductor devices with self aligned fin formation and source and drain contact compatible with the planar process, in accordance with one or more aspects of the present invention; -
FIG. 2 depicts one embodiment of an intermediate semiconductor device with a fin hard mask layer applied over the device, in accordance with one or more aspects of the present invention; -
FIGS. 3A-3B depict the intermediate device ofFIG. 2 after etching to create at least one fin hard mask, in accordance with one or more aspects of the present invention; -
FIGS. 4A-4C depict the intermediate device ofFIGS. 3A-3B after forming a sacrificial gate structure over the at least one fin hard mask, in accordance with one or more aspects of the present invention; -
FIGS. 5A-5C depict the intermediate device ofFIGS. 4A-4C after etching of the at least one fin hard mask and a portion of the first oxide layer, in accordance with one or more aspects of the present invention; -
FIGS. 6A-6B depict the intermediate device ofFIGS. 5A-5C after application of a first spacer to the side walls of the sacrificial gate structure, in accordance with one or more aspects of the present invention; -
FIGS. 7A-7B depict the intermediate device ofFIGS. 6A-6B after performing sigma etching to form the pFET regions, in accordance with one or more aspects of the present invention; -
FIGS. 8A-8B depict the intermediate device ofFIGS. 7A-7B after application of a second spacer and performing sigma etching to form the nFET regions, in accordance with one or more aspects of the present invention; -
FIGS. 9A-9B depict the intermediate device ofFIGS. 8A-8B after depositing a flowable oxide layer over the intermediate device, in accordance with one or more aspects of the present invention; -
FIGS. 10A-10C depict the intermediate device ofFIGS. 9A-9B after removal of the sacrificial gate structure, in accordance with one or more aspects of the present invention; -
FIGS. 11A-11B depict the intermediate device ofFIGS. 10A-10C after etching at least one fin into the substrate, in accordance with one or more aspects of the present invention; -
FIGS. 12A-12B depict an intermediate semiconductor device during the formation of at least one fin, in accordance with one or more aspects of the present invention; -
FIGS. 13A-13C depict the intermediate device ofFIGS. 11A-11B after application of a barrier layer and deposition of an oxide into the gate opening, in accordance with one or more aspects of the present invention; -
FIGS. 14A-14C depict the intermediate device ofFIGS. 13A-13C after etching the oxide in the gate opening, in accordance with one or more aspects of the present invention; -
FIGS. 15A-15D depict the intermediate device ofFIGS. 14A-14C after etching the barrier layer to form an inner side wall spacer, in accordance with one or more aspects of the present invention; -
FIGS. 16A-16D depict the intermediate device ofFIGS. 15A-15D after a portion of the at least one fin is etched and replaced with a high mobility material, in accordance with one or more aspects of the present invention; -
FIGS. 17A-17D depict the intermediate device ofFIGS. 15A-15D after deposition of a dielectric layer and the gate material over the at least one fin, in accordance with one or more aspects of the present invention; and -
FIG. 18 depicts the intermediate device ofFIGS. 12A-12B after deposition of a dielectric layer and gate material over the at least one fin, in accordance with one or more aspects of the present invention. - Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
- Generally stated, disclosed herein are certain novel FinFET device formation methods and FinFET structures, which provide advantages over the above noted, existing FinFET device fabrication processes and structures. Advantageously, the FinFET device fabrication processes disclosed herein provide for a FinFET fabrication process with self aligned fin formation and easier fabrication of source and drain epi contacts. The FinFET fabrication process enables fin lines to be etched into a hard mask without etching into the substrate. Thus, during fabrication the device has a low topology and the spacer, source and drain junction or epitaxy contact may be formed without having to work around the fin. After the spacer and source and drain are formed, the fin may be etched into the substrate during the replacement metal gate (RMG) process allowing for the fin to be self aligned to the gate.
- In one aspect, in one embodiment, as shown in
FIG. 1 , FinFET device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining anintermediate semiconductor device 100; depositing a hard mask layer over theintermediate semiconductor device 110; etching the hard mask layer to form at least one finhard mask 120; depositing at least one sacrificial gate structure over the at least one fin hard mask and thesubstrate 130; etching the intermediate semiconductor device to remove a portion of the at least one fin hard mask using the at least one sacrificial gate structure as amask 140; forming at least one pFET region and at least onenFET region 150; removing the at least one sacrificial gate structure to create at least oneopening 160; etching over the at least one fin hard mask to form at least one fin and removing the at least one finhard mask 170; forming a side wall spacer in the at least oneopening 180; and depositing at least one gate material into the at least oneopening 190. -
FIGS. 2-18 depict, by way of example only, one detailed embodiment of a FinFET device formation process ofFIG. 1 , and the resultant FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements. - An
intermediate semiconductor device 200 is schematically illustrated inFIGS. 2-18 at several intermediate stages of manufacturing. The terms “intermediate semiconductor device,” “intermediate device,” “semiconductor device,” and “device” may be used interchangeably herein. Thesemiconductor device 200, as shown inFIG. 2 , may have been processed through, for example, shallow trench isolation (STI) and well doping. As depicted inFIG. 2 , theintermediate device 200 may include asubstrate 202 which may be made of, for example, a semiconductor material. The semiconductor material may include, e.g., silicon, germanium, a compound semiconductor material, a layered semiconductor material, a silicon-on-insulator (SOI) material, a SiGe-on-insulator (SGOI) material, a germanium-on-insulator (GOI) material, and/or the like. Theintermediate structure 200 may also include at least one shallow trench isolation (STI)region 204 in thesubstrate 202. Theintermediate structure 200 may further include afirst oxide layer 206, for example, a sacrificial gate oxide, deposited over thesubstrate 202 and the at least oneSTI region 204. A finhard mask layer 208, for example, a SiN layer, may be applied over thefirst oxide layer 206. - As shown in
FIGS. 3A-3B , theintermediate device 200 may be patterned with, for example, lithography and then the fin hard mask layer may be etched to form at least one finhard mask 210. By way of specific example, two finhard masks 210 are shown inFIGS. 3A and 3B . The finhard mask 210 enables thedevice 200 to have a low topology during spacer and junction formation. -
FIGS. 4A-4C show theintermediate device 200 after asacrificial gate structure 212 is applied over the at least one finhard mask 210 and a portion of thefirst oxide layer 206. Thesacrificial gate structure 212 may include asacrificial material 214, for example, an a-Si, amask 216 made of, for example, SiN, and anoxide material 218 made of, for example, SiO2. Thesacrificial gate structure 212 may be formed using known methods, which may include, for example, deposition, lithography, polygate etching, and cut mask etching. - After the
sacrificial gate structure 212 is applied over the at least one finhard mask 210, thesacrificial gate structure 212 may be used as a mask during etching of the at least one finhard mask 210 and thefirst oxide layer 206. As shown inFIGS. 5A-5C , thedevice 200 has been etched to remove a portion of the at least one finhard mask 210 and a portion of thefirst oxide layer 206. Thesacrificial gate structure 212 preserves the portion of the at least one finhard mask 210 and the portion of thefirst oxide layer 206 covered by thesacrificial gate structure 212. As thedevice 200 is etched the remaining at least one finhard mask 210 is self-aligned with thesacrificial gate structure 212. - As shown in
FIGS. 6A-6B , afirst spacer 220 may then be applied to the side walls of thesacrificial gate structure 212. Thefirst spacer 220 may then be etched back to form the desired shape for thefirst spacer 220. For a pFET region, thefirst spacer 220 may be, for example, a SiN spacer. Next, as shown inFIGS. 7A-7B , sigma etching may be performed to form thepFET regions 222. After thepFET regions 222 are etched, epitaxial growth may then be performed in thepFET regions 222. The pFET epitaxial growth may be, for example, eSiGe or any other pFET material. - Next, as shown in
FIGS. 8A-8B , asecond spacer 224 may be applied over thefirst spacer 220 to the side of thesacrificial gate structure 212. Thesecond spacer 224 may then be etched back to form the desired shapesecond spacer 224. For an nFET region, thesecond spacer 224 may be, for example, a SiN spacer. Then sigma etching may be performed to form thenFET regions 226. Next, epitaxial growth may be performed in thenFET regions 226. The nFET expitaxial growth may be, for example, SiP or any other nFET material. - A
flowable oxide layer 228 may then be deposited over thedevice 200 and the surface of thedevice 200 may be planarized, as shown inFIGS. 9A-9B . Theflowable oxide layer 228 may be, for example, a flowable chemical vapor deposition (FCVD) oxide or DUO™. Planarization of thedevice 200 may be performed by, for example, chemical mechanical planarization (CMP). - As shown in
FIGS. 10A-10C , the replacement metal gate (RMG) process may be performed. The RMG process may include etching thesacrificial gate structure 212 to remove themask 216 and theoxide material 218 to create anopening 230 between thefirst spacer 220. When themask 216 and theoxide material 218 are etched the finhard mask 210 is revealed. Once the finhard mask 210 is revealed, etching may be performed using the finhard mask 210 to etch into thesubstrate 202 to form at least onefin 232. As the at least onefin 232 is formed during the RMG process the fin is self-aligned to the gate. After the at least onefin 232 is etched into thesubstrate 202, the finhard mask 210 may be removed as well as thefirst oxide layer 206, as shown inFIGS. 11A-11B . - By way of specific example, an
intermediate device 250 with a silicon on insulator (SOI)substrate 202 may also be used. Dry anistropic etching may be performed on theintermediate device 250 to form the at least onefin 232, as shown inFIGS. 12A-12B . Then the finhard mask 210 may be removed, as shown inFIG. 12B . -
FIGS. 13A-13C show theintermediate device 200 with athin barrier layer 234 applied over theflowable oxide layer 228 and into theopening 230. Thebarrier layer 234 may be, for example, SiN. Then anoxide 236 may be deposited over thebarrier layer 234 of thedevice 200 to fill the rest of theopening 230. Next thedevice 200 may be planarized to remove anyextra oxide 236 over thebarrier layer 234 on the top surface of thedevice 200 by, for example, CMP. - As shown in
FIGS. 14A-14C , theoxide 236 may then be etched back to reveal the tip of the at least onefin 232. A portion of theoxide 236 may remain in the bottom of theopenings 230 for isolation, as shown inFIG. 14C . Next thebarrier layer 234 may be etched to form an innerside wall spacer 238 and to reveal thefins 232, as shown inFIGS. 15A-15D . Theinner spacer 238 may be aligned at least partially with the first andsecond spacers FIGS. 15B-15C . Theinner spacer 238 may be, for example, wider at the top of theopening 230 and narrower at the bottom of theopening 230, as shown inFIG. 15B . This shape may enable better deposition of the gate material. - In one embodiment, as shown in
FIGS. 16A-16D , thefins 232 of thedevice 200 may includehigh mobility channels 240 made of high mobility materials. The high mobility materials for thechannels 240 may include, for example, SiGe or other materials from Groups III-V. Ifhigh mobility channels 240 are desired for thedevice 200, then a portion of the revealedfins 232 may be etched away. Next an epitaxy process may be performed to grownew channels 240 in place of the removed portions of thefins 232. - Once the
fins 232 are revealed, the gate deposition process may be performed, as shown inFIGS. 17A-17D . The gate deposition process may include applying adielectric layer 242 over thefins 232, as shown inFIGS. 17B and 17D . Thedielectric layer 242 may be, for example, a high-k dielectric material, such as an oxide. Next agate material 244 may be deposited into theopening 230 over thedielectric layer 242. Thegate material 244 may be, for example, a metal gate, a polysilicon gate, or any other known gate material. Then CMP may be performed to remove any extra material on the surface of thedevice 200 left during depositing of thegate material 244. - As shown in
FIG. 18 , thedevice 250 with a SOI substrate may skip the fabrication steps described above with reference toFIGS. 13A-15D for exposing thefins 232 and proceed to gate deposition. As described above with reference toFIGS. 17A-17D , adielectric layer 242 may be deposited over thefins 232. Then agate material 244 may be deposited over thedevice 250. After thegate material 244 is applied, CMP may be performed on the device to remove any extra material left on the device during deposition of thegate material 244 and stopping on theflowable oxide layer 228. - Following the gate deposition processes, shown in
FIGS. 17A-18 , thedevices devices - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (16)
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US9236397B2 (en) * | 2014-02-04 | 2016-01-12 | Globalfoundries Inc. | FinFET device containing a composite spacer structure |
US9263580B2 (en) * | 2014-03-24 | 2016-02-16 | Globalfoundries Inc. | Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device |
US9570554B2 (en) * | 2014-04-04 | 2017-02-14 | International Business Machines Corporation | Robust gate spacer for semiconductor devices |
US9209095B2 (en) * | 2014-04-04 | 2015-12-08 | International Business Machines Corporation | III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method |
US9087720B1 (en) * | 2014-08-04 | 2015-07-21 | Globalfoundries Inc. | Methods for forming FinFETs with reduced series resistance |
US9917195B2 (en) * | 2015-07-29 | 2018-03-13 | International Business Machines Corporation | High doped III-V source/drain junctions for field effect transistors |
US10090385B1 (en) | 2017-03-31 | 2018-10-02 | Globalfoundries Inc. | Methods of forming a vertical transistor device with a channel structure comprised of alternative semiconductor materials |
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US8513107B2 (en) * | 2010-01-26 | 2013-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement gate FinFET devices and methods for forming the same |
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