US20150311276A1 - Semiconductor devices having self-aligned contact pads and methods of manufacturing the same - Google Patents
Semiconductor devices having self-aligned contact pads and methods of manufacturing the same Download PDFInfo
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- US20150311276A1 US20150311276A1 US14/529,500 US201414529500A US2015311276A1 US 20150311276 A1 US20150311276 A1 US 20150311276A1 US 201414529500 A US201414529500 A US 201414529500A US 2015311276 A1 US2015311276 A1 US 2015311276A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Definitions
- Various embodiments described herein relate to semiconductor devices, methods of manufacturing semiconductor devices, and electronic devices and electronic systems adopting the same.
- Various embodiments described herein can provide semiconductor devices capable of reducing or preventing contact misalignment.
- Other embodiments can provide semiconductor devices having damascene bit lines.
- Other embodiments can provide methods of manufacturing semiconductor devices capable of reducing or preventing contact misalignment.
- Other embodiments can provide methods of manufacturing semiconductor devices having damascene bit lines.
- a semiconductor device including a substrate having a field area that defines active areas; gate trenches extending in a first direction in the substrate; buried gates in the gate trenches; gate capping fences in, and in some embodiments filling, the gate trenches over a respective buried gate, protruding from top surfaces of the active areas, and extending in the first direction; bit line trenches crossing the gate capping fences and extending in a second direction perpendicular to the first direction in the gate capping fence; insulator structures on inner walls of a respective bit line trench; bit lines and bit line capping patterns stacked on the insulator structures in, and in some embodiments to fill, a respective bit line trench; contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines; and a lower electrode of a capacitor on a respective contact pad.
- a top surface of the contact pad may be located at substantially the same level as a top surface of the gate capping fence.
- a depth of the bit line trench may be greater than or equal to a protruding height of the gate capping fence from a top surface of the active area.
- a top surface of the bit line may be located at a lower level than the top surface of the active area.
- the top surface of the bit line may be located at a higher level than the top surface of the active area.
- a top surface of the bit line capping pattern may be located at substantially the same level as the top surface of the gate capping fence.
- the insulator structure may include an insulating layer, an air gap, or a multi-structure having an insulating layer and an air gap.
- a method of manufacturing a semiconductor device including forming a field area in a substrate to define active areas; forming gate trenches extending in a first direction in the substrate; forming buried gates in a respective gate trench; forming gate capping fences in, and in some embodiments filling, the gate trenches over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction; forming line-shaped pad patterns self-aligned with the gate capping fences and extending in the first direction on the substrate; forming contact pads and bit line trenches by patterning a part of the pad patterns and the gate capping fences to expose at least some areas of the substrate between the adjacent gate capping fences, each contact pad being formed on the substrate between the adjacent bit line trenches and a respective bit line trench extending in a second direction perpendicular to the first direction; forming a bit line in a respective bit line trench; and forming a lower electrode
- the formation of the line-shaped pad patterns self-aligned with the gate capping fences and extending in the first direction may include forming a pad conductive layer on a surface, and in some embodiments on an entire surface, of the substrate, and partially removing the pad conductive layer until a top surface of the gate capping fence is exposed.
- a top surface of the line-shaped pad pattern may be located at substantially the same level as the top surface of the gate capping fence.
- the formation of the contact pads and the bit line trenches may include forming mask patterns extending in the second direction and defining bit line forming areas, on the substrate on which the line-shaped pad patterns are formed, forming the contact pads and the bit line trenches by etching the exposed areas of the pad patterns and some areas of the gate capping fences using the mask patterns, and removing the mask patterns.
- Insulator structures may further be formed on inner walls of a respective bit line trench.
- a respective insulator structure may include an insulating layer, an air gap, or a multi-structure having an insulating layer and an air gap.
- Bit line capping patterns may further be formed in the bit line trenches over each bit line. Top surfaces of the bit line capping patterns may be located at substantially the same level as top surfaces of the gate capping fences.
- Yet other embodiments may be realized by providing a method of manufacturing a semiconductor device, the method comprising: forming spaced-apart line-shaped structures that extend in a first direction of a substrate, the spaced-apart line-shaped structures comprising gate trenches in the substrate having buried gates therein and gate capping fences thereon that protrude from the substrate; forming line-shaped pad patterns that extend in the first direction, between the spaced-apart line-shaped structures; forming a mask pattern on the gate capping fences and on the line-shaped pad patterns to define spaced-apart line-shaped mask openings that extend in a second direction perpendicular to the first direction; and etching portions of the line-shaped pad patterns and the gate capping fences that are exposed by the mask openings to form contact pads from the line-shaped pad patterns and to form trenches in the gate capping fences that extend in the second direction.
- the formation of the line-shaped pad patterns may include forming a pad conductive layer on the spaced-apart line-shaped structures and between the spaced-apart line-shaped structures; and removing the pad conductive layer until top surfaces of the gate capping fences are exposed to form the line-shaped pad patterns.
- the method may further comprise forming a bit line in a respective bit line trench.
- the method may further comprise forming a lower electrode of a capacitor directly on a respective contact pad.
- the following may be performed between the etching and the forming a bit line: forming an insulating layer including an air gap on walls of the bit line trenches.
- FIG. 1 is a plan view showing a memory cell area of a semiconductor device in accordance with an embodiment
- FIG. 2 is a cross-sectional view of a semiconductor device taken along line V-V′ of FIG. 1 in accordance with an embodiment
- FIGS. 3 to 10 are cross-sectional views of semiconductor devices taken along the line V-V′ of FIG. 1 in accordance with other embodiments;
- FIGS. 11A to 19D and 20 to 27 are cross-sectional views and plan views of a method of manufacturing a semiconductor device in accordance with an embodiment, and the drawings A, B, C, and D included in each of the FIGS. 11 to 19 are cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ of FIG. 1 , respectively;
- FIGS. 28A to 28D are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with the another embodiment.
- FIG. 29 is a block diagram of an electronic system having the semiconductor devices in accordance with various embodiments.
- inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concepts are shown.
- inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the inventive concepts to one skilled in the art.
- first element when referred to as being “on” a second element, the first element may be directly on the second element, or one or more other elements may be interposed between the first element and the second element.
- top surface such as “top surface”, “bottom surface”, “upper end,” “lower end,” “upper surface,” “lower surface,” “upper part,” “lower part,” and the like, may be used herein for ease of description to distinguish relative locations of elements.
- the upper part when an upper part is used as a top in the drawing and a lower part is used as a bottom in the drawing for convenience, the upper part could be termed the lower part and the lower part could be termed the upper part without departing from the scope of the present inventive concepts.
- FIG. 1 is a plan view showing a memory cell area of a semiconductor device in accordance with an embodiment.
- FIG. 2 is a cross-sectional view of a semiconductor device taken along line V-V′ of FIG. 1 in accordance with an embodiment.
- the semiconductor device in accordance with the embodiment may include a substrate 100 having active areas 101 defined by field areas 102 . Buried gates 112 extending in a first direction may be formed in the substrate 100 . Bit lines 142 extending in a second direction perpendicular to the first direction may be formed in the substrate 100 . Contact pads 122 a may be formed on the substrate 100 between the adjacent bit lines 142 . Lower electrodes 150 of a capacitor may be formed on each contact pad 122 a.
- the substrate 100 may comprise a semiconductor substrate.
- the substrate 100 may comprise a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like.
- the field area 102 may be formed in the substrate 100 and define the plurality of active areas 101 .
- the field area 102 may be a shallow trench isolation (STI) area.
- the field area 102 may include a field trench formed in the substrate 100 , and a field insulating layer filling the field trench.
- the field insulating layer may include a single layer of silicon oxide or a composite layer having silicon oxide and silicon nitride according to a width of the field trench.
- Each active area 101 may be formed to have a major axis and a minor axis, and arranged two-dimensionally in directions of the major and minor axes.
- each active area 101 may have a bar shape in which a length is greater than a width.
- the active areas 101 may be oriented such that their major axes are oblique with respect to the buried gates 112 and the bit lines 142 .
- One active area 101 may intersect two buried gates 112 and one bit line 142 , and thus, one active area 101 may have a structure of two unit cells.
- One unit cell may have a length of 2F in the first direction and a length of 4F in the second direction, and have an area of 6F2.
- F refers to a minimum feature size.
- the semiconductor device in accordance with the embodiments may not be limited to the 6F2 cell structure, and the active areas 101 may also be formed in an 8F2 cell structure in which the active areas 101 intersects the buried gates 112 at right angles. Further, it is apparent that any cell structures capable of improving a degree of integration of the semiconductor device may also be included.
- Each buried gate 112 may be formed in a lower part of a gate trench 108 with a gate insulating layer 110 therebetween, the gate trench extending in the first direction and being formed in the substrate 100 .
- Upper parts of the gate trenches 108 over each buried gate 112 may be filled with gate capping fences 114 a .
- the gate capping fence 114 a may be formed to have a line shape extending in the first direction along the buried gate 112 .
- the gate capping fence 114 a may protrude from a top surface TSa of the active area 101 by a first height h 1 .
- the buried gate 112 may include poly-silicon, a metal or metal nitride, such as tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a composite layer thereof.
- the gate insulating layer 110 may include silicon oxide, an insulating material having a high dielectric constant or a combination thereof.
- the gate capping fence 114 a may include silicon nitride.
- first and second impurity areas 115 a and 115 b provided as source/drain areas of a cell transistor may be formed in the active areas 101 on both sides of each buried gate 112 .
- the first impurity area 115 a may be formed in the active area 101 between the buried gate 112 and the field area 102 .
- the first impurity area 115 a may be electrically connected to the lower electrode 150 of the capacitor through the contact pad 122 a .
- the second impurity area 115 b may be formed in the active area 101 between a pair of buried gates 112 .
- the second impurity area 115 b may be electrically connected to the bit line 142 .
- the second impurity area 115 b may be formed deeper than the first impurity area 115 a.
- Bit line trenches 128 crossing the gate capping fences 114 a and extending in the second direction perpendicular to the first direction may be formed in the gate capping fences 114 a .
- the bit line trench 128 may be formed by a damascene process using the gate capping fences 114 a protruding from a level of the active area 101 .
- the bit line trench 128 may be formed to have a depth greater than or equal to a protruding height of the gate capping fence 114 a from the top surface TSa of the active area 101 .
- the bit line 142 may be formed in a lower part of the bit line trench 128 .
- the bit line 142 may be formed as a structure fully or partially buried in the substrate 100 or a structure disposed on the substrate 100 , according to the depth of the bit line trench 128 .
- a top surface TSb of the bit line 142 may be located at a lower level than the top surface TSa of the active area 101 , the bit line 142 may be formed to have a structure fully buried in the substrate 100 .
- a bottom surface BSt of the bit line trench 128 may be controlled to ensure a stable separation between the bit line 142 and the buried gate 112 . Since the bit line 142 may be formed by a damascene process, a fine pattern can be implemented by overcoming a pattern limitation of a photolithography process.
- bit line capping patterns 144 Upper parts of the bit line trenches 128 over each bit line 142 may be filled with bit line capping patterns 144 .
- a top surface TSc of the bit line capping pattern 144 may be located at substantially the same level as a top surface TSf of the gate capping fence 114 a .
- the bit line 142 may include a low-resistance metal such as tungsten (W), titanium nitride (TiN), or the like.
- the bit line capping patterns 144 may include silicon nitride.
- Each of insulator structures 130 a may be formed on an inner wall of each bit line trench 128 .
- the insulator structures 130 a may be formed to expose source/drain areas in the active area 101 , for example, the second impurity area 115 b , and to extend in the first direction along the inner wall of the bit line trench 128 .
- the insulator structures 130 a may stably separate the contact pad 122 a from the bit line 142 .
- the insulator structure 130 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap of which dielectric constant is 1, to thereby reduce parasitic capacitance between the bit line 142 and the lower electrode 150 of the capacitor.
- the contact pad 122 a may be self-aligned with the gate capping fence 114 a and formed on the substrate 100 between the adjacent bit lines 142 .
- the contact pad 122 a may be electrically connected to the first impurity area 115 a in the active area 101 .
- the lower electrode 150 of the capacitor may be directly formed on the contact pad 122 a , which is self-aligned with the gate capping fence 114 a , without a contact hole, to thereby prevent contact misalignment.
- a top surface TSp of the contact pad 122 a may be located at substantially the same level as the top surface TSf of the gate capping fence 114 a .
- the contact pad 122 a may be stably separated from the bit line 142 by the gate capping fence 114 a and the insulator structure 130 a .
- the contact pad 122 a may include a metal, such as tungsten (W), titanium nitride (TiN), or the like, doped poly-silicon, or a multi-layer structure having a metal and poly-silicon.
- a metal silicide layer for an ohmic contact, or a barrier metal layer such as a metal oxide or the like may be formed between a surface of the active area 101 and the contact pad 122 a.
- the lower electrode 150 of the capacitor formed on the contact pad 122 a may be stably separated from the bit line 142 by the gate capping fence 114 a and the insulator structure 130 a . Due to the gate capping fence 114 a and the insulator structure 130 a , scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between the lower electrode 150 of the capacitor and the bit line 142 .
- FIGS. 3 to 10 are cross-sectional views of semiconductor devices taken along the line V-V′ of FIG. 1 in accordance with other embodiments.
- the above-described embodiments and repeated parts will be omitted, and modified parts will be mainly described.
- a gate capping fence 114 a covering a top surface of a buried gate 112 formed in a substrate 100 may extend in a first direction along the buried gate 112 , and protrude from a top surface TSa of an active area 101 by a first height h 1 .
- a bit line trench 128 crossing the gate capping fences 114 a and extending in a second direction perpendicular to the first direction may be formed in the gate capping fence 114 a .
- the bit line trench 128 may be formed to have a first depth d 1 greater than the protruding height h 1 of the gate capping fence 114 a.
- bit line 142 As a top surface TSb of a bit line 142 in the bit line trench 128 is located at a lower level than the top surface TSa of the active area 101 , the bit line 142 may be formed as a structure fully buried in the substrate 100 .
- An insulator structure 130 b extending in the first direction along an inner wall of the bit line trench 128 may be formed as a multi-layer structure having an insulating layer 134 and an air gap 135 .
- the insulating layer 134 may include an insulating material having a low dielectric constant such as silicon oxide or the like.
- an insulator structure 130 c extending in a first direction along an inner wall of a bit line trench 128 may be formed as a multi-layer structure having a first insulating layer 131 , an air gap 136 , and a second insulating layer 133 .
- Each of the first and second insulating layers 131 and 133 may include a low dielectric constant insulating material such as silicon oxide or the like.
- the bit line trench 128 may be formed to have a first depth d 1 greater than a protruding height h 1 of a gate capping fence 114 a .
- a top surface TSb of a bit line 142 formed in the bit line trench 128 is located at a lower level than a top surface TSa of an active area 101 , the bit line 142 may be formed as a structure fully buried in the substrate 100 .
- the semiconductor device in accordance with another embodiment may include a substrate 200 having active areas 201 defined by a field area 202 .
- Buried gates 212 extending in a first direction may be formed in the substrate 200 .
- Bit lines 242 extending in a second direction perpendicular to the first direction may be formed in and on the substrate 200 .
- Contact pads 222 a may be formed on the substrate 200 between the adjacent bit lines 242 .
- Lower electrodes 250 of a capacitor may be formed on each contact pad 222 a.
- the buried gate 212 may be formed in a lower part of a gate trench 208 extending in the first direction and formed in the substrate 200 , with a gate insulating layer 210 therebetween.
- An upper part of the gate trench 208 may be filled with a gate capping fence 214 a over the buried gate 212 .
- the gate capping fence 214 a may be formed to have a line shape extending in the first direction along the buried gate 212 , and protrude from a top surface TSa of the active area 201 by a second height h 2 .
- First and second impurity areas 215 a and 215 b provided as source/drain areas of a cell transistor may be formed in the active areas 201 on both sides of each buried gate 212 .
- the first impurity area 215 a may be formed in the active area 201 between the buried gate 212 and the field area 202 .
- the first impurity area 215 a may be electrically connected to the lower electrode 250 of the capacitor through the contact pad 222 a .
- the second impurity area 215 b may be formed in the active area 201 between a pair of buried gates 212 .
- the second impurity area 215 b may be electrically connected to the bit line 242 .
- the second impurity area 215 b may be formed deeper than the first impurity area 215 a.
- a bit line trench 228 crossing the gate capping fence 214 a and extending in the second direction perpendicular to the first direction may be formed in the gate capping fence 214 a .
- the bit line trench 228 may be formed to have a second depth d 2 greater than the protruding height h 2 of the gate capping fence 214 a.
- An insulator structure 230 a may be formed along an inner wall of the bit line trench 228 .
- the bit line trench 228 may be filled with the bit line 242 and a bit line capping pattern 244 .
- As a top surface TSb of the bit line 242 may be located at a higher level than the top surface TSa of the active area 201 , the bit line 242 may be formed as a structure partially buried in the substrate 200 .
- the insulator structure 230 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap, or both, to prevent parasitic capacitance between the bit line 242 and the lower electrode 250 of the capacitor.
- a low dielectric constant e.g., silicon oxide and the like, or an air gap, or both
- the contact pad 222 a may be self-aligned with the gate capping fence 214 a .
- the contact pad 222 a may be electrically connected to the first impurity area 215 a in the active area 201 .
- the lower electrode 250 of the capacitor may be directly formed on the contact pad 222 a , which is self-aligned with the gate capping fence 214 a , without a contact hole, to prevent contact misalignment.
- Scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between the lower electrode 250 of the capacitor and the bit line 242 by the gate capping fence 214 a and the insulator structure 230 a.
- a gate capping fence 214 a covering a top surface of a buried gate 212 formed in a substrate 200 may extend in a first direction along the buried gate 212 , and protrude from a top surface TSa of an active area 201 by a second height h 2 .
- a bit line trench 228 crossing the gate capping fences 214 a and extending in the second direction perpendicular to the first direction may be formed in the gate capping fence 214 a .
- the bit line trench 228 may be formed to have a second depth d 2 greater than the protruding height h 2 of the gate capping fence 214 a.
- bit line 242 in the bit line trench 228 may be located at a higher level than the top surface TSa of the active area 201 , the bit line 242 may be formed as a structure partially buried in the substrate 200 .
- An insulator structure 230 b extending in the first direction along an inner wall of the bit line trench 228 may be formed as a multi-layer structure having an insulating layer 234 and an air gap 235 .
- the insulating layer 234 may include a low dielectric constant insulating material such as silicon oxide or the like.
- an insulator structure 230 c extending in a first direction along an inner wall of a bit line trench 228 may be formed as a multi-layer structure having a first insulating layer 231 , an air gap 236 , and a second insulating layer 233 .
- Each of the first and second insulating layers 231 and 233 may include a low dielectric constant insulating material such as silicon oxide or the like.
- the bit line trench 228 may be formed to have a second depth d 2 greater than a protruding height h 2 of a gate capping fence 214 a .
- a top surface TSb of a bit line 242 formed in the bit line trench 228 may be located at a higher level than a top surface TSa of an active area 201 , the bit line 242 may be formed as a structure partially buried in the substrate 200 .
- the semiconductor device in accordance with another embodiment may include a substrate 300 having active areas 301 defined by a field area 302 .
- Buried gates 312 extending in a first direction may be formed in the substrate 300 .
- Bit lines 342 extending in a second direction perpendicular to the first direction may be formed in the substrate 300 .
- Contact pads 322 a may be formed on the substrate 300 between the adjacent bit lines 342 .
- Lower electrodes 350 of a capacitor may be formed on each contact pad 322 a.
- the buried gate 312 may be formed in a lower part of a gate trench 308 extending in the first direction and formed in the substrate 300 with a gate insulating layer 310 therebetween.
- An upper part of the gate trench 308 may be filled with a gate capping fence 314 a over the buried gate 312 .
- the gate capping fence 314 a may be formed to have a line shape extending in the first direction along the buried gate 312 , and protrude from a top surface TSa of the active area 301 by a third height h 3 .
- First and second impurity areas 315 a and 315 b provided as source/drain areas of a cell transistor may be formed in the active areas 301 on both sides of each buried gate 312 .
- the first impurity area 315 a may be formed in the active area 301 between the buried gate 312 and the field area 302 .
- the first impurity area 315 a may be electrically connected to the lower electrode 350 of the capacitor through the contact pad 322 a .
- the second impurity area 315 b may be formed in the active area 301 between a pair of buried gates 312 .
- the second impurity area 315 b may be electrically connected to the bit line 342 .
- the second impurity area 315 b may be formed deeper than the first impurity area 315 a.
- a bit line trench 328 crossing the gate capping fence 314 a and extending in the second direction perpendicular to the first direction may be formed in the gate capping fence 314 a .
- the bit line trench 328 may expose at least some areas of the substrate 300 between the adjacent gate capping fences 314 a .
- An insulator structure 330 a may be formed along an inner wall of the bit line trench 328 .
- the bit line trench 328 may be filled with the bit line 342 and a bit line capping pattern 344 .
- the bit line trench 328 may be formed to have a third depth d 3 the same as the protruding height h 3 of the gate capping fence 314 a , and a bottom surface BSt thereof may be located at the same level as the top surface TSa of the active area 301 .
- the bit line 342 in the bit line trench 328 may be formed on the substrate 300 .
- the insulator structure 330 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap, or both, to reduce parasitic capacitance between the bit line 342 and the lower electrode 350 of the capacitor.
- a low dielectric constant e.g., silicon oxide and the like, or an air gap, or both
- the contact pad 322 a may be self-aligned with the gate capping fence 314 a .
- the contact pad 322 a may be electrically connected to the first impurity area 315 a in the active area 301 .
- the lower electrode 350 of the capacitor may be directly formed on the contact pad 322 a , which is self-aligned with the gate capping fence 314 a , without a contact hole, to thereby prevent contact misalignment.
- a gate capping fence 314 a covering a top surface of a buried gate 312 formed in a substrate 300 may extend in a first direction along the buried gate 312 , and protrude from a top surface TSa of an active area 301 by a third height h 3 .
- a bit line trench 328 extending in a second direction perpendicular to the first direction may be formed in the gate capping fence 314 a to expose at least some areas of the substrate 300 between the adjacent gate capping fences 314 a .
- the bit line trench 328 may be formed to have a third depth d 3 the same as the protruding height h 3 of the gate capping fence 314 a .
- a bottom surface BSt of the bit line trench 328 may be located at the same level as the top surface TSa of the active area 301 .
- the bit line 342 in the bit line trench 328 may be formed on the substrate 300 .
- An insulator structure 330 b extending in the first direction along an inner wall of the bit line trench 328 may be formed as a multi-layer structure having an insulating layer 334 and an air gap 335 .
- the insulating layer 334 may include a low dielectric constant insulating material such as silicon oxide or the like.
- an insulator structure 330 c extending in a first direction along an inner wall of a bit line trench 328 may be formed as a multi-layer structure having a first insulating layer 331 , an air gap 336 , and a second insulating layer 333 .
- Each of the first and second insulating layers 331 and 333 may include a low dielectric constant insulating material such as silicon oxide or the like.
- the bit line trench 328 may be formed to have a third depth d 3 the same as a protruding height h 3 of the gate capping fence 314 a .
- a bottom surface BSt of the bit line trench 328 may be located at the same level as a top surface TSa of an active area 301 .
- the bit line 342 in the bit line trench 328 may be formed on the substrate 300 .
- FIGS. 11A to 19D and 20 to 27 are cross-sectional views and plan views of a method of manufacturing a semiconductor device in accordance with an embodiment.
- the drawings A, B, C, and D included in each of the FIGS. 11 to 19 are cross-sectional views showing a memory cell area of a semiconductor device taken along lines I-I′, II-II′, III-III′, and IV-IV′ of FIG. 1 , respectively.
- a substrate 100 may have a semiconductor substrate.
- the substrate 100 may have a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like.
- Field areas 102 defining active areas 101 may be formed on the substrate 100 by performing an isolation process.
- Each active area 101 may be formed to have a major axis and a minor axis, and arranged two-dimensionally in directions of the major and minor axes.
- each active area 101 may have a bar shape in which a length is greater than a width.
- the field area 102 may be formed by performing a shallow trench isolation process.
- a field trench may be formed by partially etching the substrate 100 and filled with a field insulating layer, to form the field area 102 .
- the field insulating layer may include a single layer of silicon oxide, or a composite layer having silicon oxide and silicon nitride according to a size of the field trench.
- First and second impurity areas 115 a and 115 b provided as source/drain areas of a cell transistor may be formed in the active area 101 by performing an ion implanting process.
- a buried gate forming process may be performed on the substrate 100 .
- a gate mask pattern 106 defining a buried gate forming area may be formed on the substrate 100 .
- the gate mask pattern 106 may be formed to have a first thickness t 1 , and may include silicon oxide.
- Line-shaped gate trenches 108 extending in a first direction may be formed in the substrate 100 by partially etching the active areas 101 and the field area 102 of the substrate 100 using the gate mask pattern 106 as an etch mask.
- Each gate trench 108 may include an active gate trench 108 a crossing the active area 101 , and a field gate trench 108 f in the field area 102 .
- the active gate trench 108 a and the field gate trench 108 f may have bottom surfaces at different levels.
- the bottom surface of the active gate trench 108 a may be located at a higher level than the bottom surface of the field gate trench 108 f.
- the gate trench 108 may have a bottom surface located at a lower level than the first and second impurity areas 115 a and 115 b .
- the first and second impurity areas 115 a and 115 b may be spaced-apart from each other by the gate trench 108 .
- the first impurity area 115 a may be located in the active area 101 between the active gate trench 108 a and the field area 102 .
- the second impurity area 115 b may be located in the active area 101 between the active gate trenches 108 a .
- the second impurity area 115 b may be formed deeper than the first impurity 115 a.
- a gate insulating layer 110 may be conformally formed on an inner wall of each gate trench 108 by performing a thermal oxidation process.
- the gate insulating layer 110 may include an active gate insulating layer 110 a on the active gate trench 108 a , and a field insulating layer 110 f on the field gate trench 108 f .
- the gate insulating layer 110 may be formed only on an inner wall of the active gate trench 108 a .
- the gate insulating layer 110 may include silicon oxide.
- a gate conductive layer may be deposited on the substrate 100 to fill the gate trenches 108 .
- Buried gates 112 may be formed in a lower part of the gate trench 108 by performing an etch-back process to the gate conductive layer.
- Each buried gate 112 may include an active gate 112 a in the active gate trench 108 a , and a field gate 112 f in the field gate trench 108 f .
- a bottom surface of the active gate 112 a may be located at a higher level than a bottom surface of the field gate 112 f .
- a top surface of the active gate 112 a may be located at a level substantially the same as or similar to a top surface of the field gate 112 f .
- the buried gate 112 may include poly-silicon, a metal or metal nitride, such as tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a composite layer thereof.
- tungsten W
- tungsten nitride WN
- titanium titanium nitride
- TiN tantalum
- TaN tantalum nitride
- TiAlN titanium aluminum nitride
- TaAlN tantalum aluminum nitride
- a gate capping layer 114 may be formed on the buried gates 112 and the substrate 100 to fill upper parts of the gate trenches 108 .
- the gate capping layer 114 may include silicon nitride.
- line-shaped gate capping fences 114 a covering top surfaces of the buried gates 112 and extending in the first direction may be formed by partially removing an upper part of the gate capping layer 114 with a planarization process such as an etch-pack process or a CMP process until a top surface of the gate mask pattern 106 is exposed.
- the gate mask pattern 106 may be removed by performing a wet etching process or the like.
- Each gate capping fence 114 a may be formed to have a structure protruding from a top surface TSa of the active area 101 by a first height h 1 .
- the protruding height h 1 of the gate capping fence 114 a may be substantially the same as or similar to the thickness t 1 of the gate mask pattern 106 .
- the protruding height of the gate capping fence 114 a may be controlled by the thickness of the gate mask pattern 106 .
- a cell transistor which includes a gate structure having the gate trench 108 , the gate insulating layer 110 , the buried gate 112 , and the gate capping fence 114 a , and the first and second impurity areas 115 a and 115 b provided as the source/drain, may be completely formed by performing the process described in FIGS. 11 and 12 .
- the first impurity area 115 a formed between the buried gate 112 and the field area 102 may be electrically connected to a contact pad to be formed in a subsequent process.
- the second impurity area 115 b formed between a pair of buried gates 112 crossing one active area 101 may be electrically connected to a bit line to be formed in a subsequent process.
- FIGS. 12C and 12D may also be regarded as illustrating forming spaced-apart line-shaped structures S that extend in a first direction of a substrate 100 .
- the spaced-apart line-shaped structures S comprise gate trenches 108 in the substrate 100 having buried gates 112 therein, and gate capping fences 114 a thereon that protrude from the substrate 100 .
- a pad conductive layer may be deposited on the substrate 100 , in which the gate structure is formed.
- Line-shaped pad patterns 122 self-aligned with the gate capping fences 114 a and extending in the first direction may be formed by partially removing an upper part of the pad conductive layer with a planarization process such as an etch-pack process or a CMP process until a top surface TSf of the gate capping fence 114 a is exposed.
- the top surface TSp of the line-shaped pad pattern 122 may be located at the same level as the top surface TSf of the gate capping fence 114 a .
- the pad pattern 122 may include a metal such as tungsten (W), titanium nitride (TiN) or the like, doped poly-silicon, or a composite layer having a metal and poly-silicon.
- a metal silicide layer for an ohmic contact, or a barrier metal layer such as a metal oxide or the like may be formed on surfaces of the active areas 101 exposed by the gate capping fences 114 a .
- the metal silicide layer for the ohmic contact may be formed on a top surface of each pad pattern 122 .
- FIGS. 13C and 13D may also be regarded as illustrating forming line-shaped pad patterns 122 that extend in the first direction, between the spaced-apart line-shaped structures S.
- a first hard mask layer 124 may be formed on the substrate 100 in which the line-shaped pad patterns 122 are formed.
- the first hard mask layer 124 may include a material having an etch selectivity with respect to the pad pattern 122 and the gate capping fence 114 a thereunder.
- the first hard mask layer 124 may be formed by a carbon containing layer such as a spin on hard (SOH) mask.
- SOH spin on hard
- the SOH layer may be formed by performing a spin coating process.
- Line-shaped first photoresist patterns 125 extending in a second direction perpendicular to the first direction and defining a bit line forming area may be formed on the first hard mask layer 124 .
- an anti-reflection layer may be formed on the first hard mask layer 124 .
- the anti-reflection layer may include silicon oxy-nitride (SiON).
- SiON silicon oxy-nitride
- the openings in the first photoresist patterns 125 may also define openings O in the first hard mask layer 124 , as will now be described.
- the first hard mask layer 124 may be patterned to open the bit line forming area by performing a photolithography process using the first photoresist patterns 125 .
- the first photoresist patterns 125 having a similar etch characteristic to the first hard mask layer 124 may be etched together while the first hard mask layer 124 is etched.
- a mask pattern may be formed on the gate capping fences 114 a and on the line-shaped pad patterns 122 , to define spaced-apart line-shaped mask openings that extend in a second direction perpendicular to the first direction.
- Portions of the line-shaped pad patterns 122 and the gate capping fences 114 that are exposed by the mask openings are then etched to form contact pads 122 a from the line-shaped pad patterns 122 and to form trenches 128 in the gate capping fences 114 a that extend in the second direction.
- bit line trenches 128 crossing the gate capping fences 114 a and extending in the second direction perpendicular to the first direction may be formed by partially etching the gate capping fence 114 a using the patterned first hard mask layer 124 as an etch mask.
- contact pads 122 a self-aligned with the gate capping fences 114 a may be formed by removing exposed areas of the line-shaped pad patterns 122 .
- Each contact pad 122 a may be electrically connected to the first impurity area 115 a formed between the buried gate 112 and the field area 102 .
- the bit line trench 128 may be formed to have a first depth d 1 greater than the protruding height h 1 of the gate capping fence 114 a from the top surface TSa of the active area 101 .
- the depth d 1 of the bit line trench 128 may be determined so that a top surface of the bit line to be formed in a subsequent process is located at a lower level than the top surface TSa of the active area 101 .
- the depth d 1 of the bit line trench 128 may be determined so that the top surface of the bit line to be formed in a subsequent process is located at a higher level than the top surface TSa of the active area 101 .
- a bottom surface BSt of the bit line trench 128 may be located at a lower level than the top surface TSa of the active area 101 .
- the bottom surface BSt of the bit line trench 128 may be controlled to ensure a stable separation between the bit line to be formed in a subsequent process and the buried gate 112 .
- the bottom surface BSt of the bit line trench 128 may be located at a level the same as or similar to the top surface TSa of the active area 101 .
- the top surface TSp of the contact pad 122 a may be located at a level the same as or similar to the top surface TSf of the gate capping fence 114 a.
- the first hard mask layer 124 and the remaining first photoresist patterns 125 may be removed.
- an insulator structure 130 may be formed on the substrate 100 having the bit line trenches 128 and the contact pads 122 a .
- the insulator structure 130 may include an insulating layer having a low dielectric constant, e.g., silicon oxide or the like, or an air gap, or both.
- the insulator structure 130 may be formed on an inner wall of the bit line trench 128 to have a conformal thickness.
- the insulator structure 130 including an insulating layer having a low dielectric constant or an air gap can reduce parasitic capacitance between the bit line and a low electrode of a capacitor to be formed in a subsequent process.
- a second hard mask layer 138 may be formed on the insulator structure 130 .
- the second hard mask layer 138 may include a material having an etch selectivity with respect to the insulator structure 130 thereunder.
- the second hard mask layer 138 may be formed by a carbon containing layer such as an SOH mask.
- a second photoresist pattern 139 defining bit line contact areas 140 may be formed on the second hard mask layer 138 .
- an anti-reflection layer such as a SiON or the like may be formed on the second hard mask layer 138 .
- the second hard mask layer 138 may be patterned by performing a photolithography process using the second photoresist pattern 139 .
- the second photoresist pattern 139 having a similar etch characteristic to the second hard mask layer 138 may be etched together while the second hard mask layer 138 is etched.
- the bit line contact areas 140 may be formed by etching the insulator structure 130 using the patterned second hard mask layer 138 as an etch mask.
- the insulator structure 130 may expose the bit line contact areas 140 , and extend in the first direction along the inner wall of the bit line trench 128 .
- the insulator structure 130 may stably separate the contact pad 122 a from the bit line to be formed in a subsequent process.
- the second hard mask layer 138 and the remaining second photoresist pattern 139 may be removed.
- bit line conductive layer may be deposited on the substrate 100 to fill the bit line trench 128 .
- Bit lines 142 filling each bit line trench 128 and extending in the second direction may be formed on the insulator structure 130 by partially removing the bit line conductive layer with an etch-back process or a CMP process.
- the bit line 142 may be electrically connected to the second impurity area 115 b formed in the active area 101 between a pair of buried gates 112 through the bit line contact area 140 . Since the bit line 142 is formed by performing a damascene process, a fine pattern can be implemented by overcoming a pattern limitation of a photolithography process.
- the bit line 142 may include a low-resistance metal such as tungsten (W) or titanium nitride (TiN).
- a top surface TSb of the bit line 142 may be located at a lower level than the top surface TSa of the active area 101 . Therefore, the bit line 142 may be formed as a structure fully buried in the substrate 100 . According to another embodiment, since the top surface TSb of the bit line 142 is located at a higher level than the top surface TSa of the active area 101 , the bit line 142 may be formed as a structure partially buried in the substrate 100 . According to still another embodiment, bit line 142 may be formed on the substrate 100 .
- an insulating layer may be deposited on the substrate 100 in which the bit lines 142 are formed.
- Bit line capping patterns 144 filling upper parts of the bit line trenches 128 and extending in the second direction may be formed by partially removing the insulating layer with an etch-back process or a CMP process until top surfaces of the contact pads 122 a are exposed.
- the top surfaces of the contact pads 122 a and the gate capping fences 114 a may be exposed together.
- a top surface of the bit line capping pattern 144 may be located at a level substantially the same as or similar to the top surface of the gate capping fence 114 a .
- the bit line capping pattern 144 may include silicon nitride.
- a bit line structure including a bit line trench 128 , an insulator structure 130 , a bit line 142 , and a bit line capping pattern 144 may be formed in or on the substrate 100 by the process described in FIGS. 15 to 19 .
- the lower electrode 150 of the capacitor may be formed on the contact pads 122 a .
- the lower electrode 150 of the capacitor may be electrically connected to the first impurity areal 15 a formed between the buried gate 112 and the field area 102 through the contact pad 122 a thereunder.
- the lower electrode 150 of the capacitor may be directly formed on the contact pad 122 a , which is self-aligned with the gate capping fence 114 a , without a contact hole, contact misalignment can be prevented.
- the lower electrode 150 of the capacitor may be stably separated from the bit line 142 by the insulator structure 130 and the bit line capping pattern 144 . Scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between the lower electrode 150 of the capacitor and the bit line 142 by the gate capping fence 114 a and the insulator structure 130 a.
- a process of forming a contact hole and a landing pad to connect the lower electrode 150 of the capacitor with the active area 101 of the substrate 100 , and a process of forming an interlayer insulating layer between the bit line 142 and the lower electrode 150 of the capacitor can be omitted to simplify the manufacturing process and to improve process throughput.
- FIGS. 28A to 28D are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with another embodiment.
- the process described with reference to FIGS. 11 to 15 may be performed to form buried gates 112 , gate capping fences 114 a , bit line trenches 128 , and contact pads 122 a in and on a substrate 100 having a field area 102 defining active areas 101 .
- the gate capping fence 114 a may cover a top surface of the buried gate 112 , extend in a first direction, and protrude from a top surface of the active area 101 .
- the bit line trench 128 may be formed in the gate capping fence 114 a , cross the gate capping fences 114 a , and extend in a second direction perpendicular to the first direction.
- the bit line trench 128 may be formed to have a depth greater than or equal to a protruding height of the gate capping fence 114 a from the top surface of the active area 101 .
- the contact pad 122 a may be self-aligned with the gate capping fence 114 a on the substrate 100 between the adjacent bit line trenches 128 .
- a first insulating layer 131 , a sacrificial layer 132 , and a second insulating layer 133 may be sequentially formed on the substrate 100 .
- the first insulating layer 131 , the sacrificial layer 132 , and the second insulating layer 133 may be formed to have conformal thicknesses on an inner wall of the bit line trench 128 .
- Each of the first and second insulating layers 131 and 133 may include a low dielectric constant insulating material such as silicon oxide.
- the sacrificial layer 132 may include a material having an etch selectivity with respect to the first and second insulating layers 131 and 133 , for example, silicon nitride or a polysilicon-based organic compound.
- bit line contact areas 140 may be formed by etching the second insulating layer 133 , the sacrificial layer 132 , and the first insulating layer 131 which are located on the active area 101 between a pair of buried gates 112 .
- bit lines 142 may be formed to fill lower parts of the bit line trenches 128 .
- the bit line 142 may be electrically connected to the active area 101 between a pair of buried gates 112 through the bit line contact area 140 .
- An air gap 136 may be formed between the first insulating layer 131 and the second insulating layer 133 by selectively removing the sacrificial layer 132 with a wet etching process.
- a bit line capping pattern 144 may be formed to cover top surfaces of the bit lines 142 and to fill the bit line trenches 128 .
- the bit line capping pattern 144 may be partially removed by performing an etch-back process or a CMP process until top surfaces of the contact pads 122 a are exposed.
- the top surface of the bit line 142 may be covered by the bit line capping pattern 144
- sides of the bit line 142 may be covered by an insulator structure 130 c including the first insulating layer 131 , the sacrificial layer 132 , and the second insulating layer 133 .
- a lower electrode of a capacitor may be directly formed on each contact pad 122 a without a contact hole.
- the lower electrode of the capacitor may be stably separated from the bit line 142 by the bit line capping pattern 144 and the insulator structure 130 c.
- FIG. 29 is a block diagram of an electronic system having the semiconductor devices in accordance with various embodiments.
- the semiconductor devices in accordance with various embodiments may be applied to the electronic system 1000 .
- the electronic system 1000 may include a controller 1100 , an input/output 1200 , a memory 1300 , an interface 1400 , and a bus 1500 .
- the controller 1100 , the input/output 1200 , the memory 1300 , and the interface 1400 may be combined through the bus 1500 .
- the bus 1500 may be a path through which data moves.
- the controller 1100 may include at least one of a microprocessor, a digital signal processor, a micro controller, and logical devices capable of performing a similar function thereto.
- the input/output 1200 may include a keypad, a keyboard, a display device, etc.
- the memory 1300 may store data and/or a command.
- the interface 1400 may serve to transmit data to a communication network or receive data from the communication network.
- the interface 1400 may be a wired or wireless form.
- the interface 1400 may include an antenna, a wired/wireless transceiver, or the like.
- Semiconductor devices in accordance with various embodiments described herein may be used in the controller 1100 , the input/output 1200 , the memory 1300 or the interface 1400 or in various combinations and subcombinations thereof.
- the bit line trenches may be formed by a damascene process using the gate capping fences protruding from the top surfaces of the active areas, and contact pads self-aligned with the gate capping fence may be formed on the substrate between the adjacent bit lines. Since the lower electrode of the capacitor may be directly formed on the contact pad, which is self-aligned with the gate capping fence, without a contact hole, contact misalignment can be reduced or prevented.
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Abstract
Description
- This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0051678 filed on Apr. 29, 2014, the disclosure of which is hereby incorporated by reference in its entirety.
- 1. Field
- Various embodiments described herein relate to semiconductor devices, methods of manufacturing semiconductor devices, and electronic devices and electronic systems adopting the same.
- 2. Description of Related Art
- With an increase in the degree of integration of semiconductor devices, a design rule of components of the semiconductor devices is being reduced. It is difficult to stably separate a bit line and a lower electrode of a capacitor, and parasitic capacitance between the bit line and the lower electrode of the capacitor may increase. A contact margin between an active area and the lower electrode of the capacitor also may be insufficient, which can increase the difficulty of a bit line forming process.
- Various embodiments described herein can provide semiconductor devices capable of reducing or preventing contact misalignment.
- Other embodiments can provide semiconductor devices having damascene bit lines.
- Other embodiments can provide methods of manufacturing semiconductor devices capable of reducing or preventing contact misalignment.
- Other embodiments can provide methods of manufacturing semiconductor devices having damascene bit lines.
- The technical objectives of the inventive concepts are not limited to the above disclosure; other objectives may become apparent to those of ordinary skill in the art based on the following description.
- Various embodiments described herein may be realized by providing a semiconductor device including a substrate having a field area that defines active areas; gate trenches extending in a first direction in the substrate; buried gates in the gate trenches; gate capping fences in, and in some embodiments filling, the gate trenches over a respective buried gate, protruding from top surfaces of the active areas, and extending in the first direction; bit line trenches crossing the gate capping fences and extending in a second direction perpendicular to the first direction in the gate capping fence; insulator structures on inner walls of a respective bit line trench; bit lines and bit line capping patterns stacked on the insulator structures in, and in some embodiments to fill, a respective bit line trench; contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines; and a lower electrode of a capacitor on a respective contact pad.
- A top surface of the contact pad may be located at substantially the same level as a top surface of the gate capping fence.
- A depth of the bit line trench may be greater than or equal to a protruding height of the gate capping fence from a top surface of the active area.
- A top surface of the bit line may be located at a lower level than the top surface of the active area.
- The top surface of the bit line may be located at a higher level than the top surface of the active area.
- A top surface of the bit line capping pattern may be located at substantially the same level as the top surface of the gate capping fence.
- The insulator structure may include an insulating layer, an air gap, or a multi-structure having an insulating layer and an air gap.
- Other embodiments may be realized by providing a method of manufacturing a semiconductor device, the method including forming a field area in a substrate to define active areas; forming gate trenches extending in a first direction in the substrate; forming buried gates in a respective gate trench; forming gate capping fences in, and in some embodiments filling, the gate trenches over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction; forming line-shaped pad patterns self-aligned with the gate capping fences and extending in the first direction on the substrate; forming contact pads and bit line trenches by patterning a part of the pad patterns and the gate capping fences to expose at least some areas of the substrate between the adjacent gate capping fences, each contact pad being formed on the substrate between the adjacent bit line trenches and a respective bit line trench extending in a second direction perpendicular to the first direction; forming a bit line in a respective bit line trench; and forming a lower electrode of a capacitor on a respective contact pad.
- The formation of the line-shaped pad patterns self-aligned with the gate capping fences and extending in the first direction may include forming a pad conductive layer on a surface, and in some embodiments on an entire surface, of the substrate, and partially removing the pad conductive layer until a top surface of the gate capping fence is exposed. A top surface of the line-shaped pad pattern may be located at substantially the same level as the top surface of the gate capping fence.
- The formation of the contact pads and the bit line trenches may include forming mask patterns extending in the second direction and defining bit line forming areas, on the substrate on which the line-shaped pad patterns are formed, forming the contact pads and the bit line trenches by etching the exposed areas of the pad patterns and some areas of the gate capping fences using the mask patterns, and removing the mask patterns.
- Insulator structures may further be formed on inner walls of a respective bit line trench. A respective insulator structure may include an insulating layer, an air gap, or a multi-structure having an insulating layer and an air gap.
- Bit line capping patterns may further be formed in the bit line trenches over each bit line. Top surfaces of the bit line capping patterns may be located at substantially the same level as top surfaces of the gate capping fences.
- Yet other embodiments may be realized by providing a method of manufacturing a semiconductor device, the method comprising: forming spaced-apart line-shaped structures that extend in a first direction of a substrate, the spaced-apart line-shaped structures comprising gate trenches in the substrate having buried gates therein and gate capping fences thereon that protrude from the substrate; forming line-shaped pad patterns that extend in the first direction, between the spaced-apart line-shaped structures; forming a mask pattern on the gate capping fences and on the line-shaped pad patterns to define spaced-apart line-shaped mask openings that extend in a second direction perpendicular to the first direction; and etching portions of the line-shaped pad patterns and the gate capping fences that are exposed by the mask openings to form contact pads from the line-shaped pad patterns and to form trenches in the gate capping fences that extend in the second direction.
- The formation of the line-shaped pad patterns may include forming a pad conductive layer on the spaced-apart line-shaped structures and between the spaced-apart line-shaped structures; and removing the pad conductive layer until top surfaces of the gate capping fences are exposed to form the line-shaped pad patterns.
- The method may further comprise forming a bit line in a respective bit line trench. The method may further comprise forming a lower electrode of a capacitor directly on a respective contact pad.
- The following may be performed between the etching and the forming a bit line: forming an insulating layer including an air gap on walls of the bit line trenches.
- Specific particulars of other embodiments are included in the detailed description and drawings.
- The foregoing and other features and advantages of the inventive concepts will be apparent from the more particular description of various embodiments of the inventive concepts, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:
-
FIG. 1 is a plan view showing a memory cell area of a semiconductor device in accordance with an embodiment; -
FIG. 2 is a cross-sectional view of a semiconductor device taken along line V-V′ ofFIG. 1 in accordance with an embodiment; -
FIGS. 3 to 10 are cross-sectional views of semiconductor devices taken along the line V-V′ ofFIG. 1 in accordance with other embodiments; -
FIGS. 11A to 19D and 20 to 27 are cross-sectional views and plan views of a method of manufacturing a semiconductor device in accordance with an embodiment, and the drawings A, B, C, and D included in each of theFIGS. 11 to 19 are cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1 , respectively; -
FIGS. 28A to 28D are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with the another embodiment; and -
FIG. 29 is a block diagram of an electronic system having the semiconductor devices in accordance with various embodiments. - The inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concepts are shown. The inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the inventive concepts to one skilled in the art.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present inventive concepts. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Like numerals refer to like elements throughout the specification. In the drawings, the lengths and thicknesses of layers and regions may be exaggerated for clarity. In addition, it will be understood that when a first element is referred to as being “on” a second element, the first element may be directly on the second element, or one or more other elements may be interposed between the first element and the second element.
- Spatially relative terms, such as “top surface”, “bottom surface”, “upper end,” “lower end,” “upper surface,” “lower surface,” “upper part,” “lower part,” and the like, may be used herein for ease of description to distinguish relative locations of elements. For example, when an upper part is used as a top in the drawing and a lower part is used as a bottom in the drawing for convenience, the upper part could be termed the lower part and the lower part could be termed the upper part without departing from the scope of the present inventive concepts.
- It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the inventive concepts.
- The embodiments of the inventive concepts will be described with reference to cross-sectional views and/or plan views, which are ideal views. Thicknesses of layers and areas in the drawings are exaggerated for effective description of the technical contents. Forms of the embodiments may be modified by the manufacturing technology and/or tolerance. Therefore, the embodiments of the inventive concepts are not intended to be limited to illustrated specific forms, and include modifications of forms generated according to the manufacturing processes. For example, an etching area illustrated at a right angle may be round or have a predetermined curvature. Therefore, areas illustrated in the drawings have overview properties, shapes of the areas are illustrated special forms of the areas of a device, and are not intended to limit the scope of the inventive concepts.
-
FIG. 1 is a plan view showing a memory cell area of a semiconductor device in accordance with an embodiment.FIG. 2 is a cross-sectional view of a semiconductor device taken along line V-V′ ofFIG. 1 in accordance with an embodiment. - Referring to
FIGS. 1 and 2 , the semiconductor device in accordance with the embodiment may include asubstrate 100 havingactive areas 101 defined byfield areas 102. Buriedgates 112 extending in a first direction may be formed in thesubstrate 100.Bit lines 142 extending in a second direction perpendicular to the first direction may be formed in thesubstrate 100. Contactpads 122 a may be formed on thesubstrate 100 between the adjacent bit lines 142.Lower electrodes 150 of a capacitor may be formed on eachcontact pad 122 a. - The
substrate 100 may comprise a semiconductor substrate. For example, thesubstrate 100 may comprise a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like. - The
field area 102 may be formed in thesubstrate 100 and define the plurality ofactive areas 101. Thefield area 102 may be a shallow trench isolation (STI) area. For example, thefield area 102 may include a field trench formed in thesubstrate 100, and a field insulating layer filling the field trench. The field insulating layer may include a single layer of silicon oxide or a composite layer having silicon oxide and silicon nitride according to a width of the field trench. - Each
active area 101 may be formed to have a major axis and a minor axis, and arranged two-dimensionally in directions of the major and minor axes. For example, eachactive area 101 may have a bar shape in which a length is greater than a width. - The
active areas 101 may be oriented such that their major axes are oblique with respect to the buriedgates 112 and the bit lines 142. Oneactive area 101 may intersect two buriedgates 112 and onebit line 142, and thus, oneactive area 101 may have a structure of two unit cells. One unit cell may have a length of 2F in the first direction and a length of 4F in the second direction, and have an area of 6F2. Here, F refers to a minimum feature size. The semiconductor device in accordance with the embodiments may not be limited to the 6F2 cell structure, and theactive areas 101 may also be formed in an 8F2 cell structure in which theactive areas 101 intersects the buriedgates 112 at right angles. Further, it is apparent that any cell structures capable of improving a degree of integration of the semiconductor device may also be included. - Each buried
gate 112 may be formed in a lower part of agate trench 108 with agate insulating layer 110 therebetween, the gate trench extending in the first direction and being formed in thesubstrate 100. Upper parts of thegate trenches 108 over each buriedgate 112 may be filled withgate capping fences 114 a. Thegate capping fence 114 a may be formed to have a line shape extending in the first direction along the buriedgate 112. Thegate capping fence 114 a may protrude from a top surface TSa of theactive area 101 by a first height h1. - The buried
gate 112 may include poly-silicon, a metal or metal nitride, such as tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a composite layer thereof. Thegate insulating layer 110 may include silicon oxide, an insulating material having a high dielectric constant or a combination thereof. Thegate capping fence 114 a may include silicon nitride. - According to an embodiment, first and
second impurity areas active areas 101 on both sides of each buriedgate 112. Thefirst impurity area 115 a may be formed in theactive area 101 between the buriedgate 112 and thefield area 102. Thefirst impurity area 115 a may be electrically connected to thelower electrode 150 of the capacitor through thecontact pad 122 a. Thesecond impurity area 115 b may be formed in theactive area 101 between a pair of buriedgates 112. Thesecond impurity area 115 b may be electrically connected to thebit line 142. For example, thesecond impurity area 115 b may be formed deeper than thefirst impurity area 115 a. -
Bit line trenches 128 crossing thegate capping fences 114 a and extending in the second direction perpendicular to the first direction may be formed in thegate capping fences 114 a. Thebit line trench 128 may be formed by a damascene process using thegate capping fences 114 a protruding from a level of theactive area 101. Thebit line trench 128 may be formed to have a depth greater than or equal to a protruding height of thegate capping fence 114 a from the top surface TSa of theactive area 101. - The
bit line 142 may be formed in a lower part of thebit line trench 128. Thebit line 142 may be formed as a structure fully or partially buried in thesubstrate 100 or a structure disposed on thesubstrate 100, according to the depth of thebit line trench 128. According to the embodiment, as thebit line trench 128 may be formed to have a first depth d1 greater than the protruding height h1 of thegate capping fence 114 a, a top surface TSb of thebit line 142 may be located at a lower level than the top surface TSa of theactive area 101, thebit line 142 may be formed to have a structure fully buried in thesubstrate 100. - A bottom surface BSt of the
bit line trench 128 may be controlled to ensure a stable separation between thebit line 142 and the buriedgate 112. Since thebit line 142 may be formed by a damascene process, a fine pattern can be implemented by overcoming a pattern limitation of a photolithography process. - Upper parts of the
bit line trenches 128 over eachbit line 142 may be filled with bitline capping patterns 144. A top surface TSc of the bitline capping pattern 144 may be located at substantially the same level as a top surface TSf of thegate capping fence 114 a. Thebit line 142 may include a low-resistance metal such as tungsten (W), titanium nitride (TiN), or the like. The bitline capping patterns 144 may include silicon nitride. - Each of
insulator structures 130 a may be formed on an inner wall of eachbit line trench 128. Theinsulator structures 130 a may be formed to expose source/drain areas in theactive area 101, for example, thesecond impurity area 115 b, and to extend in the first direction along the inner wall of thebit line trench 128. Theinsulator structures 130 a may stably separate thecontact pad 122 a from thebit line 142. Theinsulator structure 130 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap of which dielectric constant is 1, to thereby reduce parasitic capacitance between thebit line 142 and thelower electrode 150 of the capacitor. - The
contact pad 122 a may be self-aligned with thegate capping fence 114 a and formed on thesubstrate 100 between the adjacent bit lines 142. For example, thecontact pad 122 a may be electrically connected to thefirst impurity area 115 a in theactive area 101. Thelower electrode 150 of the capacitor may be directly formed on thecontact pad 122 a, which is self-aligned with thegate capping fence 114 a, without a contact hole, to thereby prevent contact misalignment. - A top surface TSp of the
contact pad 122 a may be located at substantially the same level as the top surface TSf of thegate capping fence 114 a. Thecontact pad 122 a may be stably separated from thebit line 142 by thegate capping fence 114 a and theinsulator structure 130 a. For example, thecontact pad 122 a may include a metal, such as tungsten (W), titanium nitride (TiN), or the like, doped poly-silicon, or a multi-layer structure having a metal and poly-silicon. In some cases, a metal silicide layer for an ohmic contact, or a barrier metal layer such as a metal oxide or the like may be formed between a surface of theactive area 101 and thecontact pad 122 a. - The
lower electrode 150 of the capacitor formed on thecontact pad 122 a may be stably separated from thebit line 142 by thegate capping fence 114 a and theinsulator structure 130 a. Due to thegate capping fence 114 a and theinsulator structure 130 a, scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between thelower electrode 150 of the capacitor and thebit line 142. -
FIGS. 3 to 10 are cross-sectional views of semiconductor devices taken along the line V-V′ ofFIG. 1 in accordance with other embodiments. Hereinafter, the above-described embodiments and repeated parts will be omitted, and modified parts will be mainly described. - Referring to
FIG. 3 , in the semiconductor device in accordance with another embodiment, agate capping fence 114 a covering a top surface of a buriedgate 112 formed in asubstrate 100 may extend in a first direction along the buriedgate 112, and protrude from a top surface TSa of anactive area 101 by a first height h1. - A
bit line trench 128 crossing thegate capping fences 114 a and extending in a second direction perpendicular to the first direction may be formed in thegate capping fence 114 a. Thebit line trench 128 may be formed to have a first depth d1 greater than the protruding height h1 of thegate capping fence 114 a. - As a top surface TSb of a
bit line 142 in thebit line trench 128 is located at a lower level than the top surface TSa of theactive area 101, thebit line 142 may be formed as a structure fully buried in thesubstrate 100. - An
insulator structure 130 b extending in the first direction along an inner wall of thebit line trench 128 may be formed as a multi-layer structure having an insulatinglayer 134 and anair gap 135. The insulatinglayer 134 may include an insulating material having a low dielectric constant such as silicon oxide or the like. - Referring to
FIG. 4 , in the semiconductor device in accordance with another embodiment, aninsulator structure 130 c extending in a first direction along an inner wall of abit line trench 128 may be formed as a multi-layer structure having a first insulatinglayer 131, anair gap 136, and a second insulatinglayer 133. Each of the first and second insulatinglayers - The
bit line trench 128 may be formed to have a first depth d1 greater than a protruding height h1 of agate capping fence 114 a. As a top surface TSb of abit line 142 formed in thebit line trench 128 is located at a lower level than a top surface TSa of anactive area 101, thebit line 142 may be formed as a structure fully buried in thesubstrate 100. - Referring to
FIG. 5 , the semiconductor device in accordance with another embodiment may include asubstrate 200 havingactive areas 201 defined by afield area 202. Buriedgates 212 extending in a first direction may be formed in thesubstrate 200.Bit lines 242 extending in a second direction perpendicular to the first direction may be formed in and on thesubstrate 200. Contactpads 222 a may be formed on thesubstrate 200 between the adjacent bit lines 242.Lower electrodes 250 of a capacitor may be formed on eachcontact pad 222 a. - The buried
gate 212 may be formed in a lower part of agate trench 208 extending in the first direction and formed in thesubstrate 200, with agate insulating layer 210 therebetween. An upper part of thegate trench 208 may be filled with agate capping fence 214 a over the buriedgate 212. Thegate capping fence 214 a may be formed to have a line shape extending in the first direction along the buriedgate 212, and protrude from a top surface TSa of theactive area 201 by a second height h2. - First and
second impurity areas active areas 201 on both sides of each buriedgate 212. Thefirst impurity area 215 a may be formed in theactive area 201 between the buriedgate 212 and thefield area 202. Thefirst impurity area 215 a may be electrically connected to thelower electrode 250 of the capacitor through thecontact pad 222 a. Thesecond impurity area 215 b may be formed in theactive area 201 between a pair of buriedgates 212. Thesecond impurity area 215 b may be electrically connected to thebit line 242. For example, thesecond impurity area 215 b may be formed deeper than thefirst impurity area 215 a. - A
bit line trench 228 crossing thegate capping fence 214 a and extending in the second direction perpendicular to the first direction may be formed in thegate capping fence 214 a. Thebit line trench 228 may be formed to have a second depth d2 greater than the protruding height h2 of thegate capping fence 214 a. - An
insulator structure 230 a may be formed along an inner wall of thebit line trench 228. Thebit line trench 228 may be filled with thebit line 242 and a bitline capping pattern 244. As a top surface TSb of thebit line 242 may be located at a higher level than the top surface TSa of theactive area 201, thebit line 242 may be formed as a structure partially buried in thesubstrate 200. - The
insulator structure 230 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap, or both, to prevent parasitic capacitance between thebit line 242 and thelower electrode 250 of the capacitor. - The
contact pad 222 a may be self-aligned with thegate capping fence 214 a. For example, thecontact pad 222 a may be electrically connected to thefirst impurity area 215 a in theactive area 201. Thelower electrode 250 of the capacitor may be directly formed on thecontact pad 222 a, which is self-aligned with thegate capping fence 214 a, without a contact hole, to prevent contact misalignment. - Scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between the
lower electrode 250 of the capacitor and thebit line 242 by thegate capping fence 214 a and theinsulator structure 230 a. - Referring to
FIG. 6 , in the semiconductor device in accordance with another embodiment, agate capping fence 214 a covering a top surface of a buriedgate 212 formed in asubstrate 200 may extend in a first direction along the buriedgate 212, and protrude from a top surface TSa of anactive area 201 by a second height h2. - A
bit line trench 228 crossing thegate capping fences 214 a and extending in the second direction perpendicular to the first direction may be formed in thegate capping fence 214 a. Thebit line trench 228 may be formed to have a second depth d2 greater than the protruding height h2 of thegate capping fence 214 a. - As a top surface TSb of a
bit line 242 in thebit line trench 228 may be located at a higher level than the top surface TSa of theactive area 201, thebit line 242 may be formed as a structure partially buried in thesubstrate 200. - An
insulator structure 230 b extending in the first direction along an inner wall of thebit line trench 228 may be formed as a multi-layer structure having an insulatinglayer 234 and anair gap 235. The insulatinglayer 234 may include a low dielectric constant insulating material such as silicon oxide or the like. - Referring to
FIG. 7 , in the semiconductor device in accordance with another embodiment, aninsulator structure 230 c extending in a first direction along an inner wall of abit line trench 228 may be formed as a multi-layer structure having a first insulatinglayer 231, anair gap 236, and a second insulatinglayer 233. Each of the first and second insulatinglayers - The
bit line trench 228 may be formed to have a second depth d2 greater than a protruding height h2 of agate capping fence 214 a. As a top surface TSb of abit line 242 formed in thebit line trench 228 may be located at a higher level than a top surface TSa of anactive area 201, thebit line 242 may be formed as a structure partially buried in thesubstrate 200. - Referring to
FIG. 8 , the semiconductor device in accordance with another embodiment may include asubstrate 300 havingactive areas 301 defined by afield area 302. Buriedgates 312 extending in a first direction may be formed in thesubstrate 300.Bit lines 342 extending in a second direction perpendicular to the first direction may be formed in thesubstrate 300. Contactpads 322 a may be formed on thesubstrate 300 between the adjacent bit lines 342.Lower electrodes 350 of a capacitor may be formed on eachcontact pad 322 a. - The buried
gate 312 may be formed in a lower part of agate trench 308 extending in the first direction and formed in thesubstrate 300 with agate insulating layer 310 therebetween. An upper part of thegate trench 308 may be filled with agate capping fence 314 a over the buriedgate 312. Thegate capping fence 314 a may be formed to have a line shape extending in the first direction along the buriedgate 312, and protrude from a top surface TSa of theactive area 301 by a third height h3. - First and
second impurity areas active areas 301 on both sides of each buriedgate 312. Thefirst impurity area 315 a may be formed in theactive area 301 between the buriedgate 312 and thefield area 302. Thefirst impurity area 315 a may be electrically connected to thelower electrode 350 of the capacitor through thecontact pad 322 a. Thesecond impurity area 315 b may be formed in theactive area 301 between a pair of buriedgates 312. Thesecond impurity area 315 b may be electrically connected to thebit line 342. For example, thesecond impurity area 315 b may be formed deeper than thefirst impurity area 315 a. - A
bit line trench 328 crossing thegate capping fence 314 a and extending in the second direction perpendicular to the first direction may be formed in thegate capping fence 314 a. Thebit line trench 328 may expose at least some areas of thesubstrate 300 between the adjacentgate capping fences 314 a. Aninsulator structure 330 a may be formed along an inner wall of thebit line trench 328. Thebit line trench 328 may be filled with thebit line 342 and a bitline capping pattern 344. - The
bit line trench 328 may be formed to have a third depth d3 the same as the protruding height h3 of thegate capping fence 314 a, and a bottom surface BSt thereof may be located at the same level as the top surface TSa of theactive area 301. Thebit line 342 in thebit line trench 328 may be formed on thesubstrate 300. - The
insulator structure 330 a may be formed by an insulating layer having a low dielectric constant, e.g., silicon oxide and the like, or an air gap, or both, to reduce parasitic capacitance between thebit line 342 and thelower electrode 350 of the capacitor. - The
contact pad 322 a may be self-aligned with thegate capping fence 314 a. For example, thecontact pad 322 a may be electrically connected to thefirst impurity area 315 a in theactive area 301. Thelower electrode 350 of the capacitor may be directly formed on thecontact pad 322 a, which is self-aligned with thegate capping fence 314 a, without a contact hole, to thereby prevent contact misalignment. - Due to the
gate capping fence 314 a and theinsulator structure 330 a, scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between thelower electrode 350 of the capacitor and thebit line 342. - Referring to
FIG. 9 , in the semiconductor device in accordance with another embodiment, agate capping fence 314 a covering a top surface of a buriedgate 312 formed in asubstrate 300 may extend in a first direction along the buriedgate 312, and protrude from a top surface TSa of anactive area 301 by a third height h3. - A
bit line trench 328 extending in a second direction perpendicular to the first direction may be formed in thegate capping fence 314 a to expose at least some areas of thesubstrate 300 between the adjacentgate capping fences 314 a. Thebit line trench 328 may be formed to have a third depth d3 the same as the protruding height h3 of thegate capping fence 314 a. A bottom surface BSt of thebit line trench 328 may be located at the same level as the top surface TSa of theactive area 301. Thebit line 342 in thebit line trench 328 may be formed on thesubstrate 300. - An
insulator structure 330 b extending in the first direction along an inner wall of thebit line trench 328 may be formed as a multi-layer structure having an insulatinglayer 334 and anair gap 335. The insulatinglayer 334 may include a low dielectric constant insulating material such as silicon oxide or the like. - Referring to
FIG. 10 , in the semiconductor device in accordance with another embodiment, aninsulator structure 330 c extending in a first direction along an inner wall of abit line trench 328 may be formed as a multi-layer structure having a first insulatinglayer 331, anair gap 336, and a second insulatinglayer 333. Each of the first and second insulatinglayers - The
bit line trench 328 may be formed to have a third depth d3 the same as a protruding height h3 of thegate capping fence 314 a. A bottom surface BSt of thebit line trench 328 may be located at the same level as a top surface TSa of anactive area 301. Thebit line 342 in thebit line trench 328 may be formed on thesubstrate 300. - Hereinafter, methods of manufacturing semiconductor devices in accordance with various embodiments will be described.
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FIGS. 11A to 19D and 20 to 27 are cross-sectional views and plan views of a method of manufacturing a semiconductor device in accordance with an embodiment. Here, the drawings A, B, C, and D included in each of theFIGS. 11 to 19 are cross-sectional views showing a memory cell area of a semiconductor device taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1 , respectively. - Referring to
FIGS. 11A to 11D , and 20, asubstrate 100 may have a semiconductor substrate. For example, thesubstrate 100 may have a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like. -
Field areas 102 definingactive areas 101 may be formed on thesubstrate 100 by performing an isolation process. Eachactive area 101 may be formed to have a major axis and a minor axis, and arranged two-dimensionally in directions of the major and minor axes. For example, eachactive area 101 may have a bar shape in which a length is greater than a width. Thefield area 102 may be formed by performing a shallow trench isolation process. For example, a field trench may be formed by partially etching thesubstrate 100 and filled with a field insulating layer, to form thefield area 102. The field insulating layer may include a single layer of silicon oxide, or a composite layer having silicon oxide and silicon nitride according to a size of the field trench. - First and
second impurity areas active area 101 by performing an ion implanting process. - A buried gate forming process may be performed on the
substrate 100. - First, a
gate mask pattern 106 defining a buried gate forming area may be formed on thesubstrate 100. Thegate mask pattern 106 may be formed to have a first thickness t1, and may include silicon oxide. - Line-shaped
gate trenches 108 extending in a first direction may be formed in thesubstrate 100 by partially etching theactive areas 101 and thefield area 102 of thesubstrate 100 using thegate mask pattern 106 as an etch mask. Eachgate trench 108 may include anactive gate trench 108 a crossing theactive area 101, and afield gate trench 108 f in thefield area 102. - The
active gate trench 108 a and thefield gate trench 108 f may have bottom surfaces at different levels. For example, the bottom surface of theactive gate trench 108 a may be located at a higher level than the bottom surface of thefield gate trench 108 f. - The
gate trench 108 may have a bottom surface located at a lower level than the first andsecond impurity areas second impurity areas gate trench 108. Thefirst impurity area 115 a may be located in theactive area 101 between theactive gate trench 108 a and thefield area 102. Thesecond impurity area 115 b may be located in theactive area 101 between theactive gate trenches 108 a. For example, thesecond impurity area 115 b may be formed deeper than thefirst impurity 115 a. - A
gate insulating layer 110 may be conformally formed on an inner wall of eachgate trench 108 by performing a thermal oxidation process. Thegate insulating layer 110 may include an activegate insulating layer 110 a on theactive gate trench 108 a, and afield insulating layer 110 f on thefield gate trench 108 f. In some cases, thegate insulating layer 110 may be formed only on an inner wall of theactive gate trench 108 a. Thegate insulating layer 110 may include silicon oxide. - A gate conductive layer may be deposited on the
substrate 100 to fill thegate trenches 108. Buriedgates 112 may be formed in a lower part of thegate trench 108 by performing an etch-back process to the gate conductive layer. Each buriedgate 112 may include anactive gate 112 a in theactive gate trench 108 a, and afield gate 112 f in thefield gate trench 108 f. A bottom surface of theactive gate 112 a may be located at a higher level than a bottom surface of thefield gate 112 f. A top surface of theactive gate 112 a may be located at a level substantially the same as or similar to a top surface of thefield gate 112 f. The buriedgate 112 may include poly-silicon, a metal or metal nitride, such as tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a composite layer thereof. - A
gate capping layer 114 may be formed on the buriedgates 112 and thesubstrate 100 to fill upper parts of thegate trenches 108. Thegate capping layer 114 may include silicon nitride. - Referring to
FIGS. 12A to 12D , and 21, line-shapedgate capping fences 114 a covering top surfaces of the buriedgates 112 and extending in the first direction may be formed by partially removing an upper part of thegate capping layer 114 with a planarization process such as an etch-pack process or a CMP process until a top surface of thegate mask pattern 106 is exposed. - The
gate mask pattern 106 may be removed by performing a wet etching process or the like. - Each
gate capping fence 114 a may be formed to have a structure protruding from a top surface TSa of theactive area 101 by a first height h1. The protruding height h1 of thegate capping fence 114 a may be substantially the same as or similar to the thickness t1 of thegate mask pattern 106. The protruding height of thegate capping fence 114 a may be controlled by the thickness of thegate mask pattern 106. - A cell transistor, which includes a gate structure having the
gate trench 108, thegate insulating layer 110, the buriedgate 112, and thegate capping fence 114 a, and the first andsecond impurity areas FIGS. 11 and 12 . - The
first impurity area 115 a formed between the buriedgate 112 and thefield area 102 may be electrically connected to a contact pad to be formed in a subsequent process. Thesecond impurity area 115 b formed between a pair of buriedgates 112 crossing oneactive area 101 may be electrically connected to a bit line to be formed in a subsequent process. -
FIGS. 12C and 12D may also be regarded as illustrating forming spaced-apart line-shaped structures S that extend in a first direction of asubstrate 100. The spaced-apart line-shaped structures S comprisegate trenches 108 in thesubstrate 100 having buriedgates 112 therein, andgate capping fences 114 a thereon that protrude from thesubstrate 100. - Referring to
FIGS. 13A to 13D , and 22, a pad conductive layer may be deposited on thesubstrate 100, in which the gate structure is formed. Line-shapedpad patterns 122 self-aligned with thegate capping fences 114 a and extending in the first direction may be formed by partially removing an upper part of the pad conductive layer with a planarization process such as an etch-pack process or a CMP process until a top surface TSf of thegate capping fence 114 a is exposed. - The top surface TSp of the line-shaped
pad pattern 122 may be located at the same level as the top surface TSf of thegate capping fence 114 a. Thepad pattern 122 may include a metal such as tungsten (W), titanium nitride (TiN) or the like, doped poly-silicon, or a composite layer having a metal and poly-silicon. - In some cases, before forming the
pad patterns 122, a metal silicide layer for an ohmic contact, or a barrier metal layer such as a metal oxide or the like may be formed on surfaces of theactive areas 101 exposed by thegate capping fences 114 a. Alternately, after forming thepad patterns 122, the metal silicide layer for the ohmic contact may be formed on a top surface of eachpad pattern 122. -
FIGS. 13C and 13D may also be regarded as illustrating forming line-shapedpad patterns 122 that extend in the first direction, between the spaced-apart line-shaped structures S. - Referring to
FIGS. 14A to 14D , and 23, a firsthard mask layer 124 may be formed on thesubstrate 100 in which the line-shapedpad patterns 122 are formed. The firsthard mask layer 124 may include a material having an etch selectivity with respect to thepad pattern 122 and thegate capping fence 114 a thereunder. For example, the firsthard mask layer 124 may be formed by a carbon containing layer such as a spin on hard (SOH) mask. The SOH layer may be formed by performing a spin coating process. - Line-shaped
first photoresist patterns 125 extending in a second direction perpendicular to the first direction and defining a bit line forming area may be formed on the firsthard mask layer 124. Before forming thefirst photoresist patterns 125, an anti-reflection layer may be formed on the firsthard mask layer 124. The anti-reflection layer may include silicon oxy-nitride (SiON). As shown inFIGS. 14A and 14B , the openings in thefirst photoresist patterns 125 may also define openings O in the firsthard mask layer 124, as will now be described. - Referring to
FIGS. 15A to 15D , and 24, the firsthard mask layer 124 may be patterned to open the bit line forming area by performing a photolithography process using thefirst photoresist patterns 125. Thefirst photoresist patterns 125 having a similar etch characteristic to the firsthard mask layer 124 may be etched together while the firsthard mask layer 124 is etched. Thus, a mask pattern may be formed on thegate capping fences 114 a and on the line-shapedpad patterns 122, to define spaced-apart line-shaped mask openings that extend in a second direction perpendicular to the first direction. Portions of the line-shapedpad patterns 122 and thegate capping fences 114 that are exposed by the mask openings are then etched to formcontact pads 122 a from the line-shapedpad patterns 122 and to formtrenches 128 in thegate capping fences 114 a that extend in the second direction. - More specifically,
bit line trenches 128 crossing thegate capping fences 114 a and extending in the second direction perpendicular to the first direction may be formed by partially etching thegate capping fence 114 a using the patterned firsthard mask layer 124 as an etch mask. At the same time,contact pads 122 a self-aligned with thegate capping fences 114 a may be formed by removing exposed areas of the line-shapedpad patterns 122. Eachcontact pad 122 a may be electrically connected to thefirst impurity area 115 a formed between the buriedgate 112 and thefield area 102. - According to an embodiment, the
bit line trench 128 may be formed to have a first depth d1 greater than the protruding height h1 of thegate capping fence 114 a from the top surface TSa of theactive area 101. The depth d1 of thebit line trench 128 may be determined so that a top surface of the bit line to be formed in a subsequent process is located at a lower level than the top surface TSa of theactive area 101. According to another embodiment, the depth d1 of thebit line trench 128 may be determined so that the top surface of the bit line to be formed in a subsequent process is located at a higher level than the top surface TSa of theactive area 101. - According to an embodiment, a bottom surface BSt of the
bit line trench 128 may be located at a lower level than the top surface TSa of theactive area 101. The bottom surface BSt of thebit line trench 128 may be controlled to ensure a stable separation between the bit line to be formed in a subsequent process and the buriedgate 112. According to another embodiment, the bottom surface BSt of thebit line trench 128 may be located at a level the same as or similar to the top surface TSa of theactive area 101. - The top surface TSp of the
contact pad 122 a may be located at a level the same as or similar to the top surface TSf of thegate capping fence 114 a. - As described above, after the
bit line trenches 128 and thecontact pads 122 a are formed, the firsthard mask layer 124 and the remainingfirst photoresist patterns 125 may be removed. - Referring to
FIGS. 16A to 16D , and 25, aninsulator structure 130 may be formed on thesubstrate 100 having thebit line trenches 128 and thecontact pads 122 a. Theinsulator structure 130 may include an insulating layer having a low dielectric constant, e.g., silicon oxide or the like, or an air gap, or both. Theinsulator structure 130 may be formed on an inner wall of thebit line trench 128 to have a conformal thickness. Theinsulator structure 130 including an insulating layer having a low dielectric constant or an air gap can reduce parasitic capacitance between the bit line and a low electrode of a capacitor to be formed in a subsequent process. - A second
hard mask layer 138 may be formed on theinsulator structure 130. The secondhard mask layer 138 may include a material having an etch selectivity with respect to theinsulator structure 130 thereunder. For example, the secondhard mask layer 138 may be formed by a carbon containing layer such as an SOH mask. - A
second photoresist pattern 139 defining bitline contact areas 140 may be formed on the secondhard mask layer 138. Before thesecond photoresist pattern 139 is formed, an anti-reflection layer such as a SiON or the like may be formed on the secondhard mask layer 138. - Referring to
FIGS. 17A to 17D , the secondhard mask layer 138 may be patterned by performing a photolithography process using thesecond photoresist pattern 139. Thesecond photoresist pattern 139 having a similar etch characteristic to the secondhard mask layer 138 may be etched together while the secondhard mask layer 138 is etched. - The bit
line contact areas 140 may be formed by etching theinsulator structure 130 using the patterned secondhard mask layer 138 as an etch mask. - The
insulator structure 130 may expose the bitline contact areas 140, and extend in the first direction along the inner wall of thebit line trench 128. Theinsulator structure 130 may stably separate thecontact pad 122 a from the bit line to be formed in a subsequent process. - The second
hard mask layer 138 and the remainingsecond photoresist pattern 139 may be removed. - Referring to
FIGS. 18A to 18D , and 26, a bit line conductive layer may be deposited on thesubstrate 100 to fill thebit line trench 128.Bit lines 142 filling eachbit line trench 128 and extending in the second direction may be formed on theinsulator structure 130 by partially removing the bit line conductive layer with an etch-back process or a CMP process. - The
bit line 142 may be electrically connected to thesecond impurity area 115 b formed in theactive area 101 between a pair of buriedgates 112 through the bitline contact area 140. Since thebit line 142 is formed by performing a damascene process, a fine pattern can be implemented by overcoming a pattern limitation of a photolithography process. For example, thebit line 142 may include a low-resistance metal such as tungsten (W) or titanium nitride (TiN). - According to an embodiment, a top surface TSb of the
bit line 142 may be located at a lower level than the top surface TSa of theactive area 101. Therefore, thebit line 142 may be formed as a structure fully buried in thesubstrate 100. According to another embodiment, since the top surface TSb of thebit line 142 is located at a higher level than the top surface TSa of theactive area 101, thebit line 142 may be formed as a structure partially buried in thesubstrate 100. According to still another embodiment,bit line 142 may be formed on thesubstrate 100. - Referring to
FIGS. 19A to 19D , and 27, an insulating layer may be deposited on thesubstrate 100 in which thebit lines 142 are formed. Bitline capping patterns 144 filling upper parts of thebit line trenches 128 and extending in the second direction may be formed by partially removing the insulating layer with an etch-back process or a CMP process until top surfaces of thecontact pads 122 a are exposed. - When the bit
line capping patterns 144 are formed, the top surfaces of thecontact pads 122 a and thegate capping fences 114 a may be exposed together. - A top surface of the bit
line capping pattern 144 may be located at a level substantially the same as or similar to the top surface of thegate capping fence 114 a. The bitline capping pattern 144 may include silicon nitride. - A bit line structure including a
bit line trench 128, aninsulator structure 130, abit line 142, and a bitline capping pattern 144 may be formed in or on thesubstrate 100 by the process described inFIGS. 15 to 19 . - As shown in
FIG. 2 , thelower electrode 150 of the capacitor may be formed on thecontact pads 122 a. Thelower electrode 150 of the capacitor may be electrically connected to the first impurity areal 15 a formed between the buriedgate 112 and thefield area 102 through thecontact pad 122 a thereunder. - Since the
lower electrode 150 of the capacitor may be directly formed on thecontact pad 122 a, which is self-aligned with thegate capping fence 114 a, without a contact hole, contact misalignment can be prevented. Thelower electrode 150 of the capacitor may be stably separated from thebit line 142 by theinsulator structure 130 and the bitline capping pattern 144. Scaling down of the semiconductor device can be implemented to sufficiently ensure a distance between thelower electrode 150 of the capacitor and thebit line 142 by thegate capping fence 114 a and theinsulator structure 130 a. - According the method of manufacturing a semiconductor device in accordance with the inventive concepts, a process of forming a contact hole and a landing pad to connect the
lower electrode 150 of the capacitor with theactive area 101 of thesubstrate 100, and a process of forming an interlayer insulating layer between thebit line 142 and thelower electrode 150 of the capacitor can be omitted to simplify the manufacturing process and to improve process throughput. -
FIGS. 28A to 28D are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with another embodiment. - Referring to
FIG. 28A , the process described with reference toFIGS. 11 to 15 may be performed to form buriedgates 112,gate capping fences 114 a,bit line trenches 128, andcontact pads 122 a in and on asubstrate 100 having afield area 102 definingactive areas 101. - The
gate capping fence 114 a may cover a top surface of the buriedgate 112, extend in a first direction, and protrude from a top surface of theactive area 101. Thebit line trench 128 may be formed in thegate capping fence 114 a, cross thegate capping fences 114 a, and extend in a second direction perpendicular to the first direction. Thebit line trench 128 may be formed to have a depth greater than or equal to a protruding height of thegate capping fence 114 a from the top surface of theactive area 101. Thecontact pad 122 a may be self-aligned with thegate capping fence 114 a on thesubstrate 100 between the adjacentbit line trenches 128. - A first insulating
layer 131, asacrificial layer 132, and a second insulatinglayer 133 may be sequentially formed on thesubstrate 100. The first insulatinglayer 131, thesacrificial layer 132, and the second insulatinglayer 133 may be formed to have conformal thicknesses on an inner wall of thebit line trench 128. Each of the first and second insulatinglayers sacrificial layer 132 may include a material having an etch selectivity with respect to the first and second insulatinglayers - Referring to
FIG. 28B , bitline contact areas 140 may be formed by etching the second insulatinglayer 133, thesacrificial layer 132, and the first insulatinglayer 131 which are located on theactive area 101 between a pair of buriedgates 112. - Referring to
FIG. 28C ,bit lines 142 may be formed to fill lower parts of thebit line trenches 128. Thebit line 142 may be electrically connected to theactive area 101 between a pair of buriedgates 112 through the bitline contact area 140. - An
air gap 136 may be formed between the first insulatinglayer 131 and the second insulatinglayer 133 by selectively removing thesacrificial layer 132 with a wet etching process. - A bit
line capping pattern 144 may be formed to cover top surfaces of thebit lines 142 and to fill thebit line trenches 128. - Referring to
FIG. 28D , the bitline capping pattern 144 may be partially removed by performing an etch-back process or a CMP process until top surfaces of thecontact pads 122 a are exposed. The top surface of thebit line 142 may be covered by the bitline capping pattern 144, and sides of thebit line 142 may be covered by aninsulator structure 130 c including the first insulatinglayer 131, thesacrificial layer 132, and the second insulatinglayer 133. - A lower electrode of a capacitor may be directly formed on each
contact pad 122 a without a contact hole. The lower electrode of the capacitor may be stably separated from thebit line 142 by the bitline capping pattern 144 and theinsulator structure 130 c. -
FIG. 29 is a block diagram of an electronic system having the semiconductor devices in accordance with various embodiments. - Referring to
FIG. 29 , the semiconductor devices in accordance with various embodiments may be applied to theelectronic system 1000. - The
electronic system 1000 may include acontroller 1100, an input/output 1200, amemory 1300, aninterface 1400, and abus 1500. - The
controller 1100, the input/output 1200, thememory 1300, and theinterface 1400 may be combined through thebus 1500. Thebus 1500 may be a path through which data moves. - The
controller 1100 may include at least one of a microprocessor, a digital signal processor, a micro controller, and logical devices capable of performing a similar function thereto. The input/output 1200 may include a keypad, a keyboard, a display device, etc. Thememory 1300 may store data and/or a command. Theinterface 1400 may serve to transmit data to a communication network or receive data from the communication network. Theinterface 1400 may be a wired or wireless form. For example, theinterface 1400 may include an antenna, a wired/wireless transceiver, or the like. Semiconductor devices in accordance with various embodiments described herein may be used in thecontroller 1100, the input/output 1200, thememory 1300 or theinterface 1400 or in various combinations and subcombinations thereof. - According to various embodiments, the bit line trenches may be formed by a damascene process using the gate capping fences protruding from the top surfaces of the active areas, and contact pads self-aligned with the gate capping fence may be formed on the substrate between the adjacent bit lines. Since the lower electrode of the capacitor may be directly formed on the contact pad, which is self-aligned with the gate capping fence, without a contact hole, contact misalignment can be reduced or prevented.
- Other various effects in accordance with various embodiments were described in the above detailed specification.
- The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
Claims (13)
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CN107634103A (en) * | 2017-10-24 | 2018-01-26 | 睿力集成电路有限公司 | Internal memory transistor and forming method thereof, semiconductor devices |
CN116017977A (en) * | 2023-03-27 | 2023-04-25 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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US20160284640A1 (en) * | 2015-03-25 | 2016-09-29 | Inotera Memories, Inc. | Semiconductor device having buried wordlines |
KR102406663B1 (en) | 2016-07-06 | 2022-06-08 | 삼성전자주식회사 | Method of manufacturing integrated circuit device |
KR102450577B1 (en) | 2016-08-12 | 2022-10-11 | 삼성전자주식회사 | Semiconductor devices |
KR102527904B1 (en) | 2016-11-18 | 2023-04-28 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
CN109935588B (en) | 2017-12-18 | 2020-12-29 | 联华电子股份有限公司 | Memory and manufacturing method thereof |
KR20230046783A (en) | 2021-09-30 | 2023-04-06 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
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KR100539272B1 (en) * | 2003-02-24 | 2005-12-27 | 삼성전자주식회사 | Semiconductor device and Method of manufacturing the same |
KR100499175B1 (en) | 2003-09-01 | 2005-07-01 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
KR20070038225A (en) * | 2005-10-05 | 2007-04-10 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
US7622354B2 (en) * | 2007-08-31 | 2009-11-24 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
KR101432619B1 (en) * | 2008-07-07 | 2014-08-21 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the semiconductor device |
KR101559063B1 (en) * | 2009-02-02 | 2015-10-08 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
KR101096188B1 (en) * | 2009-10-30 | 2011-12-22 | 주식회사 하이닉스반도체 | Method for manufacturing buried and buried bitline |
KR101725446B1 (en) * | 2011-08-24 | 2017-04-12 | 삼성전자주식회사 | Semiconductor Devices and Methods of Fabricating the Same |
KR20130026266A (en) | 2011-09-05 | 2013-03-13 | 삼성전자주식회사 | Semiconductor devices and methods of fabricating the same |
KR20130039525A (en) | 2011-10-12 | 2013-04-22 | 에스케이하이닉스 주식회사 | Semiconductor device with damascene bitline and method for fabricating the same |
KR101979752B1 (en) * | 2012-05-03 | 2019-05-17 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
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CN107634103A (en) * | 2017-10-24 | 2018-01-26 | 睿力集成电路有限公司 | Internal memory transistor and forming method thereof, semiconductor devices |
WO2019080850A1 (en) * | 2017-10-24 | 2019-05-02 | Changxin Memory Technologies, Inc. | Memory transistor, fabrication method thereof and semiconductor device |
US11329049B2 (en) | 2017-10-24 | 2022-05-10 | Changxin Memory Technologies, Inc. | Memory transistor with cavity structure |
CN116017977A (en) * | 2023-03-27 | 2023-04-25 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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US9240414B1 (en) | 2016-01-19 |
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